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TARGET_NCS36510/TOOLCHAIN_IAR/rtc_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file rtc_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief Real Time Clock HW register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor.
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 3008 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup rtc
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 * <p>
AnnaBridge 171:3a7713b1edbc 31 * Teal Time Clock HW register map description
AnnaBridge 171:3a7713b1edbc 32 * </p>
AnnaBridge 171:3a7713b1edbc 33 *
AnnaBridge 171:3a7713b1edbc 34 * <h1> Reference document(s) </h1>
AnnaBridge 171:3a7713b1edbc 35 * <p>
AnnaBridge 171:3a7713b1edbc 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
AnnaBridge 171:3a7713b1edbc 37 * IPC7206 APB RTC Design Specification v1.0 </a>
AnnaBridge 171:3a7713b1edbc 38 * </p>
AnnaBridge 171:3a7713b1edbc 39 */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #ifndef RTC_MAP_H_
AnnaBridge 171:3a7713b1edbc 42 #define RTC_MAP_H_
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** Real Time Clock Control HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 47 typedef struct {
AnnaBridge 171:3a7713b1edbc 48 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
AnnaBridge 171:3a7713b1edbc 49 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
AnnaBridge 171:3a7713b1edbc 50 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
AnnaBridge 171:3a7713b1edbc 51 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
AnnaBridge 171:3a7713b1edbc 52 union {
AnnaBridge 171:3a7713b1edbc 53 struct {
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
AnnaBridge 171:3a7713b1edbc 58 } BITS;
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 60 } CONTROL; /* 0x4000F010 */
AnnaBridge 171:3a7713b1edbc 61 union {
AnnaBridge 171:3a7713b1edbc 62 struct {
AnnaBridge 171:3a7713b1edbc 63 /**<Any write to the status register will clear the error bit. */
AnnaBridge 171:3a7713b1edbc 64 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
AnnaBridge 171:3a7713b1edbc 65 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
AnnaBridge 171:3a7713b1edbc 66 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
AnnaBridge 171:3a7713b1edbc 67 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
AnnaBridge 171:3a7713b1edbc 68 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
AnnaBridge 171:3a7713b1edbc 69 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
AnnaBridge 171:3a7713b1edbc 70 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
AnnaBridge 171:3a7713b1edbc 71 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
AnnaBridge 171:3a7713b1edbc 72 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
AnnaBridge 171:3a7713b1edbc 73 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
AnnaBridge 171:3a7713b1edbc 74 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
AnnaBridge 171:3a7713b1edbc 75 } BITS;
AnnaBridge 171:3a7713b1edbc 76 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 77 } STATUS; /* 0x4000F014 */
AnnaBridge 171:3a7713b1edbc 78 union {
AnnaBridge 171:3a7713b1edbc 79 struct {
AnnaBridge 171:3a7713b1edbc 80 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
AnnaBridge 171:3a7713b1edbc 81 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
AnnaBridge 171:3a7713b1edbc 82 } BITS;
AnnaBridge 171:3a7713b1edbc 83 __O uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 84 } INT_CLEAR; /* 0x4000F018 */
AnnaBridge 171:3a7713b1edbc 85 } RtcReg_t, *RtcReg_pt;
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 #endif /* RTC_MAP_H_ */