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TARGET_NCS36510/TOOLCHAIN_IAR/pmu_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file pmu_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief PMU hw module register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 3372 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup pmu
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 #ifndef PMU_MAP_H_
AnnaBridge 171:3a7713b1edbc 33 #define PMU_MAP_H_
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 36 * *
AnnaBridge 171:3a7713b1edbc 37 * Header files *
AnnaBridge 171:3a7713b1edbc 38 * *
AnnaBridge 171:3a7713b1edbc 39 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**************************************************************************************************
AnnaBridge 171:3a7713b1edbc 44 * *
AnnaBridge 171:3a7713b1edbc 45 * Type definitions *
AnnaBridge 171:3a7713b1edbc 46 * *
AnnaBridge 171:3a7713b1edbc 47 **************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** PMU control
AnnaBridge 171:3a7713b1edbc 50 * The Power Management Unit (PMU) is used to control the differing power modes.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef struct {
AnnaBridge 171:3a7713b1edbc 53 union {
AnnaBridge 171:3a7713b1edbc 54 struct {
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
AnnaBridge 171:3a7713b1edbc 62 __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
AnnaBridge 171:3a7713b1edbc 63 __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
AnnaBridge 171:3a7713b1edbc 64 __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
AnnaBridge 171:3a7713b1edbc 65 __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
AnnaBridge 171:3a7713b1edbc 66 __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
AnnaBridge 171:3a7713b1edbc 67 } BITS;
AnnaBridge 171:3a7713b1edbc 68 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 69 } CONTROL; /* 0x4001D000 */
AnnaBridge 171:3a7713b1edbc 70 union {
AnnaBridge 171:3a7713b1edbc 71 struct {
AnnaBridge 171:3a7713b1edbc 72 __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
AnnaBridge 171:3a7713b1edbc 73 __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 } BITS;
AnnaBridge 171:3a7713b1edbc 76 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 77 } STATUS; /* 0x4001D004 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t PLACEHOLDER; /* 0x4001D008 */
AnnaBridge 171:3a7713b1edbc 80 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
AnnaBridge 171:3a7713b1edbc 81 __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
AnnaBridge 171:3a7713b1edbc 83 union {
AnnaBridge 171:3a7713b1edbc 84 struct {
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t TH:6; /**< Threshold */
AnnaBridge 171:3a7713b1edbc 86 __I uint32_t PAD:2;
AnnaBridge 171:3a7713b1edbc 87 __I uint32_t UVIVAL:6; /**< UVI value */
AnnaBridge 171:3a7713b1edbc 88 } BITS;
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 90 } UVI_TBASE; /* 0x4001D018 */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t SRAM_TRIM; /* 0x4001D01C */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 } PmuReg_t, *PmuReg_pt;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 #endif /* PMU_MAP_H_ */