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TARGET_NCS36510/TOOLCHAIN_IAR/dma_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file dma_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief DMA hw module register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 3415 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup dma
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 #ifndef DMA_MAP_H_
AnnaBridge 171:3a7713b1edbc 33 #define DMA_MAP_H_
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 36 * *
AnnaBridge 171:3a7713b1edbc 37 * Header files *
AnnaBridge 171:3a7713b1edbc 38 * *
AnnaBridge 171:3a7713b1edbc 39 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**************************************************************************************************
AnnaBridge 171:3a7713b1edbc 44 * *
AnnaBridge 171:3a7713b1edbc 45 * Type definitions *
AnnaBridge 171:3a7713b1edbc 46 * *
AnnaBridge 171:3a7713b1edbc 47 **************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** DMA control HW registers structure overlay */
AnnaBridge 171:3a7713b1edbc 50 typedef struct {
AnnaBridge 171:3a7713b1edbc 51 union {
AnnaBridge 171:3a7713b1edbc 52 struct {
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
AnnaBridge 171:3a7713b1edbc 55 } BITS;
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 57 } CONTROL; /**< Control register */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
AnnaBridge 171:3a7713b1edbc 61 union {
AnnaBridge 171:3a7713b1edbc 62 struct {
AnnaBridge 171:3a7713b1edbc 63 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
AnnaBridge 171:3a7713b1edbc 64 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
AnnaBridge 171:3a7713b1edbc 65 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
AnnaBridge 171:3a7713b1edbc 66 } BITS;
AnnaBridge 171:3a7713b1edbc 67 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 68 } STATUS; /**< Status register */
AnnaBridge 171:3a7713b1edbc 69 union {
AnnaBridge 171:3a7713b1edbc 70 struct {
AnnaBridge 171:3a7713b1edbc 71 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
AnnaBridge 171:3a7713b1edbc 72 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
AnnaBridge 171:3a7713b1edbc 73 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
AnnaBridge 171:3a7713b1edbc 74 } BITS;
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 76 } INT_ENABLE; /**< Interrupt enable */
AnnaBridge 171:3a7713b1edbc 77 union {
AnnaBridge 171:3a7713b1edbc 78 struct {
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
AnnaBridge 171:3a7713b1edbc 80 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
AnnaBridge 171:3a7713b1edbc 81 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
AnnaBridge 171:3a7713b1edbc 82 } BITS;
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 84 } INT_CLEAR; /**< Interrupt clear */
AnnaBridge 171:3a7713b1edbc 85 union {
AnnaBridge 171:3a7713b1edbc 86 struct {
AnnaBridge 171:3a7713b1edbc 87 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
AnnaBridge 171:3a7713b1edbc 88 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
AnnaBridge 171:3a7713b1edbc 89 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
AnnaBridge 171:3a7713b1edbc 90 } BITS;
AnnaBridge 171:3a7713b1edbc 91 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 92 } INT_STATUS; /**< Interrupt status */
AnnaBridge 171:3a7713b1edbc 93 } DmaReg_t, *DmaReg_pt;
AnnaBridge 171:3a7713b1edbc 94 #endif /* DMA_MAP_H_ */