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TARGET_NCS36510/TOOLCHAIN_GCC_ARM/ticker.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file ticker.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @brief Microcontroller uSec ticker |
AnnaBridge | 171:3a7713b1edbc | 5 | * @internal |
AnnaBridge | 171:3a7713b1edbc | 6 | * @author ON Semiconductor. |
AnnaBridge | 171:3a7713b1edbc | 7 | * $Rev: |
AnnaBridge | 171:3a7713b1edbc | 8 | * $Date: |
AnnaBridge | 171:3a7713b1edbc | 9 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
AnnaBridge | 171:3a7713b1edbc | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
AnnaBridge | 171:3a7713b1edbc | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
AnnaBridge | 171:3a7713b1edbc | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
AnnaBridge | 171:3a7713b1edbc | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
AnnaBridge | 171:3a7713b1edbc | 15 | * if applicable the software license agreement. Do not use this software and/or |
AnnaBridge | 171:3a7713b1edbc | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
AnnaBridge | 171:3a7713b1edbc | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
AnnaBridge | 171:3a7713b1edbc | 18 | * terms and conditions. |
AnnaBridge | 171:3a7713b1edbc | 19 | * |
AnnaBridge | 171:3a7713b1edbc | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
AnnaBridge | 171:3a7713b1edbc | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
AnnaBridge | 171:3a7713b1edbc | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
AnnaBridge | 171:3a7713b1edbc | 25 | * @endinternal |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | */ |
AnnaBridge | 171:3a7713b1edbc | 29 | |
AnnaBridge | 171:3a7713b1edbc | 30 | #ifndef TICKER_H_ |
AnnaBridge | 171:3a7713b1edbc | 31 | #define TICKER_H_ |
AnnaBridge | 171:3a7713b1edbc | 32 | |
AnnaBridge | 171:3a7713b1edbc | 33 | #include "types.h" |
AnnaBridge | 171:3a7713b1edbc | 34 | |
AnnaBridge | 171:3a7713b1edbc | 35 | /** Core frequency definitions. / |
AnnaBridge | 171:3a7713b1edbc | 36 | * |
AnnaBridge | 171:3a7713b1edbc | 37 | * These definitions should be adjusted to setup Orion core frequencies. |
AnnaBridge | 171:3a7713b1edbc | 38 | */ |
AnnaBridge | 171:3a7713b1edbc | 39 | #define CPU_CLOCK_ROOT_HZ ( ( unsigned long ) 32000000) /**< <b> Orion 32MHz root frequency </b> */ |
AnnaBridge | 171:3a7713b1edbc | 40 | #define CPU_CLOCK_DIV_32M ( 1 ) /**< <b> Divider to set up core frequency at 32MHz </b> */ |
AnnaBridge | 171:3a7713b1edbc | 41 | #define CPU_CLOCK_DIV_16M ( 2 ) /**< <b> Divider to set up core frequency at 16MHz </b> */ |
AnnaBridge | 171:3a7713b1edbc | 42 | #define CPU_CLOCK_DIV_8M ( 4 ) /**< <b> Divider to set up core frequency at 8MHz </b> */ |
AnnaBridge | 171:3a7713b1edbc | 43 | #define CPU_CLOCK_DIV_4M ( 8 ) /**< <b> Divider to set up core frequency at 4MHz </b> */ |
AnnaBridge | 171:3a7713b1edbc | 44 | |
AnnaBridge | 171:3a7713b1edbc | 45 | #define CPU_CLOCK_DIV CPU_CLOCK_DIV_32M /**< <b> Selected divider to be used by application code </b> */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #define configCPU_CLOCK_HZ ( ( unsigned long ) (CPU_CLOCK_ROOT_HZ/CPU_CLOCK_DIV) ) |
AnnaBridge | 171:3a7713b1edbc | 48 | #define configTICK_RATE_HZ ( ( unsigned long ) 1000000 ) // 1uSec ticker rate |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /* Lowest priority */ |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | #define configKERNEL_INTERRUPT_PRIORITY ( 0xFF ) |
AnnaBridge | 171:3a7713b1edbc | 54 | #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 0x8F ) |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ |
AnnaBridge | 171:3a7713b1edbc | 57 | |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Constants required to manipulate the core. Registers first... */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) ) |
AnnaBridge | 171:3a7713b1edbc | 60 | #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) ) |
AnnaBridge | 171:3a7713b1edbc | 61 | #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) ) |
AnnaBridge | 171:3a7713b1edbc | 62 | #define portNVIC_INT_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000ed04 ) ) |
AnnaBridge | 171:3a7713b1edbc | 63 | #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) ) |
AnnaBridge | 171:3a7713b1edbc | 64 | |
AnnaBridge | 171:3a7713b1edbc | 65 | /* ...then bits in the registers. */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) |
AnnaBridge | 171:3a7713b1edbc | 67 | #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) |
AnnaBridge | 171:3a7713b1edbc | 68 | #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) |
AnnaBridge | 171:3a7713b1edbc | 69 | #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | /* Orion has 4 interrupt priority bits |
AnnaBridge | 171:3a7713b1edbc | 72 | */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | /* API definitions */ |
AnnaBridge | 171:3a7713b1edbc | 76 | void fSysTickInit(void); |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | void fSysTickHandler(void); |
AnnaBridge | 171:3a7713b1edbc | 79 | |
AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t fSysTickRead(void); |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | void fSysTickEnableInterrupt (void); |
AnnaBridge | 171:3a7713b1edbc | 83 | |
AnnaBridge | 171:3a7713b1edbc | 84 | void fSysTickDisableInterrupt (void); |
AnnaBridge | 171:3a7713b1edbc | 85 | #endif // TICKER_H_ |