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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 170:e95d10626187
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 161:aa5281ff4a02 | 1 | /* |
AnnaBridge | 161:aa5281ff4a02 | 2 | ** ################################################################### |
AnnaBridge | 170:e95d10626187 | 3 | ** Processors: MIMXRT1052CVJ5B |
AnnaBridge | 170:e95d10626187 | 4 | ** MIMXRT1052CVL5B |
AnnaBridge | 170:e95d10626187 | 5 | ** MIMXRT1052DVJ6B |
AnnaBridge | 170:e95d10626187 | 6 | ** MIMXRT1052DVL6B |
AnnaBridge | 161:aa5281ff4a02 | 7 | ** |
AnnaBridge | 161:aa5281ff4a02 | 8 | ** Compiler: IAR ANSI C/C++ Compiler for ARM |
AnnaBridge | 170:e95d10626187 | 9 | ** Reference manual: IMXRT1050RM Rev.1, 03/2018 |
AnnaBridge | 161:aa5281ff4a02 | 10 | ** Version: rev. 0.1, 2017-01-10 |
AnnaBridge | 170:e95d10626187 | 11 | ** Build: b180509 |
AnnaBridge | 161:aa5281ff4a02 | 12 | ** |
AnnaBridge | 161:aa5281ff4a02 | 13 | ** Abstract: |
AnnaBridge | 161:aa5281ff4a02 | 14 | ** Linker file for the IAR ANSI C/C++ Compiler for ARM |
AnnaBridge | 161:aa5281ff4a02 | 15 | ** |
AnnaBridge | 170:e95d10626187 | 16 | ** The Clear BSD License |
AnnaBridge | 161:aa5281ff4a02 | 17 | ** Copyright 2016 Freescale Semiconductor, Inc. |
AnnaBridge | 170:e95d10626187 | 18 | ** Copyright 2016-2018 NXP |
AnnaBridge | 170:e95d10626187 | 19 | ** All rights reserved. |
AnnaBridge | 161:aa5281ff4a02 | 20 | ** |
AnnaBridge | 170:e95d10626187 | 21 | ** Redistribution and use in source and binary forms, with or without |
AnnaBridge | 170:e95d10626187 | 22 | ** modification, are permitted (subject to the limitations in the |
AnnaBridge | 170:e95d10626187 | 23 | ** disclaimer below) provided that the following conditions are met: |
AnnaBridge | 161:aa5281ff4a02 | 24 | ** |
AnnaBridge | 170:e95d10626187 | 25 | ** * Redistributions of source code must retain the above copyright |
AnnaBridge | 170:e95d10626187 | 26 | ** notice, this list of conditions and the following disclaimer. |
AnnaBridge | 170:e95d10626187 | 27 | ** |
AnnaBridge | 170:e95d10626187 | 28 | ** * Redistributions in binary form must reproduce the above copyright |
AnnaBridge | 170:e95d10626187 | 29 | ** notice, this list of conditions and the following disclaimer in the |
AnnaBridge | 170:e95d10626187 | 30 | ** documentation and/or other materials provided with the distribution. |
AnnaBridge | 161:aa5281ff4a02 | 31 | ** |
AnnaBridge | 170:e95d10626187 | 32 | ** * Neither the name of the copyright holder nor the names of its |
AnnaBridge | 170:e95d10626187 | 33 | ** contributors may be used to endorse or promote products derived from |
AnnaBridge | 170:e95d10626187 | 34 | ** this software without specific prior written permission. |
AnnaBridge | 161:aa5281ff4a02 | 35 | ** |
AnnaBridge | 170:e95d10626187 | 36 | ** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE |
AnnaBridge | 170:e95d10626187 | 37 | ** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT |
AnnaBridge | 170:e95d10626187 | 38 | ** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 170:e95d10626187 | 39 | ** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 170:e95d10626187 | 40 | ** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 170:e95d10626187 | 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
AnnaBridge | 170:e95d10626187 | 42 | ** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
AnnaBridge | 170:e95d10626187 | 43 | ** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
AnnaBridge | 170:e95d10626187 | 44 | ** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
AnnaBridge | 170:e95d10626187 | 45 | ** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
AnnaBridge | 170:e95d10626187 | 46 | ** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
AnnaBridge | 170:e95d10626187 | 47 | ** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
AnnaBridge | 170:e95d10626187 | 48 | ** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 161:aa5281ff4a02 | 49 | ** |
AnnaBridge | 161:aa5281ff4a02 | 50 | ** http: www.nxp.com |
AnnaBridge | 161:aa5281ff4a02 | 51 | ** mail: support@nxp.com |
AnnaBridge | 161:aa5281ff4a02 | 52 | ** |
AnnaBridge | 161:aa5281ff4a02 | 53 | ** ################################################################### |
AnnaBridge | 161:aa5281ff4a02 | 54 | */ |
AnnaBridge | 170:e95d10626187 | 55 | |
AnnaBridge | 161:aa5281ff4a02 | 56 | define symbol __ram_vector_table__ = 1; |
AnnaBridge | 161:aa5281ff4a02 | 57 | |
AnnaBridge | 161:aa5281ff4a02 | 58 | define symbol __stack_size__=0x8000; |
AnnaBridge | 161:aa5281ff4a02 | 59 | define symbol __heap_size__=0x10000; |
AnnaBridge | 161:aa5281ff4a02 | 60 | |
AnnaBridge | 161:aa5281ff4a02 | 61 | define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; |
AnnaBridge | 161:aa5281ff4a02 | 62 | define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; |
AnnaBridge | 161:aa5281ff4a02 | 63 | |
AnnaBridge | 161:aa5281ff4a02 | 64 | define symbol m_interrupts_start = 0x60002000; |
AnnaBridge | 161:aa5281ff4a02 | 65 | define symbol m_interrupts_end = 0x600023FF; |
AnnaBridge | 161:aa5281ff4a02 | 66 | |
AnnaBridge | 161:aa5281ff4a02 | 67 | define symbol m_text_start = 0x60002400; |
AnnaBridge | 161:aa5281ff4a02 | 68 | define symbol m_text_end = 0x63FFFFFF; |
AnnaBridge | 161:aa5281ff4a02 | 69 | |
AnnaBridge | 170:e95d10626187 | 70 | define symbol m_text2_start = 0x00000000; |
AnnaBridge | 170:e95d10626187 | 71 | define symbol m_text2_end = 0x0001FFFF; |
AnnaBridge | 170:e95d10626187 | 72 | |
AnnaBridge | 161:aa5281ff4a02 | 73 | define symbol m_interrupts_ram_start = 0x20000000; |
AnnaBridge | 161:aa5281ff4a02 | 74 | define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__; |
AnnaBridge | 161:aa5281ff4a02 | 75 | |
AnnaBridge | 161:aa5281ff4a02 | 76 | define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; |
AnnaBridge | 161:aa5281ff4a02 | 77 | define symbol m_data_end = 0x2001FFFF; |
AnnaBridge | 161:aa5281ff4a02 | 78 | |
AnnaBridge | 161:aa5281ff4a02 | 79 | define symbol m_data2_start = 0x20200000; |
AnnaBridge | 161:aa5281ff4a02 | 80 | define symbol m_data2_end = 0x2023FFFF; |
AnnaBridge | 161:aa5281ff4a02 | 81 | |
AnnaBridge | 170:e95d10626187 | 82 | define symbol m_data3_start = 0x80000000; |
AnnaBridge | 170:e95d10626187 | 83 | define symbol m_data3_end = 0x81DFFFFF; |
AnnaBridge | 170:e95d10626187 | 84 | |
AnnaBridge | 170:e95d10626187 | 85 | define symbol m_ncache_start = 0x81E00000; |
AnnaBridge | 170:e95d10626187 | 86 | define symbol m_ncache_end = 0x81FFFFFF; |
AnnaBridge | 170:e95d10626187 | 87 | |
AnnaBridge | 170:e95d10626187 | 88 | define exported symbol m_boot_hdr_conf_start = 0x60000000; |
AnnaBridge | 170:e95d10626187 | 89 | define symbol m_boot_hdr_ivt_start = 0x60001000; |
AnnaBridge | 170:e95d10626187 | 90 | define symbol m_boot_hdr_boot_data_start = 0x60001020; |
AnnaBridge | 170:e95d10626187 | 91 | define symbol m_boot_hdr_dcd_data_start = 0x60001030; |
AnnaBridge | 170:e95d10626187 | 92 | |
AnnaBridge | 161:aa5281ff4a02 | 93 | /* Sizes */ |
AnnaBridge | 161:aa5281ff4a02 | 94 | if (isdefinedsymbol(__stack_size__)) { |
AnnaBridge | 161:aa5281ff4a02 | 95 | define symbol __size_cstack__ = __stack_size__; |
AnnaBridge | 161:aa5281ff4a02 | 96 | } else { |
AnnaBridge | 161:aa5281ff4a02 | 97 | define symbol __size_cstack__ = 0x0400; |
AnnaBridge | 161:aa5281ff4a02 | 98 | } |
AnnaBridge | 161:aa5281ff4a02 | 99 | |
AnnaBridge | 161:aa5281ff4a02 | 100 | if (isdefinedsymbol(__heap_size__)) { |
AnnaBridge | 161:aa5281ff4a02 | 101 | define symbol __size_heap__ = __heap_size__; |
AnnaBridge | 161:aa5281ff4a02 | 102 | } else { |
AnnaBridge | 161:aa5281ff4a02 | 103 | define symbol __size_heap__ = 0x0400; |
AnnaBridge | 161:aa5281ff4a02 | 104 | } |
AnnaBridge | 161:aa5281ff4a02 | 105 | |
AnnaBridge | 161:aa5281ff4a02 | 106 | define exported symbol __VECTOR_TABLE = m_interrupts_start; |
AnnaBridge | 161:aa5281ff4a02 | 107 | define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; |
AnnaBridge | 161:aa5281ff4a02 | 108 | define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; |
AnnaBridge | 161:aa5281ff4a02 | 109 | |
AnnaBridge | 161:aa5281ff4a02 | 110 | define memory mem with size = 4G; |
AnnaBridge | 161:aa5281ff4a02 | 111 | define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] |
AnnaBridge | 161:aa5281ff4a02 | 112 | | mem:[from m_text_start to m_text_end]; |
AnnaBridge | 161:aa5281ff4a02 | 113 | |
AnnaBridge | 170:e95d10626187 | 114 | define region TEXT2_region = mem:[from m_text2_start to m_text2_end]; |
AnnaBridge | 170:e95d10626187 | 115 | |
AnnaBridge | 170:e95d10626187 | 116 | define region DATA_region = mem:[from m_data_start to m_data_end]; |
AnnaBridge | 161:aa5281ff4a02 | 117 | define region DATA2_region = mem:[from m_data2_start to m_data2_end]; |
AnnaBridge | 170:e95d10626187 | 118 | define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; |
AnnaBridge | 170:e95d10626187 | 119 | define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; |
AnnaBridge | 170:e95d10626187 | 120 | define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; |
AnnaBridge | 161:aa5281ff4a02 | 121 | define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; |
AnnaBridge | 161:aa5281ff4a02 | 122 | |
AnnaBridge | 161:aa5281ff4a02 | 123 | define block CSTACK with alignment = 8, size = __size_cstack__ { }; |
AnnaBridge | 161:aa5281ff4a02 | 124 | define block HEAP with alignment = 8, size = __size_heap__ { }; |
AnnaBridge | 170:e95d10626187 | 125 | define block RW { first readwrite, section m_usb_dma_init_data }; |
AnnaBridge | 170:e95d10626187 | 126 | define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; |
AnnaBridge | 170:e95d10626187 | 127 | define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; |
AnnaBridge | 161:aa5281ff4a02 | 128 | |
AnnaBridge | 161:aa5281ff4a02 | 129 | initialize by copy { readwrite, section .textrw }; |
AnnaBridge | 161:aa5281ff4a02 | 130 | do not initialize { section .noinit }; |
AnnaBridge | 161:aa5281ff4a02 | 131 | |
AnnaBridge | 161:aa5281ff4a02 | 132 | place at address mem: m_interrupts_start { readonly section .intvec }; |
AnnaBridge | 161:aa5281ff4a02 | 133 | |
AnnaBridge | 170:e95d10626187 | 134 | place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; |
AnnaBridge | 170:e95d10626187 | 135 | place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; |
AnnaBridge | 170:e95d10626187 | 136 | place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; |
AnnaBridge | 170:e95d10626187 | 137 | place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; |
AnnaBridge | 170:e95d10626187 | 138 | |
AnnaBridge | 170:e95d10626187 | 139 | keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; |
AnnaBridge | 170:e95d10626187 | 140 | |
AnnaBridge | 161:aa5281ff4a02 | 141 | place in TEXT_region { readonly }; |
AnnaBridge | 170:e95d10626187 | 142 | place in DATA3_region { block RW }; |
AnnaBridge | 170:e95d10626187 | 143 | place in DATA3_region { block ZI }; |
AnnaBridge | 170:e95d10626187 | 144 | place in DATA3_region { last block HEAP }; |
AnnaBridge | 161:aa5281ff4a02 | 145 | place in CSTACK_region { block CSTACK }; |
AnnaBridge | 170:e95d10626187 | 146 | place in NCACHE_region { block NCACHE_VAR }; |
AnnaBridge | 170:e95d10626187 | 147 | place in TEXT2_region { section .textrw}; |
AnnaBridge | 161:aa5281ff4a02 | 148 | place in m_interrupts_ram_region { section m_interrupts_ram }; |