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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/wdt2_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief Registers, Bit Masks and Bit Positions for the WDT2 Peripheral Module. |
AnnaBridge | 171:3a7713b1edbc | 4 | */ |
AnnaBridge | 171:3a7713b1edbc | 5 | /* **************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
AnnaBridge | 171:3a7713b1edbc | 9 | * copy of this software and associated documentation files (the "Software"), |
AnnaBridge | 171:3a7713b1edbc | 10 | * to deal in the Software without restriction, including without limitation |
AnnaBridge | 171:3a7713b1edbc | 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
AnnaBridge | 171:3a7713b1edbc | 12 | * and/or sell copies of the Software, and to permit persons to whom the |
AnnaBridge | 171:3a7713b1edbc | 13 | * Software is furnished to do so, subject to the following conditions: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * The above copyright notice and this permission notice shall be included |
AnnaBridge | 171:3a7713b1edbc | 16 | * in all copies or substantial portions of the Software. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
AnnaBridge | 171:3a7713b1edbc | 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
AnnaBridge | 171:3a7713b1edbc | 21 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 22 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
AnnaBridge | 171:3a7713b1edbc | 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
AnnaBridge | 171:3a7713b1edbc | 24 | * OTHER DEALINGS IN THE SOFTWARE. |
AnnaBridge | 171:3a7713b1edbc | 25 | * |
AnnaBridge | 171:3a7713b1edbc | 26 | * Except as contained in this notice, the name of Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 27 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 28 | * Products, Inc. Branding Policy. |
AnnaBridge | 171:3a7713b1edbc | 29 | * |
AnnaBridge | 171:3a7713b1edbc | 30 | * The mere transfer of this software does not imply any licenses |
AnnaBridge | 171:3a7713b1edbc | 31 | * of trade secrets, proprietary technology, copyrights, patents, |
AnnaBridge | 171:3a7713b1edbc | 32 | * trademarks, maskwork rights, or any other form of intellectual |
AnnaBridge | 171:3a7713b1edbc | 33 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
AnnaBridge | 171:3a7713b1edbc | 34 | * ownership rights. |
AnnaBridge | 171:3a7713b1edbc | 35 | * |
AnnaBridge | 171:3a7713b1edbc | 36 | * $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $ |
AnnaBridge | 171:3a7713b1edbc | 37 | * $Revision: 24678 $ |
AnnaBridge | 171:3a7713b1edbc | 38 | * |
AnnaBridge | 171:3a7713b1edbc | 39 | *************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 40 | |
AnnaBridge | 171:3a7713b1edbc | 41 | /* **** Includes **** */ |
AnnaBridge | 171:3a7713b1edbc | 42 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Define to prevent redundant inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 45 | #ifndef _MXC_WDT2_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 46 | #define _MXC_WDT2_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 47 | |
AnnaBridge | 171:3a7713b1edbc | 48 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 49 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 50 | #endif |
AnnaBridge | 171:3a7713b1edbc | 51 | |
AnnaBridge | 171:3a7713b1edbc | 52 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 53 | /* |
AnnaBridge | 171:3a7713b1edbc | 54 | If types are not defined elsewhere (CMSIS) define them here |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #ifndef __IO |
AnnaBridge | 171:3a7713b1edbc | 57 | #define __IO volatile |
AnnaBridge | 171:3a7713b1edbc | 58 | #endif |
AnnaBridge | 171:3a7713b1edbc | 59 | #ifndef __I |
AnnaBridge | 171:3a7713b1edbc | 60 | #define __I volatile const |
AnnaBridge | 171:3a7713b1edbc | 61 | #endif |
AnnaBridge | 171:3a7713b1edbc | 62 | #ifndef __O |
AnnaBridge | 171:3a7713b1edbc | 63 | #define __O volatile |
AnnaBridge | 171:3a7713b1edbc | 64 | #endif |
AnnaBridge | 171:3a7713b1edbc | 65 | #ifndef __RO |
AnnaBridge | 171:3a7713b1edbc | 66 | #define __RO volatile const |
AnnaBridge | 171:3a7713b1edbc | 67 | #endif |
AnnaBridge | 171:3a7713b1edbc | 68 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 69 | |
AnnaBridge | 171:3a7713b1edbc | 70 | /** |
AnnaBridge | 171:3a7713b1edbc | 71 | * @ingroup wdt2 |
AnnaBridge | 171:3a7713b1edbc | 72 | * @defgroup wdt2_registers WDT2 Registers |
AnnaBridge | 171:3a7713b1edbc | 73 | * @brief Registers, Bit Masks and Bit Positions |
AnnaBridge | 171:3a7713b1edbc | 74 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 75 | */ |
AnnaBridge | 171:3a7713b1edbc | 76 | /* |
AnnaBridge | 171:3a7713b1edbc | 77 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
AnnaBridge | 171:3a7713b1edbc | 78 | access to each register in module. |
AnnaBridge | 171:3a7713b1edbc | 79 | */ |
AnnaBridge | 171:3a7713b1edbc | 80 | /** |
AnnaBridge | 171:3a7713b1edbc | 81 | * Structure type to access the WDT2 Registers, see #MXC_WDT2 to get a pointer to the WDT2 register structure. |
AnnaBridge | 171:3a7713b1edbc | 82 | * @note This is an always-on watchdog timer, it operates in all modes of operation. |
AnnaBridge | 171:3a7713b1edbc | 83 | */ |
AnnaBridge | 171:3a7713b1edbc | 84 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 85 | __IO uint32_t ctrl; /**< WDT2_CTRL Register - WDT Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 86 | __IO uint32_t clear; /**< WDT2_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */ |
AnnaBridge | 171:3a7713b1edbc | 87 | __IO uint32_t flags; /**< WDT2_FLAGS Register - WDT Interrupt and Reset Flags */ |
AnnaBridge | 171:3a7713b1edbc | 88 | __IO uint32_t enable; /**< WDT2_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */ |
AnnaBridge | 171:3a7713b1edbc | 89 | __RO uint32_t rsv010; /**< <em><b>RESERVED, DO NOT MODIFY</b></em>. */ |
AnnaBridge | 171:3a7713b1edbc | 90 | __IO uint32_t lock_ctrl; /**< WDT2_LOCK_CTRL Register - Lock for Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 91 | } mxc_wdt2_regs_t; |
AnnaBridge | 171:3a7713b1edbc | 92 | /**@} end of group wdt2_registers.*/ |
AnnaBridge | 171:3a7713b1edbc | 93 | |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /* |
AnnaBridge | 171:3a7713b1edbc | 96 | Register offsets for module WDT2. |
AnnaBridge | 171:3a7713b1edbc | 97 | */ |
AnnaBridge | 171:3a7713b1edbc | 98 | /** |
AnnaBridge | 171:3a7713b1edbc | 99 | * @ingroup wdt2_registers |
AnnaBridge | 171:3a7713b1edbc | 100 | * @defgroup WDT2_Register_Offsets Register Offsets |
AnnaBridge | 171:3a7713b1edbc | 101 | * @brief Watchdog Timer 2 Register Offsets from the WDT2 Base Peripheral Address. |
AnnaBridge | 171:3a7713b1edbc | 102 | * @details Use #MXC_WDT2 for the WDT2 Base Peripheral Address. |
AnnaBridge | 171:3a7713b1edbc | 103 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 104 | */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL) /**< WDT2_CTRL Offset: <tt>0x0000</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< WDT2_CLEAR Offset: <tt>0x0004</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< WDT2_FLAGS Offset: <tt>0x0008</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< WDT2_ENABLE Offset: <tt>0x000C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< WDT2_LOCK_CTRL Offset: <tt>0x0014</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 110 | /**@} end of group WDT2_Register_Offsets */ |
AnnaBridge | 171:3a7713b1edbc | 111 | |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | /* |
AnnaBridge | 171:3a7713b1edbc | 114 | Field positions and masks for module WDT2. |
AnnaBridge | 171:3a7713b1edbc | 115 | */ |
AnnaBridge | 171:3a7713b1edbc | 116 | /** |
AnnaBridge | 171:3a7713b1edbc | 117 | * @ingroup wdt2_registers |
AnnaBridge | 171:3a7713b1edbc | 118 | * @defgroup WDT2_CTRL_Register WDT2_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 119 | * @brief Field Positions and Bit Masks for the WDT2_CTRL register |
AnnaBridge | 171:3a7713b1edbc | 120 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 121 | */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an |
AnnaBridge | 171:3a7713b1edbc | 126 | * interrupt period has expired before the device resets. If the |
AnnaBridge | 171:3a7713b1edbc | 127 | * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration, |
AnnaBridge | 171:3a7713b1edbc | 128 | * the device will not reset. */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define MXC_F_WDT2_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10 /**< WAIT_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS)) /**< WAIT_PERIOD Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 135 | /**@} end of group WDT2_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 136 | /** |
AnnaBridge | 171:3a7713b1edbc | 137 | * @ingroup wdt2_registers |
AnnaBridge | 171:3a7713b1edbc | 138 | * @defgroup WDT2_FLAGS_Register WDT2_FLAGS Register |
AnnaBridge | 171:3a7713b1edbc | 139 | * @brief Field Positions and Bit Masks for the WDT2_FLAGS register. Watchdog Timer 2 Flags for Interrupts and Reset. |
AnnaBridge | 171:3a7713b1edbc | 140 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 141 | */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer 2 timed out. */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */ |
AnnaBridge | 171:3a7713b1edbc | 146 | /**@} end of group WDT2_FLAGS */ |
AnnaBridge | 171:3a7713b1edbc | 147 | |
AnnaBridge | 171:3a7713b1edbc | 148 | /** |
AnnaBridge | 171:3a7713b1edbc | 149 | * @ingroup wdt2_registers |
AnnaBridge | 171:3a7713b1edbc | 150 | * @defgroup WDT2_ENABLE_Register WDT2_ENABLE Register |
AnnaBridge | 171:3a7713b1edbc | 151 | * @brief Field Positions and Bit Masks for the WDT2_ENABLE register. |
AnnaBridge | 171:3a7713b1edbc | 152 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 153 | */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 158 | /**@} end of group WDT2_ENABLE */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | /** |
AnnaBridge | 171:3a7713b1edbc | 161 | * @ingroup wdt2_registers |
AnnaBridge | 171:3a7713b1edbc | 162 | * @defgroup WDT2_LOCK_CTRL_Register WDT2_LOCK_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 163 | * @brief The WDT2_LOCK_CTRL register controls read/write access to the \ref WDT2_CTRL_Register. |
AnnaBridge | 171:3a7713b1edbc | 164 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 165 | */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT2_LOCK_CTRL register. */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT2_LOCK_CTRL register. Reading a value of */ |
AnnaBridge | 171:3a7713b1edbc | 168 | /**@} end of group WDT2_ENABLE */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | |
AnnaBridge | 171:3a7713b1edbc | 171 | |
AnnaBridge | 171:3a7713b1edbc | 172 | /* |
AnnaBridge | 171:3a7713b1edbc | 173 | Field values and shifted values for module WDT2. |
AnnaBridge | 171:3a7713b1edbc | 174 | */ |
AnnaBridge | 171:3a7713b1edbc | 175 | /** |
AnnaBridge | 171:3a7713b1edbc | 176 | * @ingroup WDT2_CTRL_Register |
AnnaBridge | 171:3a7713b1edbc | 177 | * @defgroup WDT2_CTRL_field_values WDT2_CTRL Register Field and Shifted Field Values |
AnnaBridge | 171:3a7713b1edbc | 178 | * @brief Field values and Shifted Field values for the WDT2_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 179 | * @details Shifted field values are field values shifted to the loacation of the field in the register. |
AnnaBridge | 171:3a7713b1edbc | 180 | */ |
AnnaBridge | 171:3a7713b1edbc | 181 | /** |
AnnaBridge | 171:3a7713b1edbc | 182 | * @ingroup WDT2_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 183 | * @defgroup WDT2_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period |
AnnaBridge | 171:3a7713b1edbc | 184 | * @brief Sets the duration of the watchdog interrupt period. |
AnnaBridge | 171:3a7713b1edbc | 185 | * @details The INT_PERIOD field sets the duration of the watchdog interrupt |
AnnaBridge | 171:3a7713b1edbc | 186 | * period, which is the time period from the WDT2 being |
AnnaBridge | 171:3a7713b1edbc | 187 | * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_FLAGS_TIMEOUT, is |
AnnaBridge | 171:3a7713b1edbc | 188 | * set. |
AnnaBridge | 171:3a7713b1edbc | 189 | * The values defined are in the number of watchdog clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 190 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 191 | */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{15} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{14} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{13} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{12} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{11} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{10} \f$ WDT2 CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 208 | /**@} end of group WDT2_CTRL_INT_PERIOD_Value */ |
AnnaBridge | 171:3a7713b1edbc | 209 | |
AnnaBridge | 171:3a7713b1edbc | 210 | /** |
AnnaBridge | 171:3a7713b1edbc | 211 | * @ingroup WDT2_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 212 | * @defgroup WDT2_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 213 | * @brief Shifted values for the \ref WDT2_CTRL_INT_PERIOD_Value |
AnnaBridge | 171:3a7713b1edbc | 214 | * @details The shifted value is |
AnnaBridge | 171:3a7713b1edbc | 215 | * shifted to align with the fields location in the WDT2_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 216 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 217 | */ |
AnnaBridge | 171:3a7713b1edbc | 218 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 234 | /**@} end of group WDT2_CTRL_INT_PERIOD_Shifted */ |
AnnaBridge | 171:3a7713b1edbc | 235 | /** |
AnnaBridge | 171:3a7713b1edbc | 236 | * @ingroup WDT2_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 237 | * @defgroup WDT2_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period |
AnnaBridge | 171:3a7713b1edbc | 238 | * @brief Sets the duration of the watchdog reset period. |
AnnaBridge | 171:3a7713b1edbc | 239 | * @details The RST_PERIOD field sets the duration of the watchdog reset |
AnnaBridge | 171:3a7713b1edbc | 240 | * period, which is the time period from the WDT being |
AnnaBridge | 171:3a7713b1edbc | 241 | * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_CTRL_RST_PERIOD is |
AnnaBridge | 171:3a7713b1edbc | 242 | * set. |
AnnaBridge | 171:3a7713b1edbc | 243 | * The values defined are in the number of watchdog clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 244 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 245 | */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{21} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{20} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{19} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{18} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{17} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{16} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{15} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{14} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{13} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{12} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{11} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{10} \f$ WDT2 CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 262 | /**@} end of group WDT2_CTRL_RST_PERIOD_Value */ |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | /** |
AnnaBridge | 171:3a7713b1edbc | 265 | * @ingroup WDT2_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 266 | * @defgroup WDT2_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 267 | * @brief Shifted values for the \ref WDT2_CTRL_RST_PERIOD_Value |
AnnaBridge | 171:3a7713b1edbc | 268 | * @details These values are shifted to align with the field's location in the WDT2_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 269 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 274 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 287 | /**@} end of group WDT2_CTRL_RST_PERIOD_Shifted */ |
AnnaBridge | 171:3a7713b1edbc | 288 | /** |
AnnaBridge | 171:3a7713b1edbc | 289 | * @ingroup WDT2_LOCK_CTRL_Register |
AnnaBridge | 171:3a7713b1edbc | 290 | * @defgroup WDT2_LOCK_field_values Watchdog Timer WDT2_LOCK field values |
AnnaBridge | 171:3a7713b1edbc | 291 | * @brief Lock/Unlock values for the watchdog timer \ref WDT2_CTRL_Register. |
AnnaBridge | 171:3a7713b1edbc | 292 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 293 | */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define MXC_V_WDT2_LOCK_KEY 0x24 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b locks the \ref WDT2_CTRL_Register making it read only. */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define MXC_V_WDT2_UNLOCK_KEY 0x42 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b unlocks the \ref WDT2_CTRL_Register making it read/write. */ |
AnnaBridge | 171:3a7713b1edbc | 296 | /**@} end of group WDT2_LOCK_field_values */ |
AnnaBridge | 171:3a7713b1edbc | 297 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @internal |
AnnaBridge | 171:3a7713b1edbc | 300 | * @ingroup WDT2_CLEAR_Register |
AnnaBridge | 171:3a7713b1edbc | 301 | * @defgroup WDT2_CLEAR_field_values Watchdog Timer Clear Sequence Values |
AnnaBridge | 171:3a7713b1edbc | 302 | * @brief Writing the sequence of #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 to the \ref WDT2_CLEAR_Register will clear/reset the watchdog timer count. |
AnnaBridge | 171:3a7713b1edbc | 303 | * @note The values #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 must be written sequentially to the \ref WDT2_CLEAR_Register to clear the watchdog counter. |
AnnaBridge | 171:3a7713b1edbc | 304 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 305 | */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define MXC_V_WDT2_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define MXC_V_WDT2_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */ |
AnnaBridge | 171:3a7713b1edbc | 308 | /** |
AnnaBridge | 171:3a7713b1edbc | 309 | * @} end of group WDT2_CLEAR_field_values |
AnnaBridge | 171:3a7713b1edbc | 310 | * @endinternal |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 313 | /**@} wdt2_registers*/ |
AnnaBridge | 171:3a7713b1edbc | 314 | |
AnnaBridge | 171:3a7713b1edbc | 315 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 316 | } |
AnnaBridge | 171:3a7713b1edbc | 317 | #endif |
AnnaBridge | 171:3a7713b1edbc | 318 | |
AnnaBridge | 171:3a7713b1edbc | 319 | #endif /* _MXC_WDT2_REGS_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 320 |