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TARGET_MAX32600MBED/TOOLCHAIN_IAR/tmr_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_TMR_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_TMR_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file tmr_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup tmr TMR
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines timer modes for 16 and 32-bit timers
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** 32-bit or 16-bit timer one-shot mode */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_TMR_MODE_ONE_SHOT = 0,
AnnaBridge 171:3a7713b1edbc 55 /** 32-bit or 16-bit timer one-shot mode */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_TMR_MODE_CONTINUOUS,
AnnaBridge 171:3a7713b1edbc 57 /** 32-bit timer counter mode */
AnnaBridge 171:3a7713b1edbc 58 MXC_E_TMR_MODE_COUNTER,
AnnaBridge 171:3a7713b1edbc 59 /** 32-bit timer pulse width modulation mode */
AnnaBridge 171:3a7713b1edbc 60 MXC_E_TMR_MODE_PWM,
AnnaBridge 171:3a7713b1edbc 61 /** 32-bit timer capture mode */
AnnaBridge 171:3a7713b1edbc 62 MXC_E_TMR_MODE_CAPTURE,
AnnaBridge 171:3a7713b1edbc 63 /** 32-bit timer compare mode */
AnnaBridge 171:3a7713b1edbc 64 MXC_E_TMR_MODE_COMPARE,
AnnaBridge 171:3a7713b1edbc 65 /** 32-bit timer gated mode */
AnnaBridge 171:3a7713b1edbc 66 MXC_E_TMR_MODE_GATED,
AnnaBridge 171:3a7713b1edbc 67 /** 32-bit timer measure mode */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_TMR_MODE_MEASURE
AnnaBridge 171:3a7713b1edbc 69 } mxc_tmr_mode_t;
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 72 ====== ============================================== */
AnnaBridge 171:3a7713b1edbc 73 typedef struct {
AnnaBridge 171:3a7713b1edbc 74 __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */
AnnaBridge 171:3a7713b1edbc 76 __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */
AnnaBridge 171:3a7713b1edbc 77 __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */
AnnaBridge 171:3a7713b1edbc 78 __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */
AnnaBridge 171:3a7713b1edbc 80 __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */
AnnaBridge 171:3a7713b1edbc 81 __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */
AnnaBridge 171:3a7713b1edbc 84 } mxc_tmr_regs_t;
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /*
AnnaBridge 171:3a7713b1edbc 87 Register offsets for module TMR.
AnnaBridge 171:3a7713b1edbc 88 */
AnnaBridge 171:3a7713b1edbc 89 #define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 90 #define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 91 #define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 92 #define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 93 #define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 94 #define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 95 #define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 96 #define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
AnnaBridge 171:3a7713b1edbc 97 #define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
AnnaBridge 171:3a7713b1edbc 98 #define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /*
AnnaBridge 171:3a7713b1edbc 101 Field positions and masks for module TMR.
AnnaBridge 171:3a7713b1edbc 102 */
AnnaBridge 171:3a7713b1edbc 103 #define MXC_F_TMR_CTRL_MODE_POS 0
AnnaBridge 171:3a7713b1edbc 104 #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 171:3a7713b1edbc 105 #define MXC_F_TMR_CTRL_TMR2X16_POS 3
AnnaBridge 171:3a7713b1edbc 106 #define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
AnnaBridge 171:3a7713b1edbc 107 #define MXC_F_TMR_CTRL_PRESCALE_POS 4
AnnaBridge 171:3a7713b1edbc 108 #define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_TMR_CTRL_POLARITY_POS 8
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_TMR_CTRL_ENABLE0_POS 12
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_TMR_CTRL_ENABLE1_POS 13
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_TMR_COUNT16_0_VALUE_POS 0
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_TMR_COUNT16_1_VALUE_POS 0
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_TMR_INTFL_TIMER0_POS 0
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_TMR_INTFL_TIMER1_POS 1
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_TMR_INTEN_TIMER0_POS 0
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_TMR_INTEN_TIMER1_POS 1
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 139 }
AnnaBridge 171:3a7713b1edbc 140 #endif
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 /**
AnnaBridge 171:3a7713b1edbc 143 * @}
AnnaBridge 171:3a7713b1edbc 144 */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 #endif /* _MXC_TMR_REGS_H */