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TARGET_MAX32600MBED/TOOLCHAIN_IAR/gpio_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_GPIO_REGS_H_
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_GPIO_REGS_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file gpio_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup gpio GPIO
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 50 ============= ========================================== */
AnnaBridge 171:3a7713b1edbc 51 typedef struct {
AnnaBridge 171:3a7713b1edbc 52 __I uint32_t rsv000[16]; /* 0x0000-0x003C */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */
AnnaBridge 171:3a7713b1edbc 55 __I uint32_t rsv060[8]; /* 0x0060-0x007C */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */
AnnaBridge 171:3a7713b1edbc 58 __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */
AnnaBridge 171:3a7713b1edbc 61 __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */
AnnaBridge 171:3a7713b1edbc 64 __I uint32_t rsv120[8]; /* 0x0120-0x013C */
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */
AnnaBridge 171:3a7713b1edbc 67 __I uint32_t rsv160[8]; /* 0x0160-0x017C */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */
AnnaBridge 171:3a7713b1edbc 70 __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */
AnnaBridge 171:3a7713b1edbc 73 __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 76 __I uint32_t rsv220[8]; /* 0x0220-0x023C */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */
AnnaBridge 171:3a7713b1edbc 79 } mxc_gpio_regs_t;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /*
AnnaBridge 171:3a7713b1edbc 82 Register offsets for module GPIO.
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84 #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
AnnaBridge 171:3a7713b1edbc 85 #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
AnnaBridge 171:3a7713b1edbc 86 #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
AnnaBridge 171:3a7713b1edbc 87 #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
AnnaBridge 171:3a7713b1edbc 88 #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
AnnaBridge 171:3a7713b1edbc 89 #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
AnnaBridge 171:3a7713b1edbc 90 #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
AnnaBridge 171:3a7713b1edbc 91 #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL)
AnnaBridge 171:3a7713b1edbc 92 #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
AnnaBridge 171:3a7713b1edbc 93 #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
AnnaBridge 171:3a7713b1edbc 94 #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
AnnaBridge 171:3a7713b1edbc 95 #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
AnnaBridge 171:3a7713b1edbc 96 #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
AnnaBridge 171:3a7713b1edbc 97 #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
AnnaBridge 171:3a7713b1edbc 98 #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
AnnaBridge 171:3a7713b1edbc 99 #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL)
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
AnnaBridge 171:3a7713b1edbc 105 #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
AnnaBridge 171:3a7713b1edbc 106 #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
AnnaBridge 171:3a7713b1edbc 107 #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL)
AnnaBridge 171:3a7713b1edbc 108 #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
AnnaBridge 171:3a7713b1edbc 109 #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
AnnaBridge 171:3a7713b1edbc 110 #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
AnnaBridge 171:3a7713b1edbc 111 #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
AnnaBridge 171:3a7713b1edbc 112 #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL)
AnnaBridge 171:3a7713b1edbc 113 #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
AnnaBridge 171:3a7713b1edbc 114 #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
AnnaBridge 171:3a7713b1edbc 115 #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
AnnaBridge 171:3a7713b1edbc 116 #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL)
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
AnnaBridge 171:3a7713b1edbc 124 #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
AnnaBridge 171:3a7713b1edbc 125 #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
AnnaBridge 171:3a7713b1edbc 126 #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
AnnaBridge 171:3a7713b1edbc 127 #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
AnnaBridge 171:3a7713b1edbc 128 #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL)
AnnaBridge 171:3a7713b1edbc 129 #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
AnnaBridge 171:3a7713b1edbc 130 #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
AnnaBridge 171:3a7713b1edbc 131 #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
AnnaBridge 171:3a7713b1edbc 132 #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
AnnaBridge 171:3a7713b1edbc 133 #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
AnnaBridge 171:3a7713b1edbc 134 #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
AnnaBridge 171:3a7713b1edbc 135 #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
AnnaBridge 171:3a7713b1edbc 136 #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL)
AnnaBridge 171:3a7713b1edbc 137 #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
AnnaBridge 171:3a7713b1edbc 138 #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
AnnaBridge 171:3a7713b1edbc 139 #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
AnnaBridge 171:3a7713b1edbc 140 #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
AnnaBridge 171:3a7713b1edbc 141 #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
AnnaBridge 171:3a7713b1edbc 142 #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
AnnaBridge 171:3a7713b1edbc 143 #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
AnnaBridge 171:3a7713b1edbc 144 #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL)
AnnaBridge 171:3a7713b1edbc 145 #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
AnnaBridge 171:3a7713b1edbc 146 #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
AnnaBridge 171:3a7713b1edbc 147 #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
AnnaBridge 171:3a7713b1edbc 148 #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
AnnaBridge 171:3a7713b1edbc 149 #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
AnnaBridge 171:3a7713b1edbc 150 #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
AnnaBridge 171:3a7713b1edbc 151 #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
AnnaBridge 171:3a7713b1edbc 152 #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL)
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*
AnnaBridge 171:3a7713b1edbc 156 Field positions and masks for module GPIO.
AnnaBridge 171:3a7713b1edbc 157 */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_GPIO_FREE_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_GPIO_FREE_PIN1_POS 1
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_GPIO_FREE_PIN2_POS 2
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_GPIO_FREE_PIN3_POS 3
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_GPIO_FREE_PIN4_POS 4
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_GPIO_FREE_PIN5_POS 5
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_GPIO_FREE_PIN6_POS 6
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_GPIO_FREE_PIN7_POS 7
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_GPIO_IN_MODE_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_GPIO_IN_MODE_PIN1_POS 4
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_GPIO_IN_MODE_PIN2_POS 8
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_GPIO_IN_MODE_PIN3_POS 12
AnnaBridge 171:3a7713b1edbc 233 #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 234 #define MXC_F_GPIO_IN_MODE_PIN4_POS 16
AnnaBridge 171:3a7713b1edbc 235 #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 236 #define MXC_F_GPIO_IN_MODE_PIN5_POS 20
AnnaBridge 171:3a7713b1edbc 237 #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 238 #define MXC_F_GPIO_IN_MODE_PIN6_POS 24
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_GPIO_IN_MODE_PIN7_POS 28
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_GPIO_IN_VAL_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_GPIO_IN_VAL_PIN1_POS 1
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_GPIO_IN_VAL_PIN2_POS 2
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 249 #define MXC_F_GPIO_IN_VAL_PIN3_POS 3
AnnaBridge 171:3a7713b1edbc 250 #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 251 #define MXC_F_GPIO_IN_VAL_PIN4_POS 4
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 253 #define MXC_F_GPIO_IN_VAL_PIN5_POS 5
AnnaBridge 171:3a7713b1edbc 254 #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_GPIO_IN_VAL_PIN6_POS 6
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_GPIO_IN_VAL_PIN7_POS 7
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_GPIO_INT_MODE_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_GPIO_INT_MODE_PIN1_POS 4
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_GPIO_INT_MODE_PIN2_POS 8
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_GPIO_INT_MODE_PIN3_POS 12
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_GPIO_INT_MODE_PIN4_POS 16
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_GPIO_INT_MODE_PIN5_POS 20
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_GPIO_INT_MODE_PIN6_POS 24
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_GPIO_INT_MODE_PIN7_POS 28
AnnaBridge 171:3a7713b1edbc 275 #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_GPIO_INTFL_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_GPIO_INTFL_PIN1_POS 1
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_GPIO_INTFL_PIN2_POS 2
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_GPIO_INTFL_PIN3_POS 3
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_GPIO_INTFL_PIN4_POS 4
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_GPIO_INTFL_PIN5_POS 5
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_GPIO_INTFL_PIN6_POS 6
AnnaBridge 171:3a7713b1edbc 290 #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_GPIO_INTFL_PIN7_POS 7
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_GPIO_INTEN_PIN0_POS 0
AnnaBridge 171:3a7713b1edbc 295 #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 296 #define MXC_F_GPIO_INTEN_PIN1_POS 1
AnnaBridge 171:3a7713b1edbc 297 #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 298 #define MXC_F_GPIO_INTEN_PIN2_POS 2
AnnaBridge 171:3a7713b1edbc 299 #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 300 #define MXC_F_GPIO_INTEN_PIN3_POS 3
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_GPIO_INTEN_PIN4_POS 4
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_GPIO_INTEN_PIN5_POS 5
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_GPIO_INTEN_PIN6_POS 6
AnnaBridge 171:3a7713b1edbc 307 #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 308 #define MXC_F_GPIO_INTEN_PIN7_POS 7
AnnaBridge 171:3a7713b1edbc 309 #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311
AnnaBridge 171:3a7713b1edbc 312 /*
AnnaBridge 171:3a7713b1edbc 313 Field values and shifted values for module GPIO.
AnnaBridge 171:3a7713b1edbc 314 */
AnnaBridge 171:3a7713b1edbc 315 #define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 316 #define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 #define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 319 #define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 #define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 322 #define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 #define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 325 #define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 #define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 328 #define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 #define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 331 #define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 #define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 334 #define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 #define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 337 #define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 338
AnnaBridge 171:3a7713b1edbc 339 #define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 340 #define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 #define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 343 #define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 344
AnnaBridge 171:3a7713b1edbc 345 #define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 346 #define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 #define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 349 #define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 #define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 352 #define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 355 #define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 #define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
AnnaBridge 171:3a7713b1edbc 358 #define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL))
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 #define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 361 #define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
AnnaBridge 171:3a7713b1edbc 364 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
AnnaBridge 171:3a7713b1edbc 365 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
AnnaBridge 171:3a7713b1edbc 366 #define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL))
AnnaBridge 171:3a7713b1edbc 367 #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
AnnaBridge 171:3a7713b1edbc 368 #define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL))
AnnaBridge 171:3a7713b1edbc 369 #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
AnnaBridge 171:3a7713b1edbc 370 #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
AnnaBridge 171:3a7713b1edbc 371 #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
AnnaBridge 171:3a7713b1edbc 372 #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 #define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 375 #define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 376 #define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 377 #define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 378 #define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 379 #define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 380 #define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 381 #define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 382 #define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 383 #define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 #define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 386 #define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 387 #define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 388 #define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 389 #define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 390 #define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 391 #define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 392 #define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 393 #define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 394 #define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 #define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 397 #define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 398 #define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 399 #define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 400 #define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 401 #define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 402 #define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 403 #define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 404 #define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 405 #define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 408 #define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 409 #define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 410 #define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 411 #define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 412 #define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 413 #define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 414 #define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 415 #define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 416 #define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 #define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 419 #define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 420 #define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 421 #define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 422 #define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 423 #define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 424 #define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 425 #define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 426 #define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 427 #define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 #define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 430 #define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 431 #define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 432 #define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 433 #define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 434 #define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 435 #define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 436 #define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 437 #define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 438 #define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 441 #define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 442 #define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 443 #define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 444 #define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 445 #define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 446 #define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 447 #define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 448 #define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 449 #define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 #define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 452 #define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 453 #define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 454 #define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 455 #define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 456 #define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 457 #define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 458 #define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 459 #define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 460 #define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL))
AnnaBridge 171:3a7713b1edbc 463 #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
AnnaBridge 171:3a7713b1edbc 464 #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
AnnaBridge 171:3a7713b1edbc 465 #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL))
AnnaBridge 171:3a7713b1edbc 466 #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL))
AnnaBridge 171:3a7713b1edbc 467 #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL))
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 470 }
AnnaBridge 171:3a7713b1edbc 471 #endif
AnnaBridge 171:3a7713b1edbc 472
AnnaBridge 171:3a7713b1edbc 473 /**
AnnaBridge 171:3a7713b1edbc 474 * @}
AnnaBridge 171:3a7713b1edbc 475 */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 #endif /* _MXC_GPIO_REGS_H_ */