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TARGET_LPC1347/TOOLCHAIN_ARM_STD/LPC13Uxx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1
AnnaBridge 171:3a7713b1edbc 2 /****************************************************************************************************//**
AnnaBridge 171:3a7713b1edbc 3 * @file LPC13Uxx.h
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
AnnaBridge 171:3a7713b1edbc 8 * default LPC13Uxx Device Series
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * @version V0.1
AnnaBridge 171:3a7713b1edbc 11 * @date 18. Jan 2012
AnnaBridge 171:3a7713b1edbc 12 *
AnnaBridge 171:3a7713b1edbc 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
AnnaBridge 171:3a7713b1edbc 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 *******************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 /** @addtogroup NXP
AnnaBridge 171:3a7713b1edbc 21 * @{
AnnaBridge 171:3a7713b1edbc 22 */
AnnaBridge 171:3a7713b1edbc 23
AnnaBridge 171:3a7713b1edbc 24 /** @addtogroup LPC13Uxx
AnnaBridge 171:3a7713b1edbc 25 * @{
AnnaBridge 171:3a7713b1edbc 26 */
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 #ifndef __LPC13UXX_H__
AnnaBridge 171:3a7713b1edbc 29 #define __LPC13UXX_H__
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 32 extern "C" {
AnnaBridge 171:3a7713b1edbc 33 #endif
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 37 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 38 #endif
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /* Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 typedef enum {
AnnaBridge 171:3a7713b1edbc 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
AnnaBridge 171:3a7713b1edbc 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge 171:3a7713b1edbc 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
AnnaBridge 171:3a7713b1edbc 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
AnnaBridge 171:3a7713b1edbc 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
AnnaBridge 171:3a7713b1edbc 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
AnnaBridge 171:3a7713b1edbc 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
AnnaBridge 171:3a7713b1edbc 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
AnnaBridge 171:3a7713b1edbc 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
AnnaBridge 171:3a7713b1edbc 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
AnnaBridge 171:3a7713b1edbc 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
AnnaBridge 171:3a7713b1edbc 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
AnnaBridge 171:3a7713b1edbc 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
AnnaBridge 171:3a7713b1edbc 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
AnnaBridge 171:3a7713b1edbc 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
AnnaBridge 171:3a7713b1edbc 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
AnnaBridge 171:3a7713b1edbc 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
AnnaBridge 171:3a7713b1edbc 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
AnnaBridge 171:3a7713b1edbc 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
AnnaBridge 171:3a7713b1edbc 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
AnnaBridge 171:3a7713b1edbc 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
AnnaBridge 171:3a7713b1edbc 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
AnnaBridge 171:3a7713b1edbc 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
AnnaBridge 171:3a7713b1edbc 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
AnnaBridge 171:3a7713b1edbc 70 I2C_IRQn = 15, /*!< 15 I2C */
AnnaBridge 171:3a7713b1edbc 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
AnnaBridge 171:3a7713b1edbc 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
AnnaBridge 171:3a7713b1edbc 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
AnnaBridge 171:3a7713b1edbc 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
AnnaBridge 171:3a7713b1edbc 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
AnnaBridge 171:3a7713b1edbc 76 USART_IRQn = 21, /*!< 21 USART */
AnnaBridge 171:3a7713b1edbc 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
AnnaBridge 171:3a7713b1edbc 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
AnnaBridge 171:3a7713b1edbc 79 ADC_IRQn = 24, /*!< 24 ADC */
AnnaBridge 171:3a7713b1edbc 80 WDT_IRQn = 25, /*!< 25 WDT */
AnnaBridge 171:3a7713b1edbc 81 BOD_IRQn = 26, /*!< 26 BOD */
AnnaBridge 171:3a7713b1edbc 82 FMC_IRQn = 27, /*!< 27 FMC */
AnnaBridge 171:3a7713b1edbc 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
AnnaBridge 171:3a7713b1edbc 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 87 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /** @addtogroup Configuration_of_CMSIS
AnnaBridge 171:3a7713b1edbc 91 * @{
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
AnnaBridge 171:3a7713b1edbc 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 100 /** @} */ /* End of group Configuration_of_CMSIS */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /** @addtogroup Device_Peripheral_Registers
AnnaBridge 171:3a7713b1edbc 106 * @{
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 111 // ----- I2C -----
AnnaBridge 171:3a7713b1edbc 112 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
AnnaBridge 171:3a7713b1edbc 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
AnnaBridge 171:3a7713b1edbc 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
AnnaBridge 171:3a7713b1edbc 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
AnnaBridge 171:3a7713b1edbc 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge 171:3a7713b1edbc 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
AnnaBridge 171:3a7713b1edbc 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
AnnaBridge 171:3a7713b1edbc 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
AnnaBridge 171:3a7713b1edbc 125 union{
AnnaBridge 171:3a7713b1edbc 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge 171:3a7713b1edbc 127 struct{
AnnaBridge 171:3a7713b1edbc 128 __IO uint32_t ADR1;
AnnaBridge 171:3a7713b1edbc 129 __IO uint32_t ADR2;
AnnaBridge 171:3a7713b1edbc 130 __IO uint32_t ADR3;
AnnaBridge 171:3a7713b1edbc 131 };
AnnaBridge 171:3a7713b1edbc 132 };
AnnaBridge 171:3a7713b1edbc 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
AnnaBridge 171:3a7713b1edbc 134 union{
AnnaBridge 171:3a7713b1edbc 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
AnnaBridge 171:3a7713b1edbc 136 struct{
AnnaBridge 171:3a7713b1edbc 137 __IO uint32_t MASK0;
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t MASK1;
AnnaBridge 171:3a7713b1edbc 139 __IO uint32_t MASK2;
AnnaBridge 171:3a7713b1edbc 140 __IO uint32_t MASK3;
AnnaBridge 171:3a7713b1edbc 141 };
AnnaBridge 171:3a7713b1edbc 142 };
AnnaBridge 171:3a7713b1edbc 143 } LPC_I2C_Type;
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 147 // ----- WWDT -----
AnnaBridge 171:3a7713b1edbc 148 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
AnnaBridge 171:3a7713b1edbc 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
AnnaBridge 171:3a7713b1edbc 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
AnnaBridge 171:3a7713b1edbc 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
AnnaBridge 171:3a7713b1edbc 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
AnnaBridge 171:3a7713b1edbc 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
AnnaBridge 171:3a7713b1edbc 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
AnnaBridge 171:3a7713b1edbc 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
AnnaBridge 171:3a7713b1edbc 159 } LPC_WWDT_Type;
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 163 // ----- USART -----
AnnaBridge 171:3a7713b1edbc 164 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 union {
AnnaBridge 171:3a7713b1edbc 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
AnnaBridge 171:3a7713b1edbc 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
AnnaBridge 171:3a7713b1edbc 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
AnnaBridge 171:3a7713b1edbc 173 };
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 union {
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
AnnaBridge 171:3a7713b1edbc 178 };
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 union {
AnnaBridge 171:3a7713b1edbc 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
AnnaBridge 171:3a7713b1edbc 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
AnnaBridge 171:3a7713b1edbc 183 };
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
AnnaBridge 171:3a7713b1edbc 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
AnnaBridge 171:3a7713b1edbc 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
AnnaBridge 171:3a7713b1edbc 194 __I uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
AnnaBridge 171:3a7713b1edbc 196 __I uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
AnnaBridge 171:3a7713b1edbc 202 } LPC_USART_Type;
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 206 // ----- CT16B0 -----
AnnaBridge 171:3a7713b1edbc 207 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge 171:3a7713b1edbc 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge 171:3a7713b1edbc 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge 171:3a7713b1edbc 216 union {
AnnaBridge 171:3a7713b1edbc 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge 171:3a7713b1edbc 218 struct{
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
AnnaBridge 171:3a7713b1edbc 223 };
AnnaBridge 171:3a7713b1edbc 224 };
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge 171:3a7713b1edbc 226 union{
AnnaBridge 171:3a7713b1edbc 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
AnnaBridge 171:3a7713b1edbc 228 struct{
AnnaBridge 171:3a7713b1edbc 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
AnnaBridge 171:3a7713b1edbc 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
AnnaBridge 171:3a7713b1edbc 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
AnnaBridge 171:3a7713b1edbc 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
AnnaBridge 171:3a7713b1edbc 233 };
AnnaBridge 171:3a7713b1edbc 234 };
AnnaBridge 171:3a7713b1edbc 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
AnnaBridge 171:3a7713b1edbc 236 __I uint32_t RESERVED0[12];
AnnaBridge 171:3a7713b1edbc 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge 171:3a7713b1edbc 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
AnnaBridge 171:3a7713b1edbc 239 } LPC_CTxxBx_Type;
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge 171:3a7713b1edbc 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge 171:3a7713b1edbc 248 union {
AnnaBridge 171:3a7713b1edbc 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge 171:3a7713b1edbc 250 struct{
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
AnnaBridge 171:3a7713b1edbc 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
AnnaBridge 171:3a7713b1edbc 255 };
AnnaBridge 171:3a7713b1edbc 256 };
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge 171:3a7713b1edbc 258 union{
AnnaBridge 171:3a7713b1edbc 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
AnnaBridge 171:3a7713b1edbc 260 struct{
AnnaBridge 171:3a7713b1edbc 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
AnnaBridge 171:3a7713b1edbc 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
AnnaBridge 171:3a7713b1edbc 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
AnnaBridge 171:3a7713b1edbc 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
AnnaBridge 171:3a7713b1edbc 265 };
AnnaBridge 171:3a7713b1edbc 266 };
AnnaBridge 171:3a7713b1edbc 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
AnnaBridge 171:3a7713b1edbc 268 __I uint32_t RESERVED0[12];
AnnaBridge 171:3a7713b1edbc 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
AnnaBridge 171:3a7713b1edbc 271 } LPC_CT16B0_Type;
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 275 // ----- CT16B1 -----
AnnaBridge 171:3a7713b1edbc 276 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge 171:3a7713b1edbc 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge 171:3a7713b1edbc 285 union {
AnnaBridge 171:3a7713b1edbc 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge 171:3a7713b1edbc 287 struct{
AnnaBridge 171:3a7713b1edbc 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
AnnaBridge 171:3a7713b1edbc 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
AnnaBridge 171:3a7713b1edbc 292 };
AnnaBridge 171:3a7713b1edbc 293 };
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge 171:3a7713b1edbc 295 union{
AnnaBridge 171:3a7713b1edbc 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
AnnaBridge 171:3a7713b1edbc 297 struct{
AnnaBridge 171:3a7713b1edbc 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
AnnaBridge 171:3a7713b1edbc 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
AnnaBridge 171:3a7713b1edbc 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
AnnaBridge 171:3a7713b1edbc 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
AnnaBridge 171:3a7713b1edbc 302 };
AnnaBridge 171:3a7713b1edbc 303 };
AnnaBridge 171:3a7713b1edbc 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
AnnaBridge 171:3a7713b1edbc 305 __I uint32_t RESERVED0[12];
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
AnnaBridge 171:3a7713b1edbc 308 } LPC_CT16B1_Type;
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 312 // ----- CT32B0 -----
AnnaBridge 171:3a7713b1edbc 313 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge 171:3a7713b1edbc 321 union {
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge 171:3a7713b1edbc 323 struct{
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
AnnaBridge 171:3a7713b1edbc 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
AnnaBridge 171:3a7713b1edbc 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
AnnaBridge 171:3a7713b1edbc 328 };
AnnaBridge 171:3a7713b1edbc 329 };
AnnaBridge 171:3a7713b1edbc 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge 171:3a7713b1edbc 331 union{
AnnaBridge 171:3a7713b1edbc 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
AnnaBridge 171:3a7713b1edbc 333 struct{
AnnaBridge 171:3a7713b1edbc 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
AnnaBridge 171:3a7713b1edbc 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
AnnaBridge 171:3a7713b1edbc 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
AnnaBridge 171:3a7713b1edbc 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
AnnaBridge 171:3a7713b1edbc 338 };
AnnaBridge 171:3a7713b1edbc 339 };
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
AnnaBridge 171:3a7713b1edbc 341 __I uint32_t RESERVED0[12];
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
AnnaBridge 171:3a7713b1edbc 344 } LPC_CT32B0_Type;
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 348 // ----- CT32B1 -----
AnnaBridge 171:3a7713b1edbc 349 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge 171:3a7713b1edbc 357 union {
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge 171:3a7713b1edbc 359 struct{
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
AnnaBridge 171:3a7713b1edbc 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
AnnaBridge 171:3a7713b1edbc 364 };
AnnaBridge 171:3a7713b1edbc 365 };
AnnaBridge 171:3a7713b1edbc 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge 171:3a7713b1edbc 367 union{
AnnaBridge 171:3a7713b1edbc 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
AnnaBridge 171:3a7713b1edbc 369 struct{
AnnaBridge 171:3a7713b1edbc 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
AnnaBridge 171:3a7713b1edbc 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
AnnaBridge 171:3a7713b1edbc 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
AnnaBridge 171:3a7713b1edbc 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
AnnaBridge 171:3a7713b1edbc 374 };
AnnaBridge 171:3a7713b1edbc 375 };
AnnaBridge 171:3a7713b1edbc 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
AnnaBridge 171:3a7713b1edbc 377 __I uint32_t RESERVED0[12];
AnnaBridge 171:3a7713b1edbc 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
AnnaBridge 171:3a7713b1edbc 380 } LPC_CT32B1_Type;
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 384 // ----- ADC -----
AnnaBridge 171:3a7713b1edbc 385 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
AnnaBridge 171:3a7713b1edbc 389 __I uint32_t RESERVED0[1];
AnnaBridge 171:3a7713b1edbc 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
AnnaBridge 171:3a7713b1edbc 391 union{
AnnaBridge 171:3a7713b1edbc 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
AnnaBridge 171:3a7713b1edbc 393 struct{
AnnaBridge 171:3a7713b1edbc 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
AnnaBridge 171:3a7713b1edbc 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
AnnaBridge 171:3a7713b1edbc 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
AnnaBridge 171:3a7713b1edbc 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
AnnaBridge 171:3a7713b1edbc 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
AnnaBridge 171:3a7713b1edbc 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
AnnaBridge 171:3a7713b1edbc 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
AnnaBridge 171:3a7713b1edbc 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
AnnaBridge 171:3a7713b1edbc 402 };
AnnaBridge 171:3a7713b1edbc 403 };
AnnaBridge 171:3a7713b1edbc 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
AnnaBridge 171:3a7713b1edbc 405 } LPC_ADC_Type;
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 409 // ----- PMU -----
AnnaBridge 171:3a7713b1edbc 410 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
AnnaBridge 171:3a7713b1edbc 414 union{
AnnaBridge 171:3a7713b1edbc 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
AnnaBridge 171:3a7713b1edbc 416 struct{
AnnaBridge 171:3a7713b1edbc 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
AnnaBridge 171:3a7713b1edbc 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
AnnaBridge 171:3a7713b1edbc 421 };
AnnaBridge 171:3a7713b1edbc 422 };
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
AnnaBridge 171:3a7713b1edbc 424 } LPC_PMU_Type;
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 428 // ----- FLASHCTRL -----
AnnaBridge 171:3a7713b1edbc 429 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
AnnaBridge 171:3a7713b1edbc 432 __I uint32_t RESERVED0[4];
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
AnnaBridge 171:3a7713b1edbc 434 __I uint32_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
AnnaBridge 171:3a7713b1edbc 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
AnnaBridge 171:3a7713b1edbc 437 __I uint32_t RESERVED2[1];
AnnaBridge 171:3a7713b1edbc 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
AnnaBridge 171:3a7713b1edbc 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
AnnaBridge 171:3a7713b1edbc 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
AnnaBridge 171:3a7713b1edbc 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
AnnaBridge 171:3a7713b1edbc 442 __I uint32_t RESERVED3[1001];
AnnaBridge 171:3a7713b1edbc 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
AnnaBridge 171:3a7713b1edbc 444 __I uint32_t RESERVED4[1];
AnnaBridge 171:3a7713b1edbc 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
AnnaBridge 171:3a7713b1edbc 446 } LPC_FLASHCTRL_Type;
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 450 // ----- SSP -----
AnnaBridge 171:3a7713b1edbc 451 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
AnnaBridge 171:3a7713b1edbc 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
AnnaBridge 171:3a7713b1edbc 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 462 } LPC_SSPx_Type;
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 466 // ----- IOCON -----
AnnaBridge 171:3a7713b1edbc 467 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
AnnaBridge 171:3a7713b1edbc 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
AnnaBridge 171:3a7713b1edbc 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
AnnaBridge 171:3a7713b1edbc 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
AnnaBridge 171:3a7713b1edbc 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
AnnaBridge 171:3a7713b1edbc 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
AnnaBridge 171:3a7713b1edbc 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
AnnaBridge 171:3a7713b1edbc 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
AnnaBridge 171:3a7713b1edbc 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
AnnaBridge 171:3a7713b1edbc 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
AnnaBridge 171:3a7713b1edbc 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
AnnaBridge 171:3a7713b1edbc 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
AnnaBridge 171:3a7713b1edbc 525 } LPC_IOCON_Type;
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 529 // ----- SYSCON -----
AnnaBridge 171:3a7713b1edbc 530 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
AnnaBridge 171:3a7713b1edbc 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
AnnaBridge 171:3a7713b1edbc 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
AnnaBridge 171:3a7713b1edbc 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
AnnaBridge 171:3a7713b1edbc 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
AnnaBridge 171:3a7713b1edbc 539 __I uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
AnnaBridge 171:3a7713b1edbc 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
AnnaBridge 171:3a7713b1edbc 542 __I uint32_t RESERVED1[2];
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
AnnaBridge 171:3a7713b1edbc 544 __I uint32_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
AnnaBridge 171:3a7713b1edbc 546 __I uint32_t RESERVED3;
AnnaBridge 171:3a7713b1edbc 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
AnnaBridge 171:3a7713b1edbc 548 __I uint32_t RESERVED4[9];
AnnaBridge 171:3a7713b1edbc 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
AnnaBridge 171:3a7713b1edbc 550 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
AnnaBridge 171:3a7713b1edbc 552 __I uint32_t RESERVED6;
AnnaBridge 171:3a7713b1edbc 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
AnnaBridge 171:3a7713b1edbc 554 __I uint32_t RESERVED7[4];
AnnaBridge 171:3a7713b1edbc 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
AnnaBridge 171:3a7713b1edbc 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
AnnaBridge 171:3a7713b1edbc 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
AnnaBridge 171:3a7713b1edbc 558 __I uint32_t RESERVED8[3];
AnnaBridge 171:3a7713b1edbc 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
AnnaBridge 171:3a7713b1edbc 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
AnnaBridge 171:3a7713b1edbc 561 __I uint32_t RESERVED9[3];
AnnaBridge 171:3a7713b1edbc 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
AnnaBridge 171:3a7713b1edbc 563 __I uint32_t RESERVED10;
AnnaBridge 171:3a7713b1edbc 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
AnnaBridge 171:3a7713b1edbc 565 __I uint32_t RESERVED11[5];
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
AnnaBridge 171:3a7713b1edbc 567 __I uint32_t RESERVED12;
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
AnnaBridge 171:3a7713b1edbc 569 __I uint32_t RESERVED13[5];
AnnaBridge 171:3a7713b1edbc 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
AnnaBridge 171:3a7713b1edbc 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
AnnaBridge 171:3a7713b1edbc 572 __I uint32_t RESERVED14[18];
AnnaBridge 171:3a7713b1edbc 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
AnnaBridge 171:3a7713b1edbc 575 __I uint32_t RESERVED15[6];
AnnaBridge 171:3a7713b1edbc 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
AnnaBridge 171:3a7713b1edbc 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
AnnaBridge 171:3a7713b1edbc 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
AnnaBridge 171:3a7713b1edbc 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
AnnaBridge 171:3a7713b1edbc 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
AnnaBridge 171:3a7713b1edbc 581 __I uint32_t RESERVED16[25];
AnnaBridge 171:3a7713b1edbc 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
AnnaBridge 171:3a7713b1edbc 583 __I uint32_t RESERVED17[3];
AnnaBridge 171:3a7713b1edbc 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
AnnaBridge 171:3a7713b1edbc 585 __I uint32_t RESERVED18[6];
AnnaBridge 171:3a7713b1edbc 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
AnnaBridge 171:3a7713b1edbc 589 __I uint32_t RESERVED19[111];
AnnaBridge 171:3a7713b1edbc 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
AnnaBridge 171:3a7713b1edbc 591 } LPC_SYSCON_Type;
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 595 // ----- GPIO_PIN_INT -----
AnnaBridge 171:3a7713b1edbc 596 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
AnnaBridge 171:3a7713b1edbc 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
AnnaBridge 171:3a7713b1edbc 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge 171:3a7713b1edbc 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge 171:3a7713b1edbc 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
AnnaBridge 171:3a7713b1edbc 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
AnnaBridge 171:3a7713b1edbc 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
AnnaBridge 171:3a7713b1edbc 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 608 } LPC_GPIO_PIN_INT_Type;
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 612 // ----- GPIO_GROUP_INT0 -----
AnnaBridge 171:3a7713b1edbc 613 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
AnnaBridge 171:3a7713b1edbc 616 __I uint32_t RESERVED0[7];
AnnaBridge 171:3a7713b1edbc 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
AnnaBridge 171:3a7713b1edbc 618 __I uint32_t RESERVED1[6];
AnnaBridge 171:3a7713b1edbc 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
AnnaBridge 171:3a7713b1edbc 620 } LPC_GPIO_GROUP_INT0_Type;
AnnaBridge 171:3a7713b1edbc 621
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 624 // ----- GPIO_GROUP_INT1 -----
AnnaBridge 171:3a7713b1edbc 625 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
AnnaBridge 171:3a7713b1edbc 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
AnnaBridge 171:3a7713b1edbc 629 __I uint32_t RESERVED0[7];
AnnaBridge 171:3a7713b1edbc 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
AnnaBridge 171:3a7713b1edbc 631 __I uint32_t RESERVED1[6];
AnnaBridge 171:3a7713b1edbc 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
AnnaBridge 171:3a7713b1edbc 633 } LPC_GPIO_GROUP_INT1_Type;
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 637 // ----- Repetitive Interrupt Timer (RIT) -----
AnnaBridge 171:3a7713b1edbc 638 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
AnnaBridge 171:3a7713b1edbc 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
AnnaBridge 171:3a7713b1edbc 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
AnnaBridge 171:3a7713b1edbc 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
AnnaBridge 171:3a7713b1edbc 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
AnnaBridge 171:3a7713b1edbc 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
AnnaBridge 171:3a7713b1edbc 647 __I uint32_t RESERVED0[1];
AnnaBridge 171:3a7713b1edbc 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
AnnaBridge 171:3a7713b1edbc 649 } LPC_RITIMER_Type;
AnnaBridge 171:3a7713b1edbc 650
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 653 // ----- USB -----
AnnaBridge 171:3a7713b1edbc 654 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
AnnaBridge 171:3a7713b1edbc 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
AnnaBridge 171:3a7713b1edbc 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
AnnaBridge 171:3a7713b1edbc 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
AnnaBridge 171:3a7713b1edbc 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
AnnaBridge 171:3a7713b1edbc 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
AnnaBridge 171:3a7713b1edbc 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
AnnaBridge 171:3a7713b1edbc 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
AnnaBridge 171:3a7713b1edbc 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
AnnaBridge 171:3a7713b1edbc 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
AnnaBridge 171:3a7713b1edbc 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
AnnaBridge 171:3a7713b1edbc 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
AnnaBridge 171:3a7713b1edbc 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
AnnaBridge 171:3a7713b1edbc 668 __I uint32_t RESERVED0[1];
AnnaBridge 171:3a7713b1edbc 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
AnnaBridge 171:3a7713b1edbc 670 } LPC_USB_Type;
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 674 // ----- GPIO_PORT -----
AnnaBridge 171:3a7713b1edbc 675 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
AnnaBridge 171:3a7713b1edbc 678 union {
AnnaBridge 171:3a7713b1edbc 679 struct {
AnnaBridge 171:3a7713b1edbc 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
AnnaBridge 171:3a7713b1edbc 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
AnnaBridge 171:3a7713b1edbc 682 };
AnnaBridge 171:3a7713b1edbc 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
AnnaBridge 171:3a7713b1edbc 684 };
AnnaBridge 171:3a7713b1edbc 685 __I uint32_t RESERVED0[1008];
AnnaBridge 171:3a7713b1edbc 686 union {
AnnaBridge 171:3a7713b1edbc 687 struct {
AnnaBridge 171:3a7713b1edbc 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
AnnaBridge 171:3a7713b1edbc 690 };
AnnaBridge 171:3a7713b1edbc 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
AnnaBridge 171:3a7713b1edbc 692 };
AnnaBridge 171:3a7713b1edbc 693 __I uint32_t RESERVED1[960];
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
AnnaBridge 171:3a7713b1edbc 695 __I uint32_t RESERVED2[30];
AnnaBridge 171:3a7713b1edbc 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
AnnaBridge 171:3a7713b1edbc 697 __I uint32_t RESERVED3[30];
AnnaBridge 171:3a7713b1edbc 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
AnnaBridge 171:3a7713b1edbc 699 __I uint32_t RESERVED4[30];
AnnaBridge 171:3a7713b1edbc 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
AnnaBridge 171:3a7713b1edbc 701 __I uint32_t RESERVED5[30];
AnnaBridge 171:3a7713b1edbc 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
AnnaBridge 171:3a7713b1edbc 703 __I uint32_t RESERVED6[30];
AnnaBridge 171:3a7713b1edbc 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
AnnaBridge 171:3a7713b1edbc 705 __I uint32_t RESERVED7[30];
AnnaBridge 171:3a7713b1edbc 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
AnnaBridge 171:3a7713b1edbc 707 } LPC_GPIO_Type;
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709
AnnaBridge 171:3a7713b1edbc 710 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 711 #pragma no_anon_unions
AnnaBridge 171:3a7713b1edbc 712 #endif
AnnaBridge 171:3a7713b1edbc 713
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 716 // ----- Peripheral memory map -----
AnnaBridge 171:3a7713b1edbc 717 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 718
AnnaBridge 171:3a7713b1edbc 719 #define LPC_I2C_BASE (0x40000000)
AnnaBridge 171:3a7713b1edbc 720 #define LPC_WWDT_BASE (0x40004000)
AnnaBridge 171:3a7713b1edbc 721 #define LPC_USART_BASE (0x40008000)
AnnaBridge 171:3a7713b1edbc 722 #define LPC_CT16B0_BASE (0x4000C000)
AnnaBridge 171:3a7713b1edbc 723 #define LPC_CT16B1_BASE (0x40010000)
AnnaBridge 171:3a7713b1edbc 724 #define LPC_CT32B0_BASE (0x40014000)
AnnaBridge 171:3a7713b1edbc 725 #define LPC_CT32B1_BASE (0x40018000)
AnnaBridge 171:3a7713b1edbc 726 #define LPC_ADC_BASE (0x4001C000)
AnnaBridge 171:3a7713b1edbc 727 #define LPC_PMU_BASE (0x40038000)
AnnaBridge 171:3a7713b1edbc 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
AnnaBridge 171:3a7713b1edbc 729 #define LPC_SSP0_BASE (0x40040000)
AnnaBridge 171:3a7713b1edbc 730 #define LPC_IOCON_BASE (0x40044000)
AnnaBridge 171:3a7713b1edbc 731 #define LPC_SYSCON_BASE (0x40048000)
AnnaBridge 171:3a7713b1edbc 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
AnnaBridge 171:3a7713b1edbc 733 #define LPC_SSP1_BASE (0x40058000)
AnnaBridge 171:3a7713b1edbc 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
AnnaBridge 171:3a7713b1edbc 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
AnnaBridge 171:3a7713b1edbc 736 #define LPC_RITIMER_BASE (0x40064000)
AnnaBridge 171:3a7713b1edbc 737 #define LPC_USB_BASE (0x40080000)
AnnaBridge 171:3a7713b1edbc 738 #define LPC_GPIO_BASE (0x50000000)
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740
AnnaBridge 171:3a7713b1edbc 741 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 742 // ----- Peripheral declaration -----
AnnaBridge 171:3a7713b1edbc 743 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
AnnaBridge 171:3a7713b1edbc 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
AnnaBridge 171:3a7713b1edbc 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
AnnaBridge 171:3a7713b1edbc 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
AnnaBridge 171:3a7713b1edbc 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
AnnaBridge 171:3a7713b1edbc 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
AnnaBridge 171:3a7713b1edbc 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
AnnaBridge 171:3a7713b1edbc 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
AnnaBridge 171:3a7713b1edbc 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
AnnaBridge 171:3a7713b1edbc 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
AnnaBridge 171:3a7713b1edbc 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
AnnaBridge 171:3a7713b1edbc 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
AnnaBridge 171:3a7713b1edbc 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
AnnaBridge 171:3a7713b1edbc 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
AnnaBridge 171:3a7713b1edbc 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
AnnaBridge 171:3a7713b1edbc 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
AnnaBridge 171:3a7713b1edbc 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
AnnaBridge 171:3a7713b1edbc 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
AnnaBridge 171:3a7713b1edbc 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
AnnaBridge 171:3a7713b1edbc 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 /** @} */ /* End of group Device_Peripheral_Registers */
AnnaBridge 171:3a7713b1edbc 768 /** @} */ /* End of group (null) */
AnnaBridge 171:3a7713b1edbc 769 /** @} */ /* End of group h1usf */
AnnaBridge 171:3a7713b1edbc 770
AnnaBridge 171:3a7713b1edbc 771 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 772 }
AnnaBridge 171:3a7713b1edbc 773 #endif
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775
AnnaBridge 171:3a7713b1edbc 776 #endif // __LPC13UXX_H__