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TARGET_KL43Z/TOOLCHAIN_IAR/fsl_tpm.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30 #ifndef _FSL_TPM_H_
AnnaBridge 171:3a7713b1edbc 31 #define _FSL_TPM_H_
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*!
AnnaBridge 171:3a7713b1edbc 36 * @addtogroup tpm
AnnaBridge 171:3a7713b1edbc 37 * @{
AnnaBridge 171:3a7713b1edbc 38 */
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*! @file */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 43 * Definitions
AnnaBridge 171:3a7713b1edbc 44 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 47 /*@{*/
AnnaBridge 171:3a7713b1edbc 48 #define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
AnnaBridge 171:3a7713b1edbc 49 /*@}*/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /*!
AnnaBridge 171:3a7713b1edbc 52 * @brief List of TPM channels.
AnnaBridge 171:3a7713b1edbc 53 * @note Actual number of available channels is SoC dependent
AnnaBridge 171:3a7713b1edbc 54 */
AnnaBridge 171:3a7713b1edbc 55 typedef enum _tpm_chnl
AnnaBridge 171:3a7713b1edbc 56 {
AnnaBridge 171:3a7713b1edbc 57 kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
AnnaBridge 171:3a7713b1edbc 58 kTPM_Chnl_1, /*!< TPM channel number 1 */
AnnaBridge 171:3a7713b1edbc 59 kTPM_Chnl_2, /*!< TPM channel number 2 */
AnnaBridge 171:3a7713b1edbc 60 kTPM_Chnl_3, /*!< TPM channel number 3 */
AnnaBridge 171:3a7713b1edbc 61 kTPM_Chnl_4, /*!< TPM channel number 4 */
AnnaBridge 171:3a7713b1edbc 62 kTPM_Chnl_5, /*!< TPM channel number 5 */
AnnaBridge 171:3a7713b1edbc 63 kTPM_Chnl_6, /*!< TPM channel number 6 */
AnnaBridge 171:3a7713b1edbc 64 kTPM_Chnl_7 /*!< TPM channel number 7 */
AnnaBridge 171:3a7713b1edbc 65 } tpm_chnl_t;
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /*! @brief TPM PWM operation modes */
AnnaBridge 171:3a7713b1edbc 68 typedef enum _tpm_pwm_mode
AnnaBridge 171:3a7713b1edbc 69 {
AnnaBridge 171:3a7713b1edbc 70 kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
AnnaBridge 171:3a7713b1edbc 71 kTPM_CenterAlignedPwm, /*!< Center aligned PWM */
AnnaBridge 171:3a7713b1edbc 72 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
AnnaBridge 171:3a7713b1edbc 73 kTPM_CombinedPwm /*!< Combined PWM */
AnnaBridge 171:3a7713b1edbc 74 #endif
AnnaBridge 171:3a7713b1edbc 75 } tpm_pwm_mode_t;
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /*! @brief TPM PWM output pulse mode: high-true, low-true or no output */
AnnaBridge 171:3a7713b1edbc 78 typedef enum _tpm_pwm_level_select
AnnaBridge 171:3a7713b1edbc 79 {
AnnaBridge 171:3a7713b1edbc 80 kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
AnnaBridge 171:3a7713b1edbc 81 kTPM_LowTrue, /*!< Low true pulses */
AnnaBridge 171:3a7713b1edbc 82 kTPM_HighTrue /*!< High true pulses */
AnnaBridge 171:3a7713b1edbc 83 } tpm_pwm_level_select_t;
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /*! @brief Options to configure a TPM channel's PWM signal */
AnnaBridge 171:3a7713b1edbc 86 typedef struct _tpm_chnl_pwm_signal_param
AnnaBridge 171:3a7713b1edbc 87 {
AnnaBridge 171:3a7713b1edbc 88 tpm_chnl_t chnlNumber; /*!< TPM channel to configure.
AnnaBridge 171:3a7713b1edbc 89 In combined mode (available in some SoC's, this represents the
AnnaBridge 171:3a7713b1edbc 90 channel pair number */
AnnaBridge 171:3a7713b1edbc 91 tpm_pwm_level_select_t level; /*!< PWM output active level select */
AnnaBridge 171:3a7713b1edbc 92 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
AnnaBridge 171:3a7713b1edbc 93 0=inactive signal(0% duty cycle)...
AnnaBridge 171:3a7713b1edbc 94 100=always active signal (100% duty cycle)*/
AnnaBridge 171:3a7713b1edbc 95 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
AnnaBridge 171:3a7713b1edbc 96 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
AnnaBridge 171:3a7713b1edbc 97 Specifies the delay to the first edge in a PWM period.
AnnaBridge 171:3a7713b1edbc 98 If unsure, leave as 0; Should be specified as
AnnaBridge 171:3a7713b1edbc 99 percentage of the PWM period */
AnnaBridge 171:3a7713b1edbc 100 #endif
AnnaBridge 171:3a7713b1edbc 101 } tpm_chnl_pwm_signal_param_t;
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /*!
AnnaBridge 171:3a7713b1edbc 104 * @brief Trigger options available.
AnnaBridge 171:3a7713b1edbc 105 *
AnnaBridge 171:3a7713b1edbc 106 * This is used for both internal & external trigger sources (external option available in certain SoC's)
AnnaBridge 171:3a7713b1edbc 107 *
AnnaBridge 171:3a7713b1edbc 108 * @note The actual trigger options available is SoC-specific.
AnnaBridge 171:3a7713b1edbc 109 */
AnnaBridge 171:3a7713b1edbc 110 typedef enum _tpm_trigger_select
AnnaBridge 171:3a7713b1edbc 111 {
AnnaBridge 171:3a7713b1edbc 112 kTPM_Trigger_Select_0 = 0U,
AnnaBridge 171:3a7713b1edbc 113 kTPM_Trigger_Select_1,
AnnaBridge 171:3a7713b1edbc 114 kTPM_Trigger_Select_2,
AnnaBridge 171:3a7713b1edbc 115 kTPM_Trigger_Select_3,
AnnaBridge 171:3a7713b1edbc 116 kTPM_Trigger_Select_4,
AnnaBridge 171:3a7713b1edbc 117 kTPM_Trigger_Select_5,
AnnaBridge 171:3a7713b1edbc 118 kTPM_Trigger_Select_6,
AnnaBridge 171:3a7713b1edbc 119 kTPM_Trigger_Select_7,
AnnaBridge 171:3a7713b1edbc 120 kTPM_Trigger_Select_8,
AnnaBridge 171:3a7713b1edbc 121 kTPM_Trigger_Select_9,
AnnaBridge 171:3a7713b1edbc 122 kTPM_Trigger_Select_10,
AnnaBridge 171:3a7713b1edbc 123 kTPM_Trigger_Select_11,
AnnaBridge 171:3a7713b1edbc 124 kTPM_Trigger_Select_12,
AnnaBridge 171:3a7713b1edbc 125 kTPM_Trigger_Select_13,
AnnaBridge 171:3a7713b1edbc 126 kTPM_Trigger_Select_14,
AnnaBridge 171:3a7713b1edbc 127 kTPM_Trigger_Select_15
AnnaBridge 171:3a7713b1edbc 128 } tpm_trigger_select_t;
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
AnnaBridge 171:3a7713b1edbc 131 /*!
AnnaBridge 171:3a7713b1edbc 132 * @brief Trigger source options available
AnnaBridge 171:3a7713b1edbc 133 *
AnnaBridge 171:3a7713b1edbc 134 * @note This selection is available only on some SoC's. For SoC's without this selection, the only
AnnaBridge 171:3a7713b1edbc 135 * trigger source available is internal triger.
AnnaBridge 171:3a7713b1edbc 136 */
AnnaBridge 171:3a7713b1edbc 137 typedef enum _tpm_trigger_source
AnnaBridge 171:3a7713b1edbc 138 {
AnnaBridge 171:3a7713b1edbc 139 kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
AnnaBridge 171:3a7713b1edbc 140 kTPM_TriggerSource_Internal /*!< Use internal trigger */
AnnaBridge 171:3a7713b1edbc 141 } tpm_trigger_source_t;
AnnaBridge 171:3a7713b1edbc 142 #endif
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 /*! @brief TPM output compare modes */
AnnaBridge 171:3a7713b1edbc 145 typedef enum _tpm_output_compare_mode
AnnaBridge 171:3a7713b1edbc 146 {
AnnaBridge 171:3a7713b1edbc 147 kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
AnnaBridge 171:3a7713b1edbc 148 kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
AnnaBridge 171:3a7713b1edbc 149 kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */
AnnaBridge 171:3a7713b1edbc 150 kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */
AnnaBridge 171:3a7713b1edbc 151 kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
AnnaBridge 171:3a7713b1edbc 152 kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */
AnnaBridge 171:3a7713b1edbc 153 } tpm_output_compare_mode_t;
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*! @brief TPM input capture edge */
AnnaBridge 171:3a7713b1edbc 156 typedef enum _tpm_input_capture_edge
AnnaBridge 171:3a7713b1edbc 157 {
AnnaBridge 171:3a7713b1edbc 158 kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */
AnnaBridge 171:3a7713b1edbc 159 kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */
AnnaBridge 171:3a7713b1edbc 160 kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
AnnaBridge 171:3a7713b1edbc 161 } tpm_input_capture_edge_t;
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
AnnaBridge 171:3a7713b1edbc 164 /*!
AnnaBridge 171:3a7713b1edbc 165 * @brief TPM dual edge capture parameters
AnnaBridge 171:3a7713b1edbc 166 *
AnnaBridge 171:3a7713b1edbc 167 * @note This mode is available only on some SoC's.
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169 typedef struct _tpm_dual_edge_capture_param
AnnaBridge 171:3a7713b1edbc 170 {
AnnaBridge 171:3a7713b1edbc 171 bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored;
AnnaBridge 171:3a7713b1edbc 172 false: Use channel n input, channel n+1 input is ignored */
AnnaBridge 171:3a7713b1edbc 173 tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
AnnaBridge 171:3a7713b1edbc 174 tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
AnnaBridge 171:3a7713b1edbc 175 } tpm_dual_edge_capture_param_t;
AnnaBridge 171:3a7713b1edbc 176 #endif
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
AnnaBridge 171:3a7713b1edbc 179 /*!
AnnaBridge 171:3a7713b1edbc 180 * @brief TPM quadrature decode modes
AnnaBridge 171:3a7713b1edbc 181 *
AnnaBridge 171:3a7713b1edbc 182 * @note This mode is available only on some SoC's.
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 typedef enum _tpm_quad_decode_mode
AnnaBridge 171:3a7713b1edbc 185 {
AnnaBridge 171:3a7713b1edbc 186 kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
AnnaBridge 171:3a7713b1edbc 187 kTPM_QuadCountAndDir /*!< Count and direction encoding mode */
AnnaBridge 171:3a7713b1edbc 188 } tpm_quad_decode_mode_t;
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /*! @brief TPM quadrature phase polarities */
AnnaBridge 171:3a7713b1edbc 191 typedef enum _tpm_phase_polarity
AnnaBridge 171:3a7713b1edbc 192 {
AnnaBridge 171:3a7713b1edbc 193 kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
AnnaBridge 171:3a7713b1edbc 194 kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */
AnnaBridge 171:3a7713b1edbc 195 } tpm_phase_polarity_t;
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /*! @brief TPM quadrature decode phase parameters */
AnnaBridge 171:3a7713b1edbc 198 typedef struct _tpm_phase_param
AnnaBridge 171:3a7713b1edbc 199 {
AnnaBridge 171:3a7713b1edbc 200 uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */
AnnaBridge 171:3a7713b1edbc 201 tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
AnnaBridge 171:3a7713b1edbc 202 } tpm_phase_params_t;
AnnaBridge 171:3a7713b1edbc 203 #endif
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /*! @brief TPM clock source selection*/
AnnaBridge 171:3a7713b1edbc 206 typedef enum _tpm_clock_source
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208 kTPM_SystemClock = 1U, /*!< System clock */
AnnaBridge 171:3a7713b1edbc 209 kTPM_ExternalClock /*!< External clock */
AnnaBridge 171:3a7713b1edbc 210 } tpm_clock_source_t;
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /*! @brief TPM prescale value selection for the clock source*/
AnnaBridge 171:3a7713b1edbc 213 typedef enum _tpm_clock_prescale
AnnaBridge 171:3a7713b1edbc 214 {
AnnaBridge 171:3a7713b1edbc 215 kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
AnnaBridge 171:3a7713b1edbc 216 kTPM_Prescale_Divide_2, /*!< Divide by 2 */
AnnaBridge 171:3a7713b1edbc 217 kTPM_Prescale_Divide_4, /*!< Divide by 4 */
AnnaBridge 171:3a7713b1edbc 218 kTPM_Prescale_Divide_8, /*!< Divide by 8 */
AnnaBridge 171:3a7713b1edbc 219 kTPM_Prescale_Divide_16, /*!< Divide by 16 */
AnnaBridge 171:3a7713b1edbc 220 kTPM_Prescale_Divide_32, /*!< Divide by 32 */
AnnaBridge 171:3a7713b1edbc 221 kTPM_Prescale_Divide_64, /*!< Divide by 64 */
AnnaBridge 171:3a7713b1edbc 222 kTPM_Prescale_Divide_128 /*!< Divide by 128 */
AnnaBridge 171:3a7713b1edbc 223 } tpm_clock_prescale_t;
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 /*!
AnnaBridge 171:3a7713b1edbc 226 * @brief TPM config structure
AnnaBridge 171:3a7713b1edbc 227 *
AnnaBridge 171:3a7713b1edbc 228 * This structure holds the configuration settings for the TPM peripheral. To initialize this
AnnaBridge 171:3a7713b1edbc 229 * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
AnnaBridge 171:3a7713b1edbc 230 * pointer to your config structure instance.
AnnaBridge 171:3a7713b1edbc 231 *
AnnaBridge 171:3a7713b1edbc 232 * The config struct can be made const so it resides in flash
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234 typedef struct _tpm_config
AnnaBridge 171:3a7713b1edbc 235 {
AnnaBridge 171:3a7713b1edbc 236 tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */
AnnaBridge 171:3a7713b1edbc 237 bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled;
AnnaBridge 171:3a7713b1edbc 238 false: disabled */
AnnaBridge 171:3a7713b1edbc 239 tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
AnnaBridge 171:3a7713b1edbc 240 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
AnnaBridge 171:3a7713b1edbc 241 tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
AnnaBridge 171:3a7713b1edbc 242 #endif
AnnaBridge 171:3a7713b1edbc 243 bool enableDoze; /*!< true: TPM counter is paused in doze mode;
AnnaBridge 171:3a7713b1edbc 244 false: TPM counter continues in doze mode */
AnnaBridge 171:3a7713b1edbc 245 bool enableDebugMode; /*!< true: TPM counter continues in debug mode;
AnnaBridge 171:3a7713b1edbc 246 false: TPM counter is paused in debug mode */
AnnaBridge 171:3a7713b1edbc 247 bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
AnnaBridge 171:3a7713b1edbc 248 false: TPM counter not reloaded */
AnnaBridge 171:3a7713b1edbc 249 bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow;
AnnaBridge 171:3a7713b1edbc 250 false: TPM counter continues running after overflow */
AnnaBridge 171:3a7713b1edbc 251 bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected;
AnnaBridge 171:3a7713b1edbc 252 false: TPM counter starts immediately */
AnnaBridge 171:3a7713b1edbc 253 #if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
AnnaBridge 171:3a7713b1edbc 254 bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
AnnaBridge 171:3a7713b1edbc 255 false: TPM counter continues running */
AnnaBridge 171:3a7713b1edbc 256 #endif
AnnaBridge 171:3a7713b1edbc 257 } tpm_config_t;
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /*! @brief List of TPM interrupts */
AnnaBridge 171:3a7713b1edbc 260 typedef enum _tpm_interrupt_enable
AnnaBridge 171:3a7713b1edbc 261 {
AnnaBridge 171:3a7713b1edbc 262 kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/
AnnaBridge 171:3a7713b1edbc 263 kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/
AnnaBridge 171:3a7713b1edbc 264 kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/
AnnaBridge 171:3a7713b1edbc 265 kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/
AnnaBridge 171:3a7713b1edbc 266 kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/
AnnaBridge 171:3a7713b1edbc 267 kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/
AnnaBridge 171:3a7713b1edbc 268 kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/
AnnaBridge 171:3a7713b1edbc 269 kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/
AnnaBridge 171:3a7713b1edbc 270 kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/
AnnaBridge 171:3a7713b1edbc 271 } tpm_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 /*! @brief List of TPM flags */
AnnaBridge 171:3a7713b1edbc 274 typedef enum _tpm_status_flags
AnnaBridge 171:3a7713b1edbc 275 {
AnnaBridge 171:3a7713b1edbc 276 kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */
AnnaBridge 171:3a7713b1edbc 277 kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */
AnnaBridge 171:3a7713b1edbc 278 kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */
AnnaBridge 171:3a7713b1edbc 279 kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */
AnnaBridge 171:3a7713b1edbc 280 kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */
AnnaBridge 171:3a7713b1edbc 281 kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */
AnnaBridge 171:3a7713b1edbc 282 kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */
AnnaBridge 171:3a7713b1edbc 283 kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */
AnnaBridge 171:3a7713b1edbc 284 kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */
AnnaBridge 171:3a7713b1edbc 285 } tpm_status_flags_t;
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 288 * API
AnnaBridge 171:3a7713b1edbc 289 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 292 extern "C" {
AnnaBridge 171:3a7713b1edbc 293 #endif
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /*!
AnnaBridge 171:3a7713b1edbc 296 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 297 * @{
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 /*!
AnnaBridge 171:3a7713b1edbc 301 * @brief Ungates the TPM clock and configures the peripheral for basic operation.
AnnaBridge 171:3a7713b1edbc 302 *
AnnaBridge 171:3a7713b1edbc 303 * @note This API should be called at the beginning of the application using the TPM driver.
AnnaBridge 171:3a7713b1edbc 304 *
AnnaBridge 171:3a7713b1edbc 305 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 306 * @param config Pointer to user's TPM config structure.
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308 void TPM_Init(TPM_Type *base, const tpm_config_t *config);
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /*!
AnnaBridge 171:3a7713b1edbc 311 * @brief Stops the counter and gates the TPM clock
AnnaBridge 171:3a7713b1edbc 312 *
AnnaBridge 171:3a7713b1edbc 313 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 314 */
AnnaBridge 171:3a7713b1edbc 315 void TPM_Deinit(TPM_Type *base);
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /*!
AnnaBridge 171:3a7713b1edbc 318 * @brief Fill in the TPM config struct with the default settings
AnnaBridge 171:3a7713b1edbc 319 *
AnnaBridge 171:3a7713b1edbc 320 * The default values are:
AnnaBridge 171:3a7713b1edbc 321 * @code
AnnaBridge 171:3a7713b1edbc 322 * config->prescale = kTPM_Prescale_Divide_1;
AnnaBridge 171:3a7713b1edbc 323 * config->useGlobalTimeBase = false;
AnnaBridge 171:3a7713b1edbc 324 * config->dozeEnable = false;
AnnaBridge 171:3a7713b1edbc 325 * config->dbgMode = false;
AnnaBridge 171:3a7713b1edbc 326 * config->enableReloadOnTrigger = false;
AnnaBridge 171:3a7713b1edbc 327 * config->enableStopOnOverflow = false;
AnnaBridge 171:3a7713b1edbc 328 * config->enableStartOnTrigger = false;
AnnaBridge 171:3a7713b1edbc 329 *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
AnnaBridge 171:3a7713b1edbc 330 * config->enablePauseOnTrigger = false;
AnnaBridge 171:3a7713b1edbc 331 *#endif
AnnaBridge 171:3a7713b1edbc 332 * config->triggerSelect = kTPM_Trigger_Select_0;
AnnaBridge 171:3a7713b1edbc 333 *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
AnnaBridge 171:3a7713b1edbc 334 * config->triggerSource = kTPM_TriggerSource_External;
AnnaBridge 171:3a7713b1edbc 335 *#endif
AnnaBridge 171:3a7713b1edbc 336 * @endcode
AnnaBridge 171:3a7713b1edbc 337 * @param config Pointer to user's TPM config structure.
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 void TPM_GetDefaultConfig(tpm_config_t *config);
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /*! @}*/
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /*!
AnnaBridge 171:3a7713b1edbc 344 * @name Channel mode operations
AnnaBridge 171:3a7713b1edbc 345 * @{
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /*!
AnnaBridge 171:3a7713b1edbc 349 * @brief Configures the PWM signal parameters
AnnaBridge 171:3a7713b1edbc 350 *
AnnaBridge 171:3a7713b1edbc 351 * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
AnnaBridge 171:3a7713b1edbc 352 * function to configure all the TPM channels that will be used to output a PWM signal
AnnaBridge 171:3a7713b1edbc 353 *
AnnaBridge 171:3a7713b1edbc 354 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 355 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
AnnaBridge 171:3a7713b1edbc 356 * @param numOfChnls Number of channels to configure, this should be the size of the array passed in
AnnaBridge 171:3a7713b1edbc 357 * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
AnnaBridge 171:3a7713b1edbc 358 * @param pwmFreq_Hz PWM signal frequency in Hz
AnnaBridge 171:3a7713b1edbc 359 * @param srcClock_Hz TPM counter clock in Hz
AnnaBridge 171:3a7713b1edbc 360 *
AnnaBridge 171:3a7713b1edbc 361 * @return kStatus_Success if the PWM setup was successful,
AnnaBridge 171:3a7713b1edbc 362 * kStatus_Error on failure
AnnaBridge 171:3a7713b1edbc 363 */
AnnaBridge 171:3a7713b1edbc 364 status_t TPM_SetupPwm(TPM_Type *base,
AnnaBridge 171:3a7713b1edbc 365 const tpm_chnl_pwm_signal_param_t *chnlParams,
AnnaBridge 171:3a7713b1edbc 366 uint8_t numOfChnls,
AnnaBridge 171:3a7713b1edbc 367 tpm_pwm_mode_t mode,
AnnaBridge 171:3a7713b1edbc 368 uint32_t pwmFreq_Hz,
AnnaBridge 171:3a7713b1edbc 369 uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /*!
AnnaBridge 171:3a7713b1edbc 372 * @brief Update the duty cycle of an active PWM signal
AnnaBridge 171:3a7713b1edbc 373 *
AnnaBridge 171:3a7713b1edbc 374 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 375 * @param chnlNumber The channel number. In combined mode, this represents
AnnaBridge 171:3a7713b1edbc 376 * the channel pair number
AnnaBridge 171:3a7713b1edbc 377 * @param currentPwmMode The current PWM mode set during PWM setup
AnnaBridge 171:3a7713b1edbc 378 * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100
AnnaBridge 171:3a7713b1edbc 379 * 0=inactive signal(0% duty cycle)...
AnnaBridge 171:3a7713b1edbc 380 * 100=active signal (100% duty cycle)
AnnaBridge 171:3a7713b1edbc 381 */
AnnaBridge 171:3a7713b1edbc 382 void TPM_UpdatePwmDutycycle(TPM_Type *base,
AnnaBridge 171:3a7713b1edbc 383 tpm_chnl_t chnlNumber,
AnnaBridge 171:3a7713b1edbc 384 tpm_pwm_mode_t currentPwmMode,
AnnaBridge 171:3a7713b1edbc 385 uint8_t dutyCyclePercent);
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 /*!
AnnaBridge 171:3a7713b1edbc 388 * @brief Update the edge level selection for a channel
AnnaBridge 171:3a7713b1edbc 389 *
AnnaBridge 171:3a7713b1edbc 390 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 391 * @param chnlNumber The channel number
AnnaBridge 171:3a7713b1edbc 392 * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
AnnaBridge 171:3a7713b1edbc 393 * See the appropriate SoC reference manual for details about this field.
AnnaBridge 171:3a7713b1edbc 394 */
AnnaBridge 171:3a7713b1edbc 395 void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397 /*!
AnnaBridge 171:3a7713b1edbc 398 * @brief Enables capturing an input signal on the channel using the function parameters.
AnnaBridge 171:3a7713b1edbc 399 *
AnnaBridge 171:3a7713b1edbc 400 * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
AnnaBridge 171:3a7713b1edbc 401 * the CnV register. The user has to read the CnV register separately to get this value.
AnnaBridge 171:3a7713b1edbc 402 *
AnnaBridge 171:3a7713b1edbc 403 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 404 * @param chnlNumber The channel number
AnnaBridge 171:3a7713b1edbc 405 * @param captureMode Specifies which edge to capture
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407 void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 /*!
AnnaBridge 171:3a7713b1edbc 410 * @brief Configures the TPM to generate timed pulses.
AnnaBridge 171:3a7713b1edbc 411 *
AnnaBridge 171:3a7713b1edbc 412 * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
AnnaBridge 171:3a7713b1edbc 413 * output is changed based on what is specified in the compareMode argument.
AnnaBridge 171:3a7713b1edbc 414 *
AnnaBridge 171:3a7713b1edbc 415 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 416 * @param chnlNumber The channel number
AnnaBridge 171:3a7713b1edbc 417 * @param compareMode Action to take on the channel output when the compare condition is met
AnnaBridge 171:3a7713b1edbc 418 * @param compareValue Value to be programmed in the CnV register.
AnnaBridge 171:3a7713b1edbc 419 */
AnnaBridge 171:3a7713b1edbc 420 void TPM_SetupOutputCompare(TPM_Type *base,
AnnaBridge 171:3a7713b1edbc 421 tpm_chnl_t chnlNumber,
AnnaBridge 171:3a7713b1edbc 422 tpm_output_compare_mode_t compareMode,
AnnaBridge 171:3a7713b1edbc 423 uint32_t compareValue);
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
AnnaBridge 171:3a7713b1edbc 426 /*!
AnnaBridge 171:3a7713b1edbc 427 * @brief Configures the dual edge capture mode of the TPM.
AnnaBridge 171:3a7713b1edbc 428 *
AnnaBridge 171:3a7713b1edbc 429 * This function allows to measure a pulse width of the signal on the input of channel of a
AnnaBridge 171:3a7713b1edbc 430 * channel pair. The filter function is disabled if the filterVal argument passed is zero.
AnnaBridge 171:3a7713b1edbc 431 *
AnnaBridge 171:3a7713b1edbc 432 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 433 * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
AnnaBridge 171:3a7713b1edbc 434 * @param edgeParam Sets up the dual edge capture function
AnnaBridge 171:3a7713b1edbc 435 * @param filterValue Filter value, specify 0 to disable filter.
AnnaBridge 171:3a7713b1edbc 436 */
AnnaBridge 171:3a7713b1edbc 437 void TPM_SetupDualEdgeCapture(TPM_Type *base,
AnnaBridge 171:3a7713b1edbc 438 tpm_chnl_t chnlPairNumber,
AnnaBridge 171:3a7713b1edbc 439 const tpm_dual_edge_capture_param_t *edgeParam,
AnnaBridge 171:3a7713b1edbc 440 uint32_t filterValue);
AnnaBridge 171:3a7713b1edbc 441 #endif
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
AnnaBridge 171:3a7713b1edbc 444 /*!
AnnaBridge 171:3a7713b1edbc 445 * @brief Configures the parameters and activates the quadrature decode mode.
AnnaBridge 171:3a7713b1edbc 446 *
AnnaBridge 171:3a7713b1edbc 447 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 448 * @param phaseAParams Phase A configuration parameters
AnnaBridge 171:3a7713b1edbc 449 * @param phaseBParams Phase B configuration parameters
AnnaBridge 171:3a7713b1edbc 450 * @param quadMode Selects encoding mode used in quadrature decoder mode
AnnaBridge 171:3a7713b1edbc 451 */
AnnaBridge 171:3a7713b1edbc 452 void TPM_SetupQuadDecode(TPM_Type *base,
AnnaBridge 171:3a7713b1edbc 453 const tpm_phase_params_t *phaseAParams,
AnnaBridge 171:3a7713b1edbc 454 const tpm_phase_params_t *phaseBParams,
AnnaBridge 171:3a7713b1edbc 455 tpm_quad_decode_mode_t quadMode);
AnnaBridge 171:3a7713b1edbc 456 #endif
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 /*! @}*/
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /*!
AnnaBridge 171:3a7713b1edbc 461 * @name Interrupt Interface
AnnaBridge 171:3a7713b1edbc 462 * @{
AnnaBridge 171:3a7713b1edbc 463 */
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 /*!
AnnaBridge 171:3a7713b1edbc 466 * @brief Enables the selected TPM interrupts.
AnnaBridge 171:3a7713b1edbc 467 *
AnnaBridge 171:3a7713b1edbc 468 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 469 * @param mask The interrupts to enable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 470 * enumeration ::tpm_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 471 */
AnnaBridge 171:3a7713b1edbc 472 void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 /*!
AnnaBridge 171:3a7713b1edbc 475 * @brief Disables the selected TPM interrupts.
AnnaBridge 171:3a7713b1edbc 476 *
AnnaBridge 171:3a7713b1edbc 477 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 478 * @param mask The interrupts to disable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 479 * enumeration ::tpm_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 480 */
AnnaBridge 171:3a7713b1edbc 481 void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /*!
AnnaBridge 171:3a7713b1edbc 484 * @brief Gets the enabled TPM interrupts.
AnnaBridge 171:3a7713b1edbc 485 *
AnnaBridge 171:3a7713b1edbc 486 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 487 *
AnnaBridge 171:3a7713b1edbc 488 * @return The enabled interrupts. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 489 * enumeration ::tpm_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 490 */
AnnaBridge 171:3a7713b1edbc 491 uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /*! @}*/
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /*!
AnnaBridge 171:3a7713b1edbc 496 * @name Status Interface
AnnaBridge 171:3a7713b1edbc 497 * @{
AnnaBridge 171:3a7713b1edbc 498 */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /*!
AnnaBridge 171:3a7713b1edbc 501 * @brief Gets the TPM status flags
AnnaBridge 171:3a7713b1edbc 502 *
AnnaBridge 171:3a7713b1edbc 503 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 504 *
AnnaBridge 171:3a7713b1edbc 505 * @return The status flags. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 506 * enumeration ::tpm_status_flags_t
AnnaBridge 171:3a7713b1edbc 507 */
AnnaBridge 171:3a7713b1edbc 508 static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
AnnaBridge 171:3a7713b1edbc 509 {
AnnaBridge 171:3a7713b1edbc 510 return base->STATUS;
AnnaBridge 171:3a7713b1edbc 511 }
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 /*!
AnnaBridge 171:3a7713b1edbc 514 * @brief Clears the TPM status flags
AnnaBridge 171:3a7713b1edbc 515 *
AnnaBridge 171:3a7713b1edbc 516 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 517 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 518 * enumeration ::tpm_status_flags_t
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520 static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 521 {
AnnaBridge 171:3a7713b1edbc 522 /* Clear the status flags */
AnnaBridge 171:3a7713b1edbc 523 base->STATUS = mask;
AnnaBridge 171:3a7713b1edbc 524 }
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526 /*! @}*/
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 /*!
AnnaBridge 171:3a7713b1edbc 529 * @name Timer Start and Stop
AnnaBridge 171:3a7713b1edbc 530 * @{
AnnaBridge 171:3a7713b1edbc 531 */
AnnaBridge 171:3a7713b1edbc 532
AnnaBridge 171:3a7713b1edbc 533 /*!
AnnaBridge 171:3a7713b1edbc 534 * @brief Starts the TPM counter.
AnnaBridge 171:3a7713b1edbc 535 *
AnnaBridge 171:3a7713b1edbc 536 *
AnnaBridge 171:3a7713b1edbc 537 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 538 * @param clockSource TPM clock source; once clock source is set the counter will start running
AnnaBridge 171:3a7713b1edbc 539 */
AnnaBridge 171:3a7713b1edbc 540 static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
AnnaBridge 171:3a7713b1edbc 541 {
AnnaBridge 171:3a7713b1edbc 542 uint32_t reg = base->SC;
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 reg &= ~(TPM_SC_CMOD_MASK);
AnnaBridge 171:3a7713b1edbc 545 reg |= TPM_SC_CMOD(clockSource);
AnnaBridge 171:3a7713b1edbc 546 base->SC = reg;
AnnaBridge 171:3a7713b1edbc 547 }
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /*!
AnnaBridge 171:3a7713b1edbc 550 * @brief Stops the TPM counter.
AnnaBridge 171:3a7713b1edbc 551 *
AnnaBridge 171:3a7713b1edbc 552 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 553 */
AnnaBridge 171:3a7713b1edbc 554 static inline void TPM_StopTimer(TPM_Type *base)
AnnaBridge 171:3a7713b1edbc 555 {
AnnaBridge 171:3a7713b1edbc 556 /* Set clock source to none to disable counter */
AnnaBridge 171:3a7713b1edbc 557 base->SC &= ~(TPM_SC_CMOD_MASK);
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /* Wait till this reads as zero acknowledging the counter is disabled */
AnnaBridge 171:3a7713b1edbc 560 while (base->SC & TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 561 {
AnnaBridge 171:3a7713b1edbc 562 }
AnnaBridge 171:3a7713b1edbc 563 }
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 /*! @}*/
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
AnnaBridge 171:3a7713b1edbc 568 /*!
AnnaBridge 171:3a7713b1edbc 569 * @brief Performs a software reset on the TPM module.
AnnaBridge 171:3a7713b1edbc 570 *
AnnaBridge 171:3a7713b1edbc 571 * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software..
AnnaBridge 171:3a7713b1edbc 572 *
AnnaBridge 171:3a7713b1edbc 573 * @note TPM software reset is available on certain SoC's only
AnnaBridge 171:3a7713b1edbc 574 *
AnnaBridge 171:3a7713b1edbc 575 * @param base TPM peripheral base address
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577 static inline void TPM_Reset(TPM_Type *base)
AnnaBridge 171:3a7713b1edbc 578 {
AnnaBridge 171:3a7713b1edbc 579 base->GLOBAL |= TPM_GLOBAL_RST_MASK;
AnnaBridge 171:3a7713b1edbc 580 base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
AnnaBridge 171:3a7713b1edbc 581 }
AnnaBridge 171:3a7713b1edbc 582 #endif
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 585 }
AnnaBridge 171:3a7713b1edbc 586 #endif
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 /*! @}*/
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 #endif /* _FSL_TPM_H_ */