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TARGET_KL27Z/TOOLCHAIN_IAR/fsl_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used tom endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30 #ifndef _FSL_SPI_H_
AnnaBridge 171:3a7713b1edbc 31 #define _FSL_SPI_H_
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*!
AnnaBridge 171:3a7713b1edbc 36 * @addtogroup spi_driver
AnnaBridge 171:3a7713b1edbc 37 * @{
AnnaBridge 171:3a7713b1edbc 38 */
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 42 * Definitions
AnnaBridge 171:3a7713b1edbc 43 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 46 /*@{*/
AnnaBridge 171:3a7713b1edbc 47 /*! @brief SPI driver version 2.0.1. */
AnnaBridge 171:3a7713b1edbc 48 #define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
AnnaBridge 171:3a7713b1edbc 49 /*@}*/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #ifndef SPI_DUMMYDATA
AnnaBridge 171:3a7713b1edbc 52 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
AnnaBridge 171:3a7713b1edbc 53 #define SPI_DUMMYDATA (0xFFU)
AnnaBridge 171:3a7713b1edbc 54 #endif
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /*! @brief Return status for the SPI driver.*/
AnnaBridge 171:3a7713b1edbc 57 enum _spi_status
AnnaBridge 171:3a7713b1edbc 58 {
AnnaBridge 171:3a7713b1edbc 59 kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
AnnaBridge 171:3a7713b1edbc 60 kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
AnnaBridge 171:3a7713b1edbc 61 kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) /*!< SPI error */
AnnaBridge 171:3a7713b1edbc 62 };
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /*! @brief SPI clock polarity configuration.*/
AnnaBridge 171:3a7713b1edbc 65 typedef enum _spi_clock_polarity
AnnaBridge 171:3a7713b1edbc 66 {
AnnaBridge 171:3a7713b1edbc 67 kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
AnnaBridge 171:3a7713b1edbc 68 kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
AnnaBridge 171:3a7713b1edbc 69 } spi_clock_polarity_t;
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /*! @brief SPI clock phase configuration.*/
AnnaBridge 171:3a7713b1edbc 72 typedef enum _spi_clock_phase
AnnaBridge 171:3a7713b1edbc 73 {
AnnaBridge 171:3a7713b1edbc 74 kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
AnnaBridge 171:3a7713b1edbc 75 * cycle of a data transfer. */
AnnaBridge 171:3a7713b1edbc 76 kSPI_ClockPhaseSecondEdge /*!< First edge on SPSCK occurs at the start of the
AnnaBridge 171:3a7713b1edbc 77 * first cycle of a data transfer. */
AnnaBridge 171:3a7713b1edbc 78 } spi_clock_phase_t;
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /*! @brief SPI data shifter direction options.*/
AnnaBridge 171:3a7713b1edbc 81 typedef enum _spi_shift_direction
AnnaBridge 171:3a7713b1edbc 82 {
AnnaBridge 171:3a7713b1edbc 83 kSPI_MsbFirst = 0x0U, /*!< Data transfers start with most significant bit. */
AnnaBridge 171:3a7713b1edbc 84 kSPI_LsbFirst /*!< Data transfers start with least significant bit. */
AnnaBridge 171:3a7713b1edbc 85 } spi_shift_direction_t;
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /*! @brief SPI slave select output mode options.*/
AnnaBridge 171:3a7713b1edbc 88 typedef enum _spi_ss_output_mode
AnnaBridge 171:3a7713b1edbc 89 {
AnnaBridge 171:3a7713b1edbc 90 kSPI_SlaveSelectAsGpio = 0x0U, /*!< Slave select pin configured as GPIO. */
AnnaBridge 171:3a7713b1edbc 91 kSPI_SlaveSelectFaultInput = 0x2U, /*!< Slave select pin configured for fault detection. */
AnnaBridge 171:3a7713b1edbc 92 kSPI_SlaveSelectAutomaticOutput = 0x3U /*!< Slave select pin configured for automatic SPI output. */
AnnaBridge 171:3a7713b1edbc 93 } spi_ss_output_mode_t;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /*! @brief SPI pin mode options.*/
AnnaBridge 171:3a7713b1edbc 96 typedef enum _spi_pin_mode
AnnaBridge 171:3a7713b1edbc 97 {
AnnaBridge 171:3a7713b1edbc 98 kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/
AnnaBridge 171:3a7713b1edbc 99 kSPI_PinModeInput = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input;
AnnaBridge 171:3a7713b1edbc 100 * Slave: MISO pin is input. */
AnnaBridge 171:3a7713b1edbc 101 kSPI_PinModeOutput = 0x3U /*!< Bidirectional mode. Master: MOSI pin is output;
AnnaBridge 171:3a7713b1edbc 102 * Slave: MISO pin is output. */
AnnaBridge 171:3a7713b1edbc 103 } spi_pin_mode_t;
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /*! @brief SPI data length mode options.*/
AnnaBridge 171:3a7713b1edbc 106 typedef enum _spi_data_bitcount_mode
AnnaBridge 171:3a7713b1edbc 107 {
AnnaBridge 171:3a7713b1edbc 108 kSPI_8BitMode = 0x0U, /*!< 8-bit data transmission mode*/
AnnaBridge 171:3a7713b1edbc 109 kSPI_16BitMode /*!< 16-bit data transmission mode*/
AnnaBridge 171:3a7713b1edbc 110 } spi_data_bitcount_mode_t;
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /*! @brief SPI interrupt sources.*/
AnnaBridge 171:3a7713b1edbc 113 enum _spi_interrupt_enable
AnnaBridge 171:3a7713b1edbc 114 {
AnnaBridge 171:3a7713b1edbc 115 kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
AnnaBridge 171:3a7713b1edbc 116 kSPI_TxEmptyInterruptEnable = 0x2U, /*!< Transmit buffer empty interrupt */
AnnaBridge 171:3a7713b1edbc 117 kSPI_MatchInterruptEnable = 0x4U, /*!< Match interrupt */
AnnaBridge 171:3a7713b1edbc 118 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 119 kSPI_RxFifoNearFullInterruptEnable = 0x8U, /*!< Receive FIFO nearly full interrupt */
AnnaBridge 171:3a7713b1edbc 120 kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */
AnnaBridge 171:3a7713b1edbc 121 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 122 };
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /*! @brief SPI status flags.*/
AnnaBridge 171:3a7713b1edbc 125 enum _spi_flags
AnnaBridge 171:3a7713b1edbc 126 {
AnnaBridge 171:3a7713b1edbc 127 kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK, /*!< Read buffer full flag */
AnnaBridge 171:3a7713b1edbc 128 kSPI_MatchFlag = SPI_S_SPMF_MASK, /*!< Match flag */
AnnaBridge 171:3a7713b1edbc 129 kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */
AnnaBridge 171:3a7713b1edbc 130 kSPI_ModeFaultFlag = SPI_S_MODF_MASK, /*!< Mode fault flag */
AnnaBridge 171:3a7713b1edbc 131 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 132 kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK, /*!< Rx FIFO near full */
AnnaBridge 171:3a7713b1edbc 133 kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, /*!< Tx FIFO near empty */
AnnaBridge 171:3a7713b1edbc 134 kSPI_TxFifoFullFlag = SPI_S_TXFULLF_MASK, /*!< Tx FIFO full */
AnnaBridge 171:3a7713b1edbc 135 kSPI_RxFifoEmptyFlag = SPI_S_RFIFOEF_MASK, /*!< Rx FIFO empty */
AnnaBridge 171:3a7713b1edbc 136 kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */
AnnaBridge 171:3a7713b1edbc 137 kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO error */
AnnaBridge 171:3a7713b1edbc 138 kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U, /*!< Tx FIFO Overflow */
AnnaBridge 171:3a7713b1edbc 139 kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U /*!< Rx FIFO Overflow */
AnnaBridge 171:3a7713b1edbc 140 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 141 };
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 144 /*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
AnnaBridge 171:3a7713b1edbc 145 typedef enum _spi_w1c_interrupt
AnnaBridge 171:3a7713b1edbc 146 {
AnnaBridge 171:3a7713b1edbc 147 kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK, /*!< Receive FIFO full interrupt */
AnnaBridge 171:3a7713b1edbc 148 kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK, /*!< Transmit FIFO empty interrupt */
AnnaBridge 171:3a7713b1edbc 149 kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
AnnaBridge 171:3a7713b1edbc 150 kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK /*!< Transmit FIFO nearly empty interrupt */
AnnaBridge 171:3a7713b1edbc 151 } spi_w1c_interrupt_t;
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /*! @brief SPI TX FIFO watermark settings.*/
AnnaBridge 171:3a7713b1edbc 154 typedef enum _spi_txfifo_watermark
AnnaBridge 171:3a7713b1edbc 155 {
AnnaBridge 171:3a7713b1edbc 156 kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */
AnnaBridge 171:3a7713b1edbc 157 kSPI_TxFifoOneHalfEmpty = 1 /*!< SPI tx watermark at 1/2 FIFO size */
AnnaBridge 171:3a7713b1edbc 158 } spi_txfifo_watermark_t;
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /*! @brief SPI RX FIFO watermark settings.*/
AnnaBridge 171:3a7713b1edbc 161 typedef enum _spi_rxfifo_watermark
AnnaBridge 171:3a7713b1edbc 162 {
AnnaBridge 171:3a7713b1edbc 163 kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */
AnnaBridge 171:3a7713b1edbc 164 kSPI_RxFifoOneHalfFull = 1 /*!< SPI rx watermark at 1/2 FIFO size */
AnnaBridge 171:3a7713b1edbc 165 } spi_rxfifo_watermark_t;
AnnaBridge 171:3a7713b1edbc 166 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
AnnaBridge 171:3a7713b1edbc 169 /*! @brief SPI DMA source*/
AnnaBridge 171:3a7713b1edbc 170 enum _spi_dma_enable_t
AnnaBridge 171:3a7713b1edbc 171 {
AnnaBridge 171:3a7713b1edbc 172 kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK, /*!< Tx DMA request source */
AnnaBridge 171:3a7713b1edbc 173 kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK, /*!< Rx DMA request source */
AnnaBridge 171:3a7713b1edbc 174 kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/
AnnaBridge 171:3a7713b1edbc 175 };
AnnaBridge 171:3a7713b1edbc 176 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /*! @brief SPI master user configure structure.*/
AnnaBridge 171:3a7713b1edbc 179 typedef struct _spi_master_config
AnnaBridge 171:3a7713b1edbc 180 {
AnnaBridge 171:3a7713b1edbc 181 bool enableMaster; /*!< Enable SPI at initialization time */
AnnaBridge 171:3a7713b1edbc 182 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
AnnaBridge 171:3a7713b1edbc 183 spi_clock_polarity_t polarity; /*!< Clock polarity */
AnnaBridge 171:3a7713b1edbc 184 spi_clock_phase_t phase; /*!< Clock phase */
AnnaBridge 171:3a7713b1edbc 185 spi_shift_direction_t direction; /*!< MSB or LSB */
AnnaBridge 171:3a7713b1edbc 186 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
AnnaBridge 171:3a7713b1edbc 187 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
AnnaBridge 171:3a7713b1edbc 188 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
AnnaBridge 171:3a7713b1edbc 189 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 190 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
AnnaBridge 171:3a7713b1edbc 191 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
AnnaBridge 171:3a7713b1edbc 192 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 193 spi_ss_output_mode_t outputMode; /*!< SS pin setting */
AnnaBridge 171:3a7713b1edbc 194 spi_pin_mode_t pinMode; /*!< SPI pin mode select */
AnnaBridge 171:3a7713b1edbc 195 uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
AnnaBridge 171:3a7713b1edbc 196 } spi_master_config_t;
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /*! @brief SPI slave user configure structure.*/
AnnaBridge 171:3a7713b1edbc 199 typedef struct _spi_slave_config
AnnaBridge 171:3a7713b1edbc 200 {
AnnaBridge 171:3a7713b1edbc 201 bool enableSlave; /*!< Enable SPI at initialization time */
AnnaBridge 171:3a7713b1edbc 202 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
AnnaBridge 171:3a7713b1edbc 203 spi_clock_polarity_t polarity; /*!< Clock polarity */
AnnaBridge 171:3a7713b1edbc 204 spi_clock_phase_t phase; /*!< Clock phase */
AnnaBridge 171:3a7713b1edbc 205 spi_shift_direction_t direction; /*!< MSB or LSB */
AnnaBridge 171:3a7713b1edbc 206 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
AnnaBridge 171:3a7713b1edbc 207 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
AnnaBridge 171:3a7713b1edbc 208 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
AnnaBridge 171:3a7713b1edbc 209 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 210 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
AnnaBridge 171:3a7713b1edbc 211 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
AnnaBridge 171:3a7713b1edbc 212 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 213 } spi_slave_config_t;
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /*! @brief SPI transfer structure */
AnnaBridge 171:3a7713b1edbc 216 typedef struct _spi_transfer
AnnaBridge 171:3a7713b1edbc 217 {
AnnaBridge 171:3a7713b1edbc 218 uint8_t *txData; /*!< Send buffer */
AnnaBridge 171:3a7713b1edbc 219 uint8_t *rxData; /*!< Receive buffer */
AnnaBridge 171:3a7713b1edbc 220 size_t dataSize; /*!< Transfer bytes */
AnnaBridge 171:3a7713b1edbc 221 uint32_t flags; /*!< SPI control flag, useless to SPI.*/
AnnaBridge 171:3a7713b1edbc 222 } spi_transfer_t;
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 typedef struct _spi_master_handle spi_master_handle_t;
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /*! @brief Slave handle is the same with master handle */
AnnaBridge 171:3a7713b1edbc 227 typedef spi_master_handle_t spi_slave_handle_t;
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /*! @brief SPI master callback for finished transmit */
AnnaBridge 171:3a7713b1edbc 230 typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /*! @brief SPI master callback for finished transmit */
AnnaBridge 171:3a7713b1edbc 233 typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /*! @brief SPI transfer handle structure */
AnnaBridge 171:3a7713b1edbc 236 struct _spi_master_handle
AnnaBridge 171:3a7713b1edbc 237 {
AnnaBridge 171:3a7713b1edbc 238 uint8_t *volatile txData; /*!< Transfer buffer */
AnnaBridge 171:3a7713b1edbc 239 uint8_t *volatile rxData; /*!< Receive buffer */
AnnaBridge 171:3a7713b1edbc 240 volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */
AnnaBridge 171:3a7713b1edbc 241 volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */
AnnaBridge 171:3a7713b1edbc 242 volatile uint32_t state; /*!< SPI internal state */
AnnaBridge 171:3a7713b1edbc 243 size_t transferSize; /*!< Bytes to be transferred */
AnnaBridge 171:3a7713b1edbc 244 uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */
AnnaBridge 171:3a7713b1edbc 245 uint8_t watermark; /*!< Watermark value for SPI transfer */
AnnaBridge 171:3a7713b1edbc 246 spi_master_callback_t callback; /*!< SPI callback */
AnnaBridge 171:3a7713b1edbc 247 void *userData; /*!< Callback parameter */
AnnaBridge 171:3a7713b1edbc 248 };
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 251 extern "C" {
AnnaBridge 171:3a7713b1edbc 252 #endif
AnnaBridge 171:3a7713b1edbc 253 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 254 * APIs
AnnaBridge 171:3a7713b1edbc 255 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 256 /*!
AnnaBridge 171:3a7713b1edbc 257 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 258 * @{
AnnaBridge 171:3a7713b1edbc 259 */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /*!
AnnaBridge 171:3a7713b1edbc 262 * @brief Sets the SPI master configuration structure to default values.
AnnaBridge 171:3a7713b1edbc 263 *
AnnaBridge 171:3a7713b1edbc 264 * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
AnnaBridge 171:3a7713b1edbc 265 * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
AnnaBridge 171:3a7713b1edbc 266 * some fields of the structure before calling SPI_MasterInit(). After calling this API,
AnnaBridge 171:3a7713b1edbc 267 * the master is ready to transfer.
AnnaBridge 171:3a7713b1edbc 268 * Example:
AnnaBridge 171:3a7713b1edbc 269 @code
AnnaBridge 171:3a7713b1edbc 270 spi_master_config_t config;
AnnaBridge 171:3a7713b1edbc 271 SPI_MasterGetDefaultConfig(&config);
AnnaBridge 171:3a7713b1edbc 272 @endcode
AnnaBridge 171:3a7713b1edbc 273 *
AnnaBridge 171:3a7713b1edbc 274 * @param config pointer to master config structure
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276 void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /*!
AnnaBridge 171:3a7713b1edbc 279 * @brief Initializes the SPI with master configuration.
AnnaBridge 171:3a7713b1edbc 280 *
AnnaBridge 171:3a7713b1edbc 281 * The configuration structure can be filled by user from scratch, or be set with default
AnnaBridge 171:3a7713b1edbc 282 * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
AnnaBridge 171:3a7713b1edbc 283 * Example
AnnaBridge 171:3a7713b1edbc 284 @code
AnnaBridge 171:3a7713b1edbc 285 spi_master_config_t config = {
AnnaBridge 171:3a7713b1edbc 286 .baudRate_Bps = 400000,
AnnaBridge 171:3a7713b1edbc 287 ...
AnnaBridge 171:3a7713b1edbc 288 };
AnnaBridge 171:3a7713b1edbc 289 SPI_MasterInit(SPI0, &config);
AnnaBridge 171:3a7713b1edbc 290 @endcode
AnnaBridge 171:3a7713b1edbc 291 *
AnnaBridge 171:3a7713b1edbc 292 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 293 * @param config pointer to master configuration structure
AnnaBridge 171:3a7713b1edbc 294 * @param srcClock_Hz Source clock frequency.
AnnaBridge 171:3a7713b1edbc 295 */
AnnaBridge 171:3a7713b1edbc 296 void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 /*!
AnnaBridge 171:3a7713b1edbc 299 * @brief Sets the SPI slave configuration structure to default values.
AnnaBridge 171:3a7713b1edbc 300 *
AnnaBridge 171:3a7713b1edbc 301 * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
AnnaBridge 171:3a7713b1edbc 302 * Modify some fields of the structure before calling SPI_SlaveInit().
AnnaBridge 171:3a7713b1edbc 303 * Example:
AnnaBridge 171:3a7713b1edbc 304 @code
AnnaBridge 171:3a7713b1edbc 305 spi_slave_config_t config;
AnnaBridge 171:3a7713b1edbc 306 SPI_SlaveGetDefaultConfig(&config);
AnnaBridge 171:3a7713b1edbc 307 @endcode
AnnaBridge 171:3a7713b1edbc 308 *
AnnaBridge 171:3a7713b1edbc 309 * @param config pointer to slave configuration structure
AnnaBridge 171:3a7713b1edbc 310 */
AnnaBridge 171:3a7713b1edbc 311 void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /*!
AnnaBridge 171:3a7713b1edbc 314 * @brief Initializes the SPI with slave configuration.
AnnaBridge 171:3a7713b1edbc 315 *
AnnaBridge 171:3a7713b1edbc 316 * The configuration structure can be filled by user from scratch or be set with
AnnaBridge 171:3a7713b1edbc 317 * default values by SPI_SlaveGetDefaultConfig().
AnnaBridge 171:3a7713b1edbc 318 * After calling this API, the slave is ready to transfer.
AnnaBridge 171:3a7713b1edbc 319 * Example
AnnaBridge 171:3a7713b1edbc 320 @code
AnnaBridge 171:3a7713b1edbc 321 spi_slave_config_t config = {
AnnaBridge 171:3a7713b1edbc 322 .polarity = kSPIClockPolarity_ActiveHigh;
AnnaBridge 171:3a7713b1edbc 323 .phase = kSPIClockPhase_FirstEdge;
AnnaBridge 171:3a7713b1edbc 324 .direction = kSPIMsbFirst;
AnnaBridge 171:3a7713b1edbc 325 ...
AnnaBridge 171:3a7713b1edbc 326 };
AnnaBridge 171:3a7713b1edbc 327 SPI_MasterInit(SPI0, &config);
AnnaBridge 171:3a7713b1edbc 328 @endcode
AnnaBridge 171:3a7713b1edbc 329 *
AnnaBridge 171:3a7713b1edbc 330 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 331 * @param config pointer to master configuration structure
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /*!
AnnaBridge 171:3a7713b1edbc 336 * @brief De-initializes the SPI.
AnnaBridge 171:3a7713b1edbc 337 *
AnnaBridge 171:3a7713b1edbc 338 * Calling this API resets the SPI module, gates the SPI clock.
AnnaBridge 171:3a7713b1edbc 339 * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
AnnaBridge 171:3a7713b1edbc 340 *
AnnaBridge 171:3a7713b1edbc 341 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 342 */
AnnaBridge 171:3a7713b1edbc 343 void SPI_Deinit(SPI_Type *base);
AnnaBridge 171:3a7713b1edbc 344
AnnaBridge 171:3a7713b1edbc 345 /*!
AnnaBridge 171:3a7713b1edbc 346 * @brief Enables or disables the SPI.
AnnaBridge 171:3a7713b1edbc 347 *
AnnaBridge 171:3a7713b1edbc 348 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 349 * @param enable pass true to enable module, false to disable module
AnnaBridge 171:3a7713b1edbc 350 */
AnnaBridge 171:3a7713b1edbc 351 static inline void SPI_Enable(SPI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 352 {
AnnaBridge 171:3a7713b1edbc 353 if (enable)
AnnaBridge 171:3a7713b1edbc 354 {
AnnaBridge 171:3a7713b1edbc 355 base->C1 |= SPI_C1_SPE_MASK;
AnnaBridge 171:3a7713b1edbc 356 }
AnnaBridge 171:3a7713b1edbc 357 else
AnnaBridge 171:3a7713b1edbc 358 {
AnnaBridge 171:3a7713b1edbc 359 base->C1 &= ~SPI_C1_SPE_MASK;
AnnaBridge 171:3a7713b1edbc 360 }
AnnaBridge 171:3a7713b1edbc 361 }
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /*! @} */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /*!
AnnaBridge 171:3a7713b1edbc 366 * @name Status
AnnaBridge 171:3a7713b1edbc 367 * @{
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 /*!
AnnaBridge 171:3a7713b1edbc 371 * @brief Gets the status flag.
AnnaBridge 171:3a7713b1edbc 372 *
AnnaBridge 171:3a7713b1edbc 373 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 374 * @return SPI Status, use status flag to AND #_spi_flags could get the related status.
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 uint32_t SPI_GetStatusFlags(SPI_Type *base);
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 379 /*!
AnnaBridge 171:3a7713b1edbc 380 * @brief Clear the interrupt if enable INCTLR.
AnnaBridge 171:3a7713b1edbc 381 *
AnnaBridge 171:3a7713b1edbc 382 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 383 * @param interrupt Interrupt need to be cleared
AnnaBridge 171:3a7713b1edbc 384 * The parameter could be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 385 * @arg kSPIRxFifoFullClearInt
AnnaBridge 171:3a7713b1edbc 386 * @arg kSPITxFifoEmptyClearInt
AnnaBridge 171:3a7713b1edbc 387 * @arg kSPIRxNearFullClearInt
AnnaBridge 171:3a7713b1edbc 388 * @arg kSPITxNearEmptyClearInt
AnnaBridge 171:3a7713b1edbc 389 */
AnnaBridge 171:3a7713b1edbc 390 static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 391 {
AnnaBridge 171:3a7713b1edbc 392 base->CI |= mask;
AnnaBridge 171:3a7713b1edbc 393 }
AnnaBridge 171:3a7713b1edbc 394 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /*! @} */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /*!
AnnaBridge 171:3a7713b1edbc 399 * @name Interrupts
AnnaBridge 171:3a7713b1edbc 400 * @{
AnnaBridge 171:3a7713b1edbc 401 */
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 /*!
AnnaBridge 171:3a7713b1edbc 404 * @brief Enables the interrupt for the SPI.
AnnaBridge 171:3a7713b1edbc 405 *
AnnaBridge 171:3a7713b1edbc 406 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 407 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 408 * @arg kSPI_RxFullAndModfInterruptEnable
AnnaBridge 171:3a7713b1edbc 409 * @arg kSPI_TxEmptyInterruptEnable
AnnaBridge 171:3a7713b1edbc 410 * @arg kSPI_MatchInterruptEnable
AnnaBridge 171:3a7713b1edbc 411 * @arg kSPI_RxFifoNearFullInterruptEnable
AnnaBridge 171:3a7713b1edbc 412 * @arg kSPI_TxFifoNearEmptyInterruptEnable
AnnaBridge 171:3a7713b1edbc 413 */
AnnaBridge 171:3a7713b1edbc 414 void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /*!
AnnaBridge 171:3a7713b1edbc 417 * @brief Disables the interrupt for the SPI.
AnnaBridge 171:3a7713b1edbc 418 *
AnnaBridge 171:3a7713b1edbc 419 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 420 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 421 * @arg kSPI_RxFullAndModfInterruptEnable
AnnaBridge 171:3a7713b1edbc 422 * @arg kSPI_TxEmptyInterruptEnable
AnnaBridge 171:3a7713b1edbc 423 * @arg kSPI_MatchInterruptEnable
AnnaBridge 171:3a7713b1edbc 424 * @arg kSPI_RxFifoNearFullInterruptEnable
AnnaBridge 171:3a7713b1edbc 425 * @arg kSPI_TxFifoNearEmptyInterruptEnable
AnnaBridge 171:3a7713b1edbc 426 */
AnnaBridge 171:3a7713b1edbc 427 void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /*! @} */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 /*!
AnnaBridge 171:3a7713b1edbc 432 * @name DMA Control
AnnaBridge 171:3a7713b1edbc 433 * @{
AnnaBridge 171:3a7713b1edbc 434 */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
AnnaBridge 171:3a7713b1edbc 437 /*!
AnnaBridge 171:3a7713b1edbc 438 * @brief Enables the DMA source for SPI.
AnnaBridge 171:3a7713b1edbc 439 *
AnnaBridge 171:3a7713b1edbc 440 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 441 * @param source SPI DMA source.
AnnaBridge 171:3a7713b1edbc 442 * @param enable True means enable DMA, false means disable DMA
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444 static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
AnnaBridge 171:3a7713b1edbc 445 {
AnnaBridge 171:3a7713b1edbc 446 if (enable)
AnnaBridge 171:3a7713b1edbc 447 {
AnnaBridge 171:3a7713b1edbc 448 base->C2 |= mask;
AnnaBridge 171:3a7713b1edbc 449 }
AnnaBridge 171:3a7713b1edbc 450 else
AnnaBridge 171:3a7713b1edbc 451 {
AnnaBridge 171:3a7713b1edbc 452 base->C2 &= ~mask;
AnnaBridge 171:3a7713b1edbc 453 }
AnnaBridge 171:3a7713b1edbc 454 }
AnnaBridge 171:3a7713b1edbc 455 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /*!
AnnaBridge 171:3a7713b1edbc 458 * @brief Gets the SPI tx/rx data register address.
AnnaBridge 171:3a7713b1edbc 459 *
AnnaBridge 171:3a7713b1edbc 460 * This API is used to provide a transfer address for the SPI DMA transfer configuration.
AnnaBridge 171:3a7713b1edbc 461 *
AnnaBridge 171:3a7713b1edbc 462 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 463 * @return data register address
AnnaBridge 171:3a7713b1edbc 464 */
AnnaBridge 171:3a7713b1edbc 465 static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
AnnaBridge 171:3a7713b1edbc 466 {
AnnaBridge 171:3a7713b1edbc 467 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
AnnaBridge 171:3a7713b1edbc 468 return (uint32_t)(&(base->DL));
AnnaBridge 171:3a7713b1edbc 469 #else
AnnaBridge 171:3a7713b1edbc 470 return (uint32_t)(&(base->D));
AnnaBridge 171:3a7713b1edbc 471 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
AnnaBridge 171:3a7713b1edbc 472 }
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 /*! @} */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 /*!
AnnaBridge 171:3a7713b1edbc 477 * @name Bus Operations
AnnaBridge 171:3a7713b1edbc 478 * @{
AnnaBridge 171:3a7713b1edbc 479 */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /*!
AnnaBridge 171:3a7713b1edbc 482 * @brief Sets the baud rate for SPI transfer. This is only used in master.
AnnaBridge 171:3a7713b1edbc 483 *
AnnaBridge 171:3a7713b1edbc 484 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 485 * @param baudRate_Bps baud rate needed in Hz.
AnnaBridge 171:3a7713b1edbc 486 * @param srcClock_Hz SPI source clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 487 */
AnnaBridge 171:3a7713b1edbc 488 void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
AnnaBridge 171:3a7713b1edbc 489
AnnaBridge 171:3a7713b1edbc 490 /*!
AnnaBridge 171:3a7713b1edbc 491 * @brief Sets the match data for SPI.
AnnaBridge 171:3a7713b1edbc 492 *
AnnaBridge 171:3a7713b1edbc 493 * The match data is a hardware comparison value. When the value received in the SPI receive data
AnnaBridge 171:3a7713b1edbc 494 * buffer equals the hardware comparison value, the SPI Match Flag in the S register (S[SPMF]) sets.
AnnaBridge 171:3a7713b1edbc 495 * This can also generate an interrupt if the enable bit sets.
AnnaBridge 171:3a7713b1edbc 496 *
AnnaBridge 171:3a7713b1edbc 497 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 498 * @param matchData Match data.
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500 static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
AnnaBridge 171:3a7713b1edbc 501 {
AnnaBridge 171:3a7713b1edbc 502 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
AnnaBridge 171:3a7713b1edbc 503 base->ML = matchData & 0xFFU;
AnnaBridge 171:3a7713b1edbc 504 base->MH = (matchData >> 8U) & 0xFFU;
AnnaBridge 171:3a7713b1edbc 505 #else
AnnaBridge 171:3a7713b1edbc 506 base->M = matchData;
AnnaBridge 171:3a7713b1edbc 507 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
AnnaBridge 171:3a7713b1edbc 508 }
AnnaBridge 171:3a7713b1edbc 509
AnnaBridge 171:3a7713b1edbc 510 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
AnnaBridge 171:3a7713b1edbc 511 /*!
AnnaBridge 171:3a7713b1edbc 512 * @brief Enables or disables the FIFO if there is a FIFO.
AnnaBridge 171:3a7713b1edbc 513 *
AnnaBridge 171:3a7713b1edbc 514 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 515 * @param enable True means enable FIFO, false means disable FIFO.
AnnaBridge 171:3a7713b1edbc 516 */
AnnaBridge 171:3a7713b1edbc 517 void SPI_EnableFIFO(SPI_Type *base, bool enable);
AnnaBridge 171:3a7713b1edbc 518 #endif
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 /*!
AnnaBridge 171:3a7713b1edbc 521 * @brief Sends a buffer of data bytes using a blocking method.
AnnaBridge 171:3a7713b1edbc 522 *
AnnaBridge 171:3a7713b1edbc 523 * @note This function blocks via polling until all bytes have been sent.
AnnaBridge 171:3a7713b1edbc 524 *
AnnaBridge 171:3a7713b1edbc 525 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 526 * @param buffer The data bytes to send
AnnaBridge 171:3a7713b1edbc 527 * @param size The number of data bytes to send
AnnaBridge 171:3a7713b1edbc 528 */
AnnaBridge 171:3a7713b1edbc 529 void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 /*!
AnnaBridge 171:3a7713b1edbc 532 * @brief Writes a data into the SPI data register.
AnnaBridge 171:3a7713b1edbc 533 *
AnnaBridge 171:3a7713b1edbc 534 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 535 * @param data needs to be write.
AnnaBridge 171:3a7713b1edbc 536 */
AnnaBridge 171:3a7713b1edbc 537 void SPI_WriteData(SPI_Type *base, uint16_t data);
AnnaBridge 171:3a7713b1edbc 538
AnnaBridge 171:3a7713b1edbc 539 /*!
AnnaBridge 171:3a7713b1edbc 540 * @brief Gets a data from the SPI data register.
AnnaBridge 171:3a7713b1edbc 541 *
AnnaBridge 171:3a7713b1edbc 542 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 543 * @return Data in the register.
AnnaBridge 171:3a7713b1edbc 544 */
AnnaBridge 171:3a7713b1edbc 545 uint16_t SPI_ReadData(SPI_Type *base);
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /*! @} */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /*!
AnnaBridge 171:3a7713b1edbc 550 * @name Transactional
AnnaBridge 171:3a7713b1edbc 551 * @{
AnnaBridge 171:3a7713b1edbc 552 */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /*!
AnnaBridge 171:3a7713b1edbc 555 * @brief Initializes the SPI master handle.
AnnaBridge 171:3a7713b1edbc 556 *
AnnaBridge 171:3a7713b1edbc 557 * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
AnnaBridge 171:3a7713b1edbc 558 * for a specified SPI instance, call this API once to get the initialized handle.
AnnaBridge 171:3a7713b1edbc 559 *
AnnaBridge 171:3a7713b1edbc 560 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 561 * @param handle SPI handle pointer.
AnnaBridge 171:3a7713b1edbc 562 * @param callback Callback function.
AnnaBridge 171:3a7713b1edbc 563 * @param userData User data.
AnnaBridge 171:3a7713b1edbc 564 */
AnnaBridge 171:3a7713b1edbc 565 void SPI_MasterTransferCreateHandle(SPI_Type *base,
AnnaBridge 171:3a7713b1edbc 566 spi_master_handle_t *handle,
AnnaBridge 171:3a7713b1edbc 567 spi_master_callback_t callback,
AnnaBridge 171:3a7713b1edbc 568 void *userData);
AnnaBridge 171:3a7713b1edbc 569
AnnaBridge 171:3a7713b1edbc 570 /*!
AnnaBridge 171:3a7713b1edbc 571 * @brief Transfers a block of data using a polling method.
AnnaBridge 171:3a7713b1edbc 572 *
AnnaBridge 171:3a7713b1edbc 573 * @param base SPI base pointer
AnnaBridge 171:3a7713b1edbc 574 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 575 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 576 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 577 */
AnnaBridge 171:3a7713b1edbc 578 status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 /*!
AnnaBridge 171:3a7713b1edbc 581 * @brief Performs a non-blocking SPI interrupt transfer.
AnnaBridge 171:3a7713b1edbc 582 *
AnnaBridge 171:3a7713b1edbc 583 * @note The API immediately returns after transfer initialization is finished.
AnnaBridge 171:3a7713b1edbc 584 * Call SPI_GetStatusIRQ() to get the transfer status.
AnnaBridge 171:3a7713b1edbc 585 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times of the watermark.
AnnaBridge 171:3a7713b1edbc 586 * Otherwise,
AnnaBridge 171:3a7713b1edbc 587 * the last data may be lost because it cannot generate an interrupt request. Users can also call the functional API to
AnnaBridge 171:3a7713b1edbc 588 * get the last
AnnaBridge 171:3a7713b1edbc 589 * received data.
AnnaBridge 171:3a7713b1edbc 590 *
AnnaBridge 171:3a7713b1edbc 591 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 592 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 593 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 594 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 595 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 596 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
AnnaBridge 171:3a7713b1edbc 597 */
AnnaBridge 171:3a7713b1edbc 598 status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /*!
AnnaBridge 171:3a7713b1edbc 601 * @brief Gets the bytes of the SPI interrupt transferred.
AnnaBridge 171:3a7713b1edbc 602 *
AnnaBridge 171:3a7713b1edbc 603 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 604 * @param handle Pointer to SPI transfer handle, this should be a static variable.
AnnaBridge 171:3a7713b1edbc 605 * @param count Transferred bytes of SPI master.
AnnaBridge 171:3a7713b1edbc 606 * @retval kStatus_SPI_Success Succeed get the transfer count.
AnnaBridge 171:3a7713b1edbc 607 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609 status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /*!
AnnaBridge 171:3a7713b1edbc 612 * @brief Aborts an SPI transfer using interrupt.
AnnaBridge 171:3a7713b1edbc 613 *
AnnaBridge 171:3a7713b1edbc 614 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 615 * @param handle Pointer to SPI transfer handle, this should be a static variable.
AnnaBridge 171:3a7713b1edbc 616 */
AnnaBridge 171:3a7713b1edbc 617 void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 /*!
AnnaBridge 171:3a7713b1edbc 620 * @brief Interrupts the handler for the SPI.
AnnaBridge 171:3a7713b1edbc 621 *
AnnaBridge 171:3a7713b1edbc 622 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 623 * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
AnnaBridge 171:3a7713b1edbc 624 */
AnnaBridge 171:3a7713b1edbc 625 void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /*!
AnnaBridge 171:3a7713b1edbc 628 * @brief Initializes the SPI slave handle.
AnnaBridge 171:3a7713b1edbc 629 *
AnnaBridge 171:3a7713b1edbc 630 * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
AnnaBridge 171:3a7713b1edbc 631 * for a specified SPI instance, call this API once to get the initialized handle.
AnnaBridge 171:3a7713b1edbc 632 *
AnnaBridge 171:3a7713b1edbc 633 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 634 * @param handle SPI handle pointer.
AnnaBridge 171:3a7713b1edbc 635 * @param callback Callback function.
AnnaBridge 171:3a7713b1edbc 636 * @param userData User data.
AnnaBridge 171:3a7713b1edbc 637 */
AnnaBridge 171:3a7713b1edbc 638 void SPI_SlaveTransferCreateHandle(SPI_Type *base,
AnnaBridge 171:3a7713b1edbc 639 spi_slave_handle_t *handle,
AnnaBridge 171:3a7713b1edbc 640 spi_slave_callback_t callback,
AnnaBridge 171:3a7713b1edbc 641 void *userData);
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /*!
AnnaBridge 171:3a7713b1edbc 644 * @brief Performs a non-blocking SPI slave interrupt transfer.
AnnaBridge 171:3a7713b1edbc 645 *
AnnaBridge 171:3a7713b1edbc 646 * @note The API returns immediately after the transfer initialization is finished.
AnnaBridge 171:3a7713b1edbc 647 * Call SPI_GetStatusIRQ() to get the transfer status.
AnnaBridge 171:3a7713b1edbc 648 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times the watermark.
AnnaBridge 171:3a7713b1edbc 649 * Otherwise,
AnnaBridge 171:3a7713b1edbc 650 * the last data may be lost because it cannot generate an interrupt request. Call the functional API to get the last
AnnaBridge 171:3a7713b1edbc 651 * several
AnnaBridge 171:3a7713b1edbc 652 * receive data.
AnnaBridge 171:3a7713b1edbc 653 *
AnnaBridge 171:3a7713b1edbc 654 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 655 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 656 * @param xfer pointer to spi_xfer_config_t structure
AnnaBridge 171:3a7713b1edbc 657 * @retval kStatus_Success Successfully start a transfer.
AnnaBridge 171:3a7713b1edbc 658 * @retval kStatus_InvalidArgument Input argument is invalid.
AnnaBridge 171:3a7713b1edbc 659 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
AnnaBridge 171:3a7713b1edbc 660 */
AnnaBridge 171:3a7713b1edbc 661 static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
AnnaBridge 171:3a7713b1edbc 662 {
AnnaBridge 171:3a7713b1edbc 663 return SPI_MasterTransferNonBlocking(base, handle, xfer);
AnnaBridge 171:3a7713b1edbc 664 }
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /*!
AnnaBridge 171:3a7713b1edbc 667 * @brief Gets the bytes of the SPI interrupt transferred.
AnnaBridge 171:3a7713b1edbc 668 *
AnnaBridge 171:3a7713b1edbc 669 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 670 * @param handle Pointer to SPI transfer handle, this should be a static variable.
AnnaBridge 171:3a7713b1edbc 671 * @param count Transferred bytes of SPI slave.
AnnaBridge 171:3a7713b1edbc 672 * @retval kStatus_SPI_Success Succeed get the transfer count.
AnnaBridge 171:3a7713b1edbc 673 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
AnnaBridge 171:3a7713b1edbc 674 */
AnnaBridge 171:3a7713b1edbc 675 static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
AnnaBridge 171:3a7713b1edbc 676 {
AnnaBridge 171:3a7713b1edbc 677 return SPI_MasterTransferGetCount(base, handle, count);
AnnaBridge 171:3a7713b1edbc 678 }
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /*!
AnnaBridge 171:3a7713b1edbc 681 * @brief Aborts an SPI slave transfer using interrupt.
AnnaBridge 171:3a7713b1edbc 682 *
AnnaBridge 171:3a7713b1edbc 683 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 684 * @param handle Pointer to SPI transfer handle, this should be a static variable.
AnnaBridge 171:3a7713b1edbc 685 */
AnnaBridge 171:3a7713b1edbc 686 static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
AnnaBridge 171:3a7713b1edbc 687 {
AnnaBridge 171:3a7713b1edbc 688 SPI_MasterTransferAbort(base, handle);
AnnaBridge 171:3a7713b1edbc 689 }
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /*!
AnnaBridge 171:3a7713b1edbc 692 * @brief Interrupts a handler for the SPI slave.
AnnaBridge 171:3a7713b1edbc 693 *
AnnaBridge 171:3a7713b1edbc 694 * @param base SPI peripheral base address.
AnnaBridge 171:3a7713b1edbc 695 * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
AnnaBridge 171:3a7713b1edbc 696 */
AnnaBridge 171:3a7713b1edbc 697 void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699 /*! @} */
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 702 }
AnnaBridge 171:3a7713b1edbc 703 #endif
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /*! @} */
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 #endif /* _FSL_SPI_H_*/