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TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processor: MKL25Z128VLK4
AnnaBridge 171:3a7713b1edbc 4 ** Compilers: ARM Compiler
AnnaBridge 171:3a7713b1edbc 5 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 6 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 7 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 8 **
AnnaBridge 171:3a7713b1edbc 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
AnnaBridge 171:3a7713b1edbc 10 ** Version: rev. 1.1, 2012-06-21
AnnaBridge 171:3a7713b1edbc 11 **
AnnaBridge 171:3a7713b1edbc 12 ** Abstract:
AnnaBridge 171:3a7713b1edbc 13 ** CMSIS Peripheral Access Layer for MKL25Z4
AnnaBridge 171:3a7713b1edbc 14 **
AnnaBridge 171:3a7713b1edbc 15 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 16 **
AnnaBridge 171:3a7713b1edbc 17 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 18 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 19 **
AnnaBridge 171:3a7713b1edbc 20 ** Revisions:
AnnaBridge 171:3a7713b1edbc 21 ** - rev. 1.0 (2012-06-13)
AnnaBridge 171:3a7713b1edbc 22 ** Initial version.
AnnaBridge 171:3a7713b1edbc 23 ** - rev. 1.1 (2012-06-21)
AnnaBridge 171:3a7713b1edbc 24 ** Update according to reference manual rev. 1.
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 27 */
AnnaBridge 171:3a7713b1edbc 28
AnnaBridge 171:3a7713b1edbc 29 /**
AnnaBridge 171:3a7713b1edbc 30 * @file MKL25Z4.h
AnnaBridge 171:3a7713b1edbc 31 * @version 1.1
AnnaBridge 171:3a7713b1edbc 32 * @date 2012-06-21
AnnaBridge 171:3a7713b1edbc 33 * @brief CMSIS Peripheral Access Layer for MKL25Z4
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 * CMSIS Peripheral Access Layer for MKL25Z4
AnnaBridge 171:3a7713b1edbc 36 */
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 #if !defined(MKL25Z4_H_)
AnnaBridge 171:3a7713b1edbc 39 #define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 42 * compatible) */
AnnaBridge 171:3a7713b1edbc 43 #define MCU_MEM_MAP_VERSION 0x0100u
AnnaBridge 171:3a7713b1edbc 44 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 45 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 49 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 50 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /**
AnnaBridge 171:3a7713b1edbc 53 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 58 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 59 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 60 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 61 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 62 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 63 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 64 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 67 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
AnnaBridge 171:3a7713b1edbc 68 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
AnnaBridge 171:3a7713b1edbc 69 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
AnnaBridge 171:3a7713b1edbc 70 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
AnnaBridge 171:3a7713b1edbc 71 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
AnnaBridge 171:3a7713b1edbc 72 FTFA_IRQn = 5, /**< FTFA interrupt */
AnnaBridge 171:3a7713b1edbc 73 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
AnnaBridge 171:3a7713b1edbc 74 LLW_IRQn = 7, /**< Low Leakage Wakeup */
AnnaBridge 171:3a7713b1edbc 75 I2C0_IRQn = 8, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 76 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
AnnaBridge 171:3a7713b1edbc 77 SPI0_IRQn = 10, /**< SPI0 interrupt */
AnnaBridge 171:3a7713b1edbc 78 SPI1_IRQn = 11, /**< SPI1 interrupt */
AnnaBridge 171:3a7713b1edbc 79 UART0_IRQn = 12, /**< UART0 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 80 UART1_IRQn = 13, /**< UART1 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 81 UART2_IRQn = 14, /**< UART2 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 82 ADC0_IRQn = 15, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 83 CMP0_IRQn = 16, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 84 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 85 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 86 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 87 RTC_IRQn = 20, /**< RTC interrupt */
AnnaBridge 171:3a7713b1edbc 88 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
AnnaBridge 171:3a7713b1edbc 89 PIT_IRQn = 22, /**< PIT timer interrupt */
AnnaBridge 171:3a7713b1edbc 90 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
AnnaBridge 171:3a7713b1edbc 91 USB0_IRQn = 24, /**< USB0 interrupt */
AnnaBridge 171:3a7713b1edbc 92 DAC0_IRQn = 25, /**< DAC interrupt */
AnnaBridge 171:3a7713b1edbc 93 TSI0_IRQn = 26, /**< TSI0 interrupt */
AnnaBridge 171:3a7713b1edbc 94 MCG_IRQn = 27, /**< MCG interrupt */
AnnaBridge 171:3a7713b1edbc 95 LPTimer_IRQn = 28, /**< LPTimer interrupt */
AnnaBridge 171:3a7713b1edbc 96 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
AnnaBridge 171:3a7713b1edbc 97 PORTA_IRQn = 30, /**< Port A interrupt */
AnnaBridge 171:3a7713b1edbc 98 PORTD_IRQn = 31 /**< Port D interrupt */
AnnaBridge 171:3a7713b1edbc 99 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /**
AnnaBridge 171:3a7713b1edbc 102 * @}
AnnaBridge 171:3a7713b1edbc 103 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 107 -- Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 108 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /**
AnnaBridge 171:3a7713b1edbc 111 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 112 * @{
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
AnnaBridge 171:3a7713b1edbc 116 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 117 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 118 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 119 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 122 #include "system_MKL25Z4.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 * @}
AnnaBridge 171:3a7713b1edbc 126 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 130 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 131 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /**
AnnaBridge 171:3a7713b1edbc 134 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 135 * @{
AnnaBridge 171:3a7713b1edbc 136 */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /*
AnnaBridge 171:3a7713b1edbc 140 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 144 #pragma push
AnnaBridge 171:3a7713b1edbc 145 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 146 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 147 #pragma push
AnnaBridge 171:3a7713b1edbc 148 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 149 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 150 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 151 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 152 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 153 #else
AnnaBridge 171:3a7713b1edbc 154 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 155 #endif
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 158 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 159 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 163 * @{
AnnaBridge 171:3a7713b1edbc 164 */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 167 typedef struct {
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 169 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 170 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 171 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 186 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 194 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 197 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 198 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /**
AnnaBridge 171:3a7713b1edbc 201 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 202 * @{
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /* SC1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 206 #define ADC_SC1_ADCH_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 207 #define ADC_SC1_ADCH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 209 #define ADC_SC1_DIFF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 210 #define ADC_SC1_DIFF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 211 #define ADC_SC1_AIEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 212 #define ADC_SC1_AIEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 213 #define ADC_SC1_COCO_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 214 #define ADC_SC1_COCO_SHIFT 7
AnnaBridge 171:3a7713b1edbc 215 /* CFG1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 216 #define ADC_CFG1_ADICLK_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 217 #define ADC_CFG1_ADICLK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 218 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 219 #define ADC_CFG1_MODE_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 220 #define ADC_CFG1_MODE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 221 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 222 #define ADC_CFG1_ADLSMP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 223 #define ADC_CFG1_ADLSMP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 224 #define ADC_CFG1_ADIV_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 225 #define ADC_CFG1_ADIV_SHIFT 5
AnnaBridge 171:3a7713b1edbc 226 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 227 #define ADC_CFG1_ADLPC_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 228 #define ADC_CFG1_ADLPC_SHIFT 7
AnnaBridge 171:3a7713b1edbc 229 /* CFG2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 230 #define ADC_CFG2_ADLSTS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 231 #define ADC_CFG2_ADLSTS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 232 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 233 #define ADC_CFG2_ADHSC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 234 #define ADC_CFG2_ADHSC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 235 #define ADC_CFG2_ADACKEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 236 #define ADC_CFG2_ADACKEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 237 #define ADC_CFG2_MUXSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 238 #define ADC_CFG2_MUXSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 239 /* R Bit Fields */
AnnaBridge 171:3a7713b1edbc 240 #define ADC_R_D_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 241 #define ADC_R_D_SHIFT 0
AnnaBridge 171:3a7713b1edbc 242 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 243 /* CV1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 244 #define ADC_CV1_CV_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 245 #define ADC_CV1_CV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 246 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 247 /* CV2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 248 #define ADC_CV2_CV_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 249 #define ADC_CV2_CV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 250 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 251 /* SC2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 252 #define ADC_SC2_REFSEL_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 253 #define ADC_SC2_REFSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 254 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 255 #define ADC_SC2_DMAEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 256 #define ADC_SC2_DMAEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 257 #define ADC_SC2_ACREN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 258 #define ADC_SC2_ACREN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 259 #define ADC_SC2_ACFGT_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 260 #define ADC_SC2_ACFGT_SHIFT 4
AnnaBridge 171:3a7713b1edbc 261 #define ADC_SC2_ACFE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 262 #define ADC_SC2_ACFE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 263 #define ADC_SC2_ADTRG_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 264 #define ADC_SC2_ADTRG_SHIFT 6
AnnaBridge 171:3a7713b1edbc 265 #define ADC_SC2_ADACT_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 266 #define ADC_SC2_ADACT_SHIFT 7
AnnaBridge 171:3a7713b1edbc 267 /* SC3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 268 #define ADC_SC3_AVGS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 269 #define ADC_SC3_AVGS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 270 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 271 #define ADC_SC3_AVGE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 272 #define ADC_SC3_AVGE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 273 #define ADC_SC3_ADCO_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 274 #define ADC_SC3_ADCO_SHIFT 3
AnnaBridge 171:3a7713b1edbc 275 #define ADC_SC3_CALF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 276 #define ADC_SC3_CALF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 277 #define ADC_SC3_CAL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 278 #define ADC_SC3_CAL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 279 /* OFS Bit Fields */
AnnaBridge 171:3a7713b1edbc 280 #define ADC_OFS_OFS_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 281 #define ADC_OFS_OFS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 282 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 283 /* PG Bit Fields */
AnnaBridge 171:3a7713b1edbc 284 #define ADC_PG_PG_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 285 #define ADC_PG_PG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 286 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 287 /* MG Bit Fields */
AnnaBridge 171:3a7713b1edbc 288 #define ADC_MG_MG_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 289 #define ADC_MG_MG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 290 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 291 /* CLPD Bit Fields */
AnnaBridge 171:3a7713b1edbc 292 #define ADC_CLPD_CLPD_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 293 #define ADC_CLPD_CLPD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 294 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 295 /* CLPS Bit Fields */
AnnaBridge 171:3a7713b1edbc 296 #define ADC_CLPS_CLPS_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 297 #define ADC_CLPS_CLPS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 298 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 299 /* CLP4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 300 #define ADC_CLP4_CLP4_MASK 0x3FFu
AnnaBridge 171:3a7713b1edbc 301 #define ADC_CLP4_CLP4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 302 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 303 /* CLP3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 304 #define ADC_CLP3_CLP3_MASK 0x1FFu
AnnaBridge 171:3a7713b1edbc 305 #define ADC_CLP3_CLP3_SHIFT 0
AnnaBridge 171:3a7713b1edbc 306 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 307 /* CLP2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 308 #define ADC_CLP2_CLP2_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 309 #define ADC_CLP2_CLP2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 310 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 311 /* CLP1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 312 #define ADC_CLP1_CLP1_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 313 #define ADC_CLP1_CLP1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 314 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 315 /* CLP0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 316 #define ADC_CLP0_CLP0_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 317 #define ADC_CLP0_CLP0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 318 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 319 /* CLMD Bit Fields */
AnnaBridge 171:3a7713b1edbc 320 #define ADC_CLMD_CLMD_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 321 #define ADC_CLMD_CLMD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 322 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 323 /* CLMS Bit Fields */
AnnaBridge 171:3a7713b1edbc 324 #define ADC_CLMS_CLMS_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 325 #define ADC_CLMS_CLMS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 326 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 327 /* CLM4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 328 #define ADC_CLM4_CLM4_MASK 0x3FFu
AnnaBridge 171:3a7713b1edbc 329 #define ADC_CLM4_CLM4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 330 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 331 /* CLM3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 332 #define ADC_CLM3_CLM3_MASK 0x1FFu
AnnaBridge 171:3a7713b1edbc 333 #define ADC_CLM3_CLM3_SHIFT 0
AnnaBridge 171:3a7713b1edbc 334 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 335 /* CLM2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 336 #define ADC_CLM2_CLM2_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 337 #define ADC_CLM2_CLM2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 338 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 339 /* CLM1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 340 #define ADC_CLM1_CLM1_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 341 #define ADC_CLM1_CLM1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 342 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 343 /* CLM0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 344 #define ADC_CLM0_CLM0_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 345 #define ADC_CLM0_CLM0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 346 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /**
AnnaBridge 171:3a7713b1edbc 349 * @}
AnnaBridge 171:3a7713b1edbc 350 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 354 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 355 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 356 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 357 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 358 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 359 #define ADC_BASES { ADC0 }
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /**
AnnaBridge 171:3a7713b1edbc 362 * @}
AnnaBridge 171:3a7713b1edbc 363 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 367 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 368 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 /**
AnnaBridge 171:3a7713b1edbc 371 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 372 * @{
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 376 typedef struct {
AnnaBridge 171:3a7713b1edbc 377 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 378 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 379 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 380 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 381 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 382 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 383 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 386 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 387 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /**
AnnaBridge 171:3a7713b1edbc 390 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 391 * @{
AnnaBridge 171:3a7713b1edbc 392 */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 /* CR0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 395 #define CMP_CR0_HYSTCTR_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 396 #define CMP_CR0_HYSTCTR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 397 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 398 #define CMP_CR0_FILTER_CNT_MASK 0x70u
AnnaBridge 171:3a7713b1edbc 399 #define CMP_CR0_FILTER_CNT_SHIFT 4
AnnaBridge 171:3a7713b1edbc 400 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 401 /* CR1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 402 #define CMP_CR1_EN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 403 #define CMP_CR1_EN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 404 #define CMP_CR1_OPE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 405 #define CMP_CR1_OPE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 406 #define CMP_CR1_COS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 407 #define CMP_CR1_COS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 408 #define CMP_CR1_INV_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 409 #define CMP_CR1_INV_SHIFT 3
AnnaBridge 171:3a7713b1edbc 410 #define CMP_CR1_PMODE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 411 #define CMP_CR1_PMODE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 412 #define CMP_CR1_TRIGM_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 413 #define CMP_CR1_TRIGM_SHIFT 5
AnnaBridge 171:3a7713b1edbc 414 #define CMP_CR1_WE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 415 #define CMP_CR1_WE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 416 #define CMP_CR1_SE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 417 #define CMP_CR1_SE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 418 /* FPR Bit Fields */
AnnaBridge 171:3a7713b1edbc 419 #define CMP_FPR_FILT_PER_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 420 #define CMP_FPR_FILT_PER_SHIFT 0
AnnaBridge 171:3a7713b1edbc 421 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 422 /* SCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 423 #define CMP_SCR_COUT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 424 #define CMP_SCR_COUT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 425 #define CMP_SCR_CFF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 426 #define CMP_SCR_CFF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 427 #define CMP_SCR_CFR_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 428 #define CMP_SCR_CFR_SHIFT 2
AnnaBridge 171:3a7713b1edbc 429 #define CMP_SCR_IEF_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 430 #define CMP_SCR_IEF_SHIFT 3
AnnaBridge 171:3a7713b1edbc 431 #define CMP_SCR_IER_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 432 #define CMP_SCR_IER_SHIFT 4
AnnaBridge 171:3a7713b1edbc 433 #define CMP_SCR_DMAEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 434 #define CMP_SCR_DMAEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 435 /* DACCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 436 #define CMP_DACCR_VOSEL_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 437 #define CMP_DACCR_VOSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 438 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 439 #define CMP_DACCR_VRSEL_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 440 #define CMP_DACCR_VRSEL_SHIFT 6
AnnaBridge 171:3a7713b1edbc 441 #define CMP_DACCR_DACEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 442 #define CMP_DACCR_DACEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 443 /* MUXCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 444 #define CMP_MUXCR_MSEL_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 445 #define CMP_MUXCR_MSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 446 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 447 #define CMP_MUXCR_PSEL_MASK 0x38u
AnnaBridge 171:3a7713b1edbc 448 #define CMP_MUXCR_PSEL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 449 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 450 #define CMP_MUXCR_PSTM_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 451 #define CMP_MUXCR_PSTM_SHIFT 6
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 /**
AnnaBridge 171:3a7713b1edbc 454 * @}
AnnaBridge 171:3a7713b1edbc 455 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 459 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 460 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 461 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 462 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 463 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 464 #define CMP_BASES { CMP0 }
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /**
AnnaBridge 171:3a7713b1edbc 467 * @}
AnnaBridge 171:3a7713b1edbc 468 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 472 -- DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 473 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 474
AnnaBridge 171:3a7713b1edbc 475 /**
AnnaBridge 171:3a7713b1edbc 476 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 477 * @{
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /** DAC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 481 typedef struct {
AnnaBridge 171:3a7713b1edbc 482 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 483 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 484 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 485 } DAT[2];
AnnaBridge 171:3a7713b1edbc 486 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 487 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 488 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 489 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 490 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 491 } DAC_Type;
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 494 -- DAC Register Masks
AnnaBridge 171:3a7713b1edbc 495 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /**
AnnaBridge 171:3a7713b1edbc 498 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 171:3a7713b1edbc 499 * @{
AnnaBridge 171:3a7713b1edbc 500 */
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /* DATL Bit Fields */
AnnaBridge 171:3a7713b1edbc 503 #define DAC_DATL_DATA0_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 504 #define DAC_DATL_DATA0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 505 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
AnnaBridge 171:3a7713b1edbc 506 /* DATH Bit Fields */
AnnaBridge 171:3a7713b1edbc 507 #define DAC_DATH_DATA1_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 508 #define DAC_DATH_DATA1_SHIFT 0
AnnaBridge 171:3a7713b1edbc 509 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
AnnaBridge 171:3a7713b1edbc 510 /* SR Bit Fields */
AnnaBridge 171:3a7713b1edbc 511 #define DAC_SR_DACBFRPBF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 512 #define DAC_SR_DACBFRPBF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 513 #define DAC_SR_DACBFRPTF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 514 #define DAC_SR_DACBFRPTF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 515 /* C0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 516 #define DAC_C0_DACBBIEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 517 #define DAC_C0_DACBBIEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 518 #define DAC_C0_DACBTIEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 519 #define DAC_C0_DACBTIEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 520 #define DAC_C0_LPEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 521 #define DAC_C0_LPEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 522 #define DAC_C0_DACSWTRG_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 523 #define DAC_C0_DACSWTRG_SHIFT 4
AnnaBridge 171:3a7713b1edbc 524 #define DAC_C0_DACTRGSEL_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 525 #define DAC_C0_DACTRGSEL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 526 #define DAC_C0_DACRFS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 527 #define DAC_C0_DACRFS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 528 #define DAC_C0_DACEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 529 #define DAC_C0_DACEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 530 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 531 #define DAC_C1_DACBFEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 532 #define DAC_C1_DACBFEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 533 #define DAC_C1_DACBFMD_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 534 #define DAC_C1_DACBFMD_SHIFT 2
AnnaBridge 171:3a7713b1edbc 535 #define DAC_C1_DMAEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 536 #define DAC_C1_DMAEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 537 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 538 #define DAC_C2_DACBFUP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 539 #define DAC_C2_DACBFUP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 540 #define DAC_C2_DACBFRP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 541 #define DAC_C2_DACBFRP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 /**
AnnaBridge 171:3a7713b1edbc 544 * @}
AnnaBridge 171:3a7713b1edbc 545 */ /* end of group DAC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 /* DAC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 549 /** Peripheral DAC0 base address */
AnnaBridge 171:3a7713b1edbc 550 #define DAC0_BASE (0x4003F000u)
AnnaBridge 171:3a7713b1edbc 551 /** Peripheral DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 552 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 171:3a7713b1edbc 553 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 554 #define DAC_BASES { DAC0 }
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556 /**
AnnaBridge 171:3a7713b1edbc 557 * @}
AnnaBridge 171:3a7713b1edbc 558 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 562 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 563 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 /**
AnnaBridge 171:3a7713b1edbc 566 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 567 * @{
AnnaBridge 171:3a7713b1edbc 568 */
AnnaBridge 171:3a7713b1edbc 569
AnnaBridge 171:3a7713b1edbc 570 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 571 typedef struct {
AnnaBridge 171:3a7713b1edbc 572 union { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 573 __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 574 };
AnnaBridge 171:3a7713b1edbc 575 uint8_t RESERVED_0[252];
AnnaBridge 171:3a7713b1edbc 576 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 577 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 578 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 579 union { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 580 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 581 struct { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 582 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 583 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 584 } DMA_DSR_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 585 };
AnnaBridge 171:3a7713b1edbc 586 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 587 } DMA[4];
AnnaBridge 171:3a7713b1edbc 588 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 591 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 592 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /**
AnnaBridge 171:3a7713b1edbc 595 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 596 * @{
AnnaBridge 171:3a7713b1edbc 597 */
AnnaBridge 171:3a7713b1edbc 598
AnnaBridge 171:3a7713b1edbc 599 /* REQC_ARR Bit Fields */
AnnaBridge 171:3a7713b1edbc 600 #define DMA_REQC_ARR_DMAC_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 601 #define DMA_REQC_ARR_DMAC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 602 #define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
AnnaBridge 171:3a7713b1edbc 603 #define DMA_REQC_ARR_CFSM_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 604 #define DMA_REQC_ARR_CFSM_SHIFT 7
AnnaBridge 171:3a7713b1edbc 605 /* SAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 606 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 607 #define DMA_SAR_SAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 608 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
AnnaBridge 171:3a7713b1edbc 609 /* DAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 610 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 611 #define DMA_DAR_DAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 612 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
AnnaBridge 171:3a7713b1edbc 613 /* DSR_BCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 614 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
AnnaBridge 171:3a7713b1edbc 615 #define DMA_DSR_BCR_BCR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 616 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
AnnaBridge 171:3a7713b1edbc 617 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 618 #define DMA_DSR_BCR_DONE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 619 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 620 #define DMA_DSR_BCR_BSY_SHIFT 25
AnnaBridge 171:3a7713b1edbc 621 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 622 #define DMA_DSR_BCR_REQ_SHIFT 26
AnnaBridge 171:3a7713b1edbc 623 #define DMA_DSR_BCR_BED_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 624 #define DMA_DSR_BCR_BED_SHIFT 28
AnnaBridge 171:3a7713b1edbc 625 #define DMA_DSR_BCR_BES_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 626 #define DMA_DSR_BCR_BES_SHIFT 29
AnnaBridge 171:3a7713b1edbc 627 #define DMA_DSR_BCR_CE_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 628 #define DMA_DSR_BCR_CE_SHIFT 30
AnnaBridge 171:3a7713b1edbc 629 /* DCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 630 #define DMA_DCR_LCH2_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 631 #define DMA_DCR_LCH2_SHIFT 0
AnnaBridge 171:3a7713b1edbc 632 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
AnnaBridge 171:3a7713b1edbc 633 #define DMA_DCR_LCH1_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 634 #define DMA_DCR_LCH1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 635 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
AnnaBridge 171:3a7713b1edbc 636 #define DMA_DCR_LINKCC_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 637 #define DMA_DCR_LINKCC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 638 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
AnnaBridge 171:3a7713b1edbc 639 #define DMA_DCR_D_REQ_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 640 #define DMA_DCR_D_REQ_SHIFT 7
AnnaBridge 171:3a7713b1edbc 641 #define DMA_DCR_DMOD_MASK 0xF00u
AnnaBridge 171:3a7713b1edbc 642 #define DMA_DCR_DMOD_SHIFT 8
AnnaBridge 171:3a7713b1edbc 643 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 644 #define DMA_DCR_SMOD_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 645 #define DMA_DCR_SMOD_SHIFT 12
AnnaBridge 171:3a7713b1edbc 646 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 647 #define DMA_DCR_START_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 648 #define DMA_DCR_START_SHIFT 16
AnnaBridge 171:3a7713b1edbc 649 #define DMA_DCR_DSIZE_MASK 0x60000u
AnnaBridge 171:3a7713b1edbc 650 #define DMA_DCR_DSIZE_SHIFT 17
AnnaBridge 171:3a7713b1edbc 651 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 652 #define DMA_DCR_DINC_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 653 #define DMA_DCR_DINC_SHIFT 19
AnnaBridge 171:3a7713b1edbc 654 #define DMA_DCR_SSIZE_MASK 0x300000u
AnnaBridge 171:3a7713b1edbc 655 #define DMA_DCR_SSIZE_SHIFT 20
AnnaBridge 171:3a7713b1edbc 656 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 657 #define DMA_DCR_SINC_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 658 #define DMA_DCR_SINC_SHIFT 22
AnnaBridge 171:3a7713b1edbc 659 #define DMA_DCR_EADREQ_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 660 #define DMA_DCR_EADREQ_SHIFT 23
AnnaBridge 171:3a7713b1edbc 661 #define DMA_DCR_AA_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 662 #define DMA_DCR_AA_SHIFT 28
AnnaBridge 171:3a7713b1edbc 663 #define DMA_DCR_CS_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 664 #define DMA_DCR_CS_SHIFT 29
AnnaBridge 171:3a7713b1edbc 665 #define DMA_DCR_ERQ_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 666 #define DMA_DCR_ERQ_SHIFT 30
AnnaBridge 171:3a7713b1edbc 667 #define DMA_DCR_EINT_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 668 #define DMA_DCR_EINT_SHIFT 31
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 /**
AnnaBridge 171:3a7713b1edbc 671 * @}
AnnaBridge 171:3a7713b1edbc 672 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674
AnnaBridge 171:3a7713b1edbc 675 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 676 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 677 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 678 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 679 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 680 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 681 #define DMA_BASES { DMA0 }
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /**
AnnaBridge 171:3a7713b1edbc 684 * @}
AnnaBridge 171:3a7713b1edbc 685 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 689 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 690 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 691
AnnaBridge 171:3a7713b1edbc 692 /**
AnnaBridge 171:3a7713b1edbc 693 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 694 * @{
AnnaBridge 171:3a7713b1edbc 695 */
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 698 typedef struct {
AnnaBridge 171:3a7713b1edbc 699 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 700 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 703 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 704 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /**
AnnaBridge 171:3a7713b1edbc 707 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 708 * @{
AnnaBridge 171:3a7713b1edbc 709 */
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /* CHCFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 712 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 713 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 714 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 715 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 716 #define DMAMUX_CHCFG_TRIG_SHIFT 6
AnnaBridge 171:3a7713b1edbc 717 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 718 #define DMAMUX_CHCFG_ENBL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 /**
AnnaBridge 171:3a7713b1edbc 721 * @}
AnnaBridge 171:3a7713b1edbc 722 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 726 /** Peripheral DMAMUX0 base address */
AnnaBridge 171:3a7713b1edbc 727 #define DMAMUX0_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 728 /** Peripheral DMAMUX0 base pointer */
AnnaBridge 171:3a7713b1edbc 729 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
AnnaBridge 171:3a7713b1edbc 730 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 731 #define DMAMUX_BASES { DMAMUX0 }
AnnaBridge 171:3a7713b1edbc 732
AnnaBridge 171:3a7713b1edbc 733 /**
AnnaBridge 171:3a7713b1edbc 734 * @}
AnnaBridge 171:3a7713b1edbc 735 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 739 -- FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 740 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 /**
AnnaBridge 171:3a7713b1edbc 743 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 744 * @{
AnnaBridge 171:3a7713b1edbc 745 */
AnnaBridge 171:3a7713b1edbc 746
AnnaBridge 171:3a7713b1edbc 747 /** FGPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 748 typedef struct {
AnnaBridge 171:3a7713b1edbc 749 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 750 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 751 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 752 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 753 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 754 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 755 } FGPIO_Type;
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 758 -- FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 759 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 /**
AnnaBridge 171:3a7713b1edbc 762 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 763 * @{
AnnaBridge 171:3a7713b1edbc 764 */
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766 /* PDOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 767 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 768 #define FGPIO_PDOR_PDO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 769 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 770 /* PSOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 771 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 772 #define FGPIO_PSOR_PTSO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 773 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 774 /* PCOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 775 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 776 #define FGPIO_PCOR_PTCO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 777 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 778 /* PTOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 779 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 780 #define FGPIO_PTOR_PTTO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 781 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 782 /* PDIR Bit Fields */
AnnaBridge 171:3a7713b1edbc 783 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 784 #define FGPIO_PDIR_PDI_SHIFT 0
AnnaBridge 171:3a7713b1edbc 785 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 786 /* PDDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 787 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 788 #define FGPIO_PDDR_PDD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 789 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 /**
AnnaBridge 171:3a7713b1edbc 792 * @}
AnnaBridge 171:3a7713b1edbc 793 */ /* end of group FGPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 794
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /* FGPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 797 /** Peripheral FPTA base address */
AnnaBridge 171:3a7713b1edbc 798 #define FPTA_BASE (0xF80FF000u)
AnnaBridge 171:3a7713b1edbc 799 /** Peripheral FPTA base pointer */
AnnaBridge 171:3a7713b1edbc 800 #define FPTA ((FGPIO_Type *)FPTA_BASE)
AnnaBridge 171:3a7713b1edbc 801 /** Peripheral FPTB base address */
AnnaBridge 171:3a7713b1edbc 802 #define FPTB_BASE (0xF80FF040u)
AnnaBridge 171:3a7713b1edbc 803 /** Peripheral FPTB base pointer */
AnnaBridge 171:3a7713b1edbc 804 #define FPTB ((FGPIO_Type *)FPTB_BASE)
AnnaBridge 171:3a7713b1edbc 805 /** Peripheral FPTC base address */
AnnaBridge 171:3a7713b1edbc 806 #define FPTC_BASE (0xF80FF080u)
AnnaBridge 171:3a7713b1edbc 807 /** Peripheral FPTC base pointer */
AnnaBridge 171:3a7713b1edbc 808 #define FPTC ((FGPIO_Type *)FPTC_BASE)
AnnaBridge 171:3a7713b1edbc 809 /** Peripheral FPTD base address */
AnnaBridge 171:3a7713b1edbc 810 #define FPTD_BASE (0xF80FF0C0u)
AnnaBridge 171:3a7713b1edbc 811 /** Peripheral FPTD base pointer */
AnnaBridge 171:3a7713b1edbc 812 #define FPTD ((FGPIO_Type *)FPTD_BASE)
AnnaBridge 171:3a7713b1edbc 813 /** Peripheral FPTE base address */
AnnaBridge 171:3a7713b1edbc 814 #define FPTE_BASE (0xF80FF100u)
AnnaBridge 171:3a7713b1edbc 815 /** Peripheral FPTE base pointer */
AnnaBridge 171:3a7713b1edbc 816 #define FPTE ((FGPIO_Type *)FPTE_BASE)
AnnaBridge 171:3a7713b1edbc 817 /** Array initializer of FGPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 818 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820 /**
AnnaBridge 171:3a7713b1edbc 821 * @}
AnnaBridge 171:3a7713b1edbc 822 */ /* end of group FGPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 823
AnnaBridge 171:3a7713b1edbc 824
AnnaBridge 171:3a7713b1edbc 825 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 826 -- FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 827 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 828
AnnaBridge 171:3a7713b1edbc 829 /**
AnnaBridge 171:3a7713b1edbc 830 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 831 * @{
AnnaBridge 171:3a7713b1edbc 832 */
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 /** FTFA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 835 typedef struct {
AnnaBridge 171:3a7713b1edbc 836 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 837 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 838 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 839 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 840 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 841 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 842 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 843 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 844 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 845 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 846 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 847 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 848 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 849 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 850 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 851 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 852 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 853 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 854 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 855 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 856 } FTFA_Type;
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 859 -- FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 860 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 /**
AnnaBridge 171:3a7713b1edbc 863 * @addtogroup FTFA_Register_Masks FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 864 * @{
AnnaBridge 171:3a7713b1edbc 865 */
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /* FSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 868 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 869 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 870 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 871 #define FTFA_FSTAT_FPVIOL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 872 #define FTFA_FSTAT_ACCERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 873 #define FTFA_FSTAT_ACCERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 874 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 875 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
AnnaBridge 171:3a7713b1edbc 876 #define FTFA_FSTAT_CCIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 877 #define FTFA_FSTAT_CCIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 878 /* FCNFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 879 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 880 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 881 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 882 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
AnnaBridge 171:3a7713b1edbc 883 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 884 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 885 #define FTFA_FCNFG_CCIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 886 #define FTFA_FCNFG_CCIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 887 /* FSEC Bit Fields */
AnnaBridge 171:3a7713b1edbc 888 #define FTFA_FSEC_SEC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 889 #define FTFA_FSEC_SEC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 890 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 891 #define FTFA_FSEC_FSLACC_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 892 #define FTFA_FSEC_FSLACC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 893 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 894 #define FTFA_FSEC_MEEN_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 895 #define FTFA_FSEC_MEEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 896 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 897 #define FTFA_FSEC_KEYEN_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 898 #define FTFA_FSEC_KEYEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 899 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 900 /* FOPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 901 #define FTFA_FOPT_OPT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 902 #define FTFA_FOPT_OPT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 903 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 904 /* FCCOB3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 905 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 906 #define FTFA_FCCOB3_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 907 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 908 /* FCCOB2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 909 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 910 #define FTFA_FCCOB2_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 911 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 912 /* FCCOB1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 913 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 914 #define FTFA_FCCOB1_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 915 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 916 /* FCCOB0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 917 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 918 #define FTFA_FCCOB0_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 919 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 920 /* FCCOB7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 921 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 922 #define FTFA_FCCOB7_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 923 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 924 /* FCCOB6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 925 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 926 #define FTFA_FCCOB6_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 927 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 928 /* FCCOB5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 929 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 930 #define FTFA_FCCOB5_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 931 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 932 /* FCCOB4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 933 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 934 #define FTFA_FCCOB4_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 935 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 936 /* FCCOBB Bit Fields */
AnnaBridge 171:3a7713b1edbc 937 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 938 #define FTFA_FCCOBB_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 939 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 940 /* FCCOBA Bit Fields */
AnnaBridge 171:3a7713b1edbc 941 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 942 #define FTFA_FCCOBA_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 943 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 944 /* FCCOB9 Bit Fields */
AnnaBridge 171:3a7713b1edbc 945 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 946 #define FTFA_FCCOB9_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 947 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 948 /* FCCOB8 Bit Fields */
AnnaBridge 171:3a7713b1edbc 949 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 950 #define FTFA_FCCOB8_CCOBn_SHIFT 0
AnnaBridge 171:3a7713b1edbc 951 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 952 /* FPROT3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 953 #define FTFA_FPROT3_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 954 #define FTFA_FPROT3_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 955 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 956 /* FPROT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 957 #define FTFA_FPROT2_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 958 #define FTFA_FPROT2_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 959 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 960 /* FPROT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 961 #define FTFA_FPROT1_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 962 #define FTFA_FPROT1_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 963 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 964 /* FPROT0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 965 #define FTFA_FPROT0_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 966 #define FTFA_FPROT0_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 967 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 968
AnnaBridge 171:3a7713b1edbc 969 /**
AnnaBridge 171:3a7713b1edbc 970 * @}
AnnaBridge 171:3a7713b1edbc 971 */ /* end of group FTFA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 972
AnnaBridge 171:3a7713b1edbc 973
AnnaBridge 171:3a7713b1edbc 974 /* FTFA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 975 /** Peripheral FTFA base address */
AnnaBridge 171:3a7713b1edbc 976 #define FTFA_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 977 /** Peripheral FTFA base pointer */
AnnaBridge 171:3a7713b1edbc 978 #define FTFA ((FTFA_Type *)FTFA_BASE)
AnnaBridge 171:3a7713b1edbc 979 /** Array initializer of FTFA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 980 #define FTFA_BASES { FTFA }
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 /**
AnnaBridge 171:3a7713b1edbc 983 * @}
AnnaBridge 171:3a7713b1edbc 984 */ /* end of group FTFA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 985
AnnaBridge 171:3a7713b1edbc 986
AnnaBridge 171:3a7713b1edbc 987 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 988 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 989 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 990
AnnaBridge 171:3a7713b1edbc 991 /**
AnnaBridge 171:3a7713b1edbc 992 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 993 * @{
AnnaBridge 171:3a7713b1edbc 994 */
AnnaBridge 171:3a7713b1edbc 995
AnnaBridge 171:3a7713b1edbc 996 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 997 typedef struct {
AnnaBridge 171:3a7713b1edbc 998 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 999 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1000 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1001 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1002 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1003 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1004 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1007 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1008 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010 /**
AnnaBridge 171:3a7713b1edbc 1011 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1012 * @{
AnnaBridge 171:3a7713b1edbc 1013 */
AnnaBridge 171:3a7713b1edbc 1014
AnnaBridge 171:3a7713b1edbc 1015 /* PDOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1016 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1017 #define GPIO_PDOR_PDO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1018 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 1019 /* PSOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1020 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1021 #define GPIO_PSOR_PTSO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1022 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 1023 /* PCOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1024 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1025 #define GPIO_PCOR_PTCO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1026 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 1027 /* PTOR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1028 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1029 #define GPIO_PTOR_PTTO_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1030 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 1031 /* PDIR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1032 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1033 #define GPIO_PDIR_PDI_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1034 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 1035 /* PDDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1036 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1037 #define GPIO_PDDR_PDD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1038 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 1039
AnnaBridge 171:3a7713b1edbc 1040 /**
AnnaBridge 171:3a7713b1edbc 1041 * @}
AnnaBridge 171:3a7713b1edbc 1042 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1046 /** Peripheral PTA base address */
AnnaBridge 171:3a7713b1edbc 1047 #define PTA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 1048 /** Peripheral PTA base pointer */
AnnaBridge 171:3a7713b1edbc 1049 #define PTA ((GPIO_Type *)PTA_BASE)
AnnaBridge 171:3a7713b1edbc 1050 /** Peripheral PTB base address */
AnnaBridge 171:3a7713b1edbc 1051 #define PTB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 1052 /** Peripheral PTB base pointer */
AnnaBridge 171:3a7713b1edbc 1053 #define PTB ((GPIO_Type *)PTB_BASE)
AnnaBridge 171:3a7713b1edbc 1054 /** Peripheral PTC base address */
AnnaBridge 171:3a7713b1edbc 1055 #define PTC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 1056 /** Peripheral PTC base pointer */
AnnaBridge 171:3a7713b1edbc 1057 #define PTC ((GPIO_Type *)PTC_BASE)
AnnaBridge 171:3a7713b1edbc 1058 /** Peripheral PTD base address */
AnnaBridge 171:3a7713b1edbc 1059 #define PTD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 1060 /** Peripheral PTD base pointer */
AnnaBridge 171:3a7713b1edbc 1061 #define PTD ((GPIO_Type *)PTD_BASE)
AnnaBridge 171:3a7713b1edbc 1062 /** Peripheral PTE base address */
AnnaBridge 171:3a7713b1edbc 1063 #define PTE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 1064 /** Peripheral PTE base pointer */
AnnaBridge 171:3a7713b1edbc 1065 #define PTE ((GPIO_Type *)PTE_BASE)
AnnaBridge 171:3a7713b1edbc 1066 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1067 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
AnnaBridge 171:3a7713b1edbc 1068
AnnaBridge 171:3a7713b1edbc 1069 /**
AnnaBridge 171:3a7713b1edbc 1070 * @}
AnnaBridge 171:3a7713b1edbc 1071 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1072
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1075 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1076 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1077
AnnaBridge 171:3a7713b1edbc 1078 /**
AnnaBridge 171:3a7713b1edbc 1079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1080 * @{
AnnaBridge 171:3a7713b1edbc 1081 */
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1084 typedef struct {
AnnaBridge 171:3a7713b1edbc 1085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1097 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 1098
AnnaBridge 171:3a7713b1edbc 1099 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1100 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1101 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1102
AnnaBridge 171:3a7713b1edbc 1103 /**
AnnaBridge 171:3a7713b1edbc 1104 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1105 * @{
AnnaBridge 171:3a7713b1edbc 1106 */
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /* A1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1109 #define I2C_A1_AD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1110 #define I2C_A1_AD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1111 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1112 /* F Bit Fields */
AnnaBridge 171:3a7713b1edbc 1113 #define I2C_F_ICR_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 1114 #define I2C_F_ICR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1115 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 1116 #define I2C_F_MULT_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1117 #define I2C_F_MULT_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1118 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 1119 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1120 #define I2C_C1_DMAEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1121 #define I2C_C1_DMAEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1122 #define I2C_C1_WUEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1123 #define I2C_C1_WUEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1124 #define I2C_C1_RSTA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1125 #define I2C_C1_RSTA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1126 #define I2C_C1_TXAK_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1127 #define I2C_C1_TXAK_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1128 #define I2C_C1_TX_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1129 #define I2C_C1_TX_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1130 #define I2C_C1_MST_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1131 #define I2C_C1_MST_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1132 #define I2C_C1_IICIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1133 #define I2C_C1_IICIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1134 #define I2C_C1_IICEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1135 #define I2C_C1_IICEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1136 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 1137 #define I2C_S_RXAK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1138 #define I2C_S_RXAK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1139 #define I2C_S_IICIF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1140 #define I2C_S_IICIF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1141 #define I2C_S_SRW_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1142 #define I2C_S_SRW_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1143 #define I2C_S_RAM_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1144 #define I2C_S_RAM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1145 #define I2C_S_ARBL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1146 #define I2C_S_ARBL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1147 #define I2C_S_BUSY_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1148 #define I2C_S_BUSY_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1149 #define I2C_S_IAAS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1150 #define I2C_S_IAAS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1151 #define I2C_S_TCF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1152 #define I2C_S_TCF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1153 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 1154 #define I2C_D_DATA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1155 #define I2C_D_DATA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1156 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 1157 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1158 #define I2C_C2_AD_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 1159 #define I2C_C2_AD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1160 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1161 #define I2C_C2_RMEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1162 #define I2C_C2_RMEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1163 #define I2C_C2_SBRC_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1164 #define I2C_C2_SBRC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1165 #define I2C_C2_HDRS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1166 #define I2C_C2_HDRS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1167 #define I2C_C2_ADEXT_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1168 #define I2C_C2_ADEXT_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1169 #define I2C_C2_GCAEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1170 #define I2C_C2_GCAEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1171 /* FLT Bit Fields */
AnnaBridge 171:3a7713b1edbc 1172 #define I2C_FLT_FLT_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1173 #define I2C_FLT_FLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1174 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 1175 #define I2C_FLT_STOPIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1176 #define I2C_FLT_STOPIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1177 #define I2C_FLT_STOPF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1178 #define I2C_FLT_STOPF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1179 #define I2C_FLT_SHEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1180 #define I2C_FLT_SHEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1181 /* RA Bit Fields */
AnnaBridge 171:3a7713b1edbc 1182 #define I2C_RA_RAD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1183 #define I2C_RA_RAD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1184 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 1185 /* SMB Bit Fields */
AnnaBridge 171:3a7713b1edbc 1186 #define I2C_SMB_SHTF2IE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1187 #define I2C_SMB_SHTF2IE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1188 #define I2C_SMB_SHTF2_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1189 #define I2C_SMB_SHTF2_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1190 #define I2C_SMB_SHTF1_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1191 #define I2C_SMB_SHTF1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1192 #define I2C_SMB_SLTF_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1193 #define I2C_SMB_SLTF_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1194 #define I2C_SMB_TCKSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1195 #define I2C_SMB_TCKSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1196 #define I2C_SMB_SIICAEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1197 #define I2C_SMB_SIICAEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1198 #define I2C_SMB_ALERTEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1199 #define I2C_SMB_ALERTEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1200 #define I2C_SMB_FACK_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1201 #define I2C_SMB_FACK_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1202 /* A2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1203 #define I2C_A2_SAD_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 1204 #define I2C_A2_SAD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1205 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 1206 /* SLTH Bit Fields */
AnnaBridge 171:3a7713b1edbc 1207 #define I2C_SLTH_SSLT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1208 #define I2C_SLTH_SSLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1209 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1210 /* SLTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1211 #define I2C_SLTL_SSLT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1212 #define I2C_SLTL_SSLT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1213 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 /**
AnnaBridge 171:3a7713b1edbc 1216 * @}
AnnaBridge 171:3a7713b1edbc 1217 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1218
AnnaBridge 171:3a7713b1edbc 1219
AnnaBridge 171:3a7713b1edbc 1220 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1221 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 1222 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 1223 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 1224 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 1225 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 1226 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 1227 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 1228 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 1229 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1230 #define I2C_BASES { I2C0, I2C1 }
AnnaBridge 171:3a7713b1edbc 1231
AnnaBridge 171:3a7713b1edbc 1232 /**
AnnaBridge 171:3a7713b1edbc 1233 * @}
AnnaBridge 171:3a7713b1edbc 1234 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1235
AnnaBridge 171:3a7713b1edbc 1236
AnnaBridge 171:3a7713b1edbc 1237 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1238 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1239 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1240
AnnaBridge 171:3a7713b1edbc 1241 /**
AnnaBridge 171:3a7713b1edbc 1242 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1243 * @{
AnnaBridge 171:3a7713b1edbc 1244 */
AnnaBridge 171:3a7713b1edbc 1245
AnnaBridge 171:3a7713b1edbc 1246 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1247 typedef struct {
AnnaBridge 171:3a7713b1edbc 1248 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1249 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1250 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1251 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1252 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1253 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1254 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1255 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1256 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1257 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1258 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 1259
AnnaBridge 171:3a7713b1edbc 1260 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1261 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 1262 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1263
AnnaBridge 171:3a7713b1edbc 1264 /**
AnnaBridge 171:3a7713b1edbc 1265 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 1266 * @{
AnnaBridge 171:3a7713b1edbc 1267 */
AnnaBridge 171:3a7713b1edbc 1268
AnnaBridge 171:3a7713b1edbc 1269 /* PE1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1270 #define LLWU_PE1_WUPE0_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1271 #define LLWU_PE1_WUPE0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1272 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 1273 #define LLWU_PE1_WUPE1_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 1274 #define LLWU_PE1_WUPE1_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1275 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 1276 #define LLWU_PE1_WUPE2_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1277 #define LLWU_PE1_WUPE2_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1278 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 1279 #define LLWU_PE1_WUPE3_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1280 #define LLWU_PE1_WUPE3_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1281 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 1282 /* PE2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1283 #define LLWU_PE2_WUPE4_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1284 #define LLWU_PE2_WUPE4_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1285 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 1286 #define LLWU_PE2_WUPE5_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 1287 #define LLWU_PE2_WUPE5_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1288 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 1289 #define LLWU_PE2_WUPE6_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1290 #define LLWU_PE2_WUPE6_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1291 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 1292 #define LLWU_PE2_WUPE7_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1293 #define LLWU_PE2_WUPE7_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1294 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 1295 /* PE3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1296 #define LLWU_PE3_WUPE8_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1297 #define LLWU_PE3_WUPE8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1298 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 1299 #define LLWU_PE3_WUPE9_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 1300 #define LLWU_PE3_WUPE9_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1301 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 1302 #define LLWU_PE3_WUPE10_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1303 #define LLWU_PE3_WUPE10_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1304 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 1305 #define LLWU_PE3_WUPE11_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1306 #define LLWU_PE3_WUPE11_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1307 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 1308 /* PE4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1309 #define LLWU_PE4_WUPE12_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1310 #define LLWU_PE4_WUPE12_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1311 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 1312 #define LLWU_PE4_WUPE13_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 1313 #define LLWU_PE4_WUPE13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1314 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 1315 #define LLWU_PE4_WUPE14_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1316 #define LLWU_PE4_WUPE14_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1317 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 1318 #define LLWU_PE4_WUPE15_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1319 #define LLWU_PE4_WUPE15_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1320 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 1321 /* ME Bit Fields */
AnnaBridge 171:3a7713b1edbc 1322 #define LLWU_ME_WUME0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1323 #define LLWU_ME_WUME0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1324 #define LLWU_ME_WUME1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1325 #define LLWU_ME_WUME1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1326 #define LLWU_ME_WUME2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1327 #define LLWU_ME_WUME2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1328 #define LLWU_ME_WUME3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1329 #define LLWU_ME_WUME3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1330 #define LLWU_ME_WUME4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1331 #define LLWU_ME_WUME4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1332 #define LLWU_ME_WUME5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1333 #define LLWU_ME_WUME5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1334 #define LLWU_ME_WUME6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1335 #define LLWU_ME_WUME6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1336 #define LLWU_ME_WUME7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1337 #define LLWU_ME_WUME7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1338 /* F1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1339 #define LLWU_F1_WUF0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1340 #define LLWU_F1_WUF0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1341 #define LLWU_F1_WUF1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1342 #define LLWU_F1_WUF1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1343 #define LLWU_F1_WUF2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1344 #define LLWU_F1_WUF2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1345 #define LLWU_F1_WUF3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1346 #define LLWU_F1_WUF3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1347 #define LLWU_F1_WUF4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1348 #define LLWU_F1_WUF4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1349 #define LLWU_F1_WUF5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1350 #define LLWU_F1_WUF5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1351 #define LLWU_F1_WUF6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1352 #define LLWU_F1_WUF6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1353 #define LLWU_F1_WUF7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1354 #define LLWU_F1_WUF7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1355 /* F2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1356 #define LLWU_F2_WUF8_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1357 #define LLWU_F2_WUF8_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1358 #define LLWU_F2_WUF9_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1359 #define LLWU_F2_WUF9_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1360 #define LLWU_F2_WUF10_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1361 #define LLWU_F2_WUF10_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1362 #define LLWU_F2_WUF11_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1363 #define LLWU_F2_WUF11_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1364 #define LLWU_F2_WUF12_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1365 #define LLWU_F2_WUF12_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1366 #define LLWU_F2_WUF13_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1367 #define LLWU_F2_WUF13_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1368 #define LLWU_F2_WUF14_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1369 #define LLWU_F2_WUF14_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1370 #define LLWU_F2_WUF15_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1371 #define LLWU_F2_WUF15_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1372 /* F3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1373 #define LLWU_F3_MWUF0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1374 #define LLWU_F3_MWUF0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1375 #define LLWU_F3_MWUF1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1376 #define LLWU_F3_MWUF1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1377 #define LLWU_F3_MWUF2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1378 #define LLWU_F3_MWUF2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1379 #define LLWU_F3_MWUF3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1380 #define LLWU_F3_MWUF3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1381 #define LLWU_F3_MWUF4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1382 #define LLWU_F3_MWUF4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1383 #define LLWU_F3_MWUF5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1384 #define LLWU_F3_MWUF5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1385 #define LLWU_F3_MWUF6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1386 #define LLWU_F3_MWUF6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1387 #define LLWU_F3_MWUF7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1388 #define LLWU_F3_MWUF7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1389 /* FILT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1390 #define LLWU_FILT1_FILTSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 1391 #define LLWU_FILT1_FILTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1392 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1393 #define LLWU_FILT1_FILTE_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 1394 #define LLWU_FILT1_FILTE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1395 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 1396 #define LLWU_FILT1_FILTF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1397 #define LLWU_FILT1_FILTF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1398 /* FILT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1399 #define LLWU_FILT2_FILTSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 1400 #define LLWU_FILT2_FILTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1401 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1402 #define LLWU_FILT2_FILTE_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 1403 #define LLWU_FILT2_FILTE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1404 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 1405 #define LLWU_FILT2_FILTF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1406 #define LLWU_FILT2_FILTF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1407
AnnaBridge 171:3a7713b1edbc 1408 /**
AnnaBridge 171:3a7713b1edbc 1409 * @}
AnnaBridge 171:3a7713b1edbc 1410 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1411
AnnaBridge 171:3a7713b1edbc 1412
AnnaBridge 171:3a7713b1edbc 1413 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1414 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 1415 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 1416 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 1417 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 1418 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1419 #define LLWU_BASES { LLWU }
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421 /**
AnnaBridge 171:3a7713b1edbc 1422 * @}
AnnaBridge 171:3a7713b1edbc 1423 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1424
AnnaBridge 171:3a7713b1edbc 1425
AnnaBridge 171:3a7713b1edbc 1426 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1427 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1428 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1429
AnnaBridge 171:3a7713b1edbc 1430 /**
AnnaBridge 171:3a7713b1edbc 1431 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1432 * @{
AnnaBridge 171:3a7713b1edbc 1433 */
AnnaBridge 171:3a7713b1edbc 1434
AnnaBridge 171:3a7713b1edbc 1435 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1436 typedef struct {
AnnaBridge 171:3a7713b1edbc 1437 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1438 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1439 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1440 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1441 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 1442
AnnaBridge 171:3a7713b1edbc 1443 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1444 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 1445 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1446
AnnaBridge 171:3a7713b1edbc 1447 /**
AnnaBridge 171:3a7713b1edbc 1448 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 1449 * @{
AnnaBridge 171:3a7713b1edbc 1450 */
AnnaBridge 171:3a7713b1edbc 1451
AnnaBridge 171:3a7713b1edbc 1452 /* CSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1453 #define LPTMR_CSR_TEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1454 #define LPTMR_CSR_TEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1455 #define LPTMR_CSR_TMS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1456 #define LPTMR_CSR_TMS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1457 #define LPTMR_CSR_TFC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1458 #define LPTMR_CSR_TFC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1459 #define LPTMR_CSR_TPP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1460 #define LPTMR_CSR_TPP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1461 #define LPTMR_CSR_TPS_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1462 #define LPTMR_CSR_TPS_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1463 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 1464 #define LPTMR_CSR_TIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1465 #define LPTMR_CSR_TIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1466 #define LPTMR_CSR_TCF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1467 #define LPTMR_CSR_TCF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1468 /* PSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1469 #define LPTMR_PSR_PCS_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 1470 #define LPTMR_PSR_PCS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1471 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 1472 #define LPTMR_PSR_PBYP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1473 #define LPTMR_PSR_PBYP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1474 #define LPTMR_PSR_PRESCALE_MASK 0x78u
AnnaBridge 171:3a7713b1edbc 1475 #define LPTMR_PSR_PRESCALE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1476 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 1477 /* CMR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1478 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 1479 #define LPTMR_CMR_COMPARE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1480 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 1481 /* CNR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1482 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 1483 #define LPTMR_CNR_COUNTER_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1484 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 /**
AnnaBridge 171:3a7713b1edbc 1487 * @}
AnnaBridge 171:3a7713b1edbc 1488 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1489
AnnaBridge 171:3a7713b1edbc 1490
AnnaBridge 171:3a7713b1edbc 1491 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1492 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 1493 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 1494 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 1495 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 1496 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1497 #define LPTMR_BASES { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 1498
AnnaBridge 171:3a7713b1edbc 1499 /**
AnnaBridge 171:3a7713b1edbc 1500 * @}
AnnaBridge 171:3a7713b1edbc 1501 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1502
AnnaBridge 171:3a7713b1edbc 1503
AnnaBridge 171:3a7713b1edbc 1504 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1505 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1506 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1507
AnnaBridge 171:3a7713b1edbc 1508 /**
AnnaBridge 171:3a7713b1edbc 1509 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1510 * @{
AnnaBridge 171:3a7713b1edbc 1511 */
AnnaBridge 171:3a7713b1edbc 1512
AnnaBridge 171:3a7713b1edbc 1513 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1514 typedef struct {
AnnaBridge 171:3a7713b1edbc 1515 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1516 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1517 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1518 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1519 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1520 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1521 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1522 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 1523 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1524 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 1525 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1526 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1527 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1528 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 1529 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 1530 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 1531 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 1532
AnnaBridge 171:3a7713b1edbc 1533 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1534 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 1535 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1536
AnnaBridge 171:3a7713b1edbc 1537 /**
AnnaBridge 171:3a7713b1edbc 1538 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 1539 * @{
AnnaBridge 171:3a7713b1edbc 1540 */
AnnaBridge 171:3a7713b1edbc 1541
AnnaBridge 171:3a7713b1edbc 1542 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1543 #define MCG_C1_IREFSTEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1544 #define MCG_C1_IREFSTEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1545 #define MCG_C1_IRCLKEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1546 #define MCG_C1_IRCLKEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1547 #define MCG_C1_IREFS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1548 #define MCG_C1_IREFS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1549 #define MCG_C1_FRDIV_MASK 0x38u
AnnaBridge 171:3a7713b1edbc 1550 #define MCG_C1_FRDIV_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1551 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1552 #define MCG_C1_CLKS_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 1553 #define MCG_C1_CLKS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1554 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 1555 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1556 #define MCG_C2_IRCS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1557 #define MCG_C2_IRCS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1558 #define MCG_C2_LP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1559 #define MCG_C2_LP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1560 #define MCG_C2_EREFS0_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1561 #define MCG_C2_EREFS0_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1562 #define MCG_C2_HGO0_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1563 #define MCG_C2_HGO0_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1564 #define MCG_C2_RANGE0_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 1565 #define MCG_C2_RANGE0_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1566 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
AnnaBridge 171:3a7713b1edbc 1567 #define MCG_C2_LOCRE0_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1568 #define MCG_C2_LOCRE0_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1569 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1570 #define MCG_C3_SCTRIM_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1571 #define MCG_C3_SCTRIM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1572 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 1573 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1574 #define MCG_C4_SCFTRIM_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1575 #define MCG_C4_SCFTRIM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1576 #define MCG_C4_FCTRIM_MASK 0x1Eu
AnnaBridge 171:3a7713b1edbc 1577 #define MCG_C4_FCTRIM_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1578 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 1579 #define MCG_C4_DRST_DRS_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 1580 #define MCG_C4_DRST_DRS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1581 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 1582 #define MCG_C4_DMX32_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1583 #define MCG_C4_DMX32_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1584 /* C5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1585 #define MCG_C5_PRDIV0_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1586 #define MCG_C5_PRDIV0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1587 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 1588 #define MCG_C5_PLLSTEN0_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1589 #define MCG_C5_PLLSTEN0_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1590 #define MCG_C5_PLLCLKEN0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1591 #define MCG_C5_PLLCLKEN0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1592 /* C6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1593 #define MCG_C6_VDIV0_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1594 #define MCG_C6_VDIV0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1595 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 1596 #define MCG_C6_CME0_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1597 #define MCG_C6_CME0_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1598 #define MCG_C6_PLLS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1599 #define MCG_C6_PLLS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1600 #define MCG_C6_LOLIE0_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1601 #define MCG_C6_LOLIE0_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1602 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 1603 #define MCG_S_IRCST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1604 #define MCG_S_IRCST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1605 #define MCG_S_OSCINIT0_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1606 #define MCG_S_OSCINIT0_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1607 #define MCG_S_CLKST_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 1608 #define MCG_S_CLKST_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1609 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 1610 #define MCG_S_IREFST_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1611 #define MCG_S_IREFST_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1612 #define MCG_S_PLLST_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1613 #define MCG_S_PLLST_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1614 #define MCG_S_LOCK0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1615 #define MCG_S_LOCK0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1616 #define MCG_S_LOLS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1617 #define MCG_S_LOLS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1618 /* SC Bit Fields */
AnnaBridge 171:3a7713b1edbc 1619 #define MCG_SC_LOCS0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1620 #define MCG_SC_LOCS0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1621 #define MCG_SC_FCRDIV_MASK 0xEu
AnnaBridge 171:3a7713b1edbc 1622 #define MCG_SC_FCRDIV_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1623 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1624 #define MCG_SC_FLTPRSRV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 1625 #define MCG_SC_FLTPRSRV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 1626 #define MCG_SC_ATMF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1627 #define MCG_SC_ATMF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1628 #define MCG_SC_ATMS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1629 #define MCG_SC_ATMS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1630 #define MCG_SC_ATME_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1631 #define MCG_SC_ATME_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1632 /* ATCVH Bit Fields */
AnnaBridge 171:3a7713b1edbc 1633 #define MCG_ATCVH_ATCVH_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1634 #define MCG_ATCVH_ATCVH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1635 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 1636 /* ATCVL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1637 #define MCG_ATCVL_ATCVL_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1638 #define MCG_ATCVL_ATCVL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1639 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 1640 /* C8 Bit Fields */
AnnaBridge 171:3a7713b1edbc 1641 #define MCG_C8_LOLRE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1642 #define MCG_C8_LOLRE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1643
AnnaBridge 171:3a7713b1edbc 1644 /**
AnnaBridge 171:3a7713b1edbc 1645 * @}
AnnaBridge 171:3a7713b1edbc 1646 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1647
AnnaBridge 171:3a7713b1edbc 1648
AnnaBridge 171:3a7713b1edbc 1649 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1650 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 1651 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 1652 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 1653 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 1654 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1655 #define MCG_BASES { MCG }
AnnaBridge 171:3a7713b1edbc 1656
AnnaBridge 171:3a7713b1edbc 1657 /**
AnnaBridge 171:3a7713b1edbc 1658 * @}
AnnaBridge 171:3a7713b1edbc 1659 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1660
AnnaBridge 171:3a7713b1edbc 1661
AnnaBridge 171:3a7713b1edbc 1662 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1663 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1664 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1665
AnnaBridge 171:3a7713b1edbc 1666 /**
AnnaBridge 171:3a7713b1edbc 1667 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1668 * @{
AnnaBridge 171:3a7713b1edbc 1669 */
AnnaBridge 171:3a7713b1edbc 1670
AnnaBridge 171:3a7713b1edbc 1671 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1672 typedef struct {
AnnaBridge 171:3a7713b1edbc 1673 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 1674 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1675 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1676 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1677 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 1678 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 1679 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 1680
AnnaBridge 171:3a7713b1edbc 1681 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1682 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 1683 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1684
AnnaBridge 171:3a7713b1edbc 1685 /**
AnnaBridge 171:3a7713b1edbc 1686 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 1687 * @{
AnnaBridge 171:3a7713b1edbc 1688 */
AnnaBridge 171:3a7713b1edbc 1689
AnnaBridge 171:3a7713b1edbc 1690 /* PLASC Bit Fields */
AnnaBridge 171:3a7713b1edbc 1691 #define MCM_PLASC_ASC_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1692 #define MCM_PLASC_ASC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1693 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 1694 /* PLAMC Bit Fields */
AnnaBridge 171:3a7713b1edbc 1695 #define MCM_PLAMC_AMC_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 1696 #define MCM_PLAMC_AMC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1697 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 1698 /* PLACR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1699 #define MCM_PLACR_ARB_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 1700 #define MCM_PLACR_ARB_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1701 #define MCM_PLACR_CFCC_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 1702 #define MCM_PLACR_CFCC_SHIFT 10
AnnaBridge 171:3a7713b1edbc 1703 #define MCM_PLACR_DFCDA_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 1704 #define MCM_PLACR_DFCDA_SHIFT 11
AnnaBridge 171:3a7713b1edbc 1705 #define MCM_PLACR_DFCIC_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 1706 #define MCM_PLACR_DFCIC_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1707 #define MCM_PLACR_DFCC_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 1708 #define MCM_PLACR_DFCC_SHIFT 13
AnnaBridge 171:3a7713b1edbc 1709 #define MCM_PLACR_EFDS_MASK 0x4000u
AnnaBridge 171:3a7713b1edbc 1710 #define MCM_PLACR_EFDS_SHIFT 14
AnnaBridge 171:3a7713b1edbc 1711 #define MCM_PLACR_DFCS_MASK 0x8000u
AnnaBridge 171:3a7713b1edbc 1712 #define MCM_PLACR_DFCS_SHIFT 15
AnnaBridge 171:3a7713b1edbc 1713 #define MCM_PLACR_ESFC_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 1714 #define MCM_PLACR_ESFC_SHIFT 16
AnnaBridge 171:3a7713b1edbc 1715 /* CPO Bit Fields */
AnnaBridge 171:3a7713b1edbc 1716 #define MCM_CPO_CPOREQ_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1717 #define MCM_CPO_CPOREQ_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1718 #define MCM_CPO_CPOACK_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1719 #define MCM_CPO_CPOACK_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1720 #define MCM_CPO_CPOWOI_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1721 #define MCM_CPO_CPOWOI_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1722
AnnaBridge 171:3a7713b1edbc 1723 /**
AnnaBridge 171:3a7713b1edbc 1724 * @}
AnnaBridge 171:3a7713b1edbc 1725 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1726
AnnaBridge 171:3a7713b1edbc 1727
AnnaBridge 171:3a7713b1edbc 1728 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1729 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 1730 #define MCM_BASE (0xF0003000u)
AnnaBridge 171:3a7713b1edbc 1731 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 1732 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 1733 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1734 #define MCM_BASES { MCM }
AnnaBridge 171:3a7713b1edbc 1735
AnnaBridge 171:3a7713b1edbc 1736 /**
AnnaBridge 171:3a7713b1edbc 1737 * @}
AnnaBridge 171:3a7713b1edbc 1738 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1739
AnnaBridge 171:3a7713b1edbc 1740
AnnaBridge 171:3a7713b1edbc 1741 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1742 -- MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1743 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1744
AnnaBridge 171:3a7713b1edbc 1745 /**
AnnaBridge 171:3a7713b1edbc 1746 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1747 * @{
AnnaBridge 171:3a7713b1edbc 1748 */
AnnaBridge 171:3a7713b1edbc 1749
AnnaBridge 171:3a7713b1edbc 1750 /** MTB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1751 typedef struct {
AnnaBridge 171:3a7713b1edbc 1752 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1753 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1754 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1755 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1756 uint8_t RESERVED_0[3824];
AnnaBridge 171:3a7713b1edbc 1757 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
AnnaBridge 171:3a7713b1edbc 1758 uint8_t RESERVED_1[156];
AnnaBridge 171:3a7713b1edbc 1759 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
AnnaBridge 171:3a7713b1edbc 1760 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
AnnaBridge 171:3a7713b1edbc 1761 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 1762 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
AnnaBridge 171:3a7713b1edbc 1763 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
AnnaBridge 171:3a7713b1edbc 1764 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
AnnaBridge 171:3a7713b1edbc 1765 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
AnnaBridge 171:3a7713b1edbc 1766 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 1767 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 1768 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 1769 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1770 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1771 } MTB_Type;
AnnaBridge 171:3a7713b1edbc 1772
AnnaBridge 171:3a7713b1edbc 1773 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1774 -- MTB Register Masks
AnnaBridge 171:3a7713b1edbc 1775 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1776
AnnaBridge 171:3a7713b1edbc 1777 /**
AnnaBridge 171:3a7713b1edbc 1778 * @addtogroup MTB_Register_Masks MTB Register Masks
AnnaBridge 171:3a7713b1edbc 1779 * @{
AnnaBridge 171:3a7713b1edbc 1780 */
AnnaBridge 171:3a7713b1edbc 1781
AnnaBridge 171:3a7713b1edbc 1782 /* POSITION Bit Fields */
AnnaBridge 171:3a7713b1edbc 1783 #define MTB_POSITION_WRAP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1784 #define MTB_POSITION_WRAP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1785 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
AnnaBridge 171:3a7713b1edbc 1786 #define MTB_POSITION_POINTER_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1787 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
AnnaBridge 171:3a7713b1edbc 1788 /* MASTER Bit Fields */
AnnaBridge 171:3a7713b1edbc 1789 #define MTB_MASTER_MASK_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1790 #define MTB_MASTER_MASK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1791 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 1792 #define MTB_MASTER_TSTARTEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 1793 #define MTB_MASTER_TSTARTEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 1794 #define MTB_MASTER_TSTOPEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 1795 #define MTB_MASTER_TSTOPEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 1796 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 1797 #define MTB_MASTER_SFRWPRIV_SHIFT 7
AnnaBridge 171:3a7713b1edbc 1798 #define MTB_MASTER_RAMPRIV_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 1799 #define MTB_MASTER_RAMPRIV_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1800 #define MTB_MASTER_HALTREQ_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 1801 #define MTB_MASTER_HALTREQ_SHIFT 9
AnnaBridge 171:3a7713b1edbc 1802 #define MTB_MASTER_EN_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 1803 #define MTB_MASTER_EN_SHIFT 31
AnnaBridge 171:3a7713b1edbc 1804 /* FLOW Bit Fields */
AnnaBridge 171:3a7713b1edbc 1805 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1806 #define MTB_FLOW_AUTOSTOP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1807 #define MTB_FLOW_AUTOHALT_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1808 #define MTB_FLOW_AUTOHALT_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1809 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
AnnaBridge 171:3a7713b1edbc 1810 #define MTB_FLOW_WATERMARK_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1811 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 1812 /* BASE Bit Fields */
AnnaBridge 171:3a7713b1edbc 1813 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1814 #define MTB_BASE_BASEADDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1815 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
AnnaBridge 171:3a7713b1edbc 1816 /* MODECTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1817 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1818 #define MTB_MODECTRL_MODECTRL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1819 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 1820 /* TAGSET Bit Fields */
AnnaBridge 171:3a7713b1edbc 1821 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1822 #define MTB_TAGSET_TAGSET_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1823 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
AnnaBridge 171:3a7713b1edbc 1824 /* TAGCLEAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 1825 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1826 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1827 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 1828 /* LOCKACCESS Bit Fields */
AnnaBridge 171:3a7713b1edbc 1829 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1830 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1831 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 1832 /* LOCKSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 1833 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1834 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1835 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 1836 /* AUTHSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 1837 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1838 #define MTB_AUTHSTAT_BIT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1839 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1840 #define MTB_AUTHSTAT_BIT1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1841 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 1842 #define MTB_AUTHSTAT_BIT2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 1843 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 1844 #define MTB_AUTHSTAT_BIT3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 1845 /* DEVICEARCH Bit Fields */
AnnaBridge 171:3a7713b1edbc 1846 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1847 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1848 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 1849 /* DEVICECFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 1850 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1851 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1852 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 1853 /* DEVICETYPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1854 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1855 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1856 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 1857 /* PERIPHID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1858 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1859 #define MTB_PERIPHID_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1860 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 1861 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1862 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1863 #define MTB_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1864 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 1865
AnnaBridge 171:3a7713b1edbc 1866 /**
AnnaBridge 171:3a7713b1edbc 1867 * @}
AnnaBridge 171:3a7713b1edbc 1868 */ /* end of group MTB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1869
AnnaBridge 171:3a7713b1edbc 1870
AnnaBridge 171:3a7713b1edbc 1871 /* MTB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1872 /** Peripheral MTB base address */
AnnaBridge 171:3a7713b1edbc 1873 #define MTB_BASE (0xF0000000u)
AnnaBridge 171:3a7713b1edbc 1874 /** Peripheral MTB base pointer */
AnnaBridge 171:3a7713b1edbc 1875 #define MTB ((MTB_Type *)MTB_BASE)
AnnaBridge 171:3a7713b1edbc 1876 /** Array initializer of MTB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1877 #define MTB_BASES { MTB }
AnnaBridge 171:3a7713b1edbc 1878
AnnaBridge 171:3a7713b1edbc 1879 /**
AnnaBridge 171:3a7713b1edbc 1880 * @}
AnnaBridge 171:3a7713b1edbc 1881 */ /* end of group MTB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883
AnnaBridge 171:3a7713b1edbc 1884 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1885 -- MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1886 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1887
AnnaBridge 171:3a7713b1edbc 1888 /**
AnnaBridge 171:3a7713b1edbc 1889 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1890 * @{
AnnaBridge 171:3a7713b1edbc 1891 */
AnnaBridge 171:3a7713b1edbc 1892
AnnaBridge 171:3a7713b1edbc 1893 /** MTBDWT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1894 typedef struct {
AnnaBridge 171:3a7713b1edbc 1895 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1896 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 1897 struct { /* offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 1898 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 1899 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 1900 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 1901 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1902 } COMPARATOR[2];
AnnaBridge 171:3a7713b1edbc 1903 uint8_t RESERVED_1[448];
AnnaBridge 171:3a7713b1edbc 1904 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 1905 uint8_t RESERVED_2[3524];
AnnaBridge 171:3a7713b1edbc 1906 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 1907 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 1908 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1909 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1910 } MTBDWT_Type;
AnnaBridge 171:3a7713b1edbc 1911
AnnaBridge 171:3a7713b1edbc 1912 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1913 -- MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 1914 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1915
AnnaBridge 171:3a7713b1edbc 1916 /**
AnnaBridge 171:3a7713b1edbc 1917 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 1918 * @{
AnnaBridge 171:3a7713b1edbc 1919 */
AnnaBridge 171:3a7713b1edbc 1920
AnnaBridge 171:3a7713b1edbc 1921 /* CTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1922 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1923 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1924 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
AnnaBridge 171:3a7713b1edbc 1925 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 1926 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
AnnaBridge 171:3a7713b1edbc 1927 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
AnnaBridge 171:3a7713b1edbc 1928 /* COMP Bit Fields */
AnnaBridge 171:3a7713b1edbc 1929 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1930 #define MTBDWT_COMP_COMP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1931 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
AnnaBridge 171:3a7713b1edbc 1932 /* MASK Bit Fields */
AnnaBridge 171:3a7713b1edbc 1933 #define MTBDWT_MASK_MASK_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 1934 #define MTBDWT_MASK_MASK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1935 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 1936 /* FCT Bit Fields */
AnnaBridge 171:3a7713b1edbc 1937 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 1938 #define MTBDWT_FCT_FUNCTION_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1939 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
AnnaBridge 171:3a7713b1edbc 1940 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 1941 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
AnnaBridge 171:3a7713b1edbc 1942 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
AnnaBridge 171:3a7713b1edbc 1943 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
AnnaBridge 171:3a7713b1edbc 1944 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 1945 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 1946 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
AnnaBridge 171:3a7713b1edbc 1947 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 1948 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 1949 #define MTBDWT_FCT_MATCHED_SHIFT 24
AnnaBridge 171:3a7713b1edbc 1950 /* TBCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 1951 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 1952 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1953 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 1954 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 1955 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 1956 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
AnnaBridge 171:3a7713b1edbc 1957 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
AnnaBridge 171:3a7713b1edbc 1958 /* DEVICECFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 1959 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1960 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1961 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 1962 /* DEVICETYPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1963 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1964 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1965 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 1966 /* PERIPHID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1967 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1968 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1969 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 1970 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 1971 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 1972 #define MTBDWT_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 1973 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 1974
AnnaBridge 171:3a7713b1edbc 1975 /**
AnnaBridge 171:3a7713b1edbc 1976 * @}
AnnaBridge 171:3a7713b1edbc 1977 */ /* end of group MTBDWT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1978
AnnaBridge 171:3a7713b1edbc 1979
AnnaBridge 171:3a7713b1edbc 1980 /* MTBDWT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1981 /** Peripheral MTBDWT base address */
AnnaBridge 171:3a7713b1edbc 1982 #define MTBDWT_BASE (0xF0001000u)
AnnaBridge 171:3a7713b1edbc 1983 /** Peripheral MTBDWT base pointer */
AnnaBridge 171:3a7713b1edbc 1984 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
AnnaBridge 171:3a7713b1edbc 1985 /** Array initializer of MTBDWT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1986 #define MTBDWT_BASES { MTBDWT }
AnnaBridge 171:3a7713b1edbc 1987
AnnaBridge 171:3a7713b1edbc 1988 /**
AnnaBridge 171:3a7713b1edbc 1989 * @}
AnnaBridge 171:3a7713b1edbc 1990 */ /* end of group MTBDWT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1991
AnnaBridge 171:3a7713b1edbc 1992
AnnaBridge 171:3a7713b1edbc 1993 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1994 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1995 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1996
AnnaBridge 171:3a7713b1edbc 1997 /**
AnnaBridge 171:3a7713b1edbc 1998 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1999 * @{
AnnaBridge 171:3a7713b1edbc 2000 */
AnnaBridge 171:3a7713b1edbc 2001
AnnaBridge 171:3a7713b1edbc 2002 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2003 typedef struct {
AnnaBridge 171:3a7713b1edbc 2004 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2005 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2006 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2007 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 2008 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2009 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 2010 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 2011 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 2012 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2013 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 2014 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 2015 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 2016 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2017 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 2018 } NV_Type;
AnnaBridge 171:3a7713b1edbc 2019
AnnaBridge 171:3a7713b1edbc 2020 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2021 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 2022 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2023
AnnaBridge 171:3a7713b1edbc 2024 /**
AnnaBridge 171:3a7713b1edbc 2025 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 2026 * @{
AnnaBridge 171:3a7713b1edbc 2027 */
AnnaBridge 171:3a7713b1edbc 2028
AnnaBridge 171:3a7713b1edbc 2029 /* BACKKEY3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2030 #define NV_BACKKEY3_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2031 #define NV_BACKKEY3_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2032 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2033 /* BACKKEY2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2034 #define NV_BACKKEY2_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2035 #define NV_BACKKEY2_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2036 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2037 /* BACKKEY1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2038 #define NV_BACKKEY1_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2039 #define NV_BACKKEY1_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2040 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2041 /* BACKKEY0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2042 #define NV_BACKKEY0_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2043 #define NV_BACKKEY0_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2044 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2045 /* BACKKEY7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2046 #define NV_BACKKEY7_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2047 #define NV_BACKKEY7_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2048 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2049 /* BACKKEY6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2050 #define NV_BACKKEY6_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2051 #define NV_BACKKEY6_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2052 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2053 /* BACKKEY5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2054 #define NV_BACKKEY5_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2055 #define NV_BACKKEY5_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2056 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2057 /* BACKKEY4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2058 #define NV_BACKKEY4_KEY_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2059 #define NV_BACKKEY4_KEY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2060 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 2061 /* FPROT3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2062 #define NV_FPROT3_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2063 #define NV_FPROT3_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2064 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2065 /* FPROT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2066 #define NV_FPROT2_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2067 #define NV_FPROT2_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2068 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2069 /* FPROT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2070 #define NV_FPROT1_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2071 #define NV_FPROT1_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2072 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2073 /* FPROT0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2074 #define NV_FPROT0_PROT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2075 #define NV_FPROT0_PROT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2076 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2077 /* FSEC Bit Fields */
AnnaBridge 171:3a7713b1edbc 2078 #define NV_FSEC_SEC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2079 #define NV_FSEC_SEC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2080 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 2081 #define NV_FSEC_FSLACC_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2082 #define NV_FSEC_FSLACC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2083 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 2084 #define NV_FSEC_MEEN_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2085 #define NV_FSEC_MEEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2086 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 2087 #define NV_FSEC_KEYEN_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 2088 #define NV_FSEC_KEYEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2089 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 2090 /* FOPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 2091 #define NV_FOPT_LPBOOT0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2092 #define NV_FOPT_LPBOOT0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2093 #define NV_FOPT_NMI_DIS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2094 #define NV_FOPT_NMI_DIS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2095 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2096 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2097 #define NV_FOPT_LPBOOT1_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2098 #define NV_FOPT_LPBOOT1_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2099 #define NV_FOPT_FAST_INIT_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2100 #define NV_FOPT_FAST_INIT_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2101
AnnaBridge 171:3a7713b1edbc 2102 /**
AnnaBridge 171:3a7713b1edbc 2103 * @}
AnnaBridge 171:3a7713b1edbc 2104 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2105
AnnaBridge 171:3a7713b1edbc 2106
AnnaBridge 171:3a7713b1edbc 2107 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2108 /** Peripheral FTFA_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 2109 #define FTFA_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 2110 /** Peripheral FTFA_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 2111 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 2112 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2113 #define NV_BASES { FTFA_FlashConfig }
AnnaBridge 171:3a7713b1edbc 2114
AnnaBridge 171:3a7713b1edbc 2115 /**
AnnaBridge 171:3a7713b1edbc 2116 * @}
AnnaBridge 171:3a7713b1edbc 2117 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2118
AnnaBridge 171:3a7713b1edbc 2119
AnnaBridge 171:3a7713b1edbc 2120 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2121 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2122 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2123
AnnaBridge 171:3a7713b1edbc 2124 /**
AnnaBridge 171:3a7713b1edbc 2125 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2126 * @{
AnnaBridge 171:3a7713b1edbc 2127 */
AnnaBridge 171:3a7713b1edbc 2128
AnnaBridge 171:3a7713b1edbc 2129 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2130 typedef struct {
AnnaBridge 171:3a7713b1edbc 2131 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2132 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 2133
AnnaBridge 171:3a7713b1edbc 2134 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2135 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 2136 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2137
AnnaBridge 171:3a7713b1edbc 2138 /**
AnnaBridge 171:3a7713b1edbc 2139 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 2140 * @{
AnnaBridge 171:3a7713b1edbc 2141 */
AnnaBridge 171:3a7713b1edbc 2142
AnnaBridge 171:3a7713b1edbc 2143 /* CR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2144 #define OSC_CR_SC16P_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2145 #define OSC_CR_SC16P_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2146 #define OSC_CR_SC8P_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2147 #define OSC_CR_SC8P_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2148 #define OSC_CR_SC4P_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2149 #define OSC_CR_SC4P_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2150 #define OSC_CR_SC2P_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2151 #define OSC_CR_SC2P_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2152 #define OSC_CR_EREFSTEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2153 #define OSC_CR_EREFSTEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2154 #define OSC_CR_ERCLKEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2155 #define OSC_CR_ERCLKEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2156
AnnaBridge 171:3a7713b1edbc 2157 /**
AnnaBridge 171:3a7713b1edbc 2158 * @}
AnnaBridge 171:3a7713b1edbc 2159 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2160
AnnaBridge 171:3a7713b1edbc 2161
AnnaBridge 171:3a7713b1edbc 2162 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2163 /** Peripheral OSC0 base address */
AnnaBridge 171:3a7713b1edbc 2164 #define OSC0_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 2165 /** Peripheral OSC0 base pointer */
AnnaBridge 171:3a7713b1edbc 2166 #define OSC0 ((OSC_Type *)OSC0_BASE)
AnnaBridge 171:3a7713b1edbc 2167 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2168 #define OSC_BASES { OSC0 }
AnnaBridge 171:3a7713b1edbc 2169
AnnaBridge 171:3a7713b1edbc 2170 /**
AnnaBridge 171:3a7713b1edbc 2171 * @}
AnnaBridge 171:3a7713b1edbc 2172 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2173
AnnaBridge 171:3a7713b1edbc 2174
AnnaBridge 171:3a7713b1edbc 2175 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2176 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2177 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2178
AnnaBridge 171:3a7713b1edbc 2179 /**
AnnaBridge 171:3a7713b1edbc 2180 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2181 * @{
AnnaBridge 171:3a7713b1edbc 2182 */
AnnaBridge 171:3a7713b1edbc 2183
AnnaBridge 171:3a7713b1edbc 2184 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2185 typedef struct {
AnnaBridge 171:3a7713b1edbc 2186 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2187 uint8_t RESERVED_0[220];
AnnaBridge 171:3a7713b1edbc 2188 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 2189 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 2190 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 2191 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2192 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2193 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2194 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2195 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2196 } CHANNEL[2];
AnnaBridge 171:3a7713b1edbc 2197 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 2198
AnnaBridge 171:3a7713b1edbc 2199 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2200 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 2201 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2202
AnnaBridge 171:3a7713b1edbc 2203 /**
AnnaBridge 171:3a7713b1edbc 2204 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 2205 * @{
AnnaBridge 171:3a7713b1edbc 2206 */
AnnaBridge 171:3a7713b1edbc 2207
AnnaBridge 171:3a7713b1edbc 2208 /* MCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2209 #define PIT_MCR_FRZ_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2210 #define PIT_MCR_FRZ_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2211 #define PIT_MCR_MDIS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2212 #define PIT_MCR_MDIS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2213 /* LTMR64H Bit Fields */
AnnaBridge 171:3a7713b1edbc 2214 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2215 #define PIT_LTMR64H_LTH_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2216 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
AnnaBridge 171:3a7713b1edbc 2217 /* LTMR64L Bit Fields */
AnnaBridge 171:3a7713b1edbc 2218 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2219 #define PIT_LTMR64L_LTL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2220 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
AnnaBridge 171:3a7713b1edbc 2221 /* LDVAL Bit Fields */
AnnaBridge 171:3a7713b1edbc 2222 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2223 #define PIT_LDVAL_TSV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2224 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 2225 /* CVAL Bit Fields */
AnnaBridge 171:3a7713b1edbc 2226 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2227 #define PIT_CVAL_TVL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2228 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 2229 /* TCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 2230 #define PIT_TCTRL_TEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2231 #define PIT_TCTRL_TEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2232 #define PIT_TCTRL_TIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2233 #define PIT_TCTRL_TIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2234 #define PIT_TCTRL_CHN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2235 #define PIT_TCTRL_CHN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2236 /* TFLG Bit Fields */
AnnaBridge 171:3a7713b1edbc 2237 #define PIT_TFLG_TIF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2238 #define PIT_TFLG_TIF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2239
AnnaBridge 171:3a7713b1edbc 2240 /**
AnnaBridge 171:3a7713b1edbc 2241 * @}
AnnaBridge 171:3a7713b1edbc 2242 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2243
AnnaBridge 171:3a7713b1edbc 2244
AnnaBridge 171:3a7713b1edbc 2245 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2246 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 2247 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 2248 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 2249 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 2250 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2251 #define PIT_BASES { PIT }
AnnaBridge 171:3a7713b1edbc 2252
AnnaBridge 171:3a7713b1edbc 2253 /**
AnnaBridge 171:3a7713b1edbc 2254 * @}
AnnaBridge 171:3a7713b1edbc 2255 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2256
AnnaBridge 171:3a7713b1edbc 2257
AnnaBridge 171:3a7713b1edbc 2258 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2259 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2260 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2261
AnnaBridge 171:3a7713b1edbc 2262 /**
AnnaBridge 171:3a7713b1edbc 2263 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2264 * @{
AnnaBridge 171:3a7713b1edbc 2265 */
AnnaBridge 171:3a7713b1edbc 2266
AnnaBridge 171:3a7713b1edbc 2267 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2268 typedef struct {
AnnaBridge 171:3a7713b1edbc 2269 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2270 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2271 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2272 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 2273
AnnaBridge 171:3a7713b1edbc 2274 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2275 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 2276 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2277
AnnaBridge 171:3a7713b1edbc 2278 /**
AnnaBridge 171:3a7713b1edbc 2279 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 2280 * @{
AnnaBridge 171:3a7713b1edbc 2281 */
AnnaBridge 171:3a7713b1edbc 2282
AnnaBridge 171:3a7713b1edbc 2283 /* LVDSC1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2284 #define PMC_LVDSC1_LVDV_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2285 #define PMC_LVDSC1_LVDV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2286 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 2287 #define PMC_LVDSC1_LVDRE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2288 #define PMC_LVDSC1_LVDRE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2289 #define PMC_LVDSC1_LVDIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2290 #define PMC_LVDSC1_LVDIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2291 #define PMC_LVDSC1_LVDACK_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2292 #define PMC_LVDSC1_LVDACK_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2293 #define PMC_LVDSC1_LVDF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2294 #define PMC_LVDSC1_LVDF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2295 /* LVDSC2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2296 #define PMC_LVDSC2_LVWV_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2297 #define PMC_LVDSC2_LVWV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2298 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 2299 #define PMC_LVDSC2_LVWIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2300 #define PMC_LVDSC2_LVWIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2301 #define PMC_LVDSC2_LVWACK_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2302 #define PMC_LVDSC2_LVWACK_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2303 #define PMC_LVDSC2_LVWF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2304 #define PMC_LVDSC2_LVWF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2305 /* REGSC Bit Fields */
AnnaBridge 171:3a7713b1edbc 2306 #define PMC_REGSC_BGBE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2307 #define PMC_REGSC_BGBE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2308 #define PMC_REGSC_REGONS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2309 #define PMC_REGSC_REGONS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2310 #define PMC_REGSC_ACKISO_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2311 #define PMC_REGSC_ACKISO_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2312 #define PMC_REGSC_BGEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2313 #define PMC_REGSC_BGEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2314
AnnaBridge 171:3a7713b1edbc 2315 /**
AnnaBridge 171:3a7713b1edbc 2316 * @}
AnnaBridge 171:3a7713b1edbc 2317 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2318
AnnaBridge 171:3a7713b1edbc 2319
AnnaBridge 171:3a7713b1edbc 2320 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2321 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 2322 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 2323 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 2324 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 2325 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2326 #define PMC_BASES { PMC }
AnnaBridge 171:3a7713b1edbc 2327
AnnaBridge 171:3a7713b1edbc 2328 /**
AnnaBridge 171:3a7713b1edbc 2329 * @}
AnnaBridge 171:3a7713b1edbc 2330 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2331
AnnaBridge 171:3a7713b1edbc 2332
AnnaBridge 171:3a7713b1edbc 2333 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2334 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2335 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2336
AnnaBridge 171:3a7713b1edbc 2337 /**
AnnaBridge 171:3a7713b1edbc 2338 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2339 * @{
AnnaBridge 171:3a7713b1edbc 2340 */
AnnaBridge 171:3a7713b1edbc 2341
AnnaBridge 171:3a7713b1edbc 2342 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2343 typedef struct {
AnnaBridge 171:3a7713b1edbc 2344 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2345 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 2346 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 2347 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 2348 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 2349 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 2350
AnnaBridge 171:3a7713b1edbc 2351 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2352 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 2353 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2354
AnnaBridge 171:3a7713b1edbc 2355 /**
AnnaBridge 171:3a7713b1edbc 2356 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 2357 * @{
AnnaBridge 171:3a7713b1edbc 2358 */
AnnaBridge 171:3a7713b1edbc 2359
AnnaBridge 171:3a7713b1edbc 2360 /* PCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2361 #define PORT_PCR_PS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2362 #define PORT_PCR_PS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2363 #define PORT_PCR_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2364 #define PORT_PCR_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2365 #define PORT_PCR_SRE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2366 #define PORT_PCR_SRE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2367 #define PORT_PCR_PFE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2368 #define PORT_PCR_PFE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2369 #define PORT_PCR_DSE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2370 #define PORT_PCR_DSE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2371 #define PORT_PCR_MUX_MASK 0x700u
AnnaBridge 171:3a7713b1edbc 2372 #define PORT_PCR_MUX_SHIFT 8
AnnaBridge 171:3a7713b1edbc 2373 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 2374 #define PORT_PCR_IRQC_MASK 0xF0000u
AnnaBridge 171:3a7713b1edbc 2375 #define PORT_PCR_IRQC_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2376 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 2377 #define PORT_PCR_ISF_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 2378 #define PORT_PCR_ISF_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2379 /* GPCLR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2380 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 2381 #define PORT_GPCLR_GPWD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2382 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 2383 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 2384 #define PORT_GPCLR_GPWE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2385 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 2386 /* GPCHR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2387 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 2388 #define PORT_GPCHR_GPWD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2389 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 2390 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 2391 #define PORT_GPCHR_GPWE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2392 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 2393 /* ISFR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2394 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2395 #define PORT_ISFR_ISF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2396 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 2397
AnnaBridge 171:3a7713b1edbc 2398 /**
AnnaBridge 171:3a7713b1edbc 2399 * @}
AnnaBridge 171:3a7713b1edbc 2400 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2401
AnnaBridge 171:3a7713b1edbc 2402
AnnaBridge 171:3a7713b1edbc 2403 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2404 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 2405 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 2406 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 2407 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 2408 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 2409 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 2410 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 2411 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 2412 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 2413 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 2414 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 2415 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 2416 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 2417 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 2418 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 2419 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 2420 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 2421 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 2422 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 2423 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 2424 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2425 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 2426
AnnaBridge 171:3a7713b1edbc 2427 /**
AnnaBridge 171:3a7713b1edbc 2428 * @}
AnnaBridge 171:3a7713b1edbc 2429 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2430
AnnaBridge 171:3a7713b1edbc 2431
AnnaBridge 171:3a7713b1edbc 2432 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2433 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2434 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2435
AnnaBridge 171:3a7713b1edbc 2436 /**
AnnaBridge 171:3a7713b1edbc 2437 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2438 * @{
AnnaBridge 171:3a7713b1edbc 2439 */
AnnaBridge 171:3a7713b1edbc 2440
AnnaBridge 171:3a7713b1edbc 2441 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2442 typedef struct {
AnnaBridge 171:3a7713b1edbc 2443 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2444 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2445 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 2446 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2447 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 2448 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 2449
AnnaBridge 171:3a7713b1edbc 2450 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2451 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 2452 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2453
AnnaBridge 171:3a7713b1edbc 2454 /**
AnnaBridge 171:3a7713b1edbc 2455 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 2456 * @{
AnnaBridge 171:3a7713b1edbc 2457 */
AnnaBridge 171:3a7713b1edbc 2458
AnnaBridge 171:3a7713b1edbc 2459 /* SRS0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2460 #define RCM_SRS0_WAKEUP_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2461 #define RCM_SRS0_WAKEUP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2462 #define RCM_SRS0_LVD_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2463 #define RCM_SRS0_LVD_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2464 #define RCM_SRS0_LOC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2465 #define RCM_SRS0_LOC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2466 #define RCM_SRS0_LOL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2467 #define RCM_SRS0_LOL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2468 #define RCM_SRS0_WDOG_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2469 #define RCM_SRS0_WDOG_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2470 #define RCM_SRS0_PIN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2471 #define RCM_SRS0_PIN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2472 #define RCM_SRS0_POR_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2473 #define RCM_SRS0_POR_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2474 /* SRS1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2475 #define RCM_SRS1_LOCKUP_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2476 #define RCM_SRS1_LOCKUP_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2477 #define RCM_SRS1_SW_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2478 #define RCM_SRS1_SW_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2479 #define RCM_SRS1_MDM_AP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2480 #define RCM_SRS1_MDM_AP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2481 #define RCM_SRS1_SACKERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2482 #define RCM_SRS1_SACKERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2483 /* RPFC Bit Fields */
AnnaBridge 171:3a7713b1edbc 2484 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2485 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2486 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 2487 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2488 #define RCM_RPFC_RSTFLTSS_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2489 /* RPFW Bit Fields */
AnnaBridge 171:3a7713b1edbc 2490 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 2491 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2492 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2493
AnnaBridge 171:3a7713b1edbc 2494 /**
AnnaBridge 171:3a7713b1edbc 2495 * @}
AnnaBridge 171:3a7713b1edbc 2496 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2497
AnnaBridge 171:3a7713b1edbc 2498
AnnaBridge 171:3a7713b1edbc 2499 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2500 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 2501 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 2502 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 2503 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 2504 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2505 #define RCM_BASES { RCM }
AnnaBridge 171:3a7713b1edbc 2506
AnnaBridge 171:3a7713b1edbc 2507 /**
AnnaBridge 171:3a7713b1edbc 2508 * @}
AnnaBridge 171:3a7713b1edbc 2509 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2510
AnnaBridge 171:3a7713b1edbc 2511
AnnaBridge 171:3a7713b1edbc 2512 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2513 -- ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2514 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2515
AnnaBridge 171:3a7713b1edbc 2516 /**
AnnaBridge 171:3a7713b1edbc 2517 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2518 * @{
AnnaBridge 171:3a7713b1edbc 2519 */
AnnaBridge 171:3a7713b1edbc 2520
AnnaBridge 171:3a7713b1edbc 2521 /** ROM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2522 typedef struct {
AnnaBridge 171:3a7713b1edbc 2523 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2524 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2525 uint8_t RESERVED_0[4028];
AnnaBridge 171:3a7713b1edbc 2526 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 2527 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 2528 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 2529 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 2530 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 2531 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 2532 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 2533 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 2534 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 2535 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2536 } ROM_Type;
AnnaBridge 171:3a7713b1edbc 2537
AnnaBridge 171:3a7713b1edbc 2538 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2539 -- ROM Register Masks
AnnaBridge 171:3a7713b1edbc 2540 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2541
AnnaBridge 171:3a7713b1edbc 2542 /**
AnnaBridge 171:3a7713b1edbc 2543 * @addtogroup ROM_Register_Masks ROM Register Masks
AnnaBridge 171:3a7713b1edbc 2544 * @{
AnnaBridge 171:3a7713b1edbc 2545 */
AnnaBridge 171:3a7713b1edbc 2546
AnnaBridge 171:3a7713b1edbc 2547 /* ENTRY Bit Fields */
AnnaBridge 171:3a7713b1edbc 2548 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2549 #define ROM_ENTRY_ENTRY_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2550 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
AnnaBridge 171:3a7713b1edbc 2551 /* TABLEMARK Bit Fields */
AnnaBridge 171:3a7713b1edbc 2552 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2553 #define ROM_TABLEMARK_MARK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2554 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 2555 /* SYSACCESS Bit Fields */
AnnaBridge 171:3a7713b1edbc 2556 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2557 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2558 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 2559 /* PERIPHID4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2560 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2561 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2562 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2563 /* PERIPHID5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2564 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2565 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2566 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2567 /* PERIPHID6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2568 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2569 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2570 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2571 /* PERIPHID7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2572 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2573 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2574 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2575 /* PERIPHID0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2576 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2577 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2578 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2579 /* PERIPHID1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2580 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2581 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2582 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2583 /* PERIPHID2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2584 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2585 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2586 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2587 /* PERIPHID3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2588 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2589 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2590 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2591 /* COMPID Bit Fields */
AnnaBridge 171:3a7713b1edbc 2592 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2593 #define ROM_COMPID_COMPID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2594 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 2595
AnnaBridge 171:3a7713b1edbc 2596 /**
AnnaBridge 171:3a7713b1edbc 2597 * @}
AnnaBridge 171:3a7713b1edbc 2598 */ /* end of group ROM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2599
AnnaBridge 171:3a7713b1edbc 2600
AnnaBridge 171:3a7713b1edbc 2601 /* ROM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2602 /** Peripheral ROM base address */
AnnaBridge 171:3a7713b1edbc 2603 #define ROM_BASE (0xF0002000u)
AnnaBridge 171:3a7713b1edbc 2604 /** Peripheral ROM base pointer */
AnnaBridge 171:3a7713b1edbc 2605 #define ROM ((ROM_Type *)ROM_BASE)
AnnaBridge 171:3a7713b1edbc 2606 /** Array initializer of ROM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2607 #define ROM_BASES { ROM }
AnnaBridge 171:3a7713b1edbc 2608
AnnaBridge 171:3a7713b1edbc 2609 /**
AnnaBridge 171:3a7713b1edbc 2610 * @}
AnnaBridge 171:3a7713b1edbc 2611 */ /* end of group ROM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2612
AnnaBridge 171:3a7713b1edbc 2613
AnnaBridge 171:3a7713b1edbc 2614 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2615 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2616 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2617
AnnaBridge 171:3a7713b1edbc 2618 /**
AnnaBridge 171:3a7713b1edbc 2619 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2620 * @{
AnnaBridge 171:3a7713b1edbc 2621 */
AnnaBridge 171:3a7713b1edbc 2622
AnnaBridge 171:3a7713b1edbc 2623 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2624 typedef struct {
AnnaBridge 171:3a7713b1edbc 2625 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2626 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2627 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2628 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2629 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2630 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 2631 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2632 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 2633 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 2634
AnnaBridge 171:3a7713b1edbc 2635 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2636 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 2637 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2638
AnnaBridge 171:3a7713b1edbc 2639 /**
AnnaBridge 171:3a7713b1edbc 2640 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 2641 * @{
AnnaBridge 171:3a7713b1edbc 2642 */
AnnaBridge 171:3a7713b1edbc 2643
AnnaBridge 171:3a7713b1edbc 2644 /* TSR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2645 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2646 #define RTC_TSR_TSR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2647 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 2648 /* TPR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2649 #define RTC_TPR_TPR_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 2650 #define RTC_TPR_TPR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2651 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 2652 /* TAR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2653 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2654 #define RTC_TAR_TAR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2655 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 2656 /* TCR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2657 #define RTC_TCR_TCR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2658 #define RTC_TCR_TCR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2659 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 2660 #define RTC_TCR_CIR_MASK 0xFF00u
AnnaBridge 171:3a7713b1edbc 2661 #define RTC_TCR_CIR_SHIFT 8
AnnaBridge 171:3a7713b1edbc 2662 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 2663 #define RTC_TCR_TCV_MASK 0xFF0000u
AnnaBridge 171:3a7713b1edbc 2664 #define RTC_TCR_TCV_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2665 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 2666 #define RTC_TCR_CIC_MASK 0xFF000000u
AnnaBridge 171:3a7713b1edbc 2667 #define RTC_TCR_CIC_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2668 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 2669 /* CR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2670 #define RTC_CR_SWR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2671 #define RTC_CR_SWR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2672 #define RTC_CR_WPE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2673 #define RTC_CR_WPE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2674 #define RTC_CR_SUP_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2675 #define RTC_CR_SUP_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2676 #define RTC_CR_UM_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2677 #define RTC_CR_UM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2678 #define RTC_CR_OSCE_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 2679 #define RTC_CR_OSCE_SHIFT 8
AnnaBridge 171:3a7713b1edbc 2680 #define RTC_CR_CLKO_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 2681 #define RTC_CR_CLKO_SHIFT 9
AnnaBridge 171:3a7713b1edbc 2682 #define RTC_CR_SC16P_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 2683 #define RTC_CR_SC16P_SHIFT 10
AnnaBridge 171:3a7713b1edbc 2684 #define RTC_CR_SC8P_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 2685 #define RTC_CR_SC8P_SHIFT 11
AnnaBridge 171:3a7713b1edbc 2686 #define RTC_CR_SC4P_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 2687 #define RTC_CR_SC4P_SHIFT 12
AnnaBridge 171:3a7713b1edbc 2688 #define RTC_CR_SC2P_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 2689 #define RTC_CR_SC2P_SHIFT 13
AnnaBridge 171:3a7713b1edbc 2690 /* SR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2691 #define RTC_SR_TIF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2692 #define RTC_SR_TIF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2693 #define RTC_SR_TOF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2694 #define RTC_SR_TOF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2695 #define RTC_SR_TAF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2696 #define RTC_SR_TAF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2697 #define RTC_SR_TCE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2698 #define RTC_SR_TCE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2699 /* LR Bit Fields */
AnnaBridge 171:3a7713b1edbc 2700 #define RTC_LR_TCL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 2701 #define RTC_LR_TCL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 2702 #define RTC_LR_CRL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2703 #define RTC_LR_CRL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2704 #define RTC_LR_SRL_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2705 #define RTC_LR_SRL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2706 #define RTC_LR_LRL_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2707 #define RTC_LR_LRL_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2708 /* IER Bit Fields */
AnnaBridge 171:3a7713b1edbc 2709 #define RTC_IER_TIIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2710 #define RTC_IER_TIIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2711 #define RTC_IER_TOIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2712 #define RTC_IER_TOIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2713 #define RTC_IER_TAIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2714 #define RTC_IER_TAIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2715 #define RTC_IER_TSIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2716 #define RTC_IER_TSIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2717 #define RTC_IER_WPON_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2718 #define RTC_IER_WPON_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2719
AnnaBridge 171:3a7713b1edbc 2720 /**
AnnaBridge 171:3a7713b1edbc 2721 * @}
AnnaBridge 171:3a7713b1edbc 2722 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2723
AnnaBridge 171:3a7713b1edbc 2724
AnnaBridge 171:3a7713b1edbc 2725 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2726 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 2727 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 2728 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 2729 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 2730 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2731 #define RTC_BASES { RTC }
AnnaBridge 171:3a7713b1edbc 2732
AnnaBridge 171:3a7713b1edbc 2733 /**
AnnaBridge 171:3a7713b1edbc 2734 * @}
AnnaBridge 171:3a7713b1edbc 2735 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2736
AnnaBridge 171:3a7713b1edbc 2737
AnnaBridge 171:3a7713b1edbc 2738 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2739 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2740 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2741
AnnaBridge 171:3a7713b1edbc 2742 /**
AnnaBridge 171:3a7713b1edbc 2743 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2744 * @{
AnnaBridge 171:3a7713b1edbc 2745 */
AnnaBridge 171:3a7713b1edbc 2746
AnnaBridge 171:3a7713b1edbc 2747 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2748 typedef struct {
AnnaBridge 171:3a7713b1edbc 2749 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2750 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2751 uint8_t RESERVED_0[4092];
AnnaBridge 171:3a7713b1edbc 2752 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 2753 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 2754 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 2755 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 2756 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 2757 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 2758 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 2759 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 2760 uint8_t RESERVED_4[12];
AnnaBridge 171:3a7713b1edbc 2761 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 2762 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 2763 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 2764 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 2765 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 2766 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 2767 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 2768 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 2769 uint8_t RESERVED_6[4];
AnnaBridge 171:3a7713b1edbc 2770 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 2771 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 2772 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 2773 uint8_t RESERVED_7[156];
AnnaBridge 171:3a7713b1edbc 2774 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
AnnaBridge 171:3a7713b1edbc 2775 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
AnnaBridge 171:3a7713b1edbc 2776 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 2777
AnnaBridge 171:3a7713b1edbc 2778 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2779 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 2780 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2781
AnnaBridge 171:3a7713b1edbc 2782 /**
AnnaBridge 171:3a7713b1edbc 2783 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 2784 * @{
AnnaBridge 171:3a7713b1edbc 2785 */
AnnaBridge 171:3a7713b1edbc 2786
AnnaBridge 171:3a7713b1edbc 2787 /* SOPT1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2788 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
AnnaBridge 171:3a7713b1edbc 2789 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
AnnaBridge 171:3a7713b1edbc 2790 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2791 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 2792 #define SIM_SOPT1_USBVSTBY_SHIFT 29
AnnaBridge 171:3a7713b1edbc 2793 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
AnnaBridge 171:3a7713b1edbc 2794 #define SIM_SOPT1_USBSSTBY_SHIFT 30
AnnaBridge 171:3a7713b1edbc 2795 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 2796 #define SIM_SOPT1_USBREGEN_SHIFT 31
AnnaBridge 171:3a7713b1edbc 2797 /* SOPT1CFG Bit Fields */
AnnaBridge 171:3a7713b1edbc 2798 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 2799 #define SIM_SOPT1CFG_URWE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2800 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 2801 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
AnnaBridge 171:3a7713b1edbc 2802 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 2803 #define SIM_SOPT1CFG_USSWE_SHIFT 26
AnnaBridge 171:3a7713b1edbc 2804 /* SOPT2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2805 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2806 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2807 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
AnnaBridge 171:3a7713b1edbc 2808 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2809 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2810 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 2811 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2812 #define SIM_SOPT2_USBSRC_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 2813 #define SIM_SOPT2_USBSRC_SHIFT 18
AnnaBridge 171:3a7713b1edbc 2814 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
AnnaBridge 171:3a7713b1edbc 2815 #define SIM_SOPT2_TPMSRC_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2816 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2817 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
AnnaBridge 171:3a7713b1edbc 2818 #define SIM_SOPT2_UART0SRC_SHIFT 26
AnnaBridge 171:3a7713b1edbc 2819 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 2820 /* SOPT4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2821 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 2822 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
AnnaBridge 171:3a7713b1edbc 2823 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
AnnaBridge 171:3a7713b1edbc 2824 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
AnnaBridge 171:3a7713b1edbc 2825 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 2826 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2827 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 2828 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
AnnaBridge 171:3a7713b1edbc 2829 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 2830 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
AnnaBridge 171:3a7713b1edbc 2831 /* SOPT5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2832 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
AnnaBridge 171:3a7713b1edbc 2833 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2834 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2835 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 2836 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2837 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
AnnaBridge 171:3a7713b1edbc 2838 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2839 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2840 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2841 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2842 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 2843 #define SIM_SOPT5_UART0ODE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2844 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 2845 #define SIM_SOPT5_UART1ODE_SHIFT 17
AnnaBridge 171:3a7713b1edbc 2846 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 2847 #define SIM_SOPT5_UART2ODE_SHIFT 18
AnnaBridge 171:3a7713b1edbc 2848 /* SOPT7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2849 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 2850 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2851 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2852 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 2853 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
AnnaBridge 171:3a7713b1edbc 2854 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2855 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2856 /* SDID Bit Fields */
AnnaBridge 171:3a7713b1edbc 2857 #define SIM_SDID_PINID_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 2858 #define SIM_SDID_PINID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2859 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 2860 #define SIM_SDID_DIEID_MASK 0xF80u
AnnaBridge 171:3a7713b1edbc 2861 #define SIM_SDID_DIEID_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2862 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 2863 #define SIM_SDID_REVID_MASK 0xF000u
AnnaBridge 171:3a7713b1edbc 2864 #define SIM_SDID_REVID_SHIFT 12
AnnaBridge 171:3a7713b1edbc 2865 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 2866 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
AnnaBridge 171:3a7713b1edbc 2867 #define SIM_SDID_SRAMSIZE_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2868 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2869 #define SIM_SDID_SERIESID_MASK 0xF00000u
AnnaBridge 171:3a7713b1edbc 2870 #define SIM_SDID_SERIESID_SHIFT 20
AnnaBridge 171:3a7713b1edbc 2871 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 2872 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 2873 #define SIM_SDID_SUBFAMID_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2874 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 2875 #define SIM_SDID_FAMID_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 2876 #define SIM_SDID_FAMID_SHIFT 28
AnnaBridge 171:3a7713b1edbc 2877 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 2878 /* SCGC4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2879 #define SIM_SCGC4_I2C0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 2880 #define SIM_SCGC4_I2C0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 2881 #define SIM_SCGC4_I2C1_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 2882 #define SIM_SCGC4_I2C1_SHIFT 7
AnnaBridge 171:3a7713b1edbc 2883 #define SIM_SCGC4_UART0_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 2884 #define SIM_SCGC4_UART0_SHIFT 10
AnnaBridge 171:3a7713b1edbc 2885 #define SIM_SCGC4_UART1_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 2886 #define SIM_SCGC4_UART1_SHIFT 11
AnnaBridge 171:3a7713b1edbc 2887 #define SIM_SCGC4_UART2_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 2888 #define SIM_SCGC4_UART2_SHIFT 12
AnnaBridge 171:3a7713b1edbc 2889 #define SIM_SCGC4_USBOTG_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 2890 #define SIM_SCGC4_USBOTG_SHIFT 18
AnnaBridge 171:3a7713b1edbc 2891 #define SIM_SCGC4_CMP_MASK 0x80000u
AnnaBridge 171:3a7713b1edbc 2892 #define SIM_SCGC4_CMP_SHIFT 19
AnnaBridge 171:3a7713b1edbc 2893 #define SIM_SCGC4_SPI0_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 2894 #define SIM_SCGC4_SPI0_SHIFT 22
AnnaBridge 171:3a7713b1edbc 2895 #define SIM_SCGC4_SPI1_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 2896 #define SIM_SCGC4_SPI1_SHIFT 23
AnnaBridge 171:3a7713b1edbc 2897 /* SCGC5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2898 #define SIM_SCGC5_LPTMR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2899 #define SIM_SCGC5_LPTMR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2900 #define SIM_SCGC5_TSI_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 2901 #define SIM_SCGC5_TSI_SHIFT 5
AnnaBridge 171:3a7713b1edbc 2902 #define SIM_SCGC5_PORTA_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 2903 #define SIM_SCGC5_PORTA_SHIFT 9
AnnaBridge 171:3a7713b1edbc 2904 #define SIM_SCGC5_PORTB_MASK 0x400u
AnnaBridge 171:3a7713b1edbc 2905 #define SIM_SCGC5_PORTB_SHIFT 10
AnnaBridge 171:3a7713b1edbc 2906 #define SIM_SCGC5_PORTC_MASK 0x800u
AnnaBridge 171:3a7713b1edbc 2907 #define SIM_SCGC5_PORTC_SHIFT 11
AnnaBridge 171:3a7713b1edbc 2908 #define SIM_SCGC5_PORTD_MASK 0x1000u
AnnaBridge 171:3a7713b1edbc 2909 #define SIM_SCGC5_PORTD_SHIFT 12
AnnaBridge 171:3a7713b1edbc 2910 #define SIM_SCGC5_PORTE_MASK 0x2000u
AnnaBridge 171:3a7713b1edbc 2911 #define SIM_SCGC5_PORTE_SHIFT 13
AnnaBridge 171:3a7713b1edbc 2912 /* SCGC6 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2913 #define SIM_SCGC6_FTF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2914 #define SIM_SCGC6_FTF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2915 #define SIM_SCGC6_DMAMUX_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2916 #define SIM_SCGC6_DMAMUX_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2917 #define SIM_SCGC6_PIT_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 2918 #define SIM_SCGC6_PIT_SHIFT 23
AnnaBridge 171:3a7713b1edbc 2919 #define SIM_SCGC6_TPM0_MASK 0x1000000u
AnnaBridge 171:3a7713b1edbc 2920 #define SIM_SCGC6_TPM0_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2921 #define SIM_SCGC6_TPM1_MASK 0x2000000u
AnnaBridge 171:3a7713b1edbc 2922 #define SIM_SCGC6_TPM1_SHIFT 25
AnnaBridge 171:3a7713b1edbc 2923 #define SIM_SCGC6_TPM2_MASK 0x4000000u
AnnaBridge 171:3a7713b1edbc 2924 #define SIM_SCGC6_TPM2_SHIFT 26
AnnaBridge 171:3a7713b1edbc 2925 #define SIM_SCGC6_ADC0_MASK 0x8000000u
AnnaBridge 171:3a7713b1edbc 2926 #define SIM_SCGC6_ADC0_SHIFT 27
AnnaBridge 171:3a7713b1edbc 2927 #define SIM_SCGC6_RTC_MASK 0x20000000u
AnnaBridge 171:3a7713b1edbc 2928 #define SIM_SCGC6_RTC_SHIFT 29
AnnaBridge 171:3a7713b1edbc 2929 #define SIM_SCGC6_DAC0_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 2930 #define SIM_SCGC6_DAC0_SHIFT 31
AnnaBridge 171:3a7713b1edbc 2931 /* SCGC7 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2932 #define SIM_SCGC7_DMA_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 2933 #define SIM_SCGC7_DMA_SHIFT 8
AnnaBridge 171:3a7713b1edbc 2934 /* CLKDIV1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2935 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
AnnaBridge 171:3a7713b1edbc 2936 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
AnnaBridge 171:3a7713b1edbc 2937 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 2938 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 2939 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
AnnaBridge 171:3a7713b1edbc 2940 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 2941 /* FCFG1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2942 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2943 #define SIM_FCFG1_FLASHDIS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2944 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2945 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2946 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 2947 #define SIM_FCFG1_PFSIZE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2948 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2949 /* FCFG2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 2950 #define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
AnnaBridge 171:3a7713b1edbc 2951 #define SIM_FCFG2_MAXADDR_SHIFT 24
AnnaBridge 171:3a7713b1edbc 2952 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
AnnaBridge 171:3a7713b1edbc 2953 /* UIDMH Bit Fields */
AnnaBridge 171:3a7713b1edbc 2954 #define SIM_UIDMH_UID_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 2955 #define SIM_UIDMH_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2956 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 2957 /* UIDML Bit Fields */
AnnaBridge 171:3a7713b1edbc 2958 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2959 #define SIM_UIDML_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2960 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 2961 /* UIDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 2962 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
AnnaBridge 171:3a7713b1edbc 2963 #define SIM_UIDL_UID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2964 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 2965 /* COPC Bit Fields */
AnnaBridge 171:3a7713b1edbc 2966 #define SIM_COPC_COPW_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 2967 #define SIM_COPC_COPW_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2968 #define SIM_COPC_COPCLKS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 2969 #define SIM_COPC_COPCLKS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 2970 #define SIM_COPC_COPT_MASK 0xCu
AnnaBridge 171:3a7713b1edbc 2971 #define SIM_COPC_COPT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 2972 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
AnnaBridge 171:3a7713b1edbc 2973 /* SRVCOP Bit Fields */
AnnaBridge 171:3a7713b1edbc 2974 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 2975 #define SIM_SRVCOP_SRVCOP_SHIFT 0
AnnaBridge 171:3a7713b1edbc 2976 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
AnnaBridge 171:3a7713b1edbc 2977
AnnaBridge 171:3a7713b1edbc 2978 /**
AnnaBridge 171:3a7713b1edbc 2979 * @}
AnnaBridge 171:3a7713b1edbc 2980 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2981
AnnaBridge 171:3a7713b1edbc 2982
AnnaBridge 171:3a7713b1edbc 2983 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2984 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 2985 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 2986 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 2987 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 2988 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2989 #define SIM_BASES { SIM }
AnnaBridge 171:3a7713b1edbc 2990
AnnaBridge 171:3a7713b1edbc 2991 /**
AnnaBridge 171:3a7713b1edbc 2992 * @}
AnnaBridge 171:3a7713b1edbc 2993 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2994
AnnaBridge 171:3a7713b1edbc 2995
AnnaBridge 171:3a7713b1edbc 2996 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2997 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2998 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2999
AnnaBridge 171:3a7713b1edbc 3000 /**
AnnaBridge 171:3a7713b1edbc 3001 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3002 * @{
AnnaBridge 171:3a7713b1edbc 3003 */
AnnaBridge 171:3a7713b1edbc 3004
AnnaBridge 171:3a7713b1edbc 3005 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3006 typedef struct {
AnnaBridge 171:3a7713b1edbc 3007 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3008 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3009 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3010 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3011 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 3012
AnnaBridge 171:3a7713b1edbc 3013 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3014 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 3015 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3016
AnnaBridge 171:3a7713b1edbc 3017 /**
AnnaBridge 171:3a7713b1edbc 3018 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 3019 * @{
AnnaBridge 171:3a7713b1edbc 3020 */
AnnaBridge 171:3a7713b1edbc 3021
AnnaBridge 171:3a7713b1edbc 3022 /* PMPROT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3023 #define SMC_PMPROT_AVLLS_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3024 #define SMC_PMPROT_AVLLS_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3025 #define SMC_PMPROT_ALLS_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3026 #define SMC_PMPROT_ALLS_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3027 #define SMC_PMPROT_AVLP_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3028 #define SMC_PMPROT_AVLP_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3029 /* PMCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3030 #define SMC_PMCTRL_STOPM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 3031 #define SMC_PMCTRL_STOPM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3032 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 3033 #define SMC_PMCTRL_STOPA_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3034 #define SMC_PMCTRL_STOPA_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3035 #define SMC_PMCTRL_RUNM_MASK 0x60u
AnnaBridge 171:3a7713b1edbc 3036 #define SMC_PMCTRL_RUNM_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3037 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 3038 /* STOPCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3039 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 3040 #define SMC_STOPCTRL_VLLSM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3041 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
AnnaBridge 171:3a7713b1edbc 3042 #define SMC_STOPCTRL_PORPO_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3043 #define SMC_STOPCTRL_PORPO_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3044 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 3045 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3046 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 171:3a7713b1edbc 3047 /* PMSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3048 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 3049 #define SMC_PMSTAT_PMSTAT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3050 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 3051
AnnaBridge 171:3a7713b1edbc 3052 /**
AnnaBridge 171:3a7713b1edbc 3053 * @}
AnnaBridge 171:3a7713b1edbc 3054 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3055
AnnaBridge 171:3a7713b1edbc 3056
AnnaBridge 171:3a7713b1edbc 3057 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3058 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 3059 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 3060 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 3061 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 3062 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3063 #define SMC_BASES { SMC }
AnnaBridge 171:3a7713b1edbc 3064
AnnaBridge 171:3a7713b1edbc 3065 /**
AnnaBridge 171:3a7713b1edbc 3066 * @}
AnnaBridge 171:3a7713b1edbc 3067 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3068
AnnaBridge 171:3a7713b1edbc 3069
AnnaBridge 171:3a7713b1edbc 3070 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3071 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3072 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3073
AnnaBridge 171:3a7713b1edbc 3074 /**
AnnaBridge 171:3a7713b1edbc 3075 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3076 * @{
AnnaBridge 171:3a7713b1edbc 3077 */
AnnaBridge 171:3a7713b1edbc 3078
AnnaBridge 171:3a7713b1edbc 3079 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3080 typedef struct {
AnnaBridge 171:3a7713b1edbc 3081 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3082 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3083 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3084 __I uint8_t S; /**< SPI status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3085 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 3086 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3087 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 3088 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3089 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3092 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 3093 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3094
AnnaBridge 171:3a7713b1edbc 3095 /**
AnnaBridge 171:3a7713b1edbc 3096 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 3097 * @{
AnnaBridge 171:3a7713b1edbc 3098 */
AnnaBridge 171:3a7713b1edbc 3099
AnnaBridge 171:3a7713b1edbc 3100 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3101 #define SPI_C1_LSBFE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3102 #define SPI_C1_LSBFE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3103 #define SPI_C1_SSOE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3104 #define SPI_C1_SSOE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3105 #define SPI_C1_CPHA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3106 #define SPI_C1_CPHA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3107 #define SPI_C1_CPOL_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3108 #define SPI_C1_CPOL_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3109 #define SPI_C1_MSTR_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3110 #define SPI_C1_MSTR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3111 #define SPI_C1_SPTIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3112 #define SPI_C1_SPTIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3113 #define SPI_C1_SPE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3114 #define SPI_C1_SPE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3115 #define SPI_C1_SPIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3116 #define SPI_C1_SPIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3117 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3118 #define SPI_C2_SPC0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3119 #define SPI_C2_SPC0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3120 #define SPI_C2_SPISWAI_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3121 #define SPI_C2_SPISWAI_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3122 #define SPI_C2_RXDMAE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3123 #define SPI_C2_RXDMAE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3124 #define SPI_C2_BIDIROE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3125 #define SPI_C2_BIDIROE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3126 #define SPI_C2_MODFEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3127 #define SPI_C2_MODFEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3128 #define SPI_C2_TXDMAE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3129 #define SPI_C2_TXDMAE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3130 #define SPI_C2_SPLPIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3131 #define SPI_C2_SPLPIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3132 #define SPI_C2_SPMIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3133 #define SPI_C2_SPMIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3134 /* BR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3135 #define SPI_BR_SPR_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 3136 #define SPI_BR_SPR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3137 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
AnnaBridge 171:3a7713b1edbc 3138 #define SPI_BR_SPPR_MASK 0x70u
AnnaBridge 171:3a7713b1edbc 3139 #define SPI_BR_SPPR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3140 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
AnnaBridge 171:3a7713b1edbc 3141 /* S Bit Fields */
AnnaBridge 171:3a7713b1edbc 3142 #define SPI_S_MODF_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3143 #define SPI_S_MODF_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3144 #define SPI_S_SPTEF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3145 #define SPI_S_SPTEF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3146 #define SPI_S_SPMF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3147 #define SPI_S_SPMF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3148 #define SPI_S_SPRF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3149 #define SPI_S_SPRF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3150 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 3151 #define SPI_D_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3152 #define SPI_D_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3153 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 3154 /* M Bit Fields */
AnnaBridge 171:3a7713b1edbc 3155 #define SPI_M_Bits_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3156 #define SPI_M_Bits_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3157 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 3158
AnnaBridge 171:3a7713b1edbc 3159 /**
AnnaBridge 171:3a7713b1edbc 3160 * @}
AnnaBridge 171:3a7713b1edbc 3161 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3162
AnnaBridge 171:3a7713b1edbc 3163
AnnaBridge 171:3a7713b1edbc 3164 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3165 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 3166 #define SPI0_BASE (0x40076000u)
AnnaBridge 171:3a7713b1edbc 3167 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 3168 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 3169 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 3170 #define SPI1_BASE (0x40077000u)
AnnaBridge 171:3a7713b1edbc 3171 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 3172 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 3173 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3174 #define SPI_BASES { SPI0, SPI1 }
AnnaBridge 171:3a7713b1edbc 3175
AnnaBridge 171:3a7713b1edbc 3176 /**
AnnaBridge 171:3a7713b1edbc 3177 * @}
AnnaBridge 171:3a7713b1edbc 3178 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3179
AnnaBridge 171:3a7713b1edbc 3180
AnnaBridge 171:3a7713b1edbc 3181 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3182 -- TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3183 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3184
AnnaBridge 171:3a7713b1edbc 3185 /**
AnnaBridge 171:3a7713b1edbc 3186 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3187 * @{
AnnaBridge 171:3a7713b1edbc 3188 */
AnnaBridge 171:3a7713b1edbc 3189
AnnaBridge 171:3a7713b1edbc 3190 /** TPM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3191 typedef struct {
AnnaBridge 171:3a7713b1edbc 3192 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3193 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3194 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3195 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3196 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3197 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 3198 } CONTROLS[6];
AnnaBridge 171:3a7713b1edbc 3199 uint8_t RESERVED_0[20];
AnnaBridge 171:3a7713b1edbc 3200 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 3201 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 3202 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 3203 } TPM_Type;
AnnaBridge 171:3a7713b1edbc 3204
AnnaBridge 171:3a7713b1edbc 3205 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3206 -- TPM Register Masks
AnnaBridge 171:3a7713b1edbc 3207 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3208
AnnaBridge 171:3a7713b1edbc 3209 /**
AnnaBridge 171:3a7713b1edbc 3210 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 171:3a7713b1edbc 3211 * @{
AnnaBridge 171:3a7713b1edbc 3212 */
AnnaBridge 171:3a7713b1edbc 3213
AnnaBridge 171:3a7713b1edbc 3214 /* SC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3215 #define TPM_SC_PS_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 3216 #define TPM_SC_PS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3217 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 3218 #define TPM_SC_CMOD_MASK 0x18u
AnnaBridge 171:3a7713b1edbc 3219 #define TPM_SC_CMOD_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3220 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 3221 #define TPM_SC_CPWMS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3222 #define TPM_SC_CPWMS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3223 #define TPM_SC_TOIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3224 #define TPM_SC_TOIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3225 #define TPM_SC_TOF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3226 #define TPM_SC_TOF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3227 #define TPM_SC_DMA_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 3228 #define TPM_SC_DMA_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3229 /* CNT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3230 #define TPM_CNT_COUNT_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3231 #define TPM_CNT_COUNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3232 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 3233 /* MOD Bit Fields */
AnnaBridge 171:3a7713b1edbc 3234 #define TPM_MOD_MOD_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3235 #define TPM_MOD_MOD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3236 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 3237 /* CnSC Bit Fields */
AnnaBridge 171:3a7713b1edbc 3238 #define TPM_CnSC_DMA_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3239 #define TPM_CnSC_DMA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3240 #define TPM_CnSC_ELSA_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3241 #define TPM_CnSC_ELSA_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3242 #define TPM_CnSC_ELSB_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3243 #define TPM_CnSC_ELSB_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3244 #define TPM_CnSC_MSA_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3245 #define TPM_CnSC_MSA_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3246 #define TPM_CnSC_MSB_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3247 #define TPM_CnSC_MSB_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3248 #define TPM_CnSC_CHIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3249 #define TPM_CnSC_CHIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3250 #define TPM_CnSC_CHF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3251 #define TPM_CnSC_CHF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3252 /* CnV Bit Fields */
AnnaBridge 171:3a7713b1edbc 3253 #define TPM_CnV_VAL_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3254 #define TPM_CnV_VAL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3255 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 3256 /* STATUS Bit Fields */
AnnaBridge 171:3a7713b1edbc 3257 #define TPM_STATUS_CH0F_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3258 #define TPM_STATUS_CH0F_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3259 #define TPM_STATUS_CH1F_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3260 #define TPM_STATUS_CH1F_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3261 #define TPM_STATUS_CH2F_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3262 #define TPM_STATUS_CH2F_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3263 #define TPM_STATUS_CH3F_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3264 #define TPM_STATUS_CH3F_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3265 #define TPM_STATUS_CH4F_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3266 #define TPM_STATUS_CH4F_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3267 #define TPM_STATUS_CH5F_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3268 #define TPM_STATUS_CH5F_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3269 #define TPM_STATUS_TOF_MASK 0x100u
AnnaBridge 171:3a7713b1edbc 3270 #define TPM_STATUS_TOF_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3271 /* CONF Bit Fields */
AnnaBridge 171:3a7713b1edbc 3272 #define TPM_CONF_DOZEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3273 #define TPM_CONF_DOZEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3274 #define TPM_CONF_DBGMODE_MASK 0xC0u
AnnaBridge 171:3a7713b1edbc 3275 #define TPM_CONF_DBGMODE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3276 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3277 #define TPM_CONF_GTBEEN_MASK 0x200u
AnnaBridge 171:3a7713b1edbc 3278 #define TPM_CONF_GTBEEN_SHIFT 9
AnnaBridge 171:3a7713b1edbc 3279 #define TPM_CONF_CSOT_MASK 0x10000u
AnnaBridge 171:3a7713b1edbc 3280 #define TPM_CONF_CSOT_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3281 #define TPM_CONF_CSOO_MASK 0x20000u
AnnaBridge 171:3a7713b1edbc 3282 #define TPM_CONF_CSOO_SHIFT 17
AnnaBridge 171:3a7713b1edbc 3283 #define TPM_CONF_CROT_MASK 0x40000u
AnnaBridge 171:3a7713b1edbc 3284 #define TPM_CONF_CROT_SHIFT 18
AnnaBridge 171:3a7713b1edbc 3285 #define TPM_CONF_TRGSEL_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 3286 #define TPM_CONF_TRGSEL_SHIFT 24
AnnaBridge 171:3a7713b1edbc 3287 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3288
AnnaBridge 171:3a7713b1edbc 3289 /**
AnnaBridge 171:3a7713b1edbc 3290 * @}
AnnaBridge 171:3a7713b1edbc 3291 */ /* end of group TPM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3292
AnnaBridge 171:3a7713b1edbc 3293
AnnaBridge 171:3a7713b1edbc 3294 /* TPM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3295 /** Peripheral TPM0 base address */
AnnaBridge 171:3a7713b1edbc 3296 #define TPM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 3297 /** Peripheral TPM0 base pointer */
AnnaBridge 171:3a7713b1edbc 3298 #define TPM0 ((TPM_Type *)TPM0_BASE)
AnnaBridge 171:3a7713b1edbc 3299 /** Peripheral TPM1 base address */
AnnaBridge 171:3a7713b1edbc 3300 #define TPM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 3301 /** Peripheral TPM1 base pointer */
AnnaBridge 171:3a7713b1edbc 3302 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 171:3a7713b1edbc 3303 /** Peripheral TPM2 base address */
AnnaBridge 171:3a7713b1edbc 3304 #define TPM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 3305 /** Peripheral TPM2 base pointer */
AnnaBridge 171:3a7713b1edbc 3306 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 171:3a7713b1edbc 3307 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3308 #define TPM_BASES { TPM0, TPM1, TPM2 }
AnnaBridge 171:3a7713b1edbc 3309
AnnaBridge 171:3a7713b1edbc 3310 /**
AnnaBridge 171:3a7713b1edbc 3311 * @}
AnnaBridge 171:3a7713b1edbc 3312 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3313
AnnaBridge 171:3a7713b1edbc 3314
AnnaBridge 171:3a7713b1edbc 3315 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3316 -- TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3317 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3318
AnnaBridge 171:3a7713b1edbc 3319 /**
AnnaBridge 171:3a7713b1edbc 3320 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3321 * @{
AnnaBridge 171:3a7713b1edbc 3322 */
AnnaBridge 171:3a7713b1edbc 3323
AnnaBridge 171:3a7713b1edbc 3324 /** TSI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3325 typedef struct {
AnnaBridge 171:3a7713b1edbc 3326 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3327 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3328 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3329 } TSI_Type;
AnnaBridge 171:3a7713b1edbc 3330
AnnaBridge 171:3a7713b1edbc 3331 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3332 -- TSI Register Masks
AnnaBridge 171:3a7713b1edbc 3333 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3334
AnnaBridge 171:3a7713b1edbc 3335 /**
AnnaBridge 171:3a7713b1edbc 3336 * @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge 171:3a7713b1edbc 3337 * @{
AnnaBridge 171:3a7713b1edbc 3338 */
AnnaBridge 171:3a7713b1edbc 3339
AnnaBridge 171:3a7713b1edbc 3340 /* GENCS Bit Fields */
AnnaBridge 171:3a7713b1edbc 3341 #define TSI_GENCS_CURSW_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3342 #define TSI_GENCS_CURSW_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3343 #define TSI_GENCS_EOSF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3344 #define TSI_GENCS_EOSF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3345 #define TSI_GENCS_SCNIP_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3346 #define TSI_GENCS_SCNIP_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3347 #define TSI_GENCS_STM_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3348 #define TSI_GENCS_STM_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3349 #define TSI_GENCS_STPE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3350 #define TSI_GENCS_STPE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3351 #define TSI_GENCS_TSIIEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3352 #define TSI_GENCS_TSIIEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3353 #define TSI_GENCS_TSIEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3354 #define TSI_GENCS_TSIEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3355 #define TSI_GENCS_NSCN_MASK 0x1F00u
AnnaBridge 171:3a7713b1edbc 3356 #define TSI_GENCS_NSCN_SHIFT 8
AnnaBridge 171:3a7713b1edbc 3357 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
AnnaBridge 171:3a7713b1edbc 3358 #define TSI_GENCS_PS_MASK 0xE000u
AnnaBridge 171:3a7713b1edbc 3359 #define TSI_GENCS_PS_SHIFT 13
AnnaBridge 171:3a7713b1edbc 3360 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
AnnaBridge 171:3a7713b1edbc 3361 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
AnnaBridge 171:3a7713b1edbc 3362 #define TSI_GENCS_EXTCHRG_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3363 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 3364 #define TSI_GENCS_DVOLT_MASK 0x180000u
AnnaBridge 171:3a7713b1edbc 3365 #define TSI_GENCS_DVOLT_SHIFT 19
AnnaBridge 171:3a7713b1edbc 3366 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
AnnaBridge 171:3a7713b1edbc 3367 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
AnnaBridge 171:3a7713b1edbc 3368 #define TSI_GENCS_REFCHRG_SHIFT 21
AnnaBridge 171:3a7713b1edbc 3369 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 3370 #define TSI_GENCS_MODE_MASK 0xF000000u
AnnaBridge 171:3a7713b1edbc 3371 #define TSI_GENCS_MODE_SHIFT 24
AnnaBridge 171:3a7713b1edbc 3372 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 3373 #define TSI_GENCS_ESOR_MASK 0x10000000u
AnnaBridge 171:3a7713b1edbc 3374 #define TSI_GENCS_ESOR_SHIFT 28
AnnaBridge 171:3a7713b1edbc 3375 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
AnnaBridge 171:3a7713b1edbc 3376 #define TSI_GENCS_OUTRGF_SHIFT 31
AnnaBridge 171:3a7713b1edbc 3377 /* DATA Bit Fields */
AnnaBridge 171:3a7713b1edbc 3378 #define TSI_DATA_TSICNT_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3379 #define TSI_DATA_TSICNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3380 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
AnnaBridge 171:3a7713b1edbc 3381 #define TSI_DATA_SWTS_MASK 0x400000u
AnnaBridge 171:3a7713b1edbc 3382 #define TSI_DATA_SWTS_SHIFT 22
AnnaBridge 171:3a7713b1edbc 3383 #define TSI_DATA_DMAEN_MASK 0x800000u
AnnaBridge 171:3a7713b1edbc 3384 #define TSI_DATA_DMAEN_SHIFT 23
AnnaBridge 171:3a7713b1edbc 3385 #define TSI_DATA_TSICH_MASK 0xF0000000u
AnnaBridge 171:3a7713b1edbc 3386 #define TSI_DATA_TSICH_SHIFT 28
AnnaBridge 171:3a7713b1edbc 3387 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
AnnaBridge 171:3a7713b1edbc 3388 /* TSHD Bit Fields */
AnnaBridge 171:3a7713b1edbc 3389 #define TSI_TSHD_THRESL_MASK 0xFFFFu
AnnaBridge 171:3a7713b1edbc 3390 #define TSI_TSHD_THRESL_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3391 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
AnnaBridge 171:3a7713b1edbc 3392 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
AnnaBridge 171:3a7713b1edbc 3393 #define TSI_TSHD_THRESH_SHIFT 16
AnnaBridge 171:3a7713b1edbc 3394 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 3395
AnnaBridge 171:3a7713b1edbc 3396 /**
AnnaBridge 171:3a7713b1edbc 3397 * @}
AnnaBridge 171:3a7713b1edbc 3398 */ /* end of group TSI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3399
AnnaBridge 171:3a7713b1edbc 3400
AnnaBridge 171:3a7713b1edbc 3401 /* TSI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3402 /** Peripheral TSI0 base address */
AnnaBridge 171:3a7713b1edbc 3403 #define TSI0_BASE (0x40045000u)
AnnaBridge 171:3a7713b1edbc 3404 /** Peripheral TSI0 base pointer */
AnnaBridge 171:3a7713b1edbc 3405 #define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge 171:3a7713b1edbc 3406 /** Array initializer of TSI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3407 #define TSI_BASES { TSI0 }
AnnaBridge 171:3a7713b1edbc 3408
AnnaBridge 171:3a7713b1edbc 3409 /**
AnnaBridge 171:3a7713b1edbc 3410 * @}
AnnaBridge 171:3a7713b1edbc 3411 */ /* end of group TSI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3412
AnnaBridge 171:3a7713b1edbc 3413
AnnaBridge 171:3a7713b1edbc 3414 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3415 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3416 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3417
AnnaBridge 171:3a7713b1edbc 3418 /**
AnnaBridge 171:3a7713b1edbc 3419 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3420 * @{
AnnaBridge 171:3a7713b1edbc 3421 */
AnnaBridge 171:3a7713b1edbc 3422
AnnaBridge 171:3a7713b1edbc 3423 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3424 typedef struct {
AnnaBridge 171:3a7713b1edbc 3425 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3426 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3427 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3428 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3429 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3430 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3431 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3432 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3433 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3434 } UART_Type;
AnnaBridge 171:3a7713b1edbc 3435
AnnaBridge 171:3a7713b1edbc 3436 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3437 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 3438 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3439
AnnaBridge 171:3a7713b1edbc 3440 /**
AnnaBridge 171:3a7713b1edbc 3441 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 3442 * @{
AnnaBridge 171:3a7713b1edbc 3443 */
AnnaBridge 171:3a7713b1edbc 3444
AnnaBridge 171:3a7713b1edbc 3445 /* BDH Bit Fields */
AnnaBridge 171:3a7713b1edbc 3446 #define UART_BDH_SBR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3447 #define UART_BDH_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3448 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 3449 #define UART_BDH_SBNS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3450 #define UART_BDH_SBNS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3451 #define UART_BDH_RXEDGIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3452 #define UART_BDH_RXEDGIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3453 #define UART_BDH_LBKDIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3454 #define UART_BDH_LBKDIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3455 /* BDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3456 #define UART_BDL_SBR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3457 #define UART_BDL_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3458 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 3459 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3460 #define UART_C1_PT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3461 #define UART_C1_PT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3462 #define UART_C1_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3463 #define UART_C1_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3464 #define UART_C1_ILT_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3465 #define UART_C1_ILT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3466 #define UART_C1_WAKE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3467 #define UART_C1_WAKE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3468 #define UART_C1_M_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3469 #define UART_C1_M_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3470 #define UART_C1_RSRC_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3471 #define UART_C1_RSRC_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3472 #define UART_C1_UARTSWAI_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3473 #define UART_C1_UARTSWAI_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3474 #define UART_C1_LOOPS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3475 #define UART_C1_LOOPS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3476 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3477 #define UART_C2_SBK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3478 #define UART_C2_SBK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3479 #define UART_C2_RWU_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3480 #define UART_C2_RWU_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3481 #define UART_C2_RE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3482 #define UART_C2_RE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3483 #define UART_C2_TE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3484 #define UART_C2_TE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3485 #define UART_C2_ILIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3486 #define UART_C2_ILIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3487 #define UART_C2_RIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3488 #define UART_C2_RIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3489 #define UART_C2_TCIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3490 #define UART_C2_TCIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3491 #define UART_C2_TIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3492 #define UART_C2_TIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3493 /* S1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3494 #define UART_S1_PF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3495 #define UART_S1_PF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3496 #define UART_S1_FE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3497 #define UART_S1_FE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3498 #define UART_S1_NF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3499 #define UART_S1_NF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3500 #define UART_S1_OR_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3501 #define UART_S1_OR_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3502 #define UART_S1_IDLE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3503 #define UART_S1_IDLE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3504 #define UART_S1_RDRF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3505 #define UART_S1_RDRF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3506 #define UART_S1_TC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3507 #define UART_S1_TC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3508 #define UART_S1_TDRE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3509 #define UART_S1_TDRE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3510 /* S2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3511 #define UART_S2_RAF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3512 #define UART_S2_RAF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3513 #define UART_S2_LBKDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3514 #define UART_S2_LBKDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3515 #define UART_S2_BRK13_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3516 #define UART_S2_BRK13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3517 #define UART_S2_RWUID_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3518 #define UART_S2_RWUID_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3519 #define UART_S2_RXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3520 #define UART_S2_RXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3521 #define UART_S2_RXEDGIF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3522 #define UART_S2_RXEDGIF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3523 #define UART_S2_LBKDIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3524 #define UART_S2_LBKDIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3525 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3526 #define UART_C3_PEIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3527 #define UART_C3_PEIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3528 #define UART_C3_FEIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3529 #define UART_C3_FEIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3530 #define UART_C3_NEIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3531 #define UART_C3_NEIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3532 #define UART_C3_ORIE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3533 #define UART_C3_ORIE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3534 #define UART_C3_TXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3535 #define UART_C3_TXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3536 #define UART_C3_TXDIR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3537 #define UART_C3_TXDIR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3538 #define UART_C3_T8_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3539 #define UART_C3_T8_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3540 #define UART_C3_R8_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3541 #define UART_C3_R8_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3542 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 3543 #define UART_D_R0T0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3544 #define UART_D_R0T0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3545 #define UART_D_R1T1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3546 #define UART_D_R1T1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3547 #define UART_D_R2T2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3548 #define UART_D_R2T2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3549 #define UART_D_R3T3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3550 #define UART_D_R3T3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3551 #define UART_D_R4T4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3552 #define UART_D_R4T4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3553 #define UART_D_R5T5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3554 #define UART_D_R5T5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3555 #define UART_D_R6T6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3556 #define UART_D_R6T6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3557 #define UART_D_R7T7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3558 #define UART_D_R7T7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3559 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3560 #define UART_C4_LBKDDMAS_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3561 #define UART_C4_LBKDDMAS_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3562 #define UART_C4_ILDMAS_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3563 #define UART_C4_ILDMAS_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3564 #define UART_C4_RDMAS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3565 #define UART_C4_RDMAS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3566 #define UART_C4_TCDMAS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3567 #define UART_C4_TCDMAS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3568 #define UART_C4_TDMAS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3569 #define UART_C4_TDMAS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3570
AnnaBridge 171:3a7713b1edbc 3571 /**
AnnaBridge 171:3a7713b1edbc 3572 * @}
AnnaBridge 171:3a7713b1edbc 3573 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3574
AnnaBridge 171:3a7713b1edbc 3575
AnnaBridge 171:3a7713b1edbc 3576 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3577 /** Peripheral UART1 base address */
AnnaBridge 171:3a7713b1edbc 3578 #define UART1_BASE (0x4006B000u)
AnnaBridge 171:3a7713b1edbc 3579 /** Peripheral UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 3580 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 171:3a7713b1edbc 3581 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 3582 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 3583 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 3584 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 3585 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3586 #define UART_BASES { UART1, UART2 }
AnnaBridge 171:3a7713b1edbc 3587
AnnaBridge 171:3a7713b1edbc 3588 /**
AnnaBridge 171:3a7713b1edbc 3589 * @}
AnnaBridge 171:3a7713b1edbc 3590 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3591
AnnaBridge 171:3a7713b1edbc 3592
AnnaBridge 171:3a7713b1edbc 3593 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3594 -- UARTLP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3595 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3596
AnnaBridge 171:3a7713b1edbc 3597 /**
AnnaBridge 171:3a7713b1edbc 3598 * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3599 * @{
AnnaBridge 171:3a7713b1edbc 3600 */
AnnaBridge 171:3a7713b1edbc 3601
AnnaBridge 171:3a7713b1edbc 3602 /** UARTLP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3603 typedef struct {
AnnaBridge 171:3a7713b1edbc 3604 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3605 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3606 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3607 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3608 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3609 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3610 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3611 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3612 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3613 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3614 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3615 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3616 } UARTLP_Type;
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3619 -- UARTLP Register Masks
AnnaBridge 171:3a7713b1edbc 3620 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3621
AnnaBridge 171:3a7713b1edbc 3622 /**
AnnaBridge 171:3a7713b1edbc 3623 * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
AnnaBridge 171:3a7713b1edbc 3624 * @{
AnnaBridge 171:3a7713b1edbc 3625 */
AnnaBridge 171:3a7713b1edbc 3626
AnnaBridge 171:3a7713b1edbc 3627 /* BDH Bit Fields */
AnnaBridge 171:3a7713b1edbc 3628 #define UARTLP_BDH_SBR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3629 #define UARTLP_BDH_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3630 #define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 3631 #define UARTLP_BDH_SBNS_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3632 #define UARTLP_BDH_SBNS_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3633 #define UARTLP_BDH_RXEDGIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3634 #define UARTLP_BDH_RXEDGIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3635 #define UARTLP_BDH_LBKDIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3636 #define UARTLP_BDH_LBKDIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3637 /* BDL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3638 #define UARTLP_BDL_SBR_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3639 #define UARTLP_BDL_SBR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3640 #define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 3641 /* C1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3642 #define UARTLP_C1_PT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3643 #define UARTLP_C1_PT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3644 #define UARTLP_C1_PE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3645 #define UARTLP_C1_PE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3646 #define UARTLP_C1_ILT_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3647 #define UARTLP_C1_ILT_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3648 #define UARTLP_C1_WAKE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3649 #define UARTLP_C1_WAKE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3650 #define UARTLP_C1_M_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3651 #define UARTLP_C1_M_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3652 #define UARTLP_C1_RSRC_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3653 #define UARTLP_C1_RSRC_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3654 #define UARTLP_C1_DOZEEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3655 #define UARTLP_C1_DOZEEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3656 #define UARTLP_C1_LOOPS_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3657 #define UARTLP_C1_LOOPS_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3658 /* C2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3659 #define UARTLP_C2_SBK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3660 #define UARTLP_C2_SBK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3661 #define UARTLP_C2_RWU_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3662 #define UARTLP_C2_RWU_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3663 #define UARTLP_C2_RE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3664 #define UARTLP_C2_RE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3665 #define UARTLP_C2_TE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3666 #define UARTLP_C2_TE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3667 #define UARTLP_C2_ILIE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3668 #define UARTLP_C2_ILIE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3669 #define UARTLP_C2_RIE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3670 #define UARTLP_C2_RIE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3671 #define UARTLP_C2_TCIE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3672 #define UARTLP_C2_TCIE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3673 #define UARTLP_C2_TIE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3674 #define UARTLP_C2_TIE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3675 /* S1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3676 #define UARTLP_S1_PF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3677 #define UARTLP_S1_PF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3678 #define UARTLP_S1_FE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3679 #define UARTLP_S1_FE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3680 #define UARTLP_S1_NF_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3681 #define UARTLP_S1_NF_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3682 #define UARTLP_S1_OR_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3683 #define UARTLP_S1_OR_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3684 #define UARTLP_S1_IDLE_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3685 #define UARTLP_S1_IDLE_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3686 #define UARTLP_S1_RDRF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3687 #define UARTLP_S1_RDRF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3688 #define UARTLP_S1_TC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3689 #define UARTLP_S1_TC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3690 #define UARTLP_S1_TDRE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3691 #define UARTLP_S1_TDRE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3692 /* S2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3693 #define UARTLP_S2_RAF_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3694 #define UARTLP_S2_RAF_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3695 #define UARTLP_S2_LBKDE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3696 #define UARTLP_S2_LBKDE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3697 #define UARTLP_S2_BRK13_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3698 #define UARTLP_S2_BRK13_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3699 #define UARTLP_S2_RWUID_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3700 #define UARTLP_S2_RWUID_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3701 #define UARTLP_S2_RXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3702 #define UARTLP_S2_RXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3703 #define UARTLP_S2_MSBF_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3704 #define UARTLP_S2_MSBF_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3705 #define UARTLP_S2_RXEDGIF_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3706 #define UARTLP_S2_RXEDGIF_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3707 #define UARTLP_S2_LBKDIF_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3708 #define UARTLP_S2_LBKDIF_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3709 /* C3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3710 #define UARTLP_C3_PEIE_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3711 #define UARTLP_C3_PEIE_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3712 #define UARTLP_C3_FEIE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3713 #define UARTLP_C3_FEIE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3714 #define UARTLP_C3_NEIE_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3715 #define UARTLP_C3_NEIE_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3716 #define UARTLP_C3_ORIE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3717 #define UARTLP_C3_ORIE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3718 #define UARTLP_C3_TXINV_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3719 #define UARTLP_C3_TXINV_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3720 #define UARTLP_C3_TXDIR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3721 #define UARTLP_C3_TXDIR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3722 #define UARTLP_C3_R9T8_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3723 #define UARTLP_C3_R9T8_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3724 #define UARTLP_C3_R8T9_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3725 #define UARTLP_C3_R8T9_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3726 /* D Bit Fields */
AnnaBridge 171:3a7713b1edbc 3727 #define UARTLP_D_R0T0_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3728 #define UARTLP_D_R0T0_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3729 #define UARTLP_D_R1T1_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3730 #define UARTLP_D_R1T1_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3731 #define UARTLP_D_R2T2_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3732 #define UARTLP_D_R2T2_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3733 #define UARTLP_D_R3T3_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3734 #define UARTLP_D_R3T3_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3735 #define UARTLP_D_R4T4_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3736 #define UARTLP_D_R4T4_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3737 #define UARTLP_D_R5T5_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3738 #define UARTLP_D_R5T5_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3739 #define UARTLP_D_R6T6_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3740 #define UARTLP_D_R6T6_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3741 #define UARTLP_D_R7T7_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3742 #define UARTLP_D_R7T7_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3743 /* MA1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3744 #define UARTLP_MA1_MA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3745 #define UARTLP_MA1_MA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3746 #define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 3747 /* MA2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3748 #define UARTLP_MA2_MA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3749 #define UARTLP_MA2_MA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3750 #define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 3751 /* C4 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3752 #define UARTLP_C4_OSR_MASK 0x1Fu
AnnaBridge 171:3a7713b1edbc 3753 #define UARTLP_C4_OSR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3754 #define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 3755 #define UARTLP_C4_M10_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3756 #define UARTLP_C4_M10_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3757 #define UARTLP_C4_MAEN2_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3758 #define UARTLP_C4_MAEN2_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3759 #define UARTLP_C4_MAEN1_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3760 #define UARTLP_C4_MAEN1_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3761 /* C5 Bit Fields */
AnnaBridge 171:3a7713b1edbc 3762 #define UARTLP_C5_RESYNCDIS_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3763 #define UARTLP_C5_RESYNCDIS_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3764 #define UARTLP_C5_BOTHEDGE_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3765 #define UARTLP_C5_BOTHEDGE_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3766 #define UARTLP_C5_RDMAE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3767 #define UARTLP_C5_RDMAE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3768 #define UARTLP_C5_TDMAE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3769 #define UARTLP_C5_TDMAE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3770
AnnaBridge 171:3a7713b1edbc 3771 /**
AnnaBridge 171:3a7713b1edbc 3772 * @}
AnnaBridge 171:3a7713b1edbc 3773 */ /* end of group UARTLP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3774
AnnaBridge 171:3a7713b1edbc 3775
AnnaBridge 171:3a7713b1edbc 3776 /* UARTLP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3777 /** Peripheral UART0 base address */
AnnaBridge 171:3a7713b1edbc 3778 #define UART0_BASE (0x4006A000u)
AnnaBridge 171:3a7713b1edbc 3779 /** Peripheral UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 3780 #define UART0 ((UARTLP_Type *)UART0_BASE)
AnnaBridge 171:3a7713b1edbc 3781 /** Array initializer of UARTLP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3782 #define UARTLP_BASES { UART0 }
AnnaBridge 171:3a7713b1edbc 3783
AnnaBridge 171:3a7713b1edbc 3784 /**
AnnaBridge 171:3a7713b1edbc 3785 * @}
AnnaBridge 171:3a7713b1edbc 3786 */ /* end of group UARTLP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3787
AnnaBridge 171:3a7713b1edbc 3788
AnnaBridge 171:3a7713b1edbc 3789 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3790 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3791 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3792
AnnaBridge 171:3a7713b1edbc 3793 /**
AnnaBridge 171:3a7713b1edbc 3794 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3795 * @{
AnnaBridge 171:3a7713b1edbc 3796 */
AnnaBridge 171:3a7713b1edbc 3797
AnnaBridge 171:3a7713b1edbc 3798 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3799 typedef struct {
AnnaBridge 171:3a7713b1edbc 3800 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3801 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 3802 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3803 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 3804 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3805 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 3806 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3807 uint8_t RESERVED_3[3];
AnnaBridge 171:3a7713b1edbc 3808 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 3809 uint8_t RESERVED_4[3];
AnnaBridge 171:3a7713b1edbc 3810 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3811 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 3812 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 3813 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 3814 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 3815 uint8_t RESERVED_7[99];
AnnaBridge 171:3a7713b1edbc 3816 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 3817 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 3818 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 3819 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 3820 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 3821 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 3822 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 3823 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 3824 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 3825 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 3826 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 3827 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 3828 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 3829 uint8_t RESERVED_14[3];
AnnaBridge 171:3a7713b1edbc 3830 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 3831 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 3832 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 3833 uint8_t RESERVED_16[3];
AnnaBridge 171:3a7713b1edbc 3834 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 3835 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 3836 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 3837 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 3838 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 3839 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 3840 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 3841 uint8_t RESERVED_20[3];
AnnaBridge 171:3a7713b1edbc 3842 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 3843 uint8_t RESERVED_21[11];
AnnaBridge 171:3a7713b1edbc 3844 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3845 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3846 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 3847 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 3848 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 3849 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 3850 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 3851 uint8_t RESERVED_23[3];
AnnaBridge 171:3a7713b1edbc 3852 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 3853 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 3854 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 3855 } USB_Type;
AnnaBridge 171:3a7713b1edbc 3856
AnnaBridge 171:3a7713b1edbc 3857 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3858 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 3859 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3860
AnnaBridge 171:3a7713b1edbc 3861 /**
AnnaBridge 171:3a7713b1edbc 3862 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 3863 * @{
AnnaBridge 171:3a7713b1edbc 3864 */
AnnaBridge 171:3a7713b1edbc 3865
AnnaBridge 171:3a7713b1edbc 3866 /* PERID Bit Fields */
AnnaBridge 171:3a7713b1edbc 3867 #define USB_PERID_ID_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 3868 #define USB_PERID_ID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3869 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 3870 /* IDCOMP Bit Fields */
AnnaBridge 171:3a7713b1edbc 3871 #define USB_IDCOMP_NID_MASK 0x3Fu
AnnaBridge 171:3a7713b1edbc 3872 #define USB_IDCOMP_NID_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3873 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 3874 /* REV Bit Fields */
AnnaBridge 171:3a7713b1edbc 3875 #define USB_REV_REV_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 3876 #define USB_REV_REV_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3877 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 3878 /* ADDINFO Bit Fields */
AnnaBridge 171:3a7713b1edbc 3879 #define USB_ADDINFO_IEHOST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3880 #define USB_ADDINFO_IEHOST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3881 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
AnnaBridge 171:3a7713b1edbc 3882 #define USB_ADDINFO_IRQNUM_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3883 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
AnnaBridge 171:3a7713b1edbc 3884 /* OTGISTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3885 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3886 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3887 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3888 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3889 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3890 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3891 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3892 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3893 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3894 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3895 #define USB_OTGISTAT_IDCHG_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3896 #define USB_OTGISTAT_IDCHG_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3897 /* OTGICR Bit Fields */
AnnaBridge 171:3a7713b1edbc 3898 #define USB_OTGICR_AVBUSEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3899 #define USB_OTGICR_AVBUSEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3900 #define USB_OTGICR_BSESSEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3901 #define USB_OTGICR_BSESSEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3902 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3903 #define USB_OTGICR_SESSVLDEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3904 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3905 #define USB_OTGICR_LINESTATEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3906 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3907 #define USB_OTGICR_ONEMSECEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3908 #define USB_OTGICR_IDEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3909 #define USB_OTGICR_IDEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3910 /* OTGSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3911 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3912 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3913 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3914 #define USB_OTGSTAT_BSESSEND_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3915 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3916 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3917 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3918 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3919 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3920 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3921 #define USB_OTGSTAT_ID_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3922 #define USB_OTGSTAT_ID_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3923 /* OTGCTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 3924 #define USB_OTGCTL_OTGEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3925 #define USB_OTGCTL_OTGEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3926 #define USB_OTGCTL_DMLOW_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3927 #define USB_OTGCTL_DMLOW_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3928 #define USB_OTGCTL_DPLOW_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3929 #define USB_OTGCTL_DPLOW_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3930 #define USB_OTGCTL_DPHIGH_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3931 #define USB_OTGCTL_DPHIGH_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3932 /* ISTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3933 #define USB_ISTAT_USBRST_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3934 #define USB_ISTAT_USBRST_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3935 #define USB_ISTAT_ERROR_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3936 #define USB_ISTAT_ERROR_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3937 #define USB_ISTAT_SOFTOK_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3938 #define USB_ISTAT_SOFTOK_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3939 #define USB_ISTAT_TOKDNE_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3940 #define USB_ISTAT_TOKDNE_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3941 #define USB_ISTAT_SLEEP_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3942 #define USB_ISTAT_SLEEP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3943 #define USB_ISTAT_RESUME_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3944 #define USB_ISTAT_RESUME_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3945 #define USB_ISTAT_ATTACH_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3946 #define USB_ISTAT_ATTACH_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3947 #define USB_ISTAT_STALL_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3948 #define USB_ISTAT_STALL_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3949 /* INTEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 3950 #define USB_INTEN_USBRSTEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3951 #define USB_INTEN_USBRSTEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3952 #define USB_INTEN_ERROREN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3953 #define USB_INTEN_ERROREN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3954 #define USB_INTEN_SOFTOKEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3955 #define USB_INTEN_SOFTOKEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3956 #define USB_INTEN_TOKDNEEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3957 #define USB_INTEN_TOKDNEEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3958 #define USB_INTEN_SLEEPEN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3959 #define USB_INTEN_SLEEPEN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3960 #define USB_INTEN_RESUMEEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3961 #define USB_INTEN_RESUMEEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3962 #define USB_INTEN_ATTACHEN_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 3963 #define USB_INTEN_ATTACHEN_SHIFT 6
AnnaBridge 171:3a7713b1edbc 3964 #define USB_INTEN_STALLEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3965 #define USB_INTEN_STALLEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3966 /* ERRSTAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3967 #define USB_ERRSTAT_PIDERR_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3968 #define USB_ERRSTAT_PIDERR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3969 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3970 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3971 #define USB_ERRSTAT_CRC16_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3972 #define USB_ERRSTAT_CRC16_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3973 #define USB_ERRSTAT_DFN8_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3974 #define USB_ERRSTAT_DFN8_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3975 #define USB_ERRSTAT_BTOERR_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3976 #define USB_ERRSTAT_BTOERR_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3977 #define USB_ERRSTAT_DMAERR_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3978 #define USB_ERRSTAT_DMAERR_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3979 #define USB_ERRSTAT_BTSERR_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3980 #define USB_ERRSTAT_BTSERR_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3981 /* ERREN Bit Fields */
AnnaBridge 171:3a7713b1edbc 3982 #define USB_ERREN_PIDERREN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 3983 #define USB_ERREN_PIDERREN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 3984 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 3985 #define USB_ERREN_CRC5EOFEN_SHIFT 1
AnnaBridge 171:3a7713b1edbc 3986 #define USB_ERREN_CRC16EN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3987 #define USB_ERREN_CRC16EN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3988 #define USB_ERREN_DFN8EN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 3989 #define USB_ERREN_DFN8EN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 3990 #define USB_ERREN_BTOERREN_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 3991 #define USB_ERREN_BTOERREN_SHIFT 4
AnnaBridge 171:3a7713b1edbc 3992 #define USB_ERREN_DMAERREN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 3993 #define USB_ERREN_DMAERREN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 3994 #define USB_ERREN_BTSERREN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 3995 #define USB_ERREN_BTSERREN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 3996 /* STAT Bit Fields */
AnnaBridge 171:3a7713b1edbc 3997 #define USB_STAT_ODD_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 3998 #define USB_STAT_ODD_SHIFT 2
AnnaBridge 171:3a7713b1edbc 3999 #define USB_STAT_TX_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4000 #define USB_STAT_TX_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4001 #define USB_STAT_ENDP_MASK 0xF0u
AnnaBridge 171:3a7713b1edbc 4002 #define USB_STAT_ENDP_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4003 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 4004 /* CTL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4005 #define USB_CTL_USBENSOFEN_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4006 #define USB_CTL_USBENSOFEN_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4007 #define USB_CTL_ODDRST_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4008 #define USB_CTL_ODDRST_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4009 #define USB_CTL_RESUME_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4010 #define USB_CTL_RESUME_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4011 #define USB_CTL_HOSTMODEEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4012 #define USB_CTL_HOSTMODEEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4013 #define USB_CTL_RESET_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4014 #define USB_CTL_RESET_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4015 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4016 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4017 #define USB_CTL_SE0_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4018 #define USB_CTL_SE0_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4019 #define USB_CTL_JSTATE_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4020 #define USB_CTL_JSTATE_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4021 /* ADDR Bit Fields */
AnnaBridge 171:3a7713b1edbc 4022 #define USB_ADDR_ADDR_MASK 0x7Fu
AnnaBridge 171:3a7713b1edbc 4023 #define USB_ADDR_ADDR_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4024 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 4025 #define USB_ADDR_LSEN_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4026 #define USB_ADDR_LSEN_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4027 /* BDTPAGE1 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4028 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
AnnaBridge 171:3a7713b1edbc 4029 #define USB_BDTPAGE1_BDTBA_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4030 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 4031 /* FRMNUML Bit Fields */
AnnaBridge 171:3a7713b1edbc 4032 #define USB_FRMNUML_FRM_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4033 #define USB_FRMNUML_FRM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4034 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 4035 /* FRMNUMH Bit Fields */
AnnaBridge 171:3a7713b1edbc 4036 #define USB_FRMNUMH_FRM_MASK 0x7u
AnnaBridge 171:3a7713b1edbc 4037 #define USB_FRMNUMH_FRM_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4038 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 4039 /* TOKEN Bit Fields */
AnnaBridge 171:3a7713b1edbc 4040 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
AnnaBridge 171:3a7713b1edbc 4041 #define USB_TOKEN_TOKENENDPT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4042 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 4043 #define USB_TOKEN_TOKENPID_MASK 0xF0u
AnnaBridge 171:3a7713b1edbc 4044 #define USB_TOKEN_TOKENPID_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4045 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
AnnaBridge 171:3a7713b1edbc 4046 /* SOFTHLD Bit Fields */
AnnaBridge 171:3a7713b1edbc 4047 #define USB_SOFTHLD_CNT_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4048 #define USB_SOFTHLD_CNT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4049 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 4050 /* BDTPAGE2 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4051 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4052 #define USB_BDTPAGE2_BDTBA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4053 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 4054 /* BDTPAGE3 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4055 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
AnnaBridge 171:3a7713b1edbc 4056 #define USB_BDTPAGE3_BDTBA_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4057 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 4058 /* ENDPT Bit Fields */
AnnaBridge 171:3a7713b1edbc 4059 #define USB_ENDPT_EPHSHK_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4060 #define USB_ENDPT_EPHSHK_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4061 #define USB_ENDPT_EPSTALL_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4062 #define USB_ENDPT_EPSTALL_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4063 #define USB_ENDPT_EPTXEN_MASK 0x4u
AnnaBridge 171:3a7713b1edbc 4064 #define USB_ENDPT_EPTXEN_SHIFT 2
AnnaBridge 171:3a7713b1edbc 4065 #define USB_ENDPT_EPRXEN_MASK 0x8u
AnnaBridge 171:3a7713b1edbc 4066 #define USB_ENDPT_EPRXEN_SHIFT 3
AnnaBridge 171:3a7713b1edbc 4067 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4068 #define USB_ENDPT_EPCTLDIS_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4069 #define USB_ENDPT_RETRYDIS_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4070 #define USB_ENDPT_RETRYDIS_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4071 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4072 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4073 /* USBCTRL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4074 #define USB_USBCTRL_PDE_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4075 #define USB_USBCTRL_PDE_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4076 #define USB_USBCTRL_SUSP_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4077 #define USB_USBCTRL_SUSP_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4078 /* OBSERVE Bit Fields */
AnnaBridge 171:3a7713b1edbc 4079 #define USB_OBSERVE_DMPD_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4080 #define USB_OBSERVE_DMPD_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4081 #define USB_OBSERVE_DPPD_MASK 0x40u
AnnaBridge 171:3a7713b1edbc 4082 #define USB_OBSERVE_DPPD_SHIFT 6
AnnaBridge 171:3a7713b1edbc 4083 #define USB_OBSERVE_DPPU_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4084 #define USB_OBSERVE_DPPU_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4085 /* CONTROL Bit Fields */
AnnaBridge 171:3a7713b1edbc 4086 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
AnnaBridge 171:3a7713b1edbc 4087 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
AnnaBridge 171:3a7713b1edbc 4088 /* USBTRC0 Bit Fields */
AnnaBridge 171:3a7713b1edbc 4089 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
AnnaBridge 171:3a7713b1edbc 4090 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
AnnaBridge 171:3a7713b1edbc 4091 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
AnnaBridge 171:3a7713b1edbc 4092 #define USB_USBTRC0_SYNC_DET_SHIFT 1
AnnaBridge 171:3a7713b1edbc 4093 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
AnnaBridge 171:3a7713b1edbc 4094 #define USB_USBTRC0_USBRESMEN_SHIFT 5
AnnaBridge 171:3a7713b1edbc 4095 #define USB_USBTRC0_USBRESET_MASK 0x80u
AnnaBridge 171:3a7713b1edbc 4096 #define USB_USBTRC0_USBRESET_SHIFT 7
AnnaBridge 171:3a7713b1edbc 4097
AnnaBridge 171:3a7713b1edbc 4098 /**
AnnaBridge 171:3a7713b1edbc 4099 * @}
AnnaBridge 171:3a7713b1edbc 4100 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4101
AnnaBridge 171:3a7713b1edbc 4102
AnnaBridge 171:3a7713b1edbc 4103 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4104 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 4105 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 4106 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 4107 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 4108 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4109 #define USB_BASES { USB0 }
AnnaBridge 171:3a7713b1edbc 4110
AnnaBridge 171:3a7713b1edbc 4111 /**
AnnaBridge 171:3a7713b1edbc 4112 * @}
AnnaBridge 171:3a7713b1edbc 4113 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4114
AnnaBridge 171:3a7713b1edbc 4115
AnnaBridge 171:3a7713b1edbc 4116 /*
AnnaBridge 171:3a7713b1edbc 4117 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 4118 */
AnnaBridge 171:3a7713b1edbc 4119
AnnaBridge 171:3a7713b1edbc 4120 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 4121 #pragma pop
AnnaBridge 171:3a7713b1edbc 4122 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 4123 #pragma pop
AnnaBridge 171:3a7713b1edbc 4124 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 4125 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 4126 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 4127 #pragma language=default
AnnaBridge 171:3a7713b1edbc 4128 #else
AnnaBridge 171:3a7713b1edbc 4129 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 4130 #endif
AnnaBridge 171:3a7713b1edbc 4131
AnnaBridge 171:3a7713b1edbc 4132 /**
AnnaBridge 171:3a7713b1edbc 4133 * @}
AnnaBridge 171:3a7713b1edbc 4134 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 4135
AnnaBridge 171:3a7713b1edbc 4136
AnnaBridge 171:3a7713b1edbc 4137 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4138 -- Backward Compatibility
AnnaBridge 171:3a7713b1edbc 4139 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4140
AnnaBridge 171:3a7713b1edbc 4141 /**
AnnaBridge 171:3a7713b1edbc 4142 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
AnnaBridge 171:3a7713b1edbc 4143 * @{
AnnaBridge 171:3a7713b1edbc 4144 */
AnnaBridge 171:3a7713b1edbc 4145
AnnaBridge 171:3a7713b1edbc 4146 /* No backward compatibility issues. */
AnnaBridge 171:3a7713b1edbc 4147
AnnaBridge 171:3a7713b1edbc 4148 /**
AnnaBridge 171:3a7713b1edbc 4149 * @}
AnnaBridge 171:3a7713b1edbc 4150 */ /* end of group Backward_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 4151
AnnaBridge 171:3a7713b1edbc 4152
AnnaBridge 171:3a7713b1edbc 4153 #endif /* #if !defined(MKL25Z4_H_) */
AnnaBridge 171:3a7713b1edbc 4154
AnnaBridge 171:3a7713b1edbc 4155 /* MKL25Z4.h, eof. */