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mbed 2

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TARGET_K64F/TOOLCHAIN_IAR/MK64F12_features.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Version: rev. 2.15, 2016-03-21
AnnaBridge 171:3a7713b1edbc 4 ** Build: b160829
AnnaBridge 171:3a7713b1edbc 5 **
AnnaBridge 171:3a7713b1edbc 6 ** Abstract:
AnnaBridge 171:3a7713b1edbc 7 ** Chip specific module features.
AnnaBridge 171:3a7713b1edbc 8 **
AnnaBridge 171:3a7713b1edbc 9 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 10 ** All rights reserved.
AnnaBridge 171:3a7713b1edbc 11 **
AnnaBridge 171:3a7713b1edbc 12 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 13 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 **
AnnaBridge 171:3a7713b1edbc 15 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 16 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 **
AnnaBridge 171:3a7713b1edbc 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 19 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 20 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 **
AnnaBridge 171:3a7713b1edbc 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 23 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 24 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 36 **
AnnaBridge 171:3a7713b1edbc 37 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 38 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 39 **
AnnaBridge 171:3a7713b1edbc 40 ** Revisions:
AnnaBridge 171:3a7713b1edbc 41 ** - rev. 1.0 (2013-08-12)
AnnaBridge 171:3a7713b1edbc 42 ** Initial version.
AnnaBridge 171:3a7713b1edbc 43 ** - rev. 2.0 (2013-10-29)
AnnaBridge 171:3a7713b1edbc 44 ** Register accessor macros added to the memory map.
AnnaBridge 171:3a7713b1edbc 45 ** Symbols for Processor Expert memory map compatibility added to the memory map.
AnnaBridge 171:3a7713b1edbc 46 ** Startup file for gcc has been updated according to CMSIS 3.2.
AnnaBridge 171:3a7713b1edbc 47 ** System initialization updated.
AnnaBridge 171:3a7713b1edbc 48 ** MCG - registers updated.
AnnaBridge 171:3a7713b1edbc 49 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
AnnaBridge 171:3a7713b1edbc 50 ** - rev. 2.1 (2013-10-30)
AnnaBridge 171:3a7713b1edbc 51 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
AnnaBridge 171:3a7713b1edbc 52 ** - rev. 2.2 (2013-12-09)
AnnaBridge 171:3a7713b1edbc 53 ** DMA - EARS register removed.
AnnaBridge 171:3a7713b1edbc 54 ** AIPS0, AIPS1 - MPRA register updated.
AnnaBridge 171:3a7713b1edbc 55 ** - rev. 2.3 (2014-01-24)
AnnaBridge 171:3a7713b1edbc 56 ** Update according to reference manual rev. 2
AnnaBridge 171:3a7713b1edbc 57 ** ENET, MCG, MCM, SIM, USB - registers updated
AnnaBridge 171:3a7713b1edbc 58 ** - rev. 2.4 (2014-01-30)
AnnaBridge 171:3a7713b1edbc 59 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
AnnaBridge 171:3a7713b1edbc 60 ** - rev. 2.5 (2014-02-10)
AnnaBridge 171:3a7713b1edbc 61 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
AnnaBridge 171:3a7713b1edbc 62 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 171:3a7713b1edbc 63 ** - rev. 2.6 (2014-02-10)
AnnaBridge 171:3a7713b1edbc 64 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
AnnaBridge 171:3a7713b1edbc 65 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 171:3a7713b1edbc 66 ** Module access macro module_BASES replaced by module_BASE_PTRS.
AnnaBridge 171:3a7713b1edbc 67 ** - rev. 2.7 (2014-08-28)
AnnaBridge 171:3a7713b1edbc 68 ** Update of system files - default clock configuration changed.
AnnaBridge 171:3a7713b1edbc 69 ** Update of startup files - possibility to override DefaultISR added.
AnnaBridge 171:3a7713b1edbc 70 ** - rev. 2.8 (2014-10-14)
AnnaBridge 171:3a7713b1edbc 71 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
AnnaBridge 171:3a7713b1edbc 72 ** - rev. 2.9 (2015-01-21)
AnnaBridge 171:3a7713b1edbc 73 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
AnnaBridge 171:3a7713b1edbc 74 ** - rev. 2.10 (2015-02-19)
AnnaBridge 171:3a7713b1edbc 75 ** Renamed interrupt vector LLW to LLWU.
AnnaBridge 171:3a7713b1edbc 76 ** - rev. 2.11 (2015-05-19)
AnnaBridge 171:3a7713b1edbc 77 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
AnnaBridge 171:3a7713b1edbc 78 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
AnnaBridge 171:3a7713b1edbc 79 ** Added features for PDB and PORT.
AnnaBridge 171:3a7713b1edbc 80 ** - rev. 2.12 (2015-05-25)
AnnaBridge 171:3a7713b1edbc 81 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
AnnaBridge 171:3a7713b1edbc 82 ** - rev. 2.13 (2015-05-27)
AnnaBridge 171:3a7713b1edbc 83 ** Several USB features added.
AnnaBridge 171:3a7713b1edbc 84 ** - rev. 2.14 (2015-06-08)
AnnaBridge 171:3a7713b1edbc 85 ** FTM features BUS_CLOCK and FAST_CLOCK removed.
AnnaBridge 171:3a7713b1edbc 86 ** - rev. 2.15 (2016-03-21)
AnnaBridge 171:3a7713b1edbc 87 ** Added MK64FN1M0CAJ12 part.
AnnaBridge 171:3a7713b1edbc 88 **
AnnaBridge 171:3a7713b1edbc 89 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 90 */
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 #ifndef _MK64F12_FEATURES_H_
AnnaBridge 171:3a7713b1edbc 93 #define _MK64F12_FEATURES_H_
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /* SOC module features */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
AnnaBridge 171:3a7713b1edbc 98 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
AnnaBridge 171:3a7713b1edbc 99 /* @brief ACMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 100 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 101 /* @brief ADC16 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 102 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
AnnaBridge 171:3a7713b1edbc 103 /* @brief ADC12 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 104 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge 171:3a7713b1edbc 105 /* @brief AFE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 106 #define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 107 /* @brief AIPS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 108 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
AnnaBridge 171:3a7713b1edbc 109 /* @brief AOI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 110 #define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 111 /* @brief AXBS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 112 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
AnnaBridge 171:3a7713b1edbc 113 /* @brief ASMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 114 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 115 /* @brief CADC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 116 #define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 117 /* @brief FLEXCAN availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 118 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
AnnaBridge 171:3a7713b1edbc 119 /* @brief MMCAU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 120 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 121 /* @brief CMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 122 #define FSL_FEATURE_SOC_CMP_COUNT (3)
AnnaBridge 171:3a7713b1edbc 123 /* @brief CMT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 124 #define FSL_FEATURE_SOC_CMT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 125 /* @brief CNC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 126 #define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 127 /* @brief CRC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 128 #define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 129 /* @brief DAC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 130 #define FSL_FEATURE_SOC_DAC_COUNT (2)
AnnaBridge 171:3a7713b1edbc 131 /* @brief DAC32 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 132 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge 171:3a7713b1edbc 133 /* @brief DCDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 134 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 135 /* @brief DDR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 136 #define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 137 /* @brief DMA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 138 #define FSL_FEATURE_SOC_DMA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 139 /* @brief EDMA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 140 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge 171:3a7713b1edbc 141 /* @brief DMAMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 142 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge 171:3a7713b1edbc 143 /* @brief DRY availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 144 #define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge 171:3a7713b1edbc 145 /* @brief DSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 146 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
AnnaBridge 171:3a7713b1edbc 147 /* @brief EMVSIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 148 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 149 /* @brief ENC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 150 #define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 151 /* @brief ENET availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 152 #define FSL_FEATURE_SOC_ENET_COUNT (1)
AnnaBridge 171:3a7713b1edbc 153 /* @brief EWM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 154 #define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 155 /* @brief FB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 156 #define FSL_FEATURE_SOC_FB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 157 /* @brief FGPIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 158 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 159 /* @brief FLEXIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 160 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 161 /* @brief FMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 162 #define FSL_FEATURE_SOC_FMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 163 /* @brief FSKDT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 164 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 165 /* @brief FTFA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 166 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 167 /* @brief FTFE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 168 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
AnnaBridge 171:3a7713b1edbc 169 /* @brief FTFL availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 170 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge 171:3a7713b1edbc 171 /* @brief FTM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 172 #define FSL_FEATURE_SOC_FTM_COUNT (4)
AnnaBridge 171:3a7713b1edbc 173 /* @brief FTMRA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 174 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 175 /* @brief FTMRE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 176 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 177 /* @brief FTMRH availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 178 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge 171:3a7713b1edbc 179 /* @brief GPIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 180 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge 171:3a7713b1edbc 181 /* @brief HSADC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 182 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 183 /* @brief I2C availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 184 #define FSL_FEATURE_SOC_I2C_COUNT (3)
AnnaBridge 171:3a7713b1edbc 185 /* @brief I2S availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 186 #define FSL_FEATURE_SOC_I2S_COUNT (1)
AnnaBridge 171:3a7713b1edbc 187 /* @brief ICS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 188 #define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge 171:3a7713b1edbc 189 /* @brief INTMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 190 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
AnnaBridge 171:3a7713b1edbc 191 /* @brief IRQ availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 192 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge 171:3a7713b1edbc 193 /* @brief KBI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 194 #define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 195 /* @brief SLCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 196 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 197 /* @brief LCDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 198 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 199 /* @brief LDO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 200 #define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 201 /* @brief LLWU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 202 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 203 /* @brief LMEM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 204 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 205 /* @brief LPI2C availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 206 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge 171:3a7713b1edbc 207 /* @brief LPIT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 208 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 209 /* @brief LPSCI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 210 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 211 /* @brief LPSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 212 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 213 /* @brief LPTMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 214 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
AnnaBridge 171:3a7713b1edbc 215 /* @brief LPTPM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 216 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 217 /* @brief LPUART availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 218 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
AnnaBridge 171:3a7713b1edbc 219 /* @brief LTC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 220 #define FSL_FEATURE_SOC_LTC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 221 /* @brief MC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 222 #define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 223 /* @brief MCG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 224 #define FSL_FEATURE_SOC_MCG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 225 /* @brief MCGLITE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 226 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 227 /* @brief MCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 228 #define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 229 /* @brief MMAU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 230 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge 171:3a7713b1edbc 231 /* @brief MMDVSQ availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 232 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge 171:3a7713b1edbc 233 /* @brief SYSMPU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 234 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 235 /* @brief MSCAN availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 236 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge 171:3a7713b1edbc 237 /* @brief MSCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 238 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 239 /* @brief MTB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 240 #define FSL_FEATURE_SOC_MTB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 241 /* @brief MTBDWT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 242 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 243 /* @brief MU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 244 #define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge 171:3a7713b1edbc 245 /* @brief NFC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 246 #define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 247 /* @brief OPAMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 248 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 249 /* @brief OSC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 250 #define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 251 /* @brief OSC32 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 252 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge 171:3a7713b1edbc 253 /* @brief OTFAD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 254 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 255 /* @brief PDB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 256 #define FSL_FEATURE_SOC_PDB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 257 /* @brief PCC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 258 #define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 259 /* @brief PGA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 260 #define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 261 /* @brief PIT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 262 #define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 263 /* @brief PMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 264 #define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 265 /* @brief PORT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 266 #define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge 171:3a7713b1edbc 267 /* @brief PWM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 268 #define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 269 /* @brief PWT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 270 #define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 271 /* @brief QuadSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 272 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 273 /* @brief RCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 274 #define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 275 /* @brief RFSYS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 276 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
AnnaBridge 171:3a7713b1edbc 277 /* @brief RFVBAT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 278 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 279 /* @brief RNG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 280 #define FSL_FEATURE_SOC_RNG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 281 /* @brief RNGB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 282 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 283 /* @brief ROM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 284 #define FSL_FEATURE_SOC_ROM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 285 /* @brief RSIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 286 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 287 /* @brief RTC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 288 #define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 289 /* @brief SCG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 290 #define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge 171:3a7713b1edbc 291 /* @brief SCI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 292 #define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 293 /* @brief SDHC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 294 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 295 /* @brief SDRAM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 296 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 297 /* @brief SEMA42 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 298 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge 171:3a7713b1edbc 299 /* @brief SIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 300 #define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 301 /* @brief SMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 302 #define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 303 /* @brief SPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 304 #define FSL_FEATURE_SOC_SPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 305 /* @brief TMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 306 #define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 307 /* @brief TPM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 308 #define FSL_FEATURE_SOC_TPM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 309 /* @brief TRGMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 310 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge 171:3a7713b1edbc 311 /* @brief TRIAMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 312 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 313 /* @brief TRNG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 314 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
AnnaBridge 171:3a7713b1edbc 315 /* @brief TSI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 316 #define FSL_FEATURE_SOC_TSI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 317 /* @brief TSTMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 318 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 319 /* @brief UART availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 320 #define FSL_FEATURE_SOC_UART_COUNT (6)
AnnaBridge 171:3a7713b1edbc 321 /* @brief USB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 322 #define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 323 /* @brief USBDCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 324 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
AnnaBridge 171:3a7713b1edbc 325 /* @brief USBHSDCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 326 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 327 /* @brief USBPHY availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 328 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge 171:3a7713b1edbc 329 /* @brief VREF availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 330 #define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge 171:3a7713b1edbc 331 /* @brief WDOG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 332 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 333 /* @brief XBAR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 334 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 335 /* @brief XBARA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 336 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 337 /* @brief XBARB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 338 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 339 /* @brief XCVR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 340 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 341 /* @brief XRDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 342 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 343 /* @brief ZLL availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 344 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge 171:3a7713b1edbc 345 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12)
AnnaBridge 171:3a7713b1edbc 346 /* @brief ACMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 347 #define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 348 /* @brief ADC16 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 349 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
AnnaBridge 171:3a7713b1edbc 350 /* @brief ADC12 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 351 #define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge 171:3a7713b1edbc 352 /* @brief AFE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 353 #define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 354 /* @brief AIPS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 355 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
AnnaBridge 171:3a7713b1edbc 356 /* @brief AOI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 357 #define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 358 /* @brief AXBS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 359 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
AnnaBridge 171:3a7713b1edbc 360 /* @brief ASMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 361 #define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 362 /* @brief CADC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 363 #define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 364 /* @brief FLEXCAN availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 365 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
AnnaBridge 171:3a7713b1edbc 366 /* @brief MMCAU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 367 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 368 /* @brief CMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 369 #define FSL_FEATURE_SOC_CMP_COUNT (3)
AnnaBridge 171:3a7713b1edbc 370 /* @brief CMT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 371 #define FSL_FEATURE_SOC_CMT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 372 /* @brief CNC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 373 #define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 374 /* @brief CRC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 375 #define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 376 /* @brief DAC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 377 #define FSL_FEATURE_SOC_DAC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 378 /* @brief DAC32 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 379 #define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge 171:3a7713b1edbc 380 /* @brief DCDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 381 #define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 382 /* @brief DDR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 383 #define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 384 /* @brief DMA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 385 #define FSL_FEATURE_SOC_DMA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 386 /* @brief EDMA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 387 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge 171:3a7713b1edbc 388 /* @brief DMAMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 389 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge 171:3a7713b1edbc 390 /* @brief DRY availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 391 #define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge 171:3a7713b1edbc 392 /* @brief DSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 393 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
AnnaBridge 171:3a7713b1edbc 394 /* @brief EMVSIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 395 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 396 /* @brief ENC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 397 #define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 398 /* @brief ENET availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 399 #define FSL_FEATURE_SOC_ENET_COUNT (1)
AnnaBridge 171:3a7713b1edbc 400 /* @brief EWM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 401 #define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 402 /* @brief FB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 403 #define FSL_FEATURE_SOC_FB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 404 /* @brief FGPIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 405 #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 406 /* @brief FLEXIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 407 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 408 /* @brief FMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 409 #define FSL_FEATURE_SOC_FMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 410 /* @brief FSKDT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 411 #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 412 /* @brief FTFA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 413 #define FSL_FEATURE_SOC_FTFA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 414 /* @brief FTFE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 415 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
AnnaBridge 171:3a7713b1edbc 416 /* @brief FTFL availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 417 #define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge 171:3a7713b1edbc 418 /* @brief FTM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 419 #define FSL_FEATURE_SOC_FTM_COUNT (4)
AnnaBridge 171:3a7713b1edbc 420 /* @brief FTMRA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 421 #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 422 /* @brief FTMRE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 423 #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 424 /* @brief FTMRH availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 425 #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge 171:3a7713b1edbc 426 /* @brief GPIO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 427 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge 171:3a7713b1edbc 428 /* @brief HSADC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 429 #define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 430 /* @brief I2C availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 431 #define FSL_FEATURE_SOC_I2C_COUNT (3)
AnnaBridge 171:3a7713b1edbc 432 /* @brief I2S availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 433 #define FSL_FEATURE_SOC_I2S_COUNT (1)
AnnaBridge 171:3a7713b1edbc 434 /* @brief ICS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 435 #define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge 171:3a7713b1edbc 436 /* @brief INTMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 437 #define FSL_FEATURE_SOC_INTMUX_COUNT (0)
AnnaBridge 171:3a7713b1edbc 438 /* @brief IRQ availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 439 #define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge 171:3a7713b1edbc 440 /* @brief KBI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 441 #define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 442 /* @brief SLCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 443 #define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 444 /* @brief LCDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 445 #define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 446 /* @brief LDO availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 447 #define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge 171:3a7713b1edbc 448 /* @brief LLWU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 449 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 450 /* @brief LMEM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 451 #define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 452 /* @brief LPI2C availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 453 #define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge 171:3a7713b1edbc 454 /* @brief LPIT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 455 #define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 456 /* @brief LPSCI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 457 #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 458 /* @brief LPSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 459 #define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 460 /* @brief LPTMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 461 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
AnnaBridge 171:3a7713b1edbc 462 /* @brief LPTPM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 463 #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 464 /* @brief LPUART availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 465 #define FSL_FEATURE_SOC_LPUART_COUNT (0)
AnnaBridge 171:3a7713b1edbc 466 /* @brief LTC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 467 #define FSL_FEATURE_SOC_LTC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 468 /* @brief MC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 469 #define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 470 /* @brief MCG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 471 #define FSL_FEATURE_SOC_MCG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 472 /* @brief MCGLITE availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 473 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
AnnaBridge 171:3a7713b1edbc 474 /* @brief MCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 475 #define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 476 /* @brief MMAU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 477 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge 171:3a7713b1edbc 478 /* @brief MMDVSQ availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 479 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge 171:3a7713b1edbc 480 /* @brief SYSMPU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 481 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
AnnaBridge 171:3a7713b1edbc 482 /* @brief MSCAN availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 483 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge 171:3a7713b1edbc 484 /* @brief MSCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 485 #define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 486 /* @brief MTB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 487 #define FSL_FEATURE_SOC_MTB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 488 /* @brief MTBDWT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 489 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 490 /* @brief MU availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 491 #define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge 171:3a7713b1edbc 492 /* @brief NFC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 493 #define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 494 /* @brief OPAMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 495 #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 496 /* @brief OSC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 497 #define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 498 /* @brief OSC32 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 499 #define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge 171:3a7713b1edbc 500 /* @brief OTFAD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 501 #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 502 /* @brief PDB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 503 #define FSL_FEATURE_SOC_PDB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 504 /* @brief PCC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 505 #define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 506 /* @brief PGA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 507 #define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 508 /* @brief PIT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 509 #define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 510 /* @brief PMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 511 #define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 512 /* @brief PORT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 513 #define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge 171:3a7713b1edbc 514 /* @brief PWM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 515 #define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 516 /* @brief PWT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 517 #define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge 171:3a7713b1edbc 518 /* @brief QuadSPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 519 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 520 /* @brief RCM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 521 #define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 522 /* @brief RFSYS availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 523 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
AnnaBridge 171:3a7713b1edbc 524 /* @brief RFVBAT availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 525 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 526 /* @brief RNG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 527 #define FSL_FEATURE_SOC_RNG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 528 /* @brief RNGB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 529 #define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 530 /* @brief ROM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 531 #define FSL_FEATURE_SOC_ROM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 532 /* @brief RSIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 533 #define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 534 /* @brief RTC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 535 #define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 536 /* @brief SCG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 537 #define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge 171:3a7713b1edbc 538 /* @brief SCI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 539 #define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 540 /* @brief SDHC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 541 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 542 /* @brief SDRAM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 543 #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 544 /* @brief SEMA42 availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 545 #define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge 171:3a7713b1edbc 546 /* @brief SIM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 547 #define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge 171:3a7713b1edbc 548 /* @brief SMC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 549 #define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 550 /* @brief SPI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 551 #define FSL_FEATURE_SOC_SPI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 552 /* @brief TMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 553 #define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 554 /* @brief TPM availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 555 #define FSL_FEATURE_SOC_TPM_COUNT (0)
AnnaBridge 171:3a7713b1edbc 556 /* @brief TRGMUX availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 557 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge 171:3a7713b1edbc 558 /* @brief TRIAMP availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 559 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge 171:3a7713b1edbc 560 /* @brief TRNG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 561 #define FSL_FEATURE_SOC_TRNG_COUNT (0)
AnnaBridge 171:3a7713b1edbc 562 /* @brief TSI availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 563 #define FSL_FEATURE_SOC_TSI_COUNT (0)
AnnaBridge 171:3a7713b1edbc 564 /* @brief TSTMR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 565 #define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 566 /* @brief UART availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 567 #define FSL_FEATURE_SOC_UART_COUNT (6)
AnnaBridge 171:3a7713b1edbc 568 /* @brief USB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 569 #define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge 171:3a7713b1edbc 570 /* @brief USBDCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 571 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
AnnaBridge 171:3a7713b1edbc 572 /* @brief USBHSDCD availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 573 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge 171:3a7713b1edbc 574 /* @brief USBPHY availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 575 #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge 171:3a7713b1edbc 576 /* @brief VREF availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 577 #define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge 171:3a7713b1edbc 578 /* @brief WDOG availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 579 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
AnnaBridge 171:3a7713b1edbc 580 /* @brief XBAR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 581 #define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 582 /* @brief XBARA availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 583 #define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge 171:3a7713b1edbc 584 /* @brief XBARB availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 585 #define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge 171:3a7713b1edbc 586 /* @brief XCVR availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 587 #define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge 171:3a7713b1edbc 588 /* @brief XRDC availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 589 #define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge 171:3a7713b1edbc 590 /* @brief ZLL availability on the SoC. */
AnnaBridge 171:3a7713b1edbc 591 #define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge 171:3a7713b1edbc 592 #endif
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /* ADC16 module features */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
AnnaBridge 171:3a7713b1edbc 597 #define FSL_FEATURE_ADC16_HAS_PGA (0)
AnnaBridge 171:3a7713b1edbc 598 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
AnnaBridge 171:3a7713b1edbc 599 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
AnnaBridge 171:3a7713b1edbc 600 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
AnnaBridge 171:3a7713b1edbc 601 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
AnnaBridge 171:3a7713b1edbc 602 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
AnnaBridge 171:3a7713b1edbc 603 #define FSL_FEATURE_ADC16_HAS_DMA (1)
AnnaBridge 171:3a7713b1edbc 604 /* @brief Has differential mode (bitfield SC1x[DIFF]). */
AnnaBridge 171:3a7713b1edbc 605 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
AnnaBridge 171:3a7713b1edbc 606 /* @brief Has FIFO (bit SC4[AFDEP]). */
AnnaBridge 171:3a7713b1edbc 607 #define FSL_FEATURE_ADC16_HAS_FIFO (0)
AnnaBridge 171:3a7713b1edbc 608 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */
AnnaBridge 171:3a7713b1edbc 609 #define FSL_FEATURE_ADC16_FIFO_SIZE (0)
AnnaBridge 171:3a7713b1edbc 610 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
AnnaBridge 171:3a7713b1edbc 611 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
AnnaBridge 171:3a7713b1edbc 612 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
AnnaBridge 171:3a7713b1edbc 613 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
AnnaBridge 171:3a7713b1edbc 614 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
AnnaBridge 171:3a7713b1edbc 615 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
AnnaBridge 171:3a7713b1edbc 616 /* @brief Has HW averaging (bit SC3[AVGE]). */
AnnaBridge 171:3a7713b1edbc 617 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
AnnaBridge 171:3a7713b1edbc 618 /* @brief Has offset correction (register OFS). */
AnnaBridge 171:3a7713b1edbc 619 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
AnnaBridge 171:3a7713b1edbc 620 /* @brief Maximum ADC resolution. */
AnnaBridge 171:3a7713b1edbc 621 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
AnnaBridge 171:3a7713b1edbc 622 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
AnnaBridge 171:3a7713b1edbc 623 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /* FLEXCAN module features */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /* @brief Message buffer size */
AnnaBridge 171:3a7713b1edbc 628 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
AnnaBridge 171:3a7713b1edbc 629 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
AnnaBridge 171:3a7713b1edbc 630 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 631 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
AnnaBridge 171:3a7713b1edbc 632 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
AnnaBridge 171:3a7713b1edbc 633 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
AnnaBridge 171:3a7713b1edbc 634 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
AnnaBridge 171:3a7713b1edbc 635 /* @brief Has extended bit timing register (register CBT). */
AnnaBridge 171:3a7713b1edbc 636 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
AnnaBridge 171:3a7713b1edbc 637 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
AnnaBridge 171:3a7713b1edbc 638 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
AnnaBridge 171:3a7713b1edbc 639 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
AnnaBridge 171:3a7713b1edbc 640 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
AnnaBridge 171:3a7713b1edbc 641 /* @brief Has bitfield name BUF31TO0M. */
AnnaBridge 171:3a7713b1edbc 642 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
AnnaBridge 171:3a7713b1edbc 643 /* @brief Number of interrupt vectors. */
AnnaBridge 171:3a7713b1edbc 644 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
AnnaBridge 171:3a7713b1edbc 645 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
AnnaBridge 171:3a7713b1edbc 646 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648 /* CMP module features */
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
AnnaBridge 171:3a7713b1edbc 651 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
AnnaBridge 171:3a7713b1edbc 652 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */
AnnaBridge 171:3a7713b1edbc 653 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
AnnaBridge 171:3a7713b1edbc 654 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
AnnaBridge 171:3a7713b1edbc 655 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 656 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
AnnaBridge 171:3a7713b1edbc 657 #define FSL_FEATURE_CMP_HAS_DMA (1)
AnnaBridge 171:3a7713b1edbc 658 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
AnnaBridge 171:3a7713b1edbc 659 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
AnnaBridge 171:3a7713b1edbc 660 /* @brief Has DAC Test function in CMP (register DACTEST). */
AnnaBridge 171:3a7713b1edbc 661 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /* CRC module features */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 /* @brief Has data register with name CRC */
AnnaBridge 171:3a7713b1edbc 666 #define FSL_FEATURE_CRC_HAS_CRC_REG (0)
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 /* DAC module features */
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 /* @brief Define the size of hardware buffer */
AnnaBridge 171:3a7713b1edbc 671 #define FSL_FEATURE_DAC_BUFFER_SIZE (16)
AnnaBridge 171:3a7713b1edbc 672 /* @brief Define whether the buffer supports watermark event detection or not. */
AnnaBridge 171:3a7713b1edbc 673 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
AnnaBridge 171:3a7713b1edbc 674 /* @brief Define whether the buffer supports watermark selection detection or not. */
AnnaBridge 171:3a7713b1edbc 675 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 676 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
AnnaBridge 171:3a7713b1edbc 677 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
AnnaBridge 171:3a7713b1edbc 678 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
AnnaBridge 171:3a7713b1edbc 679 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
AnnaBridge 171:3a7713b1edbc 680 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
AnnaBridge 171:3a7713b1edbc 681 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
AnnaBridge 171:3a7713b1edbc 682 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
AnnaBridge 171:3a7713b1edbc 683 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
AnnaBridge 171:3a7713b1edbc 684 /* @brief Define whether FIFO buffer mode is available or not. */
AnnaBridge 171:3a7713b1edbc 685 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
AnnaBridge 171:3a7713b1edbc 686 /* @brief Define whether swing buffer mode is available or not.. */
AnnaBridge 171:3a7713b1edbc 687 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /* EDMA module features */
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
AnnaBridge 171:3a7713b1edbc 692 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
AnnaBridge 171:3a7713b1edbc 693 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 171:3a7713b1edbc 694 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16)
AnnaBridge 171:3a7713b1edbc 695 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
AnnaBridge 171:3a7713b1edbc 696 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
AnnaBridge 171:3a7713b1edbc 697 /* @brief Has DMA_Error interrupt vector. */
AnnaBridge 171:3a7713b1edbc 698 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
AnnaBridge 171:3a7713b1edbc 699 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
AnnaBridge 171:3a7713b1edbc 700 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 /* DMAMUX module features */
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 /* @brief Number of DMA channels (related to number of register CHCFGn). */
AnnaBridge 171:3a7713b1edbc 705 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
AnnaBridge 171:3a7713b1edbc 706 /* @brief Total number of DMA channels on all modules. */
AnnaBridge 171:3a7713b1edbc 707 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
AnnaBridge 171:3a7713b1edbc 708 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
AnnaBridge 171:3a7713b1edbc 709 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /* ENET module features */
AnnaBridge 171:3a7713b1edbc 712
AnnaBridge 171:3a7713b1edbc 713 /* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
AnnaBridge 171:3a7713b1edbc 714 #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
AnnaBridge 171:3a7713b1edbc 715 /* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
AnnaBridge 171:3a7713b1edbc 716 #define FSL_FEATURE_ENET_SUPPORT_PTP (1)
AnnaBridge 171:3a7713b1edbc 717 /* @brief Number of associated interrupt vectors. */
AnnaBridge 171:3a7713b1edbc 718 #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
AnnaBridge 171:3a7713b1edbc 719 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
AnnaBridge 171:3a7713b1edbc 720 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 /* EWM module features */
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724 /* @brief Has clock select (register CLKCTRL). */
AnnaBridge 171:3a7713b1edbc 725 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
AnnaBridge 171:3a7713b1edbc 726 /* @brief Has clock prescaler (register CLKPRESCALER). */
AnnaBridge 171:3a7713b1edbc 727 #define FSL_FEATURE_EWM_HAS_PRESCALER (0)
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 /* FLEXBUS module features */
AnnaBridge 171:3a7713b1edbc 730
AnnaBridge 171:3a7713b1edbc 731 /* No feature definitions */
AnnaBridge 171:3a7713b1edbc 732
AnnaBridge 171:3a7713b1edbc 733 /* FLASH module features */
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \
AnnaBridge 171:3a7713b1edbc 736 defined(CPU_MK64FN1M0VMD12)
AnnaBridge 171:3a7713b1edbc 737 /* @brief Is of type FTFA. */
AnnaBridge 171:3a7713b1edbc 738 #define FSL_FEATURE_FLASH_IS_FTFA (0)
AnnaBridge 171:3a7713b1edbc 739 /* @brief Is of type FTFE. */
AnnaBridge 171:3a7713b1edbc 740 #define FSL_FEATURE_FLASH_IS_FTFE (1)
AnnaBridge 171:3a7713b1edbc 741 /* @brief Is of type FTFL. */
AnnaBridge 171:3a7713b1edbc 742 #define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge 171:3a7713b1edbc 743 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge 171:3a7713b1edbc 744 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
AnnaBridge 171:3a7713b1edbc 745 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge 171:3a7713b1edbc 746 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
AnnaBridge 171:3a7713b1edbc 747 /* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge 171:3a7713b1edbc 748 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
AnnaBridge 171:3a7713b1edbc 749 /* @brief Has data flash region protection (register FDPROT). */
AnnaBridge 171:3a7713b1edbc 750 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
AnnaBridge 171:3a7713b1edbc 751 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge 171:3a7713b1edbc 752 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
AnnaBridge 171:3a7713b1edbc 753 /* @brief Has flash cache control in FMC module. */
AnnaBridge 171:3a7713b1edbc 754 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
AnnaBridge 171:3a7713b1edbc 755 /* @brief Has flash cache control in MCM module. */
AnnaBridge 171:3a7713b1edbc 756 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge 171:3a7713b1edbc 757 /* @brief Has flash cache control in MSCM module. */
AnnaBridge 171:3a7713b1edbc 758 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge 171:3a7713b1edbc 759 /* @brief P-Flash start address. */
AnnaBridge 171:3a7713b1edbc 760 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge 171:3a7713b1edbc 761 /* @brief P-Flash block count. */
AnnaBridge 171:3a7713b1edbc 762 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
AnnaBridge 171:3a7713b1edbc 763 /* @brief P-Flash block size. */
AnnaBridge 171:3a7713b1edbc 764 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
AnnaBridge 171:3a7713b1edbc 765 /* @brief P-Flash sector size. */
AnnaBridge 171:3a7713b1edbc 766 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
AnnaBridge 171:3a7713b1edbc 767 /* @brief P-Flash write unit size. */
AnnaBridge 171:3a7713b1edbc 768 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
AnnaBridge 171:3a7713b1edbc 769 /* @brief P-Flash data path width. */
AnnaBridge 171:3a7713b1edbc 770 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
AnnaBridge 171:3a7713b1edbc 771 /* @brief P-Flash block swap feature. */
AnnaBridge 171:3a7713b1edbc 772 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
AnnaBridge 171:3a7713b1edbc 773 /* @brief P-Flash protection region count. */
AnnaBridge 171:3a7713b1edbc 774 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge 171:3a7713b1edbc 775 /* @brief Has FlexNVM memory. */
AnnaBridge 171:3a7713b1edbc 776 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
AnnaBridge 171:3a7713b1edbc 777 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge 171:3a7713b1edbc 778 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
AnnaBridge 171:3a7713b1edbc 779 /* @brief FlexNVM block count. */
AnnaBridge 171:3a7713b1edbc 780 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
AnnaBridge 171:3a7713b1edbc 781 /* @brief FlexNVM block size. */
AnnaBridge 171:3a7713b1edbc 782 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
AnnaBridge 171:3a7713b1edbc 783 /* @brief FlexNVM sector size. */
AnnaBridge 171:3a7713b1edbc 784 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
AnnaBridge 171:3a7713b1edbc 785 /* @brief FlexNVM write unit size. */
AnnaBridge 171:3a7713b1edbc 786 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
AnnaBridge 171:3a7713b1edbc 787 /* @brief FlexNVM data path width. */
AnnaBridge 171:3a7713b1edbc 788 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 789 /* @brief Has FlexRAM memory. */
AnnaBridge 171:3a7713b1edbc 790 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
AnnaBridge 171:3a7713b1edbc 791 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge 171:3a7713b1edbc 792 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
AnnaBridge 171:3a7713b1edbc 793 /* @brief FlexRAM size. */
AnnaBridge 171:3a7713b1edbc 794 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
AnnaBridge 171:3a7713b1edbc 795 /* @brief Has 0x00 Read 1s Block command. */
AnnaBridge 171:3a7713b1edbc 796 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
AnnaBridge 171:3a7713b1edbc 797 /* @brief Has 0x01 Read 1s Section command. */
AnnaBridge 171:3a7713b1edbc 798 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge 171:3a7713b1edbc 799 /* @brief Has 0x02 Program Check command. */
AnnaBridge 171:3a7713b1edbc 800 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge 171:3a7713b1edbc 801 /* @brief Has 0x03 Read Resource command. */
AnnaBridge 171:3a7713b1edbc 802 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 803 /* @brief Has 0x06 Program Longword command. */
AnnaBridge 171:3a7713b1edbc 804 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
AnnaBridge 171:3a7713b1edbc 805 /* @brief Has 0x07 Program Phrase command. */
AnnaBridge 171:3a7713b1edbc 806 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
AnnaBridge 171:3a7713b1edbc 807 /* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge 171:3a7713b1edbc 808 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
AnnaBridge 171:3a7713b1edbc 809 /* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge 171:3a7713b1edbc 810 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge 171:3a7713b1edbc 811 /* @brief Has 0x0B Program Section command. */
AnnaBridge 171:3a7713b1edbc 812 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
AnnaBridge 171:3a7713b1edbc 813 /* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge 171:3a7713b1edbc 814 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
AnnaBridge 171:3a7713b1edbc 815 /* @brief Has 0x41 Read Once command. */
AnnaBridge 171:3a7713b1edbc 816 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 817 /* @brief Has 0x43 Program Once command. */
AnnaBridge 171:3a7713b1edbc 818 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 819 /* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge 171:3a7713b1edbc 820 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
AnnaBridge 171:3a7713b1edbc 821 /* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge 171:3a7713b1edbc 822 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge 171:3a7713b1edbc 823 /* @brief Has 0x46 Swap Control command. */
AnnaBridge 171:3a7713b1edbc 824 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
AnnaBridge 171:3a7713b1edbc 825 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge 171:3a7713b1edbc 826 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
AnnaBridge 171:3a7713b1edbc 827 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
AnnaBridge 171:3a7713b1edbc 828 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge 171:3a7713b1edbc 829 /* @brief Has 0x4B Erase All Execute-only Segments command. */
AnnaBridge 171:3a7713b1edbc 830 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge 171:3a7713b1edbc 831 /* @brief Has 0x80 Program Partition command. */
AnnaBridge 171:3a7713b1edbc 832 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
AnnaBridge 171:3a7713b1edbc 833 /* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge 171:3a7713b1edbc 834 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
AnnaBridge 171:3a7713b1edbc 835 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge 171:3a7713b1edbc 836 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 837 /* @brief P-Flash Erase sector command address alignment. */
AnnaBridge 171:3a7713b1edbc 838 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 839 /* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge 171:3a7713b1edbc 840 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 841 /* @brief P-Flash Read resource command address alignment. */
AnnaBridge 171:3a7713b1edbc 842 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge 171:3a7713b1edbc 843 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 844 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 171:3a7713b1edbc 845 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 846 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 847 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge 171:3a7713b1edbc 848 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 849 /* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge 171:3a7713b1edbc 850 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 851 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge 171:3a7713b1edbc 852 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 853 /* @brief FlexNVM Read resource command address alignment. */
AnnaBridge 171:3a7713b1edbc 854 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 855 /* @brief FlexNVM Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 856 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 857 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 858 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 859 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 860 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 861 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 862 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 863 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 864 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 865 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 866 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 867 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 868 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 869 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 870 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 871 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 872 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 873 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 874 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 875 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 876 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 877 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 878 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 879 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 880 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 881 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 882 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 883 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 884 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 885 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 886 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 887 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 888 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 889 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 890 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 891 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 892 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 893 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 894 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
AnnaBridge 171:3a7713b1edbc 895 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 896 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
AnnaBridge 171:3a7713b1edbc 897 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 898 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
AnnaBridge 171:3a7713b1edbc 899 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 900 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
AnnaBridge 171:3a7713b1edbc 901 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 902 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
AnnaBridge 171:3a7713b1edbc 903 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 904 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
AnnaBridge 171:3a7713b1edbc 905 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 906 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
AnnaBridge 171:3a7713b1edbc 907 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 908 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
AnnaBridge 171:3a7713b1edbc 909 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 910 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 911 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 912 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 913 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 914 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 915 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 916 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 917 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 918 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 919 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 920 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
AnnaBridge 171:3a7713b1edbc 921 #elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
AnnaBridge 171:3a7713b1edbc 922 /* @brief Is of type FTFA. */
AnnaBridge 171:3a7713b1edbc 923 #define FSL_FEATURE_FLASH_IS_FTFA (0)
AnnaBridge 171:3a7713b1edbc 924 /* @brief Is of type FTFE. */
AnnaBridge 171:3a7713b1edbc 925 #define FSL_FEATURE_FLASH_IS_FTFE (1)
AnnaBridge 171:3a7713b1edbc 926 /* @brief Is of type FTFL. */
AnnaBridge 171:3a7713b1edbc 927 #define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge 171:3a7713b1edbc 928 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge 171:3a7713b1edbc 929 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
AnnaBridge 171:3a7713b1edbc 930 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge 171:3a7713b1edbc 931 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
AnnaBridge 171:3a7713b1edbc 932 /* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge 171:3a7713b1edbc 933 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
AnnaBridge 171:3a7713b1edbc 934 /* @brief Has data flash region protection (register FDPROT). */
AnnaBridge 171:3a7713b1edbc 935 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
AnnaBridge 171:3a7713b1edbc 936 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge 171:3a7713b1edbc 937 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
AnnaBridge 171:3a7713b1edbc 938 /* @brief Has flash cache control in FMC module. */
AnnaBridge 171:3a7713b1edbc 939 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
AnnaBridge 171:3a7713b1edbc 940 /* @brief Has flash cache control in MCM module. */
AnnaBridge 171:3a7713b1edbc 941 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge 171:3a7713b1edbc 942 /* @brief Has flash cache control in MSCM module. */
AnnaBridge 171:3a7713b1edbc 943 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge 171:3a7713b1edbc 944 /* @brief P-Flash start address. */
AnnaBridge 171:3a7713b1edbc 945 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge 171:3a7713b1edbc 946 /* @brief P-Flash block count. */
AnnaBridge 171:3a7713b1edbc 947 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
AnnaBridge 171:3a7713b1edbc 948 /* @brief P-Flash block size. */
AnnaBridge 171:3a7713b1edbc 949 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
AnnaBridge 171:3a7713b1edbc 950 /* @brief P-Flash sector size. */
AnnaBridge 171:3a7713b1edbc 951 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
AnnaBridge 171:3a7713b1edbc 952 /* @brief P-Flash write unit size. */
AnnaBridge 171:3a7713b1edbc 953 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
AnnaBridge 171:3a7713b1edbc 954 /* @brief P-Flash data path width. */
AnnaBridge 171:3a7713b1edbc 955 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
AnnaBridge 171:3a7713b1edbc 956 /* @brief P-Flash block swap feature. */
AnnaBridge 171:3a7713b1edbc 957 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
AnnaBridge 171:3a7713b1edbc 958 /* @brief P-Flash protection region count. */
AnnaBridge 171:3a7713b1edbc 959 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge 171:3a7713b1edbc 960 /* @brief Has FlexNVM memory. */
AnnaBridge 171:3a7713b1edbc 961 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
AnnaBridge 171:3a7713b1edbc 962 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge 171:3a7713b1edbc 963 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
AnnaBridge 171:3a7713b1edbc 964 /* @brief FlexNVM block count. */
AnnaBridge 171:3a7713b1edbc 965 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
AnnaBridge 171:3a7713b1edbc 966 /* @brief FlexNVM block size. */
AnnaBridge 171:3a7713b1edbc 967 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
AnnaBridge 171:3a7713b1edbc 968 /* @brief FlexNVM sector size. */
AnnaBridge 171:3a7713b1edbc 969 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
AnnaBridge 171:3a7713b1edbc 970 /* @brief FlexNVM write unit size. */
AnnaBridge 171:3a7713b1edbc 971 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
AnnaBridge 171:3a7713b1edbc 972 /* @brief FlexNVM data path width. */
AnnaBridge 171:3a7713b1edbc 973 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
AnnaBridge 171:3a7713b1edbc 974 /* @brief Has FlexRAM memory. */
AnnaBridge 171:3a7713b1edbc 975 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
AnnaBridge 171:3a7713b1edbc 976 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge 171:3a7713b1edbc 977 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
AnnaBridge 171:3a7713b1edbc 978 /* @brief FlexRAM size. */
AnnaBridge 171:3a7713b1edbc 979 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
AnnaBridge 171:3a7713b1edbc 980 /* @brief Has 0x00 Read 1s Block command. */
AnnaBridge 171:3a7713b1edbc 981 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
AnnaBridge 171:3a7713b1edbc 982 /* @brief Has 0x01 Read 1s Section command. */
AnnaBridge 171:3a7713b1edbc 983 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge 171:3a7713b1edbc 984 /* @brief Has 0x02 Program Check command. */
AnnaBridge 171:3a7713b1edbc 985 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge 171:3a7713b1edbc 986 /* @brief Has 0x03 Read Resource command. */
AnnaBridge 171:3a7713b1edbc 987 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 988 /* @brief Has 0x06 Program Longword command. */
AnnaBridge 171:3a7713b1edbc 989 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
AnnaBridge 171:3a7713b1edbc 990 /* @brief Has 0x07 Program Phrase command. */
AnnaBridge 171:3a7713b1edbc 991 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
AnnaBridge 171:3a7713b1edbc 992 /* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge 171:3a7713b1edbc 993 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
AnnaBridge 171:3a7713b1edbc 994 /* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge 171:3a7713b1edbc 995 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge 171:3a7713b1edbc 996 /* @brief Has 0x0B Program Section command. */
AnnaBridge 171:3a7713b1edbc 997 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
AnnaBridge 171:3a7713b1edbc 998 /* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge 171:3a7713b1edbc 999 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
AnnaBridge 171:3a7713b1edbc 1000 /* @brief Has 0x41 Read Once command. */
AnnaBridge 171:3a7713b1edbc 1001 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 1002 /* @brief Has 0x43 Program Once command. */
AnnaBridge 171:3a7713b1edbc 1003 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge 171:3a7713b1edbc 1004 /* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge 171:3a7713b1edbc 1005 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
AnnaBridge 171:3a7713b1edbc 1006 /* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge 171:3a7713b1edbc 1007 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge 171:3a7713b1edbc 1008 /* @brief Has 0x46 Swap Control command. */
AnnaBridge 171:3a7713b1edbc 1009 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
AnnaBridge 171:3a7713b1edbc 1010 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge 171:3a7713b1edbc 1011 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
AnnaBridge 171:3a7713b1edbc 1012 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
AnnaBridge 171:3a7713b1edbc 1013 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge 171:3a7713b1edbc 1014 /* @brief Has 0x4B Erase All Execute-only Segments command. */
AnnaBridge 171:3a7713b1edbc 1015 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge 171:3a7713b1edbc 1016 /* @brief Has 0x80 Program Partition command. */
AnnaBridge 171:3a7713b1edbc 1017 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
AnnaBridge 171:3a7713b1edbc 1018 /* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge 171:3a7713b1edbc 1019 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
AnnaBridge 171:3a7713b1edbc 1020 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge 171:3a7713b1edbc 1021 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1022 /* @brief P-Flash Erase sector command address alignment. */
AnnaBridge 171:3a7713b1edbc 1023 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1024 /* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge 171:3a7713b1edbc 1025 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1026 /* @brief P-Flash Read resource command address alignment. */
AnnaBridge 171:3a7713b1edbc 1027 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge 171:3a7713b1edbc 1028 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 1029 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 171:3a7713b1edbc 1030 /* @brief P-Flash Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 1031 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge 171:3a7713b1edbc 1032 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge 171:3a7713b1edbc 1033 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1034 /* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge 171:3a7713b1edbc 1035 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1036 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge 171:3a7713b1edbc 1037 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge 171:3a7713b1edbc 1038 /* @brief FlexNVM Read resource command address alignment. */
AnnaBridge 171:3a7713b1edbc 1039 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge 171:3a7713b1edbc 1040 /* @brief FlexNVM Program check command address alignment. */
AnnaBridge 171:3a7713b1edbc 1041 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge 171:3a7713b1edbc 1042 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1043 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
AnnaBridge 171:3a7713b1edbc 1044 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1045 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 1046 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1047 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
AnnaBridge 171:3a7713b1edbc 1048 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1049 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
AnnaBridge 171:3a7713b1edbc 1050 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1051 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
AnnaBridge 171:3a7713b1edbc 1052 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1053 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
AnnaBridge 171:3a7713b1edbc 1054 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1055 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 1056 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1057 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 1058 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1059 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
AnnaBridge 171:3a7713b1edbc 1060 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1061 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 1062 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1063 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
AnnaBridge 171:3a7713b1edbc 1064 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1065 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
AnnaBridge 171:3a7713b1edbc 1066 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1067 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
AnnaBridge 171:3a7713b1edbc 1068 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1069 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
AnnaBridge 171:3a7713b1edbc 1070 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1071 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge 171:3a7713b1edbc 1072 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1073 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
AnnaBridge 171:3a7713b1edbc 1074 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1075 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1076 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1077 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1078 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1079 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
AnnaBridge 171:3a7713b1edbc 1080 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1081 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
AnnaBridge 171:3a7713b1edbc 1082 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1083 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
AnnaBridge 171:3a7713b1edbc 1084 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1085 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
AnnaBridge 171:3a7713b1edbc 1086 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1087 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
AnnaBridge 171:3a7713b1edbc 1088 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1089 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
AnnaBridge 171:3a7713b1edbc 1090 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1091 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
AnnaBridge 171:3a7713b1edbc 1092 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1093 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
AnnaBridge 171:3a7713b1edbc 1094 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1095 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1096 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1097 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1098 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1099 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1100 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1101 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1102 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1103 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge 171:3a7713b1edbc 1104 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge 171:3a7713b1edbc 1105 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
AnnaBridge 171:3a7713b1edbc 1106 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \
AnnaBridge 171:3a7713b1edbc 1107 defined(CPU_MK64FN1M0VMD12) */
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 /* FTM module features */
AnnaBridge 171:3a7713b1edbc 1110
AnnaBridge 171:3a7713b1edbc 1111 /* @brief Number of channels. */
AnnaBridge 171:3a7713b1edbc 1112 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
AnnaBridge 171:3a7713b1edbc 1113 ((x) == FTM0 ? (8) : \
AnnaBridge 171:3a7713b1edbc 1114 ((x) == FTM1 ? (2) : \
AnnaBridge 171:3a7713b1edbc 1115 ((x) == FTM2 ? (2) : \
AnnaBridge 171:3a7713b1edbc 1116 ((x) == FTM3 ? (8) : (-1)))))
AnnaBridge 171:3a7713b1edbc 1117 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
AnnaBridge 171:3a7713b1edbc 1118 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
AnnaBridge 171:3a7713b1edbc 1119 /* @brief Has extended deadtime value. */
AnnaBridge 171:3a7713b1edbc 1120 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
AnnaBridge 171:3a7713b1edbc 1121 /* @brief Enable pwm output for the module. */
AnnaBridge 171:3a7713b1edbc 1122 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
AnnaBridge 171:3a7713b1edbc 1123 /* @brief Has half-cycle reload for the module. */
AnnaBridge 171:3a7713b1edbc 1124 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
AnnaBridge 171:3a7713b1edbc 1125 /* @brief Has reload interrupt. */
AnnaBridge 171:3a7713b1edbc 1126 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
AnnaBridge 171:3a7713b1edbc 1127 /* @brief Has reload initialization trigger. */
AnnaBridge 171:3a7713b1edbc 1128 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
AnnaBridge 171:3a7713b1edbc 1129
AnnaBridge 171:3a7713b1edbc 1130 /* GPIO module features */
AnnaBridge 171:3a7713b1edbc 1131
AnnaBridge 171:3a7713b1edbc 1132 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */
AnnaBridge 171:3a7713b1edbc 1133 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
AnnaBridge 171:3a7713b1edbc 1134 /* @brief Has port input disable register (PIDR). */
AnnaBridge 171:3a7713b1edbc 1135 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
AnnaBridge 171:3a7713b1edbc 1136 /* @brief Has dedicated interrupt vector. */
AnnaBridge 171:3a7713b1edbc 1137 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /* I2C module features */
AnnaBridge 171:3a7713b1edbc 1140
AnnaBridge 171:3a7713b1edbc 1141 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
AnnaBridge 171:3a7713b1edbc 1142 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
AnnaBridge 171:3a7713b1edbc 1143 /* @brief Maximum supported baud rate in kilobit per second. */
AnnaBridge 171:3a7713b1edbc 1144 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
AnnaBridge 171:3a7713b1edbc 1145 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
AnnaBridge 171:3a7713b1edbc 1146 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
AnnaBridge 171:3a7713b1edbc 1147 /* @brief Has DMA support (register bit C1[DMAEN]). */
AnnaBridge 171:3a7713b1edbc 1148 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 1149 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
AnnaBridge 171:3a7713b1edbc 1150 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
AnnaBridge 171:3a7713b1edbc 1151 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
AnnaBridge 171:3a7713b1edbc 1152 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
AnnaBridge 171:3a7713b1edbc 1153 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
AnnaBridge 171:3a7713b1edbc 1154 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
AnnaBridge 171:3a7713b1edbc 1155 /* @brief Maximum width of the glitch filter in number of bus clocks. */
AnnaBridge 171:3a7713b1edbc 1156 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
AnnaBridge 171:3a7713b1edbc 1157 /* @brief Has control of the drive capability of the I2C pins. */
AnnaBridge 171:3a7713b1edbc 1158 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1159 /* @brief Has double buffering support (register S2). */
AnnaBridge 171:3a7713b1edbc 1160 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
AnnaBridge 171:3a7713b1edbc 1161 /* @brief Has double buffer enable. */
AnnaBridge 171:3a7713b1edbc 1162 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
AnnaBridge 171:3a7713b1edbc 1163
AnnaBridge 171:3a7713b1edbc 1164 /* SAI module features */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
AnnaBridge 171:3a7713b1edbc 1167 #define FSL_FEATURE_SAI_FIFO_COUNT (8)
AnnaBridge 171:3a7713b1edbc 1168 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
AnnaBridge 171:3a7713b1edbc 1169 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
AnnaBridge 171:3a7713b1edbc 1170 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
AnnaBridge 171:3a7713b1edbc 1171 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
AnnaBridge 171:3a7713b1edbc 1172 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
AnnaBridge 171:3a7713b1edbc 1173 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
AnnaBridge 171:3a7713b1edbc 1174 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
AnnaBridge 171:3a7713b1edbc 1175 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
AnnaBridge 171:3a7713b1edbc 1176 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
AnnaBridge 171:3a7713b1edbc 1177 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
AnnaBridge 171:3a7713b1edbc 1178 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
AnnaBridge 171:3a7713b1edbc 1179 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
AnnaBridge 171:3a7713b1edbc 1180 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
AnnaBridge 171:3a7713b1edbc 1181 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
AnnaBridge 171:3a7713b1edbc 1182 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
AnnaBridge 171:3a7713b1edbc 1183 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
AnnaBridge 171:3a7713b1edbc 1184 /* @brief Ihe interrupt source number */
AnnaBridge 171:3a7713b1edbc 1185 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
AnnaBridge 171:3a7713b1edbc 1186 /* @brief Has register of MCR. */
AnnaBridge 171:3a7713b1edbc 1187 #define FSL_FEATURE_SAI_HAS_MCR (1)
AnnaBridge 171:3a7713b1edbc 1188 /* @brief Has register of MDR */
AnnaBridge 171:3a7713b1edbc 1189 #define FSL_FEATURE_SAI_HAS_MDR (1)
AnnaBridge 171:3a7713b1edbc 1190
AnnaBridge 171:3a7713b1edbc 1191 /* LLWU module features */
AnnaBridge 171:3a7713b1edbc 1192
AnnaBridge 171:3a7713b1edbc 1193 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1194 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
AnnaBridge 171:3a7713b1edbc 1195 /* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1196 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge 171:3a7713b1edbc 1197 /* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1198 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge 171:3a7713b1edbc 1199 /* @brief Number of digital filters. */
AnnaBridge 171:3a7713b1edbc 1200 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
AnnaBridge 171:3a7713b1edbc 1201 /* @brief Has MF register. */
AnnaBridge 171:3a7713b1edbc 1202 #define FSL_FEATURE_LLWU_HAS_MF (0)
AnnaBridge 171:3a7713b1edbc 1203 /* @brief Has PF register. */
AnnaBridge 171:3a7713b1edbc 1204 #define FSL_FEATURE_LLWU_HAS_PF (0)
AnnaBridge 171:3a7713b1edbc 1205 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge 171:3a7713b1edbc 1206 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
AnnaBridge 171:3a7713b1edbc 1207 /* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1208 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
AnnaBridge 171:3a7713b1edbc 1209 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1210 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
AnnaBridge 171:3a7713b1edbc 1211 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1212 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
AnnaBridge 171:3a7713b1edbc 1213 /* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1214 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
AnnaBridge 171:3a7713b1edbc 1215 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1216 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
AnnaBridge 171:3a7713b1edbc 1217 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1218 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
AnnaBridge 171:3a7713b1edbc 1219 /* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1220 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
AnnaBridge 171:3a7713b1edbc 1221 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1222 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
AnnaBridge 171:3a7713b1edbc 1223 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1224 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
AnnaBridge 171:3a7713b1edbc 1225 /* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1226 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
AnnaBridge 171:3a7713b1edbc 1227 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1228 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
AnnaBridge 171:3a7713b1edbc 1229 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1230 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
AnnaBridge 171:3a7713b1edbc 1231 /* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1232 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
AnnaBridge 171:3a7713b1edbc 1233 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1234 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
AnnaBridge 171:3a7713b1edbc 1235 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1236 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
AnnaBridge 171:3a7713b1edbc 1237 /* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1238 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge 171:3a7713b1edbc 1239 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1240 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge 171:3a7713b1edbc 1241 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1242 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1243 /* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1244 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge 171:3a7713b1edbc 1245 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1246 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1247 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1248 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge 171:3a7713b1edbc 1249 /* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1250 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge 171:3a7713b1edbc 1251 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1252 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1253 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1254 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge 171:3a7713b1edbc 1255 /* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1256 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge 171:3a7713b1edbc 1257 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1258 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1259 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1260 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge 171:3a7713b1edbc 1261 /* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1262 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge 171:3a7713b1edbc 1263 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1264 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1265 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1266 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge 171:3a7713b1edbc 1267 /* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1268 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge 171:3a7713b1edbc 1269 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1270 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1271 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1272 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge 171:3a7713b1edbc 1273 /* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1274 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
AnnaBridge 171:3a7713b1edbc 1275 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1276 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
AnnaBridge 171:3a7713b1edbc 1277 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1278 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
AnnaBridge 171:3a7713b1edbc 1279 /* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1280 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
AnnaBridge 171:3a7713b1edbc 1281 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1282 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
AnnaBridge 171:3a7713b1edbc 1283 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1284 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1285 /* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1286 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
AnnaBridge 171:3a7713b1edbc 1287 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1288 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
AnnaBridge 171:3a7713b1edbc 1289 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1290 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
AnnaBridge 171:3a7713b1edbc 1291 /* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1292 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge 171:3a7713b1edbc 1293 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1294 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge 171:3a7713b1edbc 1295 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1296 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge 171:3a7713b1edbc 1297 /* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1298 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge 171:3a7713b1edbc 1299 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1300 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge 171:3a7713b1edbc 1301 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1302 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge 171:3a7713b1edbc 1303 /* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1304 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
AnnaBridge 171:3a7713b1edbc 1305 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1306 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1307 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1308 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1309 /* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1310 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
AnnaBridge 171:3a7713b1edbc 1311 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1312 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1313 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1314 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1315 /* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1316 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
AnnaBridge 171:3a7713b1edbc 1317 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1318 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1319 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1320 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1321 /* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1322 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge 171:3a7713b1edbc 1323 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1324 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1325 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1326 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1327 /* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1328 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge 171:3a7713b1edbc 1329 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1330 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1331 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1332 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1333 /* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1334 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge 171:3a7713b1edbc 1335 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1336 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1337 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1338 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1339 /* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1340 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
AnnaBridge 171:3a7713b1edbc 1341 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1342 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1343 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1344 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1345 /* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1346 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
AnnaBridge 171:3a7713b1edbc 1347 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1348 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1349 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1350 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1351 /* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1352 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
AnnaBridge 171:3a7713b1edbc 1353 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1354 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1355 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1356 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1357 /* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1358 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
AnnaBridge 171:3a7713b1edbc 1359 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1360 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1361 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1362 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1363 /* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1364 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge 171:3a7713b1edbc 1365 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1366 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1367 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1368 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1369 /* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1370 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge 171:3a7713b1edbc 1371 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1372 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1373 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1374 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1375 /* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1376 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge 171:3a7713b1edbc 1377 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1378 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1379 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1380 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1381 /* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1382 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge 171:3a7713b1edbc 1383 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1384 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1385 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1386 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1387 /* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1388 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge 171:3a7713b1edbc 1389 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1390 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1391 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1392 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1393 /* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1394 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge 171:3a7713b1edbc 1395 /* @brief Index of port of external pin. */
AnnaBridge 171:3a7713b1edbc 1396 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge 171:3a7713b1edbc 1397 /* @brief Number of external pin port on specified port. */
AnnaBridge 171:3a7713b1edbc 1398 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge 171:3a7713b1edbc 1399 /* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1400 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge 171:3a7713b1edbc 1401 /* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1402 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge 171:3a7713b1edbc 1403 /* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1404 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
AnnaBridge 171:3a7713b1edbc 1405 /* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1406 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
AnnaBridge 171:3a7713b1edbc 1407 /* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1408 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
AnnaBridge 171:3a7713b1edbc 1409 /* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1410 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge 171:3a7713b1edbc 1411 /* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1412 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge 171:3a7713b1edbc 1413 /* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge 171:3a7713b1edbc 1414 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge 171:3a7713b1edbc 1415 /* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge 171:3a7713b1edbc 1416 #define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge 171:3a7713b1edbc 1417 /* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge 171:3a7713b1edbc 1418 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge 171:3a7713b1edbc 1419 /* @brief Width of registers of the LLWU. */
AnnaBridge 171:3a7713b1edbc 1420 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge 171:3a7713b1edbc 1421 /* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge 171:3a7713b1edbc 1422 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge 171:3a7713b1edbc 1423
AnnaBridge 171:3a7713b1edbc 1424 /* LPTMR module features */
AnnaBridge 171:3a7713b1edbc 1425
AnnaBridge 171:3a7713b1edbc 1426 /* @brief Has shared interrupt handler with another LPTMR module. */
AnnaBridge 171:3a7713b1edbc 1427 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge 171:3a7713b1edbc 1428 /* @brief Whether LPTMR counter is 32 bits width. */
AnnaBridge 171:3a7713b1edbc 1429 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
AnnaBridge 171:3a7713b1edbc 1430
AnnaBridge 171:3a7713b1edbc 1431 /* MCG module features */
AnnaBridge 171:3a7713b1edbc 1432
AnnaBridge 171:3a7713b1edbc 1433 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
AnnaBridge 171:3a7713b1edbc 1434 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
AnnaBridge 171:3a7713b1edbc 1435 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
AnnaBridge 171:3a7713b1edbc 1436 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
AnnaBridge 171:3a7713b1edbc 1437 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
AnnaBridge 171:3a7713b1edbc 1438 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
AnnaBridge 171:3a7713b1edbc 1439 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */
AnnaBridge 171:3a7713b1edbc 1440 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
AnnaBridge 171:3a7713b1edbc 1441 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */
AnnaBridge 171:3a7713b1edbc 1442 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
AnnaBridge 171:3a7713b1edbc 1443 /* @brief The PLL clock is divided by 2 before VCO divider. */
AnnaBridge 171:3a7713b1edbc 1444 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
AnnaBridge 171:3a7713b1edbc 1445 /* @brief FRDIV supports 1280. */
AnnaBridge 171:3a7713b1edbc 1446 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
AnnaBridge 171:3a7713b1edbc 1447 /* @brief FRDIV supports 1536. */
AnnaBridge 171:3a7713b1edbc 1448 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
AnnaBridge 171:3a7713b1edbc 1449 /* @brief MCGFFCLK divider. */
AnnaBridge 171:3a7713b1edbc 1450 #define FSL_FEATURE_MCG_FFCLK_DIV (1)
AnnaBridge 171:3a7713b1edbc 1451 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
AnnaBridge 171:3a7713b1edbc 1452 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
AnnaBridge 171:3a7713b1edbc 1453 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
AnnaBridge 171:3a7713b1edbc 1454 #define FSL_FEATURE_MCG_HAS_RTC_32K (1)
AnnaBridge 171:3a7713b1edbc 1455 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
AnnaBridge 171:3a7713b1edbc 1456 #define FSL_FEATURE_MCG_HAS_PLL1 (0)
AnnaBridge 171:3a7713b1edbc 1457 /* @brief Has 48MHz internal oscillator. */
AnnaBridge 171:3a7713b1edbc 1458 #define FSL_FEATURE_MCG_HAS_IRC_48M (1)
AnnaBridge 171:3a7713b1edbc 1459 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
AnnaBridge 171:3a7713b1edbc 1460 #define FSL_FEATURE_MCG_HAS_OSC1 (0)
AnnaBridge 171:3a7713b1edbc 1461 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
AnnaBridge 171:3a7713b1edbc 1462 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
AnnaBridge 171:3a7713b1edbc 1463 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
AnnaBridge 171:3a7713b1edbc 1464 #define FSL_FEATURE_MCG_HAS_LOLRE (1)
AnnaBridge 171:3a7713b1edbc 1465 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
AnnaBridge 171:3a7713b1edbc 1466 #define FSL_FEATURE_MCG_USE_OSCSEL (1)
AnnaBridge 171:3a7713b1edbc 1467 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
AnnaBridge 171:3a7713b1edbc 1468 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
AnnaBridge 171:3a7713b1edbc 1469 /* @brief TBD */
AnnaBridge 171:3a7713b1edbc 1470 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
AnnaBridge 171:3a7713b1edbc 1471 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
AnnaBridge 171:3a7713b1edbc 1472 #define FSL_FEATURE_MCG_HAS_PLL (1)
AnnaBridge 171:3a7713b1edbc 1473 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
AnnaBridge 171:3a7713b1edbc 1474 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
AnnaBridge 171:3a7713b1edbc 1475 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
AnnaBridge 171:3a7713b1edbc 1476 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
AnnaBridge 171:3a7713b1edbc 1477 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
AnnaBridge 171:3a7713b1edbc 1478 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
AnnaBridge 171:3a7713b1edbc 1479 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
AnnaBridge 171:3a7713b1edbc 1480 #define FSL_FEATURE_MCG_HAS_FLL (1)
AnnaBridge 171:3a7713b1edbc 1481 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
AnnaBridge 171:3a7713b1edbc 1482 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
AnnaBridge 171:3a7713b1edbc 1483 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
AnnaBridge 171:3a7713b1edbc 1484 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
AnnaBridge 171:3a7713b1edbc 1485 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
AnnaBridge 171:3a7713b1edbc 1486 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1487 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
AnnaBridge 171:3a7713b1edbc 1488 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
AnnaBridge 171:3a7713b1edbc 1489 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
AnnaBridge 171:3a7713b1edbc 1490 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
AnnaBridge 171:3a7713b1edbc 1491 /* @brief Has external clock monitor (register bit C6[CME]). */
AnnaBridge 171:3a7713b1edbc 1492 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
AnnaBridge 171:3a7713b1edbc 1493 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
AnnaBridge 171:3a7713b1edbc 1494 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
AnnaBridge 171:3a7713b1edbc 1495 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
AnnaBridge 171:3a7713b1edbc 1496 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
AnnaBridge 171:3a7713b1edbc 1497 /* @brief Has PEI mode or PBI mode. */
AnnaBridge 171:3a7713b1edbc 1498 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
AnnaBridge 171:3a7713b1edbc 1499 /* @brief Reset clock mode is BLPI. */
AnnaBridge 171:3a7713b1edbc 1500 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
AnnaBridge 171:3a7713b1edbc 1501
AnnaBridge 171:3a7713b1edbc 1502 /* interrupt module features */
AnnaBridge 171:3a7713b1edbc 1503
AnnaBridge 171:3a7713b1edbc 1504 /* @brief Lowest interrupt request number. */
AnnaBridge 171:3a7713b1edbc 1505 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
AnnaBridge 171:3a7713b1edbc 1506 /* @brief Highest interrupt request number. */
AnnaBridge 171:3a7713b1edbc 1507 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
AnnaBridge 171:3a7713b1edbc 1508
AnnaBridge 171:3a7713b1edbc 1509 /* OSC module features */
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511 /* @brief Has OSC1 external oscillator. */
AnnaBridge 171:3a7713b1edbc 1512 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
AnnaBridge 171:3a7713b1edbc 1513 /* @brief Has OSC0 external oscillator. */
AnnaBridge 171:3a7713b1edbc 1514 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
AnnaBridge 171:3a7713b1edbc 1515 /* @brief Has OSC external oscillator (without index). */
AnnaBridge 171:3a7713b1edbc 1516 #define FSL_FEATURE_OSC_HAS_OSC (1)
AnnaBridge 171:3a7713b1edbc 1517 /* @brief Number of OSC external oscillators. */
AnnaBridge 171:3a7713b1edbc 1518 #define FSL_FEATURE_OSC_OSC_COUNT (1)
AnnaBridge 171:3a7713b1edbc 1519 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
AnnaBridge 171:3a7713b1edbc 1520 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
AnnaBridge 171:3a7713b1edbc 1521
AnnaBridge 171:3a7713b1edbc 1522 /* PDB module features */
AnnaBridge 171:3a7713b1edbc 1523
AnnaBridge 171:3a7713b1edbc 1524 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
AnnaBridge 171:3a7713b1edbc 1525 #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
AnnaBridge 171:3a7713b1edbc 1526 /* @brief Has DAC support. */
AnnaBridge 171:3a7713b1edbc 1527 #define FSL_FEATURE_PDB_HAS_DAC (1)
AnnaBridge 171:3a7713b1edbc 1528 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge 171:3a7713b1edbc 1529 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge 171:3a7713b1edbc 1530
AnnaBridge 171:3a7713b1edbc 1531 /* PIT module features */
AnnaBridge 171:3a7713b1edbc 1532
AnnaBridge 171:3a7713b1edbc 1533 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
AnnaBridge 171:3a7713b1edbc 1534 #define FSL_FEATURE_PIT_TIMER_COUNT (4)
AnnaBridge 171:3a7713b1edbc 1535 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
AnnaBridge 171:3a7713b1edbc 1536 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
AnnaBridge 171:3a7713b1edbc 1537 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
AnnaBridge 171:3a7713b1edbc 1538 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
AnnaBridge 171:3a7713b1edbc 1539 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge 171:3a7713b1edbc 1540 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge 171:3a7713b1edbc 1541
AnnaBridge 171:3a7713b1edbc 1542 /* PMC module features */
AnnaBridge 171:3a7713b1edbc 1543
AnnaBridge 171:3a7713b1edbc 1544 /* @brief Has Bandgap Enable In VLPx Operation support. */
AnnaBridge 171:3a7713b1edbc 1545 #define FSL_FEATURE_PMC_HAS_BGEN (1)
AnnaBridge 171:3a7713b1edbc 1546 /* @brief Has Bandgap Buffer Enable. */
AnnaBridge 171:3a7713b1edbc 1547 #define FSL_FEATURE_PMC_HAS_BGBE (1)
AnnaBridge 171:3a7713b1edbc 1548 /* @brief Has Bandgap Buffer Drive Select. */
AnnaBridge 171:3a7713b1edbc 1549 #define FSL_FEATURE_PMC_HAS_BGBDS (0)
AnnaBridge 171:3a7713b1edbc 1550 /* @brief Has Low-Voltage Detect Voltage Select support. */
AnnaBridge 171:3a7713b1edbc 1551 #define FSL_FEATURE_PMC_HAS_LVDV (1)
AnnaBridge 171:3a7713b1edbc 1552 /* @brief Has Low-Voltage Warning Voltage Select support. */
AnnaBridge 171:3a7713b1edbc 1553 #define FSL_FEATURE_PMC_HAS_LVWV (1)
AnnaBridge 171:3a7713b1edbc 1554 /* @brief Has LPO. */
AnnaBridge 171:3a7713b1edbc 1555 #define FSL_FEATURE_PMC_HAS_LPO (0)
AnnaBridge 171:3a7713b1edbc 1556 /* @brief Has VLPx option PMC_REGSC[VLPO]. */
AnnaBridge 171:3a7713b1edbc 1557 #define FSL_FEATURE_PMC_HAS_VLPO (0)
AnnaBridge 171:3a7713b1edbc 1558 /* @brief Has acknowledge isolation support. */
AnnaBridge 171:3a7713b1edbc 1559 #define FSL_FEATURE_PMC_HAS_ACKISO (1)
AnnaBridge 171:3a7713b1edbc 1560 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
AnnaBridge 171:3a7713b1edbc 1561 #define FSL_FEATURE_PMC_HAS_REGFPM (0)
AnnaBridge 171:3a7713b1edbc 1562 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
AnnaBridge 171:3a7713b1edbc 1563 #define FSL_FEATURE_PMC_HAS_REGONS (1)
AnnaBridge 171:3a7713b1edbc 1564 /* @brief Has PMC_HVDSC1. */
AnnaBridge 171:3a7713b1edbc 1565 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
AnnaBridge 171:3a7713b1edbc 1566 /* @brief Has PMC_PARAM. */
AnnaBridge 171:3a7713b1edbc 1567 #define FSL_FEATURE_PMC_HAS_PARAM (0)
AnnaBridge 171:3a7713b1edbc 1568 /* @brief Has PMC_VERID. */
AnnaBridge 171:3a7713b1edbc 1569 #define FSL_FEATURE_PMC_HAS_VERID (0)
AnnaBridge 171:3a7713b1edbc 1570
AnnaBridge 171:3a7713b1edbc 1571 /* PORT module features */
AnnaBridge 171:3a7713b1edbc 1572
AnnaBridge 171:3a7713b1edbc 1573 /* @brief Has control lock (register bit PCR[LK]). */
AnnaBridge 171:3a7713b1edbc 1574 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
AnnaBridge 171:3a7713b1edbc 1575 /* @brief Has open drain control (register bit PCR[ODE]). */
AnnaBridge 171:3a7713b1edbc 1576 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
AnnaBridge 171:3a7713b1edbc 1577 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
AnnaBridge 171:3a7713b1edbc 1578 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
AnnaBridge 171:3a7713b1edbc 1579 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
AnnaBridge 171:3a7713b1edbc 1580 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
AnnaBridge 171:3a7713b1edbc 1581 /* @brief Has pull resistor selection available. */
AnnaBridge 171:3a7713b1edbc 1582 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1583 /* @brief Has pull resistor enable (register bit PCR[PE]). */
AnnaBridge 171:3a7713b1edbc 1584 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
AnnaBridge 171:3a7713b1edbc 1585 /* @brief Has slew rate control (register bit PCR[SRE]). */
AnnaBridge 171:3a7713b1edbc 1586 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
AnnaBridge 171:3a7713b1edbc 1587 /* @brief Has passive filter (register bit field PCR[PFE]). */
AnnaBridge 171:3a7713b1edbc 1588 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
AnnaBridge 171:3a7713b1edbc 1589 /* @brief Has drive strength control (register bit PCR[DSE]). */
AnnaBridge 171:3a7713b1edbc 1590 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
AnnaBridge 171:3a7713b1edbc 1591 /* @brief Has separate drive strength register (HDRVE). */
AnnaBridge 171:3a7713b1edbc 1592 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
AnnaBridge 171:3a7713b1edbc 1593 /* @brief Has glitch filter (register IOFLT). */
AnnaBridge 171:3a7713b1edbc 1594 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
AnnaBridge 171:3a7713b1edbc 1595 /* @brief Defines width of PCR[MUX] field. */
AnnaBridge 171:3a7713b1edbc 1596 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
AnnaBridge 171:3a7713b1edbc 1597 /* @brief Has dedicated interrupt vector. */
AnnaBridge 171:3a7713b1edbc 1598 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
AnnaBridge 171:3a7713b1edbc 1599 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
AnnaBridge 171:3a7713b1edbc 1600 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
AnnaBridge 171:3a7713b1edbc 1601 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
AnnaBridge 171:3a7713b1edbc 1602 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
AnnaBridge 171:3a7713b1edbc 1603
AnnaBridge 171:3a7713b1edbc 1604 /* RCM module features */
AnnaBridge 171:3a7713b1edbc 1605
AnnaBridge 171:3a7713b1edbc 1606 /* @brief Has Loss-of-Lock Reset support. */
AnnaBridge 171:3a7713b1edbc 1607 #define FSL_FEATURE_RCM_HAS_LOL (1)
AnnaBridge 171:3a7713b1edbc 1608 /* @brief Has Loss-of-Clock Reset support. */
AnnaBridge 171:3a7713b1edbc 1609 #define FSL_FEATURE_RCM_HAS_LOC (1)
AnnaBridge 171:3a7713b1edbc 1610 /* @brief Has JTAG generated Reset support. */
AnnaBridge 171:3a7713b1edbc 1611 #define FSL_FEATURE_RCM_HAS_JTAG (1)
AnnaBridge 171:3a7713b1edbc 1612 /* @brief Has EzPort generated Reset support. */
AnnaBridge 171:3a7713b1edbc 1613 #define FSL_FEATURE_RCM_HAS_EZPORT (1)
AnnaBridge 171:3a7713b1edbc 1614 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
AnnaBridge 171:3a7713b1edbc 1615 #define FSL_FEATURE_RCM_HAS_EZPMS (1)
AnnaBridge 171:3a7713b1edbc 1616 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
AnnaBridge 171:3a7713b1edbc 1617 #define FSL_FEATURE_RCM_HAS_BOOTROM (0)
AnnaBridge 171:3a7713b1edbc 1618 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
AnnaBridge 171:3a7713b1edbc 1619 #define FSL_FEATURE_RCM_HAS_SSRS (0)
AnnaBridge 171:3a7713b1edbc 1620 /* @brief Has Version ID Register (RCM_VERID). */
AnnaBridge 171:3a7713b1edbc 1621 #define FSL_FEATURE_RCM_HAS_VERID (0)
AnnaBridge 171:3a7713b1edbc 1622 /* @brief Has Parameter Register (RCM_PARAM). */
AnnaBridge 171:3a7713b1edbc 1623 #define FSL_FEATURE_RCM_HAS_PARAM (0)
AnnaBridge 171:3a7713b1edbc 1624 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
AnnaBridge 171:3a7713b1edbc 1625 #define FSL_FEATURE_RCM_HAS_SRIE (0)
AnnaBridge 171:3a7713b1edbc 1626 /* @brief Width of registers of the RCM. */
AnnaBridge 171:3a7713b1edbc 1627 #define FSL_FEATURE_RCM_REG_WIDTH (8)
AnnaBridge 171:3a7713b1edbc 1628 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
AnnaBridge 171:3a7713b1edbc 1629 #define FSL_FEATURE_RCM_HAS_CORE1 (0)
AnnaBridge 171:3a7713b1edbc 1630 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
AnnaBridge 171:3a7713b1edbc 1631 #define FSL_FEATURE_RCM_HAS_MDM_AP (1)
AnnaBridge 171:3a7713b1edbc 1632 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
AnnaBridge 171:3a7713b1edbc 1633 #define FSL_FEATURE_RCM_HAS_WAKEUP (1)
AnnaBridge 171:3a7713b1edbc 1634
AnnaBridge 171:3a7713b1edbc 1635 /* RTC module features */
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \
AnnaBridge 171:3a7713b1edbc 1638 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12)
AnnaBridge 171:3a7713b1edbc 1639 /* @brief Has wakeup pin. */
AnnaBridge 171:3a7713b1edbc 1640 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
AnnaBridge 171:3a7713b1edbc 1641 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
AnnaBridge 171:3a7713b1edbc 1642 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1643 /* @brief Has low power features (registers MER, MCLR and MCHR). */
AnnaBridge 171:3a7713b1edbc 1644 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
AnnaBridge 171:3a7713b1edbc 1645 /* @brief Has read/write access control (registers WAR and RAR). */
AnnaBridge 171:3a7713b1edbc 1646 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
AnnaBridge 171:3a7713b1edbc 1647 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
AnnaBridge 171:3a7713b1edbc 1648 #define FSL_FEATURE_RTC_HAS_SECURITY (1)
AnnaBridge 171:3a7713b1edbc 1649 /* @brief Has RTC_CLKIN available. */
AnnaBridge 171:3a7713b1edbc 1650 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
AnnaBridge 171:3a7713b1edbc 1651 /* @brief Has prescaler adjust for LPO. */
AnnaBridge 171:3a7713b1edbc 1652 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
AnnaBridge 171:3a7713b1edbc 1653 /* @brief Has Clock Pin Enable field. */
AnnaBridge 171:3a7713b1edbc 1654 #define FSL_FEATURE_RTC_HAS_CPE (0)
AnnaBridge 171:3a7713b1edbc 1655 /* @brief Has Timer Seconds Interrupt Configuration field. */
AnnaBridge 171:3a7713b1edbc 1656 #define FSL_FEATURE_RTC_HAS_TSIC (0)
AnnaBridge 171:3a7713b1edbc 1657 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
AnnaBridge 171:3a7713b1edbc 1658 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
AnnaBridge 171:3a7713b1edbc 1659 #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
AnnaBridge 171:3a7713b1edbc 1660 /* @brief Has wakeup pin. */
AnnaBridge 171:3a7713b1edbc 1661 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
AnnaBridge 171:3a7713b1edbc 1662 /* @brief Has wakeup pin selection (bit field CR[WPS]). */
AnnaBridge 171:3a7713b1edbc 1663 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1664 /* @brief Has low power features (registers MER, MCLR and MCHR). */
AnnaBridge 171:3a7713b1edbc 1665 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
AnnaBridge 171:3a7713b1edbc 1666 /* @brief Has read/write access control (registers WAR and RAR). */
AnnaBridge 171:3a7713b1edbc 1667 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
AnnaBridge 171:3a7713b1edbc 1668 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
AnnaBridge 171:3a7713b1edbc 1669 #define FSL_FEATURE_RTC_HAS_SECURITY (0)
AnnaBridge 171:3a7713b1edbc 1670 /* @brief Has RTC_CLKIN available. */
AnnaBridge 171:3a7713b1edbc 1671 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
AnnaBridge 171:3a7713b1edbc 1672 /* @brief Has prescaler adjust for LPO. */
AnnaBridge 171:3a7713b1edbc 1673 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
AnnaBridge 171:3a7713b1edbc 1674 /* @brief Has Clock Pin Enable field. */
AnnaBridge 171:3a7713b1edbc 1675 #define FSL_FEATURE_RTC_HAS_CPE (0)
AnnaBridge 171:3a7713b1edbc 1676 /* @brief Has Timer Seconds Interrupt Configuration field. */
AnnaBridge 171:3a7713b1edbc 1677 #define FSL_FEATURE_RTC_HAS_TSIC (0)
AnnaBridge 171:3a7713b1edbc 1678 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
AnnaBridge 171:3a7713b1edbc 1679 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
AnnaBridge 171:3a7713b1edbc 1680 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \
AnnaBridge 171:3a7713b1edbc 1681 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */
AnnaBridge 171:3a7713b1edbc 1682
AnnaBridge 171:3a7713b1edbc 1683 /* SDHC module features */
AnnaBridge 171:3a7713b1edbc 1684
AnnaBridge 171:3a7713b1edbc 1685 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
AnnaBridge 171:3a7713b1edbc 1686 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 1687 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
AnnaBridge 171:3a7713b1edbc 1688 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 1689 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
AnnaBridge 171:3a7713b1edbc 1690 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 1691
AnnaBridge 171:3a7713b1edbc 1692 /* SIM module features */
AnnaBridge 171:3a7713b1edbc 1693
AnnaBridge 171:3a7713b1edbc 1694 /* @brief Has USB FS divider. */
AnnaBridge 171:3a7713b1edbc 1695 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
AnnaBridge 171:3a7713b1edbc 1696 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
AnnaBridge 171:3a7713b1edbc 1697 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
AnnaBridge 171:3a7713b1edbc 1698 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
AnnaBridge 171:3a7713b1edbc 1699 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
AnnaBridge 171:3a7713b1edbc 1700 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
AnnaBridge 171:3a7713b1edbc 1701 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
AnnaBridge 171:3a7713b1edbc 1702 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
AnnaBridge 171:3a7713b1edbc 1703 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1704 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
AnnaBridge 171:3a7713b1edbc 1705 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
AnnaBridge 171:3a7713b1edbc 1706 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
AnnaBridge 171:3a7713b1edbc 1707 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1708 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
AnnaBridge 171:3a7713b1edbc 1709 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
AnnaBridge 171:3a7713b1edbc 1710 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
AnnaBridge 171:3a7713b1edbc 1711 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
AnnaBridge 171:3a7713b1edbc 1712 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
AnnaBridge 171:3a7713b1edbc 1713 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
AnnaBridge 171:3a7713b1edbc 1714 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
AnnaBridge 171:3a7713b1edbc 1715 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
AnnaBridge 171:3a7713b1edbc 1716 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
AnnaBridge 171:3a7713b1edbc 1717 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
AnnaBridge 171:3a7713b1edbc 1718 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
AnnaBridge 171:3a7713b1edbc 1719 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
AnnaBridge 171:3a7713b1edbc 1720 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
AnnaBridge 171:3a7713b1edbc 1721 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
AnnaBridge 171:3a7713b1edbc 1722 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
AnnaBridge 171:3a7713b1edbc 1723 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
AnnaBridge 171:3a7713b1edbc 1724 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
AnnaBridge 171:3a7713b1edbc 1725 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
AnnaBridge 171:3a7713b1edbc 1726 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
AnnaBridge 171:3a7713b1edbc 1727 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
AnnaBridge 171:3a7713b1edbc 1728 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
AnnaBridge 171:3a7713b1edbc 1729 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
AnnaBridge 171:3a7713b1edbc 1730 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
AnnaBridge 171:3a7713b1edbc 1731 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
AnnaBridge 171:3a7713b1edbc 1732 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
AnnaBridge 171:3a7713b1edbc 1733 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
AnnaBridge 171:3a7713b1edbc 1734 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
AnnaBridge 171:3a7713b1edbc 1735 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
AnnaBridge 171:3a7713b1edbc 1736 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
AnnaBridge 171:3a7713b1edbc 1737 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
AnnaBridge 171:3a7713b1edbc 1738 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
AnnaBridge 171:3a7713b1edbc 1739 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
AnnaBridge 171:3a7713b1edbc 1740 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1741 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
AnnaBridge 171:3a7713b1edbc 1742 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
AnnaBridge 171:3a7713b1edbc 1743 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
AnnaBridge 171:3a7713b1edbc 1744 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1745 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
AnnaBridge 171:3a7713b1edbc 1746 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
AnnaBridge 171:3a7713b1edbc 1747 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
AnnaBridge 171:3a7713b1edbc 1748 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
AnnaBridge 171:3a7713b1edbc 1749 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
AnnaBridge 171:3a7713b1edbc 1750 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1751 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
AnnaBridge 171:3a7713b1edbc 1752 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1753 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
AnnaBridge 171:3a7713b1edbc 1754 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
AnnaBridge 171:3a7713b1edbc 1755 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
AnnaBridge 171:3a7713b1edbc 1756 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1757 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
AnnaBridge 171:3a7713b1edbc 1758 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
AnnaBridge 171:3a7713b1edbc 1759 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
AnnaBridge 171:3a7713b1edbc 1760 /* @brief Has FTM module(s) configuration. */
AnnaBridge 171:3a7713b1edbc 1761 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
AnnaBridge 171:3a7713b1edbc 1762 /* @brief Number of FTM modules. */
AnnaBridge 171:3a7713b1edbc 1763 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
AnnaBridge 171:3a7713b1edbc 1764 /* @brief Number of FTM triggers with selectable source. */
AnnaBridge 171:3a7713b1edbc 1765 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
AnnaBridge 171:3a7713b1edbc 1766 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
AnnaBridge 171:3a7713b1edbc 1767 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
AnnaBridge 171:3a7713b1edbc 1768 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
AnnaBridge 171:3a7713b1edbc 1769 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
AnnaBridge 171:3a7713b1edbc 1770 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1771 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
AnnaBridge 171:3a7713b1edbc 1772 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1773 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
AnnaBridge 171:3a7713b1edbc 1774 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1775 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
AnnaBridge 171:3a7713b1edbc 1776 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
AnnaBridge 171:3a7713b1edbc 1777 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
AnnaBridge 171:3a7713b1edbc 1778 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
AnnaBridge 171:3a7713b1edbc 1779 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
AnnaBridge 171:3a7713b1edbc 1780 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
AnnaBridge 171:3a7713b1edbc 1781 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 1782 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
AnnaBridge 171:3a7713b1edbc 1783 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 1784 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
AnnaBridge 171:3a7713b1edbc 1785 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
AnnaBridge 171:3a7713b1edbc 1786 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
AnnaBridge 171:3a7713b1edbc 1787 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
AnnaBridge 171:3a7713b1edbc 1788 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
AnnaBridge 171:3a7713b1edbc 1789 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
AnnaBridge 171:3a7713b1edbc 1790 /* @brief Has TPM module(s) configuration. */
AnnaBridge 171:3a7713b1edbc 1791 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
AnnaBridge 171:3a7713b1edbc 1792 /* @brief The highest TPM module index. */
AnnaBridge 171:3a7713b1edbc 1793 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
AnnaBridge 171:3a7713b1edbc 1794 /* @brief Has TPM module with index 0. */
AnnaBridge 171:3a7713b1edbc 1795 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
AnnaBridge 171:3a7713b1edbc 1796 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1797 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
AnnaBridge 171:3a7713b1edbc 1798 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
AnnaBridge 171:3a7713b1edbc 1799 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
AnnaBridge 171:3a7713b1edbc 1800 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1801 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
AnnaBridge 171:3a7713b1edbc 1802 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1803 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
AnnaBridge 171:3a7713b1edbc 1804 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1805 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1806 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
AnnaBridge 171:3a7713b1edbc 1807 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
AnnaBridge 171:3a7713b1edbc 1808 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1809 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
AnnaBridge 171:3a7713b1edbc 1810 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge 171:3a7713b1edbc 1811 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
AnnaBridge 171:3a7713b1edbc 1812 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge 171:3a7713b1edbc 1813 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
AnnaBridge 171:3a7713b1edbc 1814 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
AnnaBridge 171:3a7713b1edbc 1815 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
AnnaBridge 171:3a7713b1edbc 1816 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
AnnaBridge 171:3a7713b1edbc 1817 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
AnnaBridge 171:3a7713b1edbc 1818 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
AnnaBridge 171:3a7713b1edbc 1819 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
AnnaBridge 171:3a7713b1edbc 1820 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1821 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
AnnaBridge 171:3a7713b1edbc 1822 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
AnnaBridge 171:3a7713b1edbc 1823 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
AnnaBridge 171:3a7713b1edbc 1824 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
AnnaBridge 171:3a7713b1edbc 1825 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
AnnaBridge 171:3a7713b1edbc 1826 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
AnnaBridge 171:3a7713b1edbc 1827 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
AnnaBridge 171:3a7713b1edbc 1828 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
AnnaBridge 171:3a7713b1edbc 1829 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
AnnaBridge 171:3a7713b1edbc 1830 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
AnnaBridge 171:3a7713b1edbc 1831 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
AnnaBridge 171:3a7713b1edbc 1832 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
AnnaBridge 171:3a7713b1edbc 1833 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
AnnaBridge 171:3a7713b1edbc 1834 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
AnnaBridge 171:3a7713b1edbc 1835 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
AnnaBridge 171:3a7713b1edbc 1836 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
AnnaBridge 171:3a7713b1edbc 1837 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
AnnaBridge 171:3a7713b1edbc 1838 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
AnnaBridge 171:3a7713b1edbc 1839 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
AnnaBridge 171:3a7713b1edbc 1840 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
AnnaBridge 171:3a7713b1edbc 1841 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
AnnaBridge 171:3a7713b1edbc 1842 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
AnnaBridge 171:3a7713b1edbc 1843 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
AnnaBridge 171:3a7713b1edbc 1844 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1845 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
AnnaBridge 171:3a7713b1edbc 1846 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
AnnaBridge 171:3a7713b1edbc 1847 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
AnnaBridge 171:3a7713b1edbc 1848 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1849 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
AnnaBridge 171:3a7713b1edbc 1850 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1851 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
AnnaBridge 171:3a7713b1edbc 1852 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1853 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1854 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1855 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1856 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1857 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1858 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1859 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1860 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1861 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1862 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1863 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1864 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1865 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1866 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
AnnaBridge 171:3a7713b1edbc 1867 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
AnnaBridge 171:3a7713b1edbc 1868 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
AnnaBridge 171:3a7713b1edbc 1869 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
AnnaBridge 171:3a7713b1edbc 1870 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
AnnaBridge 171:3a7713b1edbc 1871 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
AnnaBridge 171:3a7713b1edbc 1872 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge 171:3a7713b1edbc 1873 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
AnnaBridge 171:3a7713b1edbc 1874 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge 171:3a7713b1edbc 1875 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
AnnaBridge 171:3a7713b1edbc 1876 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
AnnaBridge 171:3a7713b1edbc 1877 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
AnnaBridge 171:3a7713b1edbc 1878 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
AnnaBridge 171:3a7713b1edbc 1879 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
AnnaBridge 171:3a7713b1edbc 1880 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
AnnaBridge 171:3a7713b1edbc 1881 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
AnnaBridge 171:3a7713b1edbc 1882 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
AnnaBridge 171:3a7713b1edbc 1883 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
AnnaBridge 171:3a7713b1edbc 1884 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
AnnaBridge 171:3a7713b1edbc 1885 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
AnnaBridge 171:3a7713b1edbc 1886 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
AnnaBridge 171:3a7713b1edbc 1887 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
AnnaBridge 171:3a7713b1edbc 1888 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
AnnaBridge 171:3a7713b1edbc 1889 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
AnnaBridge 171:3a7713b1edbc 1890 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
AnnaBridge 171:3a7713b1edbc 1891 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
AnnaBridge 171:3a7713b1edbc 1892 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
AnnaBridge 171:3a7713b1edbc 1893 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
AnnaBridge 171:3a7713b1edbc 1894 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
AnnaBridge 171:3a7713b1edbc 1895 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
AnnaBridge 171:3a7713b1edbc 1896 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
AnnaBridge 171:3a7713b1edbc 1897 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
AnnaBridge 171:3a7713b1edbc 1898 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
AnnaBridge 171:3a7713b1edbc 1899 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
AnnaBridge 171:3a7713b1edbc 1900 /* @brief Has device die ID (register bit field SDID[DIEID]). */
AnnaBridge 171:3a7713b1edbc 1901 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
AnnaBridge 171:3a7713b1edbc 1902 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
AnnaBridge 171:3a7713b1edbc 1903 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
AnnaBridge 171:3a7713b1edbc 1904 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
AnnaBridge 171:3a7713b1edbc 1905 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
AnnaBridge 171:3a7713b1edbc 1906 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
AnnaBridge 171:3a7713b1edbc 1907 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
AnnaBridge 171:3a7713b1edbc 1908 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
AnnaBridge 171:3a7713b1edbc 1909 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
AnnaBridge 171:3a7713b1edbc 1910 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
AnnaBridge 171:3a7713b1edbc 1911 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
AnnaBridge 171:3a7713b1edbc 1912 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
AnnaBridge 171:3a7713b1edbc 1913 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
AnnaBridge 171:3a7713b1edbc 1914 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
AnnaBridge 171:3a7713b1edbc 1915 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
AnnaBridge 171:3a7713b1edbc 1916 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
AnnaBridge 171:3a7713b1edbc 1917 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
AnnaBridge 171:3a7713b1edbc 1918 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
AnnaBridge 171:3a7713b1edbc 1919 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
AnnaBridge 171:3a7713b1edbc 1920 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
AnnaBridge 171:3a7713b1edbc 1921 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
AnnaBridge 171:3a7713b1edbc 1922 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
AnnaBridge 171:3a7713b1edbc 1923 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
AnnaBridge 171:3a7713b1edbc 1924 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
AnnaBridge 171:3a7713b1edbc 1925 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
AnnaBridge 171:3a7713b1edbc 1926 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
AnnaBridge 171:3a7713b1edbc 1927 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
AnnaBridge 171:3a7713b1edbc 1928 /* @brief Has miscellanious control register (register MCR). */
AnnaBridge 171:3a7713b1edbc 1929 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
AnnaBridge 171:3a7713b1edbc 1930 /* @brief Has COP watchdog (registers COPC and SRVCOP). */
AnnaBridge 171:3a7713b1edbc 1931 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
AnnaBridge 171:3a7713b1edbc 1932 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
AnnaBridge 171:3a7713b1edbc 1933 #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
AnnaBridge 171:3a7713b1edbc 1934 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
AnnaBridge 171:3a7713b1edbc 1935 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
AnnaBridge 171:3a7713b1edbc 1936
AnnaBridge 171:3a7713b1edbc 1937 /* SMC module features */
AnnaBridge 171:3a7713b1edbc 1938
AnnaBridge 171:3a7713b1edbc 1939 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
AnnaBridge 171:3a7713b1edbc 1940 #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
AnnaBridge 171:3a7713b1edbc 1941 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
AnnaBridge 171:3a7713b1edbc 1942 #define FSL_FEATURE_SMC_HAS_LPOPO (0)
AnnaBridge 171:3a7713b1edbc 1943 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
AnnaBridge 171:3a7713b1edbc 1944 #define FSL_FEATURE_SMC_HAS_PORPO (1)
AnnaBridge 171:3a7713b1edbc 1945 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
AnnaBridge 171:3a7713b1edbc 1946 #define FSL_FEATURE_SMC_HAS_LPWUI (1)
AnnaBridge 171:3a7713b1edbc 1947 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
AnnaBridge 171:3a7713b1edbc 1948 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
AnnaBridge 171:3a7713b1edbc 1949 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
AnnaBridge 171:3a7713b1edbc 1950 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
AnnaBridge 171:3a7713b1edbc 1951 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
AnnaBridge 171:3a7713b1edbc 1952 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
AnnaBridge 171:3a7713b1edbc 1953 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
AnnaBridge 171:3a7713b1edbc 1954 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
AnnaBridge 171:3a7713b1edbc 1955 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
AnnaBridge 171:3a7713b1edbc 1956 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
AnnaBridge 171:3a7713b1edbc 1957 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
AnnaBridge 171:3a7713b1edbc 1958 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge 171:3a7713b1edbc 1959 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
AnnaBridge 171:3a7713b1edbc 1960 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge 171:3a7713b1edbc 1961 /* @brief Has stop submode. */
AnnaBridge 171:3a7713b1edbc 1962 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
AnnaBridge 171:3a7713b1edbc 1963 /* @brief Has stop submode 0(VLLS0). */
AnnaBridge 171:3a7713b1edbc 1964 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
AnnaBridge 171:3a7713b1edbc 1965 /* @brief Has stop submode 2(VLLS2). */
AnnaBridge 171:3a7713b1edbc 1966 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
AnnaBridge 171:3a7713b1edbc 1967 /* @brief Has SMC_PARAM. */
AnnaBridge 171:3a7713b1edbc 1968 #define FSL_FEATURE_SMC_HAS_PARAM (0)
AnnaBridge 171:3a7713b1edbc 1969 /* @brief Has SMC_VERID. */
AnnaBridge 171:3a7713b1edbc 1970 #define FSL_FEATURE_SMC_HAS_VERID (0)
AnnaBridge 171:3a7713b1edbc 1971
AnnaBridge 171:3a7713b1edbc 1972 /* DSPI module features */
AnnaBridge 171:3a7713b1edbc 1973
AnnaBridge 171:3a7713b1edbc 1974 /* @brief Receive/transmit FIFO size in number of items. */
AnnaBridge 171:3a7713b1edbc 1975 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
AnnaBridge 171:3a7713b1edbc 1976 ((x) == DSPI0 ? (4) : \
AnnaBridge 171:3a7713b1edbc 1977 ((x) == DSPI1 ? (1) : \
AnnaBridge 171:3a7713b1edbc 1978 ((x) == DSPI2 ? (1) : (-1))))
AnnaBridge 171:3a7713b1edbc 1979 /* @brief Maximum transfer data width in bits. */
AnnaBridge 171:3a7713b1edbc 1980 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
AnnaBridge 171:3a7713b1edbc 1981 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
AnnaBridge 171:3a7713b1edbc 1982 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
AnnaBridge 171:3a7713b1edbc 1983 /* @brief Number of chip select pins. */
AnnaBridge 171:3a7713b1edbc 1984 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
AnnaBridge 171:3a7713b1edbc 1985 /* @brief Has chip select strobe capability on the PCS5 pin. */
AnnaBridge 171:3a7713b1edbc 1986 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
AnnaBridge 171:3a7713b1edbc 1987 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
AnnaBridge 171:3a7713b1edbc 1988 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
AnnaBridge 171:3a7713b1edbc 1989 /* @brief Has 16-bit data transfer support. */
AnnaBridge 171:3a7713b1edbc 1990 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
AnnaBridge 171:3a7713b1edbc 1991 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 171:3a7713b1edbc 1992 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
AnnaBridge 171:3a7713b1edbc 1993 ((x) == DSPI0 ? (1) : \
AnnaBridge 171:3a7713b1edbc 1994 ((x) == DSPI1 ? (0) : \
AnnaBridge 171:3a7713b1edbc 1995 ((x) == DSPI2 ? (0) : (-1))))
AnnaBridge 171:3a7713b1edbc 1996
AnnaBridge 171:3a7713b1edbc 1997 /* SYSMPU module features */
AnnaBridge 171:3a7713b1edbc 1998
AnnaBridge 171:3a7713b1edbc 1999 /* @brief Specifies number of descriptors available. */
AnnaBridge 171:3a7713b1edbc 2000 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
AnnaBridge 171:3a7713b1edbc 2001 /* @brief Has process identifier support. */
AnnaBridge 171:3a7713b1edbc 2002 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
AnnaBridge 171:3a7713b1edbc 2003 /* @brief Total number of MPU slave. */
AnnaBridge 171:3a7713b1edbc 2004 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
AnnaBridge 171:3a7713b1edbc 2005 /* @brief Total number of MPU master. */
AnnaBridge 171:3a7713b1edbc 2006 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6)
AnnaBridge 171:3a7713b1edbc 2007
AnnaBridge 171:3a7713b1edbc 2008 /* SysTick module features */
AnnaBridge 171:3a7713b1edbc 2009
AnnaBridge 171:3a7713b1edbc 2010 /* @brief Systick has external reference clock. */
AnnaBridge 171:3a7713b1edbc 2011 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
AnnaBridge 171:3a7713b1edbc 2012 /* @brief Systick external reference clock is core clock divided by this value. */
AnnaBridge 171:3a7713b1edbc 2013 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
AnnaBridge 171:3a7713b1edbc 2014
AnnaBridge 171:3a7713b1edbc 2015 /* UART module features */
AnnaBridge 171:3a7713b1edbc 2016
AnnaBridge 171:3a7713b1edbc 2017 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge 171:3a7713b1edbc 2018 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
AnnaBridge 171:3a7713b1edbc 2019 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge 171:3a7713b1edbc 2020 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2021 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge 171:3a7713b1edbc 2022 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge 171:3a7713b1edbc 2023 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 171:3a7713b1edbc 2024 #define FSL_FEATURE_UART_HAS_FIFO (1)
AnnaBridge 171:3a7713b1edbc 2025 /* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge 171:3a7713b1edbc 2026 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2027 /* @brief Infrared (modulation) is supported. */
AnnaBridge 171:3a7713b1edbc 2028 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2029 /* @brief 2 bits long stop bit is available. */
AnnaBridge 171:3a7713b1edbc 2030 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2031 /* @brief If 10-bit mode is supported. */
AnnaBridge 171:3a7713b1edbc 2032 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2033 /* @brief Baud rate fine adjustment is available. */
AnnaBridge 171:3a7713b1edbc 2034 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2035 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge 171:3a7713b1edbc 2036 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2037 /* @brief Baud rate oversampling is available. */
AnnaBridge 171:3a7713b1edbc 2038 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2039 /* @brief Baud rate oversampling is available. */
AnnaBridge 171:3a7713b1edbc 2040 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2041 /* @brief Peripheral type. */
AnnaBridge 171:3a7713b1edbc 2042 #define FSL_FEATURE_UART_IS_SCI (0)
AnnaBridge 171:3a7713b1edbc 2043 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge 171:3a7713b1edbc 2044 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
AnnaBridge 171:3a7713b1edbc 2045 ((x) == UART0 ? (8) : \
AnnaBridge 171:3a7713b1edbc 2046 ((x) == UART1 ? (8) : \
AnnaBridge 171:3a7713b1edbc 2047 ((x) == UART2 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2048 ((x) == UART3 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2049 ((x) == UART4 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2050 ((x) == UART5 ? (1) : (-1)))))))
AnnaBridge 171:3a7713b1edbc 2051 /* @brief Maximal data width without parity bit. */
AnnaBridge 171:3a7713b1edbc 2052 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
AnnaBridge 171:3a7713b1edbc 2053 /* @brief Maximal data width with parity bit. */
AnnaBridge 171:3a7713b1edbc 2054 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
AnnaBridge 171:3a7713b1edbc 2055 /* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge 171:3a7713b1edbc 2056 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
AnnaBridge 171:3a7713b1edbc 2057 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge 171:3a7713b1edbc 2058 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
AnnaBridge 171:3a7713b1edbc 2059 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge 171:3a7713b1edbc 2060 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
AnnaBridge 171:3a7713b1edbc 2061 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge 171:3a7713b1edbc 2062 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge 171:3a7713b1edbc 2063 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge 171:3a7713b1edbc 2064 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
AnnaBridge 171:3a7713b1edbc 2065 /* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge 171:3a7713b1edbc 2066 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2067 /* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge 171:3a7713b1edbc 2068 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge 171:3a7713b1edbc 2069 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge 171:3a7713b1edbc 2070 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
AnnaBridge 171:3a7713b1edbc 2071 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
AnnaBridge 171:3a7713b1edbc 2072 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
AnnaBridge 171:3a7713b1edbc 2073 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge 171:3a7713b1edbc 2074 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
AnnaBridge 171:3a7713b1edbc 2075 /* @brief Has separate DMA RX and TX requests. */
AnnaBridge 171:3a7713b1edbc 2076 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
AnnaBridge 171:3a7713b1edbc 2077 ((x) == UART0 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2078 ((x) == UART1 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2079 ((x) == UART2 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2080 ((x) == UART3 ? (1) : \
AnnaBridge 171:3a7713b1edbc 2081 ((x) == UART4 ? (0) : \
AnnaBridge 171:3a7713b1edbc 2082 ((x) == UART5 ? (0) : (-1)))))))
AnnaBridge 171:3a7713b1edbc 2083
AnnaBridge 171:3a7713b1edbc 2084 /* USB module features */
AnnaBridge 171:3a7713b1edbc 2085
AnnaBridge 171:3a7713b1edbc 2086 /* @brief HOST mode enabled */
AnnaBridge 171:3a7713b1edbc 2087 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
AnnaBridge 171:3a7713b1edbc 2088 /* @brief OTG mode enabled */
AnnaBridge 171:3a7713b1edbc 2089 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
AnnaBridge 171:3a7713b1edbc 2090 /* @brief Size of the USB dedicated RAM */
AnnaBridge 171:3a7713b1edbc 2091 #define FSL_FEATURE_USB_KHCI_USB_RAM (0)
AnnaBridge 171:3a7713b1edbc 2092 /* @brief Has KEEP_ALIVE_CTRL register */
AnnaBridge 171:3a7713b1edbc 2093 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
AnnaBridge 171:3a7713b1edbc 2094 /* @brief Has the Dynamic SOF threshold compare support */
AnnaBridge 171:3a7713b1edbc 2095 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
AnnaBridge 171:3a7713b1edbc 2096 /* @brief Has the VBUS detect support */
AnnaBridge 171:3a7713b1edbc 2097 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
AnnaBridge 171:3a7713b1edbc 2098 /* @brief Has the IRC48M module clock support */
AnnaBridge 171:3a7713b1edbc 2099 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
AnnaBridge 171:3a7713b1edbc 2100 /* @brief Number of endpoints supported */
AnnaBridge 171:3a7713b1edbc 2101 #define FSL_FEATURE_USB_ENDPT_COUNT (16)
AnnaBridge 171:3a7713b1edbc 2102
AnnaBridge 171:3a7713b1edbc 2103 /* VREF module features */
AnnaBridge 171:3a7713b1edbc 2104
AnnaBridge 171:3a7713b1edbc 2105 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */
AnnaBridge 171:3a7713b1edbc 2106 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
AnnaBridge 171:3a7713b1edbc 2107 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
AnnaBridge 171:3a7713b1edbc 2108 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
AnnaBridge 171:3a7713b1edbc 2109 /* @brief If high/low buffer mode supported */
AnnaBridge 171:3a7713b1edbc 2110 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
AnnaBridge 171:3a7713b1edbc 2111 /* @brief Module has also low reference (registers VREFL/VREFH) */
AnnaBridge 171:3a7713b1edbc 2112 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
AnnaBridge 171:3a7713b1edbc 2113 /* @brief Has VREF_TRM4. */
AnnaBridge 171:3a7713b1edbc 2114 #define FSL_FEATURE_VREF_HAS_TRM4 (0)
AnnaBridge 171:3a7713b1edbc 2115
AnnaBridge 171:3a7713b1edbc 2116 /* WDOG module features */
AnnaBridge 171:3a7713b1edbc 2117
AnnaBridge 171:3a7713b1edbc 2118 /* @brief Watchdog is available. */
AnnaBridge 171:3a7713b1edbc 2119 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
AnnaBridge 171:3a7713b1edbc 2120 /* @brief Has Wait mode support. */
AnnaBridge 171:3a7713b1edbc 2121 #define FSL_FEATURE_WDOG_HAS_WAITEN (1)
AnnaBridge 171:3a7713b1edbc 2122
AnnaBridge 171:3a7713b1edbc 2123 #endif /* _MK64F12_FEATURES_H_ */
AnnaBridge 171:3a7713b1edbc 2124