mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F302R8/cmsis_gcc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:31:38 2017 +0100
Revision:: 145:64910690c574
Child:: 160:5571c4ff569f

Release 145 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/************************************************************************//
AnnaBridge	145:64910690c574	2	* @file cmsis_gcc.h
AnnaBridge	145:64910690c574	3	* @brief CMSIS compiler GCC header file
AnnaBridge	145:64910690c574	4	* @version V5.0.2
AnnaBridge	145:64910690c574	5	* @date 13. February 2017
AnnaBridge	145:64910690c574	6	******************************************************************************/
AnnaBridge	145:64910690c574	7	/*
AnnaBridge	145:64910690c574	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	145:64910690c574	9	*
AnnaBridge	145:64910690c574	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	145:64910690c574	11	*
AnnaBridge	145:64910690c574	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	145:64910690c574	13	* not use this file except in compliance with the License.
AnnaBridge	145:64910690c574	14	* You may obtain a copy of the License at
AnnaBridge	145:64910690c574	15	*
AnnaBridge	145:64910690c574	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	145:64910690c574	17	*
AnnaBridge	145:64910690c574	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	145:64910690c574	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	145:64910690c574	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	145:64910690c574	21	* See the License for the specific language governing permissions and
AnnaBridge	145:64910690c574	22	* limitations under the License.
AnnaBridge	145:64910690c574	23	*/
AnnaBridge	145:64910690c574	24
AnnaBridge	145:64910690c574	25	#ifndef __CMSIS_GCC_H
AnnaBridge	145:64910690c574	26	#define __CMSIS_GCC_H
AnnaBridge	145:64910690c574	27
AnnaBridge	145:64910690c574	28	/* ignore some GCC warnings */
AnnaBridge	145:64910690c574	29	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	30	#pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge	145:64910690c574	31	#pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge	145:64910690c574	32	#pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge	145:64910690c574	33
AnnaBridge	145:64910690c574	34	/* CMSIS compiler specific defines */
AnnaBridge	145:64910690c574	35	#ifndef __ASM
AnnaBridge	145:64910690c574	36	#define __ASM __asm
AnnaBridge	145:64910690c574	37	#endif
AnnaBridge	145:64910690c574	38	#ifndef __INLINE
AnnaBridge	145:64910690c574	39	#define __INLINE inline
AnnaBridge	145:64910690c574	40	#endif
AnnaBridge	145:64910690c574	41	#ifndef __STATIC_INLINE
AnnaBridge	145:64910690c574	42	#define __STATIC_INLINE static inline
AnnaBridge	145:64910690c574	43	#endif
AnnaBridge	145:64910690c574	44	#ifndef __NO_RETURN
AnnaBridge	145:64910690c574	45	#define __NO_RETURN __attribute__((noreturn))
AnnaBridge	145:64910690c574	46	#endif
AnnaBridge	145:64910690c574	47	#ifndef __USED
AnnaBridge	145:64910690c574	48	#define __USED __attribute__((used))
AnnaBridge	145:64910690c574	49	#endif
AnnaBridge	145:64910690c574	50	#ifndef __WEAK
AnnaBridge	145:64910690c574	51	#define __WEAK __attribute__((weak))
AnnaBridge	145:64910690c574	52	#endif
AnnaBridge	145:64910690c574	53	#ifndef __PACKED
AnnaBridge	145:64910690c574	54	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	145:64910690c574	55	#endif
AnnaBridge	145:64910690c574	56	#ifndef __PACKED_STRUCT
AnnaBridge	145:64910690c574	57	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	145:64910690c574	58	#endif
AnnaBridge	145:64910690c574	59	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	145:64910690c574	60	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	61	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	62	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	63	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	145:64910690c574	64	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	65	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	145:64910690c574	66	#endif
AnnaBridge	145:64910690c574	67	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	145:64910690c574	68	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	69	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	70	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	71	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	145:64910690c574	72	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	73	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	145:64910690c574	74	#endif
AnnaBridge	145:64910690c574	75	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	145:64910690c574	76	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	77	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	78	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	79	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	145:64910690c574	80	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	81	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	145:64910690c574	82	#endif
AnnaBridge	145:64910690c574	83	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	145:64910690c574	84	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	85	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	86	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	87	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	145:64910690c574	88	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	89	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	145:64910690c574	90	#endif
AnnaBridge	145:64910690c574	91	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	145:64910690c574	92	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	93	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	94	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	95	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	145:64910690c574	96	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	97	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	145:64910690c574	98	#endif
AnnaBridge	145:64910690c574	99	#ifndef __ALIGNED
AnnaBridge	145:64910690c574	100	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	145:64910690c574	101	#endif
AnnaBridge	145:64910690c574	102
AnnaBridge	145:64910690c574	103
AnnaBridge	145:64910690c574	104	/* ########################### Core Function Access ########################### */
AnnaBridge	145:64910690c574	105	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	106	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	145:64910690c574	107	@{
AnnaBridge	145:64910690c574	108	*/
AnnaBridge	145:64910690c574	109
AnnaBridge	145:64910690c574	110	/**
AnnaBridge	145:64910690c574	111	\brief Enable IRQ Interrupts
AnnaBridge	145:64910690c574	112	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	145:64910690c574	113	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	114	*/
AnnaBridge	145:64910690c574	115	__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
AnnaBridge	145:64910690c574	116	{
AnnaBridge	145:64910690c574	117	__ASM volatile ("cpsie i" : : : "memory");
AnnaBridge	145:64910690c574	118	}
AnnaBridge	145:64910690c574	119
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	/**
AnnaBridge	145:64910690c574	122	\brief Disable IRQ Interrupts
AnnaBridge	145:64910690c574	123	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	145:64910690c574	124	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	125	*/
AnnaBridge	145:64910690c574	126	__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
AnnaBridge	145:64910690c574	127	{
AnnaBridge	145:64910690c574	128	__ASM volatile ("cpsid i" : : : "memory");
AnnaBridge	145:64910690c574	129	}
AnnaBridge	145:64910690c574	130
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	/**
AnnaBridge	145:64910690c574	133	\brief Get Control Register
AnnaBridge	145:64910690c574	134	\details Returns the content of the Control Register.
AnnaBridge	145:64910690c574	135	\return Control Register value
AnnaBridge	145:64910690c574	136	*/
AnnaBridge	145:64910690c574	137	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge	145:64910690c574	138	{
AnnaBridge	145:64910690c574	139	uint32_t result;
AnnaBridge	145:64910690c574	140
AnnaBridge	145:64910690c574	141	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	145:64910690c574	142	return(result);
AnnaBridge	145:64910690c574	143	}
AnnaBridge	145:64910690c574	144
AnnaBridge	145:64910690c574	145
AnnaBridge	145:64910690c574	146	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	147	/**
AnnaBridge	145:64910690c574	148	\brief Get Control Register (non-secure)
AnnaBridge	145:64910690c574	149	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	145:64910690c574	150	\return non-secure Control Register value
AnnaBridge	145:64910690c574	151	*/
AnnaBridge	145:64910690c574	152	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	145:64910690c574	153	{
AnnaBridge	145:64910690c574	154	uint32_t result;
AnnaBridge	145:64910690c574	155
AnnaBridge	145:64910690c574	156	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	157	return(result);
AnnaBridge	145:64910690c574	158	}
AnnaBridge	145:64910690c574	159	#endif
AnnaBridge	145:64910690c574	160
AnnaBridge	145:64910690c574	161
AnnaBridge	145:64910690c574	162	/**
AnnaBridge	145:64910690c574	163	\brief Set Control Register
AnnaBridge	145:64910690c574	164	\details Writes the given value to the Control Register.
AnnaBridge	145:64910690c574	165	\param [in] control Control Register value to set
AnnaBridge	145:64910690c574	166	*/
AnnaBridge	145:64910690c574	167	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge	145:64910690c574	168	{
AnnaBridge	145:64910690c574	169	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	145:64910690c574	170	}
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172
AnnaBridge	145:64910690c574	173	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	174	/**
AnnaBridge	145:64910690c574	175	\brief Set Control Register (non-secure)
AnnaBridge	145:64910690c574	176	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	145:64910690c574	177	\param [in] control Control Register value to set
AnnaBridge	145:64910690c574	178	*/
AnnaBridge	145:64910690c574	179	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	145:64910690c574	180	{
AnnaBridge	145:64910690c574	181	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	145:64910690c574	182	}
AnnaBridge	145:64910690c574	183	#endif
AnnaBridge	145:64910690c574	184
AnnaBridge	145:64910690c574	185
AnnaBridge	145:64910690c574	186	/**
AnnaBridge	145:64910690c574	187	\brief Get IPSR Register
AnnaBridge	145:64910690c574	188	\details Returns the content of the IPSR Register.
AnnaBridge	145:64910690c574	189	\return IPSR Register value
AnnaBridge	145:64910690c574	190	*/
AnnaBridge	145:64910690c574	191	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge	145:64910690c574	192	{
AnnaBridge	145:64910690c574	193	uint32_t result;
AnnaBridge	145:64910690c574	194
AnnaBridge	145:64910690c574	195	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	145:64910690c574	196	return(result);
AnnaBridge	145:64910690c574	197	}
AnnaBridge	145:64910690c574	198
AnnaBridge	145:64910690c574	199
AnnaBridge	145:64910690c574	200	/**
AnnaBridge	145:64910690c574	201	\brief Get APSR Register
AnnaBridge	145:64910690c574	202	\details Returns the content of the APSR Register.
AnnaBridge	145:64910690c574	203	\return APSR Register value
AnnaBridge	145:64910690c574	204	*/
AnnaBridge	145:64910690c574	205	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge	145:64910690c574	206	{
AnnaBridge	145:64910690c574	207	uint32_t result;
AnnaBridge	145:64910690c574	208
AnnaBridge	145:64910690c574	209	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	145:64910690c574	210	return(result);
AnnaBridge	145:64910690c574	211	}
AnnaBridge	145:64910690c574	212
AnnaBridge	145:64910690c574	213
AnnaBridge	145:64910690c574	214	/**
AnnaBridge	145:64910690c574	215	\brief Get xPSR Register
AnnaBridge	145:64910690c574	216	\details Returns the content of the xPSR Register.
AnnaBridge	145:64910690c574	217	\return xPSR Register value
AnnaBridge	145:64910690c574	218	*/
AnnaBridge	145:64910690c574	219	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge	145:64910690c574	220	{
AnnaBridge	145:64910690c574	221	uint32_t result;
AnnaBridge	145:64910690c574	222
AnnaBridge	145:64910690c574	223	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	145:64910690c574	224	return(result);
AnnaBridge	145:64910690c574	225	}
AnnaBridge	145:64910690c574	226
AnnaBridge	145:64910690c574	227
AnnaBridge	145:64910690c574	228	/**
AnnaBridge	145:64910690c574	229	\brief Get Process Stack Pointer
AnnaBridge	145:64910690c574	230	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	145:64910690c574	231	\return PSP Register value
AnnaBridge	145:64910690c574	232	*/
AnnaBridge	145:64910690c574	233	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge	145:64910690c574	234	{
AnnaBridge	145:64910690c574	235	register uint32_t result;
AnnaBridge	145:64910690c574	236
AnnaBridge	145:64910690c574	237	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	145:64910690c574	238	return(result);
AnnaBridge	145:64910690c574	239	}
AnnaBridge	145:64910690c574	240
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	243	/**
AnnaBridge	145:64910690c574	244	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	245	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	145:64910690c574	246	\return PSP Register value
AnnaBridge	145:64910690c574	247	*/
AnnaBridge	145:64910690c574	248	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	145:64910690c574	249	{
AnnaBridge	145:64910690c574	250	register uint32_t result;
AnnaBridge	145:64910690c574	251
AnnaBridge	145:64910690c574	252	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	253	return(result);
AnnaBridge	145:64910690c574	254	}
AnnaBridge	145:64910690c574	255	#endif
AnnaBridge	145:64910690c574	256
AnnaBridge	145:64910690c574	257
AnnaBridge	145:64910690c574	258	/**
AnnaBridge	145:64910690c574	259	\brief Set Process Stack Pointer
AnnaBridge	145:64910690c574	260	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	145:64910690c574	261	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	145:64910690c574	262	*/
AnnaBridge	145:64910690c574	263	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	145:64910690c574	264	{
AnnaBridge	145:64910690c574	265	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	145:64910690c574	266	}
AnnaBridge	145:64910690c574	267
AnnaBridge	145:64910690c574	268
AnnaBridge	145:64910690c574	269	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	270	/**
AnnaBridge	145:64910690c574	271	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	272	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	145:64910690c574	273	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	145:64910690c574	274	*/
AnnaBridge	145:64910690c574	275	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	145:64910690c574	276	{
AnnaBridge	145:64910690c574	277	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	145:64910690c574	278	}
AnnaBridge	145:64910690c574	279	#endif
AnnaBridge	145:64910690c574	280
AnnaBridge	145:64910690c574	281
AnnaBridge	145:64910690c574	282	/**
AnnaBridge	145:64910690c574	283	\brief Get Main Stack Pointer
AnnaBridge	145:64910690c574	284	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	145:64910690c574	285	\return MSP Register value
AnnaBridge	145:64910690c574	286	*/
AnnaBridge	145:64910690c574	287	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge	145:64910690c574	288	{
AnnaBridge	145:64910690c574	289	register uint32_t result;
AnnaBridge	145:64910690c574	290
AnnaBridge	145:64910690c574	291	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	145:64910690c574	292	return(result);
AnnaBridge	145:64910690c574	293	}
AnnaBridge	145:64910690c574	294
AnnaBridge	145:64910690c574	295
AnnaBridge	145:64910690c574	296	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	297	/**
AnnaBridge	145:64910690c574	298	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	299	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	145:64910690c574	300	\return MSP Register value
AnnaBridge	145:64910690c574	301	*/
AnnaBridge	145:64910690c574	302	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	145:64910690c574	303	{
AnnaBridge	145:64910690c574	304	register uint32_t result;
AnnaBridge	145:64910690c574	305
AnnaBridge	145:64910690c574	306	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	307	return(result);
AnnaBridge	145:64910690c574	308	}
AnnaBridge	145:64910690c574	309	#endif
AnnaBridge	145:64910690c574	310
AnnaBridge	145:64910690c574	311
AnnaBridge	145:64910690c574	312	/**
AnnaBridge	145:64910690c574	313	\brief Set Main Stack Pointer
AnnaBridge	145:64910690c574	314	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	145:64910690c574	315	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	145:64910690c574	316	*/
AnnaBridge	145:64910690c574	317	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	145:64910690c574	318	{
AnnaBridge	145:64910690c574	319	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	145:64910690c574	320	}
AnnaBridge	145:64910690c574	321
AnnaBridge	145:64910690c574	322
AnnaBridge	145:64910690c574	323	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	324	/**
AnnaBridge	145:64910690c574	325	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	326	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	145:64910690c574	327	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	145:64910690c574	328	*/
AnnaBridge	145:64910690c574	329	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	145:64910690c574	330	{
AnnaBridge	145:64910690c574	331	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	145:64910690c574	332	}
AnnaBridge	145:64910690c574	333	#endif
AnnaBridge	145:64910690c574	334
AnnaBridge	145:64910690c574	335
AnnaBridge	145:64910690c574	336	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	337	/**
AnnaBridge	145:64910690c574	338	\brief Get Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	339	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	145:64910690c574	340	\return SP Register value
AnnaBridge	145:64910690c574	341	*/
AnnaBridge	145:64910690c574	342	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	145:64910690c574	343	{
AnnaBridge	145:64910690c574	344	register uint32_t result;
AnnaBridge	145:64910690c574	345
AnnaBridge	145:64910690c574	346	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	347	return(result);
AnnaBridge	145:64910690c574	348	}
AnnaBridge	145:64910690c574	349
AnnaBridge	145:64910690c574	350
AnnaBridge	145:64910690c574	351	/**
AnnaBridge	145:64910690c574	352	\brief Set Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	353	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	145:64910690c574	354	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	145:64910690c574	355	*/
AnnaBridge	145:64910690c574	356	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	145:64910690c574	357	{
AnnaBridge	145:64910690c574	358	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	145:64910690c574	359	}
AnnaBridge	145:64910690c574	360	#endif
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362
AnnaBridge	145:64910690c574	363	/**
AnnaBridge	145:64910690c574	364	\brief Get Priority Mask
AnnaBridge	145:64910690c574	365	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	145:64910690c574	366	\return Priority Mask value
AnnaBridge	145:64910690c574	367	*/
AnnaBridge	145:64910690c574	368	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge	145:64910690c574	369	{
AnnaBridge	145:64910690c574	370	uint32_t result;
AnnaBridge	145:64910690c574	371
AnnaBridge	145:64910690c574	372	__ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge	145:64910690c574	373	return(result);
AnnaBridge	145:64910690c574	374	}
AnnaBridge	145:64910690c574	375
AnnaBridge	145:64910690c574	376
AnnaBridge	145:64910690c574	377	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	378	/**
AnnaBridge	145:64910690c574	379	\brief Get Priority Mask (non-secure)
AnnaBridge	145:64910690c574	380	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	145:64910690c574	381	\return Priority Mask value
AnnaBridge	145:64910690c574	382	*/
AnnaBridge	145:64910690c574	383	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	145:64910690c574	384	{
AnnaBridge	145:64910690c574	385	uint32_t result;
AnnaBridge	145:64910690c574	386
AnnaBridge	145:64910690c574	387	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	388	return(result);
AnnaBridge	145:64910690c574	389	}
AnnaBridge	145:64910690c574	390	#endif
AnnaBridge	145:64910690c574	391
AnnaBridge	145:64910690c574	392
AnnaBridge	145:64910690c574	393	/**
AnnaBridge	145:64910690c574	394	\brief Set Priority Mask
AnnaBridge	145:64910690c574	395	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	145:64910690c574	396	\param [in] priMask Priority Mask
AnnaBridge	145:64910690c574	397	*/
AnnaBridge	145:64910690c574	398	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	145:64910690c574	399	{
AnnaBridge	145:64910690c574	400	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	145:64910690c574	401	}
AnnaBridge	145:64910690c574	402
AnnaBridge	145:64910690c574	403
AnnaBridge	145:64910690c574	404	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	405	/**
AnnaBridge	145:64910690c574	406	\brief Set Priority Mask (non-secure)
AnnaBridge	145:64910690c574	407	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	145:64910690c574	408	\param [in] priMask Priority Mask
AnnaBridge	145:64910690c574	409	*/
AnnaBridge	145:64910690c574	410	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	145:64910690c574	411	{
AnnaBridge	145:64910690c574	412	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	145:64910690c574	413	}
AnnaBridge	145:64910690c574	414	#endif
AnnaBridge	145:64910690c574	415
AnnaBridge	145:64910690c574	416
AnnaBridge	145:64910690c574	417	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	418	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	419	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	420	/**
AnnaBridge	145:64910690c574	421	\brief Enable FIQ
AnnaBridge	145:64910690c574	422	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	145:64910690c574	423	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	424	*/
AnnaBridge	145:64910690c574	425	__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
AnnaBridge	145:64910690c574	426	{
AnnaBridge	145:64910690c574	427	__ASM volatile ("cpsie f" : : : "memory");
AnnaBridge	145:64910690c574	428	}
AnnaBridge	145:64910690c574	429
AnnaBridge	145:64910690c574	430
AnnaBridge	145:64910690c574	431	/**
AnnaBridge	145:64910690c574	432	\brief Disable FIQ
AnnaBridge	145:64910690c574	433	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	145:64910690c574	434	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	435	*/
AnnaBridge	145:64910690c574	436	__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
AnnaBridge	145:64910690c574	437	{
AnnaBridge	145:64910690c574	438	__ASM volatile ("cpsid f" : : : "memory");
AnnaBridge	145:64910690c574	439	}
AnnaBridge	145:64910690c574	440
AnnaBridge	145:64910690c574	441
AnnaBridge	145:64910690c574	442	/**
AnnaBridge	145:64910690c574	443	\brief Get Base Priority
AnnaBridge	145:64910690c574	444	\details Returns the current value of the Base Priority register.
AnnaBridge	145:64910690c574	445	\return Base Priority register value
AnnaBridge	145:64910690c574	446	*/
AnnaBridge	145:64910690c574	447	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge	145:64910690c574	448	{
AnnaBridge	145:64910690c574	449	uint32_t result;
AnnaBridge	145:64910690c574	450
AnnaBridge	145:64910690c574	451	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	145:64910690c574	452	return(result);
AnnaBridge	145:64910690c574	453	}
AnnaBridge	145:64910690c574	454
AnnaBridge	145:64910690c574	455
AnnaBridge	145:64910690c574	456	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	457	/**
AnnaBridge	145:64910690c574	458	\brief Get Base Priority (non-secure)
AnnaBridge	145:64910690c574	459	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	145:64910690c574	460	\return Base Priority register value
AnnaBridge	145:64910690c574	461	*/
AnnaBridge	145:64910690c574	462	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	145:64910690c574	463	{
AnnaBridge	145:64910690c574	464	uint32_t result;
AnnaBridge	145:64910690c574	465
AnnaBridge	145:64910690c574	466	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	467	return(result);
AnnaBridge	145:64910690c574	468	}
AnnaBridge	145:64910690c574	469	#endif
AnnaBridge	145:64910690c574	470
AnnaBridge	145:64910690c574	471
AnnaBridge	145:64910690c574	472	/**
AnnaBridge	145:64910690c574	473	\brief Set Base Priority
AnnaBridge	145:64910690c574	474	\details Assigns the given value to the Base Priority register.
AnnaBridge	145:64910690c574	475	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	476	*/
AnnaBridge	145:64910690c574	477	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	145:64910690c574	478	{
AnnaBridge	145:64910690c574	479	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	480	}
AnnaBridge	145:64910690c574	481
AnnaBridge	145:64910690c574	482
AnnaBridge	145:64910690c574	483	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	484	/**
AnnaBridge	145:64910690c574	485	\brief Set Base Priority (non-secure)
AnnaBridge	145:64910690c574	486	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	145:64910690c574	487	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	488	*/
AnnaBridge	145:64910690c574	489	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	145:64910690c574	490	{
AnnaBridge	145:64910690c574	491	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	492	}
AnnaBridge	145:64910690c574	493	#endif
AnnaBridge	145:64910690c574	494
AnnaBridge	145:64910690c574	495
AnnaBridge	145:64910690c574	496	/**
AnnaBridge	145:64910690c574	497	\brief Set Base Priority with condition
AnnaBridge	145:64910690c574	498	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	145:64910690c574	499	or the new value increases the BASEPRI priority level.
AnnaBridge	145:64910690c574	500	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	501	*/
AnnaBridge	145:64910690c574	502	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	145:64910690c574	503	{
AnnaBridge	145:64910690c574	504	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	505	}
AnnaBridge	145:64910690c574	506
AnnaBridge	145:64910690c574	507
AnnaBridge	145:64910690c574	508	/**
AnnaBridge	145:64910690c574	509	\brief Get Fault Mask
AnnaBridge	145:64910690c574	510	\details Returns the current value of the Fault Mask register.
AnnaBridge	145:64910690c574	511	\return Fault Mask register value
AnnaBridge	145:64910690c574	512	*/
AnnaBridge	145:64910690c574	513	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	145:64910690c574	514	{
AnnaBridge	145:64910690c574	515	uint32_t result;
AnnaBridge	145:64910690c574	516
AnnaBridge	145:64910690c574	517	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	145:64910690c574	518	return(result);
AnnaBridge	145:64910690c574	519	}
AnnaBridge	145:64910690c574	520
AnnaBridge	145:64910690c574	521
AnnaBridge	145:64910690c574	522	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	523	/**
AnnaBridge	145:64910690c574	524	\brief Get Fault Mask (non-secure)
AnnaBridge	145:64910690c574	525	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	145:64910690c574	526	\return Fault Mask register value
AnnaBridge	145:64910690c574	527	*/
AnnaBridge	145:64910690c574	528	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	145:64910690c574	529	{
AnnaBridge	145:64910690c574	530	uint32_t result;
AnnaBridge	145:64910690c574	531
AnnaBridge	145:64910690c574	532	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	533	return(result);
AnnaBridge	145:64910690c574	534	}
AnnaBridge	145:64910690c574	535	#endif
AnnaBridge	145:64910690c574	536
AnnaBridge	145:64910690c574	537
AnnaBridge	145:64910690c574	538	/**
AnnaBridge	145:64910690c574	539	\brief Set Fault Mask
AnnaBridge	145:64910690c574	540	\details Assigns the given value to the Fault Mask register.
AnnaBridge	145:64910690c574	541	\param [in] faultMask Fault Mask value to set
AnnaBridge	145:64910690c574	542	*/
AnnaBridge	145:64910690c574	543	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	145:64910690c574	544	{
AnnaBridge	145:64910690c574	545	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	145:64910690c574	546	}
AnnaBridge	145:64910690c574	547
AnnaBridge	145:64910690c574	548
AnnaBridge	145:64910690c574	549	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	550	/**
AnnaBridge	145:64910690c574	551	\brief Set Fault Mask (non-secure)
AnnaBridge	145:64910690c574	552	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	145:64910690c574	553	\param [in] faultMask Fault Mask value to set
AnnaBridge	145:64910690c574	554	*/
AnnaBridge	145:64910690c574	555	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	145:64910690c574	556	{
AnnaBridge	145:64910690c574	557	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	145:64910690c574	558	}
AnnaBridge	145:64910690c574	559	#endif
AnnaBridge	145:64910690c574	560
AnnaBridge	145:64910690c574	561	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	562	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	563	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	564
AnnaBridge	145:64910690c574	565
AnnaBridge	145:64910690c574	566	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	567	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	568
AnnaBridge	145:64910690c574	569	/**
AnnaBridge	145:64910690c574	570	\brief Get Process Stack Pointer Limit
AnnaBridge	145:64910690c574	571	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	145:64910690c574	572	\return PSPLIM Register value
AnnaBridge	145:64910690c574	573	*/
AnnaBridge	145:64910690c574	574	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge	145:64910690c574	575	{
AnnaBridge	145:64910690c574	576	register uint32_t result;
AnnaBridge	145:64910690c574	577
AnnaBridge	145:64910690c574	578	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge	145:64910690c574	579	return(result);
AnnaBridge	145:64910690c574	580	}
AnnaBridge	145:64910690c574	581
AnnaBridge	145:64910690c574	582
AnnaBridge	145:64910690c574	583	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	584	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	585	/**
AnnaBridge	145:64910690c574	586	\brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	587	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	145:64910690c574	588	\return PSPLIM Register value
AnnaBridge	145:64910690c574	589	*/
AnnaBridge	145:64910690c574	590	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	145:64910690c574	591	{
AnnaBridge	145:64910690c574	592	register uint32_t result;
AnnaBridge	145:64910690c574	593
AnnaBridge	145:64910690c574	594	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	595	return(result);
AnnaBridge	145:64910690c574	596	}
AnnaBridge	145:64910690c574	597	#endif
AnnaBridge	145:64910690c574	598
AnnaBridge	145:64910690c574	599
AnnaBridge	145:64910690c574	600	/**
AnnaBridge	145:64910690c574	601	\brief Set Process Stack Pointer Limit
AnnaBridge	145:64910690c574	602	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	145:64910690c574	603	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	604	*/
AnnaBridge	145:64910690c574	605	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	145:64910690c574	606	{
AnnaBridge	145:64910690c574	607	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge	145:64910690c574	608	}
AnnaBridge	145:64910690c574	609
AnnaBridge	145:64910690c574	610
AnnaBridge	145:64910690c574	611	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	612	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	613	/**
AnnaBridge	145:64910690c574	614	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	615	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	145:64910690c574	616	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	617	*/
AnnaBridge	145:64910690c574	618	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	145:64910690c574	619	{
AnnaBridge	145:64910690c574	620	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge	145:64910690c574	621	}
AnnaBridge	145:64910690c574	622	#endif
AnnaBridge	145:64910690c574	623
AnnaBridge	145:64910690c574	624
AnnaBridge	145:64910690c574	625	/**
AnnaBridge	145:64910690c574	626	\brief Get Main Stack Pointer Limit
AnnaBridge	145:64910690c574	627	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	145:64910690c574	628	\return MSPLIM Register value
AnnaBridge	145:64910690c574	629	*/
AnnaBridge	145:64910690c574	630	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge	145:64910690c574	631	{
AnnaBridge	145:64910690c574	632	register uint32_t result;
AnnaBridge	145:64910690c574	633
AnnaBridge	145:64910690c574	634	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge	145:64910690c574	635
AnnaBridge	145:64910690c574	636	return(result);
AnnaBridge	145:64910690c574	637	}
AnnaBridge	145:64910690c574	638
AnnaBridge	145:64910690c574	639
AnnaBridge	145:64910690c574	640	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	641	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	642	/**
AnnaBridge	145:64910690c574	643	\brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	644	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	145:64910690c574	645	\return MSPLIM Register value
AnnaBridge	145:64910690c574	646	*/
AnnaBridge	145:64910690c574	647	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	145:64910690c574	648	{
AnnaBridge	145:64910690c574	649	register uint32_t result;
AnnaBridge	145:64910690c574	650
AnnaBridge	145:64910690c574	651	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	652	return(result);
AnnaBridge	145:64910690c574	653	}
AnnaBridge	145:64910690c574	654	#endif
AnnaBridge	145:64910690c574	655
AnnaBridge	145:64910690c574	656
AnnaBridge	145:64910690c574	657	/**
AnnaBridge	145:64910690c574	658	\brief Set Main Stack Pointer Limit
AnnaBridge	145:64910690c574	659	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	145:64910690c574	660	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	661	*/
AnnaBridge	145:64910690c574	662	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	145:64910690c574	663	{
AnnaBridge	145:64910690c574	664	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	145:64910690c574	665	}
AnnaBridge	145:64910690c574	666
AnnaBridge	145:64910690c574	667
AnnaBridge	145:64910690c574	668	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	669	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	670	/**
AnnaBridge	145:64910690c574	671	\brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	672	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	145:64910690c574	673	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	145:64910690c574	674	*/
AnnaBridge	145:64910690c574	675	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	145:64910690c574	676	{
AnnaBridge	145:64910690c574	677	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	145:64910690c574	678	}
AnnaBridge	145:64910690c574	679	#endif
AnnaBridge	145:64910690c574	680
AnnaBridge	145:64910690c574	681	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	682	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	683
AnnaBridge	145:64910690c574	684
AnnaBridge	145:64910690c574	685	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	686	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	687
AnnaBridge	145:64910690c574	688	/**
AnnaBridge	145:64910690c574	689	\brief Get FPSCR
AnnaBridge	145:64910690c574	690	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	145:64910690c574	691	\return Floating Point Status/Control register value
AnnaBridge	145:64910690c574	692	*/
AnnaBridge	145:64910690c574	693	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge	145:64910690c574	694	{
AnnaBridge	145:64910690c574	695	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	145:64910690c574	696	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	145:64910690c574	697	uint32_t result;
AnnaBridge	145:64910690c574	698
AnnaBridge	145:64910690c574	699	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge	145:64910690c574	700	return(result);
AnnaBridge	145:64910690c574	701	#else
AnnaBridge	145:64910690c574	702	return(0U);
AnnaBridge	145:64910690c574	703	#endif
AnnaBridge	145:64910690c574	704	}
AnnaBridge	145:64910690c574	705
AnnaBridge	145:64910690c574	706
AnnaBridge	145:64910690c574	707	/**
AnnaBridge	145:64910690c574	708	\brief Set FPSCR
AnnaBridge	145:64910690c574	709	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	145:64910690c574	710	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	145:64910690c574	711	*/
AnnaBridge	145:64910690c574	712	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge	145:64910690c574	713	{
AnnaBridge	145:64910690c574	714	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	145:64910690c574	715	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	145:64910690c574	716	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge	145:64910690c574	717	#else
AnnaBridge	145:64910690c574	718	(void)fpscr;
AnnaBridge	145:64910690c574	719	#endif
AnnaBridge	145:64910690c574	720	}
AnnaBridge	145:64910690c574	721
AnnaBridge	145:64910690c574	722	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	723	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	724
AnnaBridge	145:64910690c574	725
AnnaBridge	145:64910690c574	726
AnnaBridge	145:64910690c574	727	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	145:64910690c574	728
AnnaBridge	145:64910690c574	729
AnnaBridge	145:64910690c574	730	/* ########################## Core Instruction Access ######################### */
AnnaBridge	145:64910690c574	731	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	145:64910690c574	732	Access to dedicated instructions
AnnaBridge	145:64910690c574	733	@{
AnnaBridge	145:64910690c574	734	*/
AnnaBridge	145:64910690c574	735
AnnaBridge	145:64910690c574	736	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	145:64910690c574	737	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	145:64910690c574	738	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	145:64910690c574	739	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	145:64910690c574	740	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	145:64910690c574	741	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge	145:64910690c574	742	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	145:64910690c574	743	#else
AnnaBridge	145:64910690c574	744	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	145:64910690c574	745	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge	145:64910690c574	746	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	145:64910690c574	747	#endif
AnnaBridge	145:64910690c574	748
AnnaBridge	145:64910690c574	749	/**
AnnaBridge	145:64910690c574	750	\brief No Operation
AnnaBridge	145:64910690c574	751	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	145:64910690c574	752	*/
AnnaBridge	145:64910690c574	753	//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
AnnaBridge	145:64910690c574	754	//{
AnnaBridge	145:64910690c574	755	// __ASM volatile ("nop");
AnnaBridge	145:64910690c574	756	//}
AnnaBridge	145:64910690c574	757	#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	758
AnnaBridge	145:64910690c574	759	/**
AnnaBridge	145:64910690c574	760	\brief Wait For Interrupt
AnnaBridge	145:64910690c574	761	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	145:64910690c574	762	*/
AnnaBridge	145:64910690c574	763	//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
AnnaBridge	145:64910690c574	764	//{
AnnaBridge	145:64910690c574	765	// __ASM volatile ("wfi");
AnnaBridge	145:64910690c574	766	//}
AnnaBridge	145:64910690c574	767	#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	768
AnnaBridge	145:64910690c574	769
AnnaBridge	145:64910690c574	770	/**
AnnaBridge	145:64910690c574	771	\brief Wait For Event
AnnaBridge	145:64910690c574	772	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	145:64910690c574	773	a low-power state until one of a number of events occurs.
AnnaBridge	145:64910690c574	774	*/
AnnaBridge	145:64910690c574	775	//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
AnnaBridge	145:64910690c574	776	//{
AnnaBridge	145:64910690c574	777	// __ASM volatile ("wfe");
AnnaBridge	145:64910690c574	778	//}
AnnaBridge	145:64910690c574	779	#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	780
AnnaBridge	145:64910690c574	781
AnnaBridge	145:64910690c574	782	/**
AnnaBridge	145:64910690c574	783	\brief Send Event
AnnaBridge	145:64910690c574	784	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	145:64910690c574	785	*/
AnnaBridge	145:64910690c574	786	//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
AnnaBridge	145:64910690c574	787	//{
AnnaBridge	145:64910690c574	788	// __ASM volatile ("sev");
AnnaBridge	145:64910690c574	789	//}
AnnaBridge	145:64910690c574	790	#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	791
AnnaBridge	145:64910690c574	792
AnnaBridge	145:64910690c574	793	/**
AnnaBridge	145:64910690c574	794	\brief Instruction Synchronization Barrier
AnnaBridge	145:64910690c574	795	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	145:64910690c574	796	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	145:64910690c574	797	after the instruction has been completed.
AnnaBridge	145:64910690c574	798	*/
AnnaBridge	145:64910690c574	799	__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
AnnaBridge	145:64910690c574	800	{
AnnaBridge	145:64910690c574	801	__ASM volatile ("isb 0xF":::"memory");
AnnaBridge	145:64910690c574	802	}
AnnaBridge	145:64910690c574	803
AnnaBridge	145:64910690c574	804
AnnaBridge	145:64910690c574	805	/**
AnnaBridge	145:64910690c574	806	\brief Data Synchronization Barrier
AnnaBridge	145:64910690c574	807	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	145:64910690c574	808	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	145:64910690c574	809	*/
AnnaBridge	145:64910690c574	810	__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
AnnaBridge	145:64910690c574	811	{
AnnaBridge	145:64910690c574	812	__ASM volatile ("dsb 0xF":::"memory");
AnnaBridge	145:64910690c574	813	}
AnnaBridge	145:64910690c574	814
AnnaBridge	145:64910690c574	815
AnnaBridge	145:64910690c574	816	/**
AnnaBridge	145:64910690c574	817	\brief Data Memory Barrier
AnnaBridge	145:64910690c574	818	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	145:64910690c574	819	and after the instruction, without ensuring their completion.
AnnaBridge	145:64910690c574	820	*/
AnnaBridge	145:64910690c574	821	__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
AnnaBridge	145:64910690c574	822	{
AnnaBridge	145:64910690c574	823	__ASM volatile ("dmb 0xF":::"memory");
AnnaBridge	145:64910690c574	824	}
AnnaBridge	145:64910690c574	825
AnnaBridge	145:64910690c574	826
AnnaBridge	145:64910690c574	827	/**
AnnaBridge	145:64910690c574	828	\brief Reverse byte order (32 bit)
AnnaBridge	145:64910690c574	829	\details Reverses the byte order in integer value.
AnnaBridge	145:64910690c574	830	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	831	\return Reversed value
AnnaBridge	145:64910690c574	832	*/
AnnaBridge	145:64910690c574	833	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
AnnaBridge	145:64910690c574	834	{
AnnaBridge	145:64910690c574	835	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge	145:64910690c574	836	return __builtin_bswap32(value);
AnnaBridge	145:64910690c574	837	#else
AnnaBridge	145:64910690c574	838	uint32_t result;
AnnaBridge	145:64910690c574	839
AnnaBridge	145:64910690c574	840	__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	841	return(result);
AnnaBridge	145:64910690c574	842	#endif
AnnaBridge	145:64910690c574	843	}
AnnaBridge	145:64910690c574	844
AnnaBridge	145:64910690c574	845
AnnaBridge	145:64910690c574	846	/**
AnnaBridge	145:64910690c574	847	\brief Reverse byte order (16 bit)
AnnaBridge	145:64910690c574	848	\details Reverses the byte order in two unsigned short values.
AnnaBridge	145:64910690c574	849	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	850	\return Reversed value
AnnaBridge	145:64910690c574	851	*/
AnnaBridge	145:64910690c574	852	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge	145:64910690c574	853	{
AnnaBridge	145:64910690c574	854	uint32_t result;
AnnaBridge	145:64910690c574	855
AnnaBridge	145:64910690c574	856	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	857	return(result);
AnnaBridge	145:64910690c574	858	}
AnnaBridge	145:64910690c574	859
AnnaBridge	145:64910690c574	860
AnnaBridge	145:64910690c574	861	/**
AnnaBridge	145:64910690c574	862	\brief Reverse byte order in signed short value
AnnaBridge	145:64910690c574	863	\details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge	145:64910690c574	864	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	865	\return Reversed value
AnnaBridge	145:64910690c574	866	*/
AnnaBridge	145:64910690c574	867	__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
AnnaBridge	145:64910690c574	868	{
AnnaBridge	145:64910690c574	869	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	870	return (short)__builtin_bswap16(value);
AnnaBridge	145:64910690c574	871	#else
AnnaBridge	145:64910690c574	872	int32_t result;
AnnaBridge	145:64910690c574	873
AnnaBridge	145:64910690c574	874	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	875	return(result);
AnnaBridge	145:64910690c574	876	#endif
AnnaBridge	145:64910690c574	877	}
AnnaBridge	145:64910690c574	878
AnnaBridge	145:64910690c574	879
AnnaBridge	145:64910690c574	880	/**
AnnaBridge	145:64910690c574	881	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	145:64910690c574	882	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	145:64910690c574	883	\param [in] op1 Value to rotate
AnnaBridge	145:64910690c574	884	\param [in] op2 Number of Bits to rotate
AnnaBridge	145:64910690c574	885	\return Rotated value
AnnaBridge	145:64910690c574	886	*/
AnnaBridge	145:64910690c574	887	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	888	{
AnnaBridge	145:64910690c574	889	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	145:64910690c574	890	}
AnnaBridge	145:64910690c574	891
AnnaBridge	145:64910690c574	892
AnnaBridge	145:64910690c574	893	/**
AnnaBridge	145:64910690c574	894	\brief Breakpoint
AnnaBridge	145:64910690c574	895	\details Causes the processor to enter Debug state.
AnnaBridge	145:64910690c574	896	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	145:64910690c574	897	\param [in] value is ignored by the processor.
AnnaBridge	145:64910690c574	898	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	145:64910690c574	899	*/
AnnaBridge	145:64910690c574	900	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	145:64910690c574	901
AnnaBridge	145:64910690c574	902
AnnaBridge	145:64910690c574	903	/**
AnnaBridge	145:64910690c574	904	\brief Reverse bit order of value
AnnaBridge	145:64910690c574	905	\details Reverses the bit order of the given value.
AnnaBridge	145:64910690c574	906	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	907	\return Reversed value
AnnaBridge	145:64910690c574	908	*/
AnnaBridge	145:64910690c574	909	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge	145:64910690c574	910	{
AnnaBridge	145:64910690c574	911	uint32_t result;
AnnaBridge	145:64910690c574	912
AnnaBridge	145:64910690c574	913	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	914	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	915	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	916	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge	145:64910690c574	917	#else
AnnaBridge	145:64910690c574	918	int32_t s = (4 /sizeof(v)/ * 8) - 1; /* extra shift needed at end */
AnnaBridge	145:64910690c574	919
AnnaBridge	145:64910690c574	920	result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge	145:64910690c574	921	for (value >>= 1U; value; value >>= 1U)
AnnaBridge	145:64910690c574	922	{
AnnaBridge	145:64910690c574	923	result <<= 1U;
AnnaBridge	145:64910690c574	924	result \|= value & 1U;
AnnaBridge	145:64910690c574	925	s--;
AnnaBridge	145:64910690c574	926	}
AnnaBridge	145:64910690c574	927	result <<= s; /* shift when v's highest bits are zero */
AnnaBridge	145:64910690c574	928	#endif
AnnaBridge	145:64910690c574	929	return(result);
AnnaBridge	145:64910690c574	930	}
AnnaBridge	145:64910690c574	931
AnnaBridge	145:64910690c574	932
AnnaBridge	145:64910690c574	933	/**
AnnaBridge	145:64910690c574	934	\brief Count leading zeros
AnnaBridge	145:64910690c574	935	\details Counts the number of leading zeros of a data value.
AnnaBridge	145:64910690c574	936	\param [in] value Value to count the leading zeros
AnnaBridge	145:64910690c574	937	\return number of leading zeros in value
AnnaBridge	145:64910690c574	938	*/
AnnaBridge	145:64910690c574	939	#define __CLZ __builtin_clz
AnnaBridge	145:64910690c574	940
AnnaBridge	145:64910690c574	941
AnnaBridge	145:64910690c574	942	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	943	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	944	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	945	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	946	/**
AnnaBridge	145:64910690c574	947	\brief LDR Exclusive (8 bit)
AnnaBridge	145:64910690c574	948	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	145:64910690c574	949	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	950	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	951	*/
AnnaBridge	145:64910690c574	952	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge	145:64910690c574	953	{
AnnaBridge	145:64910690c574	954	uint32_t result;
AnnaBridge	145:64910690c574	955
AnnaBridge	145:64910690c574	956	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	957	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	958	#else
AnnaBridge	145:64910690c574	959	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	960	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	961	*/
AnnaBridge	145:64910690c574	962	__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	145:64910690c574	963	#endif
AnnaBridge	145:64910690c574	964	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	965	}
AnnaBridge	145:64910690c574	966
AnnaBridge	145:64910690c574	967
AnnaBridge	145:64910690c574	968	/**
AnnaBridge	145:64910690c574	969	\brief LDR Exclusive (16 bit)
AnnaBridge	145:64910690c574	970	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	145:64910690c574	971	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	972	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	973	*/
AnnaBridge	145:64910690c574	974	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge	145:64910690c574	975	{
AnnaBridge	145:64910690c574	976	uint32_t result;
AnnaBridge	145:64910690c574	977
AnnaBridge	145:64910690c574	978	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	979	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	980	#else
AnnaBridge	145:64910690c574	981	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	982	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	983	*/
AnnaBridge	145:64910690c574	984	__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	145:64910690c574	985	#endif
AnnaBridge	145:64910690c574	986	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	987	}
AnnaBridge	145:64910690c574	988
AnnaBridge	145:64910690c574	989
AnnaBridge	145:64910690c574	990	/**
AnnaBridge	145:64910690c574	991	\brief LDR Exclusive (32 bit)
AnnaBridge	145:64910690c574	992	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	145:64910690c574	993	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	994	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	995	*/
AnnaBridge	145:64910690c574	996	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge	145:64910690c574	997	{
AnnaBridge	145:64910690c574	998	uint32_t result;
AnnaBridge	145:64910690c574	999
AnnaBridge	145:64910690c574	1000	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	1001	return(result);
AnnaBridge	145:64910690c574	1002	}
AnnaBridge	145:64910690c574	1003
AnnaBridge	145:64910690c574	1004
AnnaBridge	145:64910690c574	1005	/**
AnnaBridge	145:64910690c574	1006	\brief STR Exclusive (8 bit)
AnnaBridge	145:64910690c574	1007	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	145:64910690c574	1008	\param [in] value Value to store
AnnaBridge	145:64910690c574	1009	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1010	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1011	\return 1 Function failed
AnnaBridge	145:64910690c574	1012	*/
AnnaBridge	145:64910690c574	1013	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge	145:64910690c574	1014	{
AnnaBridge	145:64910690c574	1015	uint32_t result;
AnnaBridge	145:64910690c574	1016
AnnaBridge	145:64910690c574	1017	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1018	return(result);
AnnaBridge	145:64910690c574	1019	}
AnnaBridge	145:64910690c574	1020
AnnaBridge	145:64910690c574	1021
AnnaBridge	145:64910690c574	1022	/**
AnnaBridge	145:64910690c574	1023	\brief STR Exclusive (16 bit)
AnnaBridge	145:64910690c574	1024	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	145:64910690c574	1025	\param [in] value Value to store
AnnaBridge	145:64910690c574	1026	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1027	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1028	\return 1 Function failed
AnnaBridge	145:64910690c574	1029	*/
AnnaBridge	145:64910690c574	1030	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge	145:64910690c574	1031	{
AnnaBridge	145:64910690c574	1032	uint32_t result;
AnnaBridge	145:64910690c574	1033
AnnaBridge	145:64910690c574	1034	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1035	return(result);
AnnaBridge	145:64910690c574	1036	}
AnnaBridge	145:64910690c574	1037
AnnaBridge	145:64910690c574	1038
AnnaBridge	145:64910690c574	1039	/**
AnnaBridge	145:64910690c574	1040	\brief STR Exclusive (32 bit)
AnnaBridge	145:64910690c574	1041	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	145:64910690c574	1042	\param [in] value Value to store
AnnaBridge	145:64910690c574	1043	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1044	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1045	\return 1 Function failed
AnnaBridge	145:64910690c574	1046	*/
AnnaBridge	145:64910690c574	1047	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge	145:64910690c574	1048	{
AnnaBridge	145:64910690c574	1049	uint32_t result;
AnnaBridge	145:64910690c574	1050
AnnaBridge	145:64910690c574	1051	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge	145:64910690c574	1052	return(result);
AnnaBridge	145:64910690c574	1053	}
AnnaBridge	145:64910690c574	1054
AnnaBridge	145:64910690c574	1055
AnnaBridge	145:64910690c574	1056	/**
AnnaBridge	145:64910690c574	1057	\brief Remove the exclusive lock
AnnaBridge	145:64910690c574	1058	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	145:64910690c574	1059	*/
AnnaBridge	145:64910690c574	1060	__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
AnnaBridge	145:64910690c574	1061	{
AnnaBridge	145:64910690c574	1062	__ASM volatile ("clrex" ::: "memory");
AnnaBridge	145:64910690c574	1063	}
AnnaBridge	145:64910690c574	1064
AnnaBridge	145:64910690c574	1065	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1066	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1067	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1068	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	1069
AnnaBridge	145:64910690c574	1070
AnnaBridge	145:64910690c574	1071	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1072	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1073	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	1074	/**
AnnaBridge	145:64910690c574	1075	\brief Signed Saturate
AnnaBridge	145:64910690c574	1076	\details Saturates a signed value.
AnnaBridge	145:64910690c574	1077	\param [in] value Value to be saturated
AnnaBridge	145:64910690c574	1078	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	145:64910690c574	1079	\return Saturated value
AnnaBridge	145:64910690c574	1080	*/
AnnaBridge	145:64910690c574	1081	#define __SSAT(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1082	({ \
AnnaBridge	145:64910690c574	1083	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1084	__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1085	__RES; \
AnnaBridge	145:64910690c574	1086	})
AnnaBridge	145:64910690c574	1087
AnnaBridge	145:64910690c574	1088
AnnaBridge	145:64910690c574	1089	/**
AnnaBridge	145:64910690c574	1090	\brief Unsigned Saturate
AnnaBridge	145:64910690c574	1091	\details Saturates an unsigned value.
AnnaBridge	145:64910690c574	1092	\param [in] value Value to be saturated
AnnaBridge	145:64910690c574	1093	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	145:64910690c574	1094	\return Saturated value
AnnaBridge	145:64910690c574	1095	*/
AnnaBridge	145:64910690c574	1096	#define __USAT(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1097	({ \
AnnaBridge	145:64910690c574	1098	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1099	__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1100	__RES; \
AnnaBridge	145:64910690c574	1101	})
AnnaBridge	145:64910690c574	1102
AnnaBridge	145:64910690c574	1103
AnnaBridge	145:64910690c574	1104	/**
AnnaBridge	145:64910690c574	1105	\brief Rotate Right with Extend (32 bit)
AnnaBridge	145:64910690c574	1106	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	145:64910690c574	1107	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	145:64910690c574	1108	\param [in] value Value to rotate
AnnaBridge	145:64910690c574	1109	\return Rotated value
AnnaBridge	145:64910690c574	1110	*/
AnnaBridge	145:64910690c574	1111	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge	145:64910690c574	1112	{
AnnaBridge	145:64910690c574	1113	uint32_t result;
AnnaBridge	145:64910690c574	1114
AnnaBridge	145:64910690c574	1115	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	1116	return(result);
AnnaBridge	145:64910690c574	1117	}
AnnaBridge	145:64910690c574	1118
AnnaBridge	145:64910690c574	1119
AnnaBridge	145:64910690c574	1120	/**
AnnaBridge	145:64910690c574	1121	\brief LDRT Unprivileged (8 bit)
AnnaBridge	145:64910690c574	1122	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	145:64910690c574	1123	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1124	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1125	*/
AnnaBridge	145:64910690c574	1126	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1127	{
AnnaBridge	145:64910690c574	1128	uint32_t result;
AnnaBridge	145:64910690c574	1129
AnnaBridge	145:64910690c574	1130	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	1131	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1132	#else
AnnaBridge	145:64910690c574	1133	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	1134	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	1135	*/
AnnaBridge	145:64910690c574	1136	__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	145:64910690c574	1137	#endif
AnnaBridge	145:64910690c574	1138	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	1139	}
AnnaBridge	145:64910690c574	1140
AnnaBridge	145:64910690c574	1141
AnnaBridge	145:64910690c574	1142	/**
AnnaBridge	145:64910690c574	1143	\brief LDRT Unprivileged (16 bit)
AnnaBridge	145:64910690c574	1144	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	145:64910690c574	1145	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1146	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1147	*/
AnnaBridge	145:64910690c574	1148	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1149	{
AnnaBridge	145:64910690c574	1150	uint32_t result;
AnnaBridge	145:64910690c574	1151
AnnaBridge	145:64910690c574	1152	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	1153	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1154	#else
AnnaBridge	145:64910690c574	1155	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	1156	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	1157	*/
AnnaBridge	145:64910690c574	1158	__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	145:64910690c574	1159	#endif
AnnaBridge	145:64910690c574	1160	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	1161	}
AnnaBridge	145:64910690c574	1162
AnnaBridge	145:64910690c574	1163
AnnaBridge	145:64910690c574	1164	/**
AnnaBridge	145:64910690c574	1165	\brief LDRT Unprivileged (32 bit)
AnnaBridge	145:64910690c574	1166	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	145:64910690c574	1167	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1168	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1169	*/
AnnaBridge	145:64910690c574	1170	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1171	{
AnnaBridge	145:64910690c574	1172	uint32_t result;
AnnaBridge	145:64910690c574	1173
AnnaBridge	145:64910690c574	1174	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1175	return(result);
AnnaBridge	145:64910690c574	1176	}
AnnaBridge	145:64910690c574	1177
AnnaBridge	145:64910690c574	1178
AnnaBridge	145:64910690c574	1179	/**
AnnaBridge	145:64910690c574	1180	\brief STRT Unprivileged (8 bit)
AnnaBridge	145:64910690c574	1181	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	145:64910690c574	1182	\param [in] value Value to store
AnnaBridge	145:64910690c574	1183	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1184	*/
AnnaBridge	145:64910690c574	1185	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1186	{
AnnaBridge	145:64910690c574	1187	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1188	}
AnnaBridge	145:64910690c574	1189
AnnaBridge	145:64910690c574	1190
AnnaBridge	145:64910690c574	1191	/**
AnnaBridge	145:64910690c574	1192	\brief STRT Unprivileged (16 bit)
AnnaBridge	145:64910690c574	1193	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	145:64910690c574	1194	\param [in] value Value to store
AnnaBridge	145:64910690c574	1195	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1196	*/
AnnaBridge	145:64910690c574	1197	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1198	{
AnnaBridge	145:64910690c574	1199	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1200	}
AnnaBridge	145:64910690c574	1201
AnnaBridge	145:64910690c574	1202
AnnaBridge	145:64910690c574	1203	/**
AnnaBridge	145:64910690c574	1204	\brief STRT Unprivileged (32 bit)
AnnaBridge	145:64910690c574	1205	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	145:64910690c574	1206	\param [in] value Value to store
AnnaBridge	145:64910690c574	1207	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1208	*/
AnnaBridge	145:64910690c574	1209	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1210	{
AnnaBridge	145:64910690c574	1211	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	145:64910690c574	1212	}
AnnaBridge	145:64910690c574	1213
AnnaBridge	145:64910690c574	1214	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1215	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1216	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	1217
AnnaBridge	145:64910690c574	1218
AnnaBridge	145:64910690c574	1219	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1220	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	1221	/**
AnnaBridge	145:64910690c574	1222	\brief Load-Acquire (8 bit)
AnnaBridge	145:64910690c574	1223	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	145:64910690c574	1224	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1225	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1226	*/
AnnaBridge	145:64910690c574	1227	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1228	{
AnnaBridge	145:64910690c574	1229	uint32_t result;
AnnaBridge	145:64910690c574	1230
AnnaBridge	145:64910690c574	1231	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1232	return ((uint8_t) result);
AnnaBridge	145:64910690c574	1233	}
AnnaBridge	145:64910690c574	1234
AnnaBridge	145:64910690c574	1235
AnnaBridge	145:64910690c574	1236	/**
AnnaBridge	145:64910690c574	1237	\brief Load-Acquire (16 bit)
AnnaBridge	145:64910690c574	1238	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	145:64910690c574	1239	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1240	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1241	*/
AnnaBridge	145:64910690c574	1242	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1243	{
AnnaBridge	145:64910690c574	1244	uint32_t result;
AnnaBridge	145:64910690c574	1245
AnnaBridge	145:64910690c574	1246	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1247	return ((uint16_t) result);
AnnaBridge	145:64910690c574	1248	}
AnnaBridge	145:64910690c574	1249
AnnaBridge	145:64910690c574	1250
AnnaBridge	145:64910690c574	1251	/**
AnnaBridge	145:64910690c574	1252	\brief Load-Acquire (32 bit)
AnnaBridge	145:64910690c574	1253	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	145:64910690c574	1254	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1255	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1256	*/
AnnaBridge	145:64910690c574	1257	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1258	{
AnnaBridge	145:64910690c574	1259	uint32_t result;
AnnaBridge	145:64910690c574	1260
AnnaBridge	145:64910690c574	1261	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1262	return(result);
AnnaBridge	145:64910690c574	1263	}
AnnaBridge	145:64910690c574	1264
AnnaBridge	145:64910690c574	1265
AnnaBridge	145:64910690c574	1266	/**
AnnaBridge	145:64910690c574	1267	\brief Store-Release (8 bit)
AnnaBridge	145:64910690c574	1268	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	145:64910690c574	1269	\param [in] value Value to store
AnnaBridge	145:64910690c574	1270	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1271	*/
AnnaBridge	145:64910690c574	1272	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1273	{
AnnaBridge	145:64910690c574	1274	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1275	}
AnnaBridge	145:64910690c574	1276
AnnaBridge	145:64910690c574	1277
AnnaBridge	145:64910690c574	1278	/**
AnnaBridge	145:64910690c574	1279	\brief Store-Release (16 bit)
AnnaBridge	145:64910690c574	1280	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	145:64910690c574	1281	\param [in] value Value to store
AnnaBridge	145:64910690c574	1282	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1283	*/
AnnaBridge	145:64910690c574	1284	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1285	{
AnnaBridge	145:64910690c574	1286	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1287	}
AnnaBridge	145:64910690c574	1288
AnnaBridge	145:64910690c574	1289
AnnaBridge	145:64910690c574	1290	/**
AnnaBridge	145:64910690c574	1291	\brief Store-Release (32 bit)
AnnaBridge	145:64910690c574	1292	\details Executes a STL instruction for 32 bit values.
AnnaBridge	145:64910690c574	1293	\param [in] value Value to store
AnnaBridge	145:64910690c574	1294	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1295	*/
AnnaBridge	145:64910690c574	1296	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1297	{
AnnaBridge	145:64910690c574	1298	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1299	}
AnnaBridge	145:64910690c574	1300
AnnaBridge	145:64910690c574	1301
AnnaBridge	145:64910690c574	1302	/**
AnnaBridge	145:64910690c574	1303	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	145:64910690c574	1304	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	145:64910690c574	1305	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1306	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1307	*/
AnnaBridge	145:64910690c574	1308	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1309	{
AnnaBridge	145:64910690c574	1310	uint32_t result;
AnnaBridge	145:64910690c574	1311
AnnaBridge	145:64910690c574	1312	__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1313	return ((uint8_t) result);
AnnaBridge	145:64910690c574	1314	}
AnnaBridge	145:64910690c574	1315
AnnaBridge	145:64910690c574	1316
AnnaBridge	145:64910690c574	1317	/**
AnnaBridge	145:64910690c574	1318	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	145:64910690c574	1319	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	145:64910690c574	1320	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1321	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1322	*/
AnnaBridge	145:64910690c574	1323	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1324	{
AnnaBridge	145:64910690c574	1325	uint32_t result;
AnnaBridge	145:64910690c574	1326
AnnaBridge	145:64910690c574	1327	__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1328	return ((uint16_t) result);
AnnaBridge	145:64910690c574	1329	}
AnnaBridge	145:64910690c574	1330
AnnaBridge	145:64910690c574	1331
AnnaBridge	145:64910690c574	1332	/**
AnnaBridge	145:64910690c574	1333	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	145:64910690c574	1334	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	145:64910690c574	1335	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1336	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1337	*/
AnnaBridge	145:64910690c574	1338	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1339	{
AnnaBridge	145:64910690c574	1340	uint32_t result;
AnnaBridge	145:64910690c574	1341
AnnaBridge	145:64910690c574	1342	__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1343	return(result);
AnnaBridge	145:64910690c574	1344	}
AnnaBridge	145:64910690c574	1345
AnnaBridge	145:64910690c574	1346
AnnaBridge	145:64910690c574	1347	/**
AnnaBridge	145:64910690c574	1348	\brief Store-Release Exclusive (8 bit)
AnnaBridge	145:64910690c574	1349	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	145:64910690c574	1350	\param [in] value Value to store
AnnaBridge	145:64910690c574	1351	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1352	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1353	\return 1 Function failed
AnnaBridge	145:64910690c574	1354	*/
AnnaBridge	145:64910690c574	1355	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1356	{
AnnaBridge	145:64910690c574	1357	uint32_t result;
AnnaBridge	145:64910690c574	1358
AnnaBridge	145:64910690c574	1359	__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1360	return(result);
AnnaBridge	145:64910690c574	1361	}
AnnaBridge	145:64910690c574	1362
AnnaBridge	145:64910690c574	1363
AnnaBridge	145:64910690c574	1364	/**
AnnaBridge	145:64910690c574	1365	\brief Store-Release Exclusive (16 bit)
AnnaBridge	145:64910690c574	1366	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	145:64910690c574	1367	\param [in] value Value to store
AnnaBridge	145:64910690c574	1368	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1369	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1370	\return 1 Function failed
AnnaBridge	145:64910690c574	1371	*/
AnnaBridge	145:64910690c574	1372	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1373	{
AnnaBridge	145:64910690c574	1374	uint32_t result;
AnnaBridge	145:64910690c574	1375
AnnaBridge	145:64910690c574	1376	__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1377	return(result);
AnnaBridge	145:64910690c574	1378	}
AnnaBridge	145:64910690c574	1379
AnnaBridge	145:64910690c574	1380
AnnaBridge	145:64910690c574	1381	/**
AnnaBridge	145:64910690c574	1382	\brief Store-Release Exclusive (32 bit)
AnnaBridge	145:64910690c574	1383	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	145:64910690c574	1384	\param [in] value Value to store
AnnaBridge	145:64910690c574	1385	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1386	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1387	\return 1 Function failed
AnnaBridge	145:64910690c574	1388	*/
AnnaBridge	145:64910690c574	1389	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1390	{
AnnaBridge	145:64910690c574	1391	uint32_t result;
AnnaBridge	145:64910690c574	1392
AnnaBridge	145:64910690c574	1393	__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1394	return(result);
AnnaBridge	145:64910690c574	1395	}
AnnaBridge	145:64910690c574	1396
AnnaBridge	145:64910690c574	1397	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1398	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	1399
AnnaBridge	145:64910690c574	1400	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	145:64910690c574	1401
AnnaBridge	145:64910690c574	1402
AnnaBridge	145:64910690c574	1403	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	145:64910690c574	1404	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	145:64910690c574	1405	Access to dedicated SIMD instructions
AnnaBridge	145:64910690c574	1406	@{
AnnaBridge	145:64910690c574	1407	*/
AnnaBridge	145:64910690c574	1408
AnnaBridge	145:64910690c574	1409	#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
AnnaBridge	145:64910690c574	1410
AnnaBridge	145:64910690c574	1411	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1412	{
AnnaBridge	145:64910690c574	1413	uint32_t result;
AnnaBridge	145:64910690c574	1414
AnnaBridge	145:64910690c574	1415	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1416	return(result);
AnnaBridge	145:64910690c574	1417	}
AnnaBridge	145:64910690c574	1418
AnnaBridge	145:64910690c574	1419	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1420	{
AnnaBridge	145:64910690c574	1421	uint32_t result;
AnnaBridge	145:64910690c574	1422
AnnaBridge	145:64910690c574	1423	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1424	return(result);
AnnaBridge	145:64910690c574	1425	}
AnnaBridge	145:64910690c574	1426
AnnaBridge	145:64910690c574	1427	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1428	{
AnnaBridge	145:64910690c574	1429	uint32_t result;
AnnaBridge	145:64910690c574	1430
AnnaBridge	145:64910690c574	1431	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1432	return(result);
AnnaBridge	145:64910690c574	1433	}
AnnaBridge	145:64910690c574	1434
AnnaBridge	145:64910690c574	1435	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1436	{
AnnaBridge	145:64910690c574	1437	uint32_t result;
AnnaBridge	145:64910690c574	1438
AnnaBridge	145:64910690c574	1439	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1440	return(result);
AnnaBridge	145:64910690c574	1441	}
AnnaBridge	145:64910690c574	1442
AnnaBridge	145:64910690c574	1443	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1444	{
AnnaBridge	145:64910690c574	1445	uint32_t result;
AnnaBridge	145:64910690c574	1446
AnnaBridge	145:64910690c574	1447	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1448	return(result);
AnnaBridge	145:64910690c574	1449	}
AnnaBridge	145:64910690c574	1450
AnnaBridge	145:64910690c574	1451	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1452	{
AnnaBridge	145:64910690c574	1453	uint32_t result;
AnnaBridge	145:64910690c574	1454
AnnaBridge	145:64910690c574	1455	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1456	return(result);
AnnaBridge	145:64910690c574	1457	}
AnnaBridge	145:64910690c574	1458
AnnaBridge	145:64910690c574	1459
AnnaBridge	145:64910690c574	1460	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1461	{
AnnaBridge	145:64910690c574	1462	uint32_t result;
AnnaBridge	145:64910690c574	1463
AnnaBridge	145:64910690c574	1464	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1465	return(result);
AnnaBridge	145:64910690c574	1466	}
AnnaBridge	145:64910690c574	1467
AnnaBridge	145:64910690c574	1468	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1469	{
AnnaBridge	145:64910690c574	1470	uint32_t result;
AnnaBridge	145:64910690c574	1471
AnnaBridge	145:64910690c574	1472	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1473	return(result);
AnnaBridge	145:64910690c574	1474	}
AnnaBridge	145:64910690c574	1475
AnnaBridge	145:64910690c574	1476	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1477	{
AnnaBridge	145:64910690c574	1478	uint32_t result;
AnnaBridge	145:64910690c574	1479
AnnaBridge	145:64910690c574	1480	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1481	return(result);
AnnaBridge	145:64910690c574	1482	}
AnnaBridge	145:64910690c574	1483
AnnaBridge	145:64910690c574	1484	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1485	{
AnnaBridge	145:64910690c574	1486	uint32_t result;
AnnaBridge	145:64910690c574	1487
AnnaBridge	145:64910690c574	1488	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1489	return(result);
AnnaBridge	145:64910690c574	1490	}
AnnaBridge	145:64910690c574	1491
AnnaBridge	145:64910690c574	1492	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1493	{
AnnaBridge	145:64910690c574	1494	uint32_t result;
AnnaBridge	145:64910690c574	1495
AnnaBridge	145:64910690c574	1496	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1497	return(result);
AnnaBridge	145:64910690c574	1498	}
AnnaBridge	145:64910690c574	1499
AnnaBridge	145:64910690c574	1500	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1501	{
AnnaBridge	145:64910690c574	1502	uint32_t result;
AnnaBridge	145:64910690c574	1503
AnnaBridge	145:64910690c574	1504	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1505	return(result);
AnnaBridge	145:64910690c574	1506	}
AnnaBridge	145:64910690c574	1507
AnnaBridge	145:64910690c574	1508
AnnaBridge	145:64910690c574	1509	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1510	{
AnnaBridge	145:64910690c574	1511	uint32_t result;
AnnaBridge	145:64910690c574	1512
AnnaBridge	145:64910690c574	1513	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1514	return(result);
AnnaBridge	145:64910690c574	1515	}
AnnaBridge	145:64910690c574	1516
AnnaBridge	145:64910690c574	1517	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1518	{
AnnaBridge	145:64910690c574	1519	uint32_t result;
AnnaBridge	145:64910690c574	1520
AnnaBridge	145:64910690c574	1521	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1522	return(result);
AnnaBridge	145:64910690c574	1523	}
AnnaBridge	145:64910690c574	1524
AnnaBridge	145:64910690c574	1525	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1526	{
AnnaBridge	145:64910690c574	1527	uint32_t result;
AnnaBridge	145:64910690c574	1528
AnnaBridge	145:64910690c574	1529	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1530	return(result);
AnnaBridge	145:64910690c574	1531	}
AnnaBridge	145:64910690c574	1532
AnnaBridge	145:64910690c574	1533	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1534	{
AnnaBridge	145:64910690c574	1535	uint32_t result;
AnnaBridge	145:64910690c574	1536
AnnaBridge	145:64910690c574	1537	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1538	return(result);
AnnaBridge	145:64910690c574	1539	}
AnnaBridge	145:64910690c574	1540
AnnaBridge	145:64910690c574	1541	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1542	{
AnnaBridge	145:64910690c574	1543	uint32_t result;
AnnaBridge	145:64910690c574	1544
AnnaBridge	145:64910690c574	1545	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1546	return(result);
AnnaBridge	145:64910690c574	1547	}
AnnaBridge	145:64910690c574	1548
AnnaBridge	145:64910690c574	1549	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1550	{
AnnaBridge	145:64910690c574	1551	uint32_t result;
AnnaBridge	145:64910690c574	1552
AnnaBridge	145:64910690c574	1553	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1554	return(result);
AnnaBridge	145:64910690c574	1555	}
AnnaBridge	145:64910690c574	1556
AnnaBridge	145:64910690c574	1557	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1558	{
AnnaBridge	145:64910690c574	1559	uint32_t result;
AnnaBridge	145:64910690c574	1560
AnnaBridge	145:64910690c574	1561	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1562	return(result);
AnnaBridge	145:64910690c574	1563	}
AnnaBridge	145:64910690c574	1564
AnnaBridge	145:64910690c574	1565	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1566	{
AnnaBridge	145:64910690c574	1567	uint32_t result;
AnnaBridge	145:64910690c574	1568
AnnaBridge	145:64910690c574	1569	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1570	return(result);
AnnaBridge	145:64910690c574	1571	}
AnnaBridge	145:64910690c574	1572
AnnaBridge	145:64910690c574	1573	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1574	{
AnnaBridge	145:64910690c574	1575	uint32_t result;
AnnaBridge	145:64910690c574	1576
AnnaBridge	145:64910690c574	1577	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1578	return(result);
AnnaBridge	145:64910690c574	1579	}
AnnaBridge	145:64910690c574	1580
AnnaBridge	145:64910690c574	1581	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1582	{
AnnaBridge	145:64910690c574	1583	uint32_t result;
AnnaBridge	145:64910690c574	1584
AnnaBridge	145:64910690c574	1585	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1586	return(result);
AnnaBridge	145:64910690c574	1587	}
AnnaBridge	145:64910690c574	1588
AnnaBridge	145:64910690c574	1589	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1590	{
AnnaBridge	145:64910690c574	1591	uint32_t result;
AnnaBridge	145:64910690c574	1592
AnnaBridge	145:64910690c574	1593	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1594	return(result);
AnnaBridge	145:64910690c574	1595	}
AnnaBridge	145:64910690c574	1596
AnnaBridge	145:64910690c574	1597	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1598	{
AnnaBridge	145:64910690c574	1599	uint32_t result;
AnnaBridge	145:64910690c574	1600
AnnaBridge	145:64910690c574	1601	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1602	return(result);
AnnaBridge	145:64910690c574	1603	}
AnnaBridge	145:64910690c574	1604
AnnaBridge	145:64910690c574	1605	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1606	{
AnnaBridge	145:64910690c574	1607	uint32_t result;
AnnaBridge	145:64910690c574	1608
AnnaBridge	145:64910690c574	1609	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1610	return(result);
AnnaBridge	145:64910690c574	1611	}
AnnaBridge	145:64910690c574	1612
AnnaBridge	145:64910690c574	1613	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1614	{
AnnaBridge	145:64910690c574	1615	uint32_t result;
AnnaBridge	145:64910690c574	1616
AnnaBridge	145:64910690c574	1617	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1618	return(result);
AnnaBridge	145:64910690c574	1619	}
AnnaBridge	145:64910690c574	1620
AnnaBridge	145:64910690c574	1621	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1622	{
AnnaBridge	145:64910690c574	1623	uint32_t result;
AnnaBridge	145:64910690c574	1624
AnnaBridge	145:64910690c574	1625	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1626	return(result);
AnnaBridge	145:64910690c574	1627	}
AnnaBridge	145:64910690c574	1628
AnnaBridge	145:64910690c574	1629	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1630	{
AnnaBridge	145:64910690c574	1631	uint32_t result;
AnnaBridge	145:64910690c574	1632
AnnaBridge	145:64910690c574	1633	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1634	return(result);
AnnaBridge	145:64910690c574	1635	}
AnnaBridge	145:64910690c574	1636
AnnaBridge	145:64910690c574	1637	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1638	{
AnnaBridge	145:64910690c574	1639	uint32_t result;
AnnaBridge	145:64910690c574	1640
AnnaBridge	145:64910690c574	1641	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1642	return(result);
AnnaBridge	145:64910690c574	1643	}
AnnaBridge	145:64910690c574	1644
AnnaBridge	145:64910690c574	1645	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1646	{
AnnaBridge	145:64910690c574	1647	uint32_t result;
AnnaBridge	145:64910690c574	1648
AnnaBridge	145:64910690c574	1649	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1650	return(result);
AnnaBridge	145:64910690c574	1651	}
AnnaBridge	145:64910690c574	1652
AnnaBridge	145:64910690c574	1653	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1654	{
AnnaBridge	145:64910690c574	1655	uint32_t result;
AnnaBridge	145:64910690c574	1656
AnnaBridge	145:64910690c574	1657	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1658	return(result);
AnnaBridge	145:64910690c574	1659	}
AnnaBridge	145:64910690c574	1660
AnnaBridge	145:64910690c574	1661	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1662	{
AnnaBridge	145:64910690c574	1663	uint32_t result;
AnnaBridge	145:64910690c574	1664
AnnaBridge	145:64910690c574	1665	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1666	return(result);
AnnaBridge	145:64910690c574	1667	}
AnnaBridge	145:64910690c574	1668
AnnaBridge	145:64910690c574	1669	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1670	{
AnnaBridge	145:64910690c574	1671	uint32_t result;
AnnaBridge	145:64910690c574	1672
AnnaBridge	145:64910690c574	1673	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1674	return(result);
AnnaBridge	145:64910690c574	1675	}
AnnaBridge	145:64910690c574	1676
AnnaBridge	145:64910690c574	1677	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1678	{
AnnaBridge	145:64910690c574	1679	uint32_t result;
AnnaBridge	145:64910690c574	1680
AnnaBridge	145:64910690c574	1681	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1682	return(result);
AnnaBridge	145:64910690c574	1683	}
AnnaBridge	145:64910690c574	1684
AnnaBridge	145:64910690c574	1685	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1686	{
AnnaBridge	145:64910690c574	1687	uint32_t result;
AnnaBridge	145:64910690c574	1688
AnnaBridge	145:64910690c574	1689	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1690	return(result);
AnnaBridge	145:64910690c574	1691	}
AnnaBridge	145:64910690c574	1692
AnnaBridge	145:64910690c574	1693	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1694	{
AnnaBridge	145:64910690c574	1695	uint32_t result;
AnnaBridge	145:64910690c574	1696
AnnaBridge	145:64910690c574	1697	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1698	return(result);
AnnaBridge	145:64910690c574	1699	}
AnnaBridge	145:64910690c574	1700
AnnaBridge	145:64910690c574	1701	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1702	{
AnnaBridge	145:64910690c574	1703	uint32_t result;
AnnaBridge	145:64910690c574	1704
AnnaBridge	145:64910690c574	1705	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1706	return(result);
AnnaBridge	145:64910690c574	1707	}
AnnaBridge	145:64910690c574	1708
AnnaBridge	145:64910690c574	1709	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1710	{
AnnaBridge	145:64910690c574	1711	uint32_t result;
AnnaBridge	145:64910690c574	1712
AnnaBridge	145:64910690c574	1713	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1714	return(result);
AnnaBridge	145:64910690c574	1715	}
AnnaBridge	145:64910690c574	1716
AnnaBridge	145:64910690c574	1717	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1718	({ \
AnnaBridge	145:64910690c574	1719	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1720	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1721	__RES; \
AnnaBridge	145:64910690c574	1722	})
AnnaBridge	145:64910690c574	1723
AnnaBridge	145:64910690c574	1724	#define __USAT16(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1725	({ \
AnnaBridge	145:64910690c574	1726	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1727	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1728	__RES; \
AnnaBridge	145:64910690c574	1729	})
AnnaBridge	145:64910690c574	1730
AnnaBridge	145:64910690c574	1731	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	145:64910690c574	1732	{
AnnaBridge	145:64910690c574	1733	uint32_t result;
AnnaBridge	145:64910690c574	1734
AnnaBridge	145:64910690c574	1735	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	145:64910690c574	1736	return(result);
AnnaBridge	145:64910690c574	1737	}
AnnaBridge	145:64910690c574	1738
AnnaBridge	145:64910690c574	1739	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1740	{
AnnaBridge	145:64910690c574	1741	uint32_t result;
AnnaBridge	145:64910690c574	1742
AnnaBridge	145:64910690c574	1743	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1744	return(result);
AnnaBridge	145:64910690c574	1745	}
AnnaBridge	145:64910690c574	1746
AnnaBridge	145:64910690c574	1747	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	145:64910690c574	1748	{
AnnaBridge	145:64910690c574	1749	uint32_t result;
AnnaBridge	145:64910690c574	1750
AnnaBridge	145:64910690c574	1751	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	145:64910690c574	1752	return(result);
AnnaBridge	145:64910690c574	1753	}
AnnaBridge	145:64910690c574	1754
AnnaBridge	145:64910690c574	1755	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1756	{
AnnaBridge	145:64910690c574	1757	uint32_t result;
AnnaBridge	145:64910690c574	1758
AnnaBridge	145:64910690c574	1759	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1760	return(result);
AnnaBridge	145:64910690c574	1761	}
AnnaBridge	145:64910690c574	1762
AnnaBridge	145:64910690c574	1763	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1764	{
AnnaBridge	145:64910690c574	1765	uint32_t result;
AnnaBridge	145:64910690c574	1766
AnnaBridge	145:64910690c574	1767	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1768	return(result);
AnnaBridge	145:64910690c574	1769	}
AnnaBridge	145:64910690c574	1770
AnnaBridge	145:64910690c574	1771	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1772	{
AnnaBridge	145:64910690c574	1773	uint32_t result;
AnnaBridge	145:64910690c574	1774
AnnaBridge	145:64910690c574	1775	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1776	return(result);
AnnaBridge	145:64910690c574	1777	}
AnnaBridge	145:64910690c574	1778
AnnaBridge	145:64910690c574	1779	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1780	{
AnnaBridge	145:64910690c574	1781	uint32_t result;
AnnaBridge	145:64910690c574	1782
AnnaBridge	145:64910690c574	1783	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1784	return(result);
AnnaBridge	145:64910690c574	1785	}
AnnaBridge	145:64910690c574	1786
AnnaBridge	145:64910690c574	1787	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1788	{
AnnaBridge	145:64910690c574	1789	uint32_t result;
AnnaBridge	145:64910690c574	1790
AnnaBridge	145:64910690c574	1791	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1792	return(result);
AnnaBridge	145:64910690c574	1793	}
AnnaBridge	145:64910690c574	1794
AnnaBridge	145:64910690c574	1795	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1796	{
AnnaBridge	145:64910690c574	1797	union llreg_u{
AnnaBridge	145:64910690c574	1798	uint32_t w32[2];
AnnaBridge	145:64910690c574	1799	uint64_t w64;
AnnaBridge	145:64910690c574	1800	} llr;
AnnaBridge	145:64910690c574	1801	llr.w64 = acc;
AnnaBridge	145:64910690c574	1802
AnnaBridge	145:64910690c574	1803	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1804	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1805	#else /* Big endian */
AnnaBridge	145:64910690c574	1806	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1807	#endif
AnnaBridge	145:64910690c574	1808
AnnaBridge	145:64910690c574	1809	return(llr.w64);
AnnaBridge	145:64910690c574	1810	}
AnnaBridge	145:64910690c574	1811
AnnaBridge	145:64910690c574	1812	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1813	{
AnnaBridge	145:64910690c574	1814	union llreg_u{
AnnaBridge	145:64910690c574	1815	uint32_t w32[2];
AnnaBridge	145:64910690c574	1816	uint64_t w64;
AnnaBridge	145:64910690c574	1817	} llr;
AnnaBridge	145:64910690c574	1818	llr.w64 = acc;
AnnaBridge	145:64910690c574	1819
AnnaBridge	145:64910690c574	1820	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1821	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1822	#else /* Big endian */
AnnaBridge	145:64910690c574	1823	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1824	#endif
AnnaBridge	145:64910690c574	1825
AnnaBridge	145:64910690c574	1826	return(llr.w64);
AnnaBridge	145:64910690c574	1827	}
AnnaBridge	145:64910690c574	1828
AnnaBridge	145:64910690c574	1829	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1830	{
AnnaBridge	145:64910690c574	1831	uint32_t result;
AnnaBridge	145:64910690c574	1832
AnnaBridge	145:64910690c574	1833	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1834	return(result);
AnnaBridge	145:64910690c574	1835	}
AnnaBridge	145:64910690c574	1836
AnnaBridge	145:64910690c574	1837	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1838	{
AnnaBridge	145:64910690c574	1839	uint32_t result;
AnnaBridge	145:64910690c574	1840
AnnaBridge	145:64910690c574	1841	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1842	return(result);
AnnaBridge	145:64910690c574	1843	}
AnnaBridge	145:64910690c574	1844
AnnaBridge	145:64910690c574	1845	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1846	{
AnnaBridge	145:64910690c574	1847	uint32_t result;
AnnaBridge	145:64910690c574	1848
AnnaBridge	145:64910690c574	1849	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1850	return(result);
AnnaBridge	145:64910690c574	1851	}
AnnaBridge	145:64910690c574	1852
AnnaBridge	145:64910690c574	1853	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1854	{
AnnaBridge	145:64910690c574	1855	uint32_t result;
AnnaBridge	145:64910690c574	1856
AnnaBridge	145:64910690c574	1857	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1858	return(result);
AnnaBridge	145:64910690c574	1859	}
AnnaBridge	145:64910690c574	1860
AnnaBridge	145:64910690c574	1861	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1862	{
AnnaBridge	145:64910690c574	1863	union llreg_u{
AnnaBridge	145:64910690c574	1864	uint32_t w32[2];
AnnaBridge	145:64910690c574	1865	uint64_t w64;
AnnaBridge	145:64910690c574	1866	} llr;
AnnaBridge	145:64910690c574	1867	llr.w64 = acc;
AnnaBridge	145:64910690c574	1868
AnnaBridge	145:64910690c574	1869	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1870	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1871	#else /* Big endian */
AnnaBridge	145:64910690c574	1872	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1873	#endif
AnnaBridge	145:64910690c574	1874
AnnaBridge	145:64910690c574	1875	return(llr.w64);
AnnaBridge	145:64910690c574	1876	}
AnnaBridge	145:64910690c574	1877
AnnaBridge	145:64910690c574	1878	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1879	{
AnnaBridge	145:64910690c574	1880	union llreg_u{
AnnaBridge	145:64910690c574	1881	uint32_t w32[2];
AnnaBridge	145:64910690c574	1882	uint64_t w64;
AnnaBridge	145:64910690c574	1883	} llr;
AnnaBridge	145:64910690c574	1884	llr.w64 = acc;
AnnaBridge	145:64910690c574	1885
AnnaBridge	145:64910690c574	1886	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1887	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1888	#else /* Big endian */
AnnaBridge	145:64910690c574	1889	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1890	#endif
AnnaBridge	145:64910690c574	1891
AnnaBridge	145:64910690c574	1892	return(llr.w64);
AnnaBridge	145:64910690c574	1893	}
AnnaBridge	145:64910690c574	1894
AnnaBridge	145:64910690c574	1895	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1896	{
AnnaBridge	145:64910690c574	1897	uint32_t result;
AnnaBridge	145:64910690c574	1898
AnnaBridge	145:64910690c574	1899	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1900	return(result);
AnnaBridge	145:64910690c574	1901	}
AnnaBridge	145:64910690c574	1902
AnnaBridge	145:64910690c574	1903	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	145:64910690c574	1904	{
AnnaBridge	145:64910690c574	1905	int32_t result;
AnnaBridge	145:64910690c574	1906
AnnaBridge	145:64910690c574	1907	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1908	return(result);
AnnaBridge	145:64910690c574	1909	}
AnnaBridge	145:64910690c574	1910
AnnaBridge	145:64910690c574	1911	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	145:64910690c574	1912	{
AnnaBridge	145:64910690c574	1913	int32_t result;
AnnaBridge	145:64910690c574	1914
AnnaBridge	145:64910690c574	1915	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1916	return(result);
AnnaBridge	145:64910690c574	1917	}
AnnaBridge	145:64910690c574	1918
AnnaBridge	145:64910690c574	1919	#if 0
AnnaBridge	145:64910690c574	1920	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	145:64910690c574	1921	({ \
AnnaBridge	145:64910690c574	1922	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	145:64910690c574	1923	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	145:64910690c574	1924	__RES; \
AnnaBridge	145:64910690c574	1925	})
AnnaBridge	145:64910690c574	1926
AnnaBridge	145:64910690c574	1927	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	145:64910690c574	1928	({ \
AnnaBridge	145:64910690c574	1929	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	145:64910690c574	1930	if (ARG3 == 0) \
AnnaBridge	145:64910690c574	1931	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	145:64910690c574	1932	else \
AnnaBridge	145:64910690c574	1933	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	145:64910690c574	1934	__RES; \
AnnaBridge	145:64910690c574	1935	})
AnnaBridge	145:64910690c574	1936	#endif
AnnaBridge	145:64910690c574	1937
AnnaBridge	145:64910690c574	1938	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	145:64910690c574	1939	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	145:64910690c574	1940
AnnaBridge	145:64910690c574	1941	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	145:64910690c574	1942	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	145:64910690c574	1943
AnnaBridge	145:64910690c574	1944	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	145:64910690c574	1945	{
AnnaBridge	145:64910690c574	1946	int32_t result;
AnnaBridge	145:64910690c574	1947
AnnaBridge	145:64910690c574	1948	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1949	return(result);
AnnaBridge	145:64910690c574	1950	}
AnnaBridge	145:64910690c574	1951
AnnaBridge	145:64910690c574	1952	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	145:64910690c574	1953	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	145:64910690c574	1954
AnnaBridge	145:64910690c574	1955
AnnaBridge	145:64910690c574	1956	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	1957
AnnaBridge	145:64910690c574	1958	#endif /* __CMSIS_GCC_H */