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TARGET_NRF51_DK/cmsis_armclang.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Child:
160:5571c4ff569f
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**************************************************************************//**
AnnaBridge 145:64910690c574 2 * @file cmsis_armclang.h
AnnaBridge 145:64910690c574 3 * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
AnnaBridge 145:64910690c574 4 * @version V5.0.3
AnnaBridge 145:64910690c574 5 * @date 27. March 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 145:64910690c574 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 145:64910690c574 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
AnnaBridge 145:64910690c574 24
AnnaBridge 145:64910690c574 25 //lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn
AnnaBridge 145:64910690c574 26
AnnaBridge 145:64910690c574 27 #ifndef __CMSIS_ARMCLANG_H
AnnaBridge 145:64910690c574 28 #define __CMSIS_ARMCLANG_H
AnnaBridge 145:64910690c574 29
AnnaBridge 145:64910690c574 30 #ifndef __ARM_COMPAT_H
AnnaBridge 145:64910690c574 31 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
AnnaBridge 145:64910690c574 32 #endif
AnnaBridge 145:64910690c574 33
AnnaBridge 145:64910690c574 34 /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 35 #ifndef __ASM
AnnaBridge 145:64910690c574 36 #define __ASM __asm
AnnaBridge 145:64910690c574 37 #endif
AnnaBridge 145:64910690c574 38 #ifndef __INLINE
AnnaBridge 145:64910690c574 39 #define __INLINE __inline
AnnaBridge 145:64910690c574 40 #endif
AnnaBridge 145:64910690c574 41 #ifndef __STATIC_INLINE
AnnaBridge 145:64910690c574 42 #define __STATIC_INLINE static __inline
AnnaBridge 145:64910690c574 43 #endif
AnnaBridge 145:64910690c574 44 #ifndef __NO_RETURN
AnnaBridge 145:64910690c574 45 #define __NO_RETURN __attribute__((noreturn))
AnnaBridge 145:64910690c574 46 #endif
AnnaBridge 145:64910690c574 47 #ifndef __USED
AnnaBridge 145:64910690c574 48 #define __USED __attribute__((used))
AnnaBridge 145:64910690c574 49 #endif
AnnaBridge 145:64910690c574 50 #ifndef __WEAK
AnnaBridge 145:64910690c574 51 #define __WEAK __attribute__((weak))
AnnaBridge 145:64910690c574 52 #endif
AnnaBridge 145:64910690c574 53 #ifndef __PACKED
AnnaBridge 145:64910690c574 54 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 145:64910690c574 55 #endif
AnnaBridge 145:64910690c574 56 #ifndef __PACKED_STRUCT
AnnaBridge 145:64910690c574 57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 145:64910690c574 58 #endif
AnnaBridge 145:64910690c574 59 #ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge 145:64910690c574 60 #pragma clang diagnostic push
AnnaBridge 145:64910690c574 61 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 145:64910690c574 62 //lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32
AnnaBridge 145:64910690c574 63 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge 145:64910690c574 64 #pragma clang diagnostic pop
AnnaBridge 145:64910690c574 65 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge 145:64910690c574 66 #endif
AnnaBridge 145:64910690c574 67 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 145:64910690c574 68 #pragma clang diagnostic push
AnnaBridge 145:64910690c574 69 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 145:64910690c574 70 //lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE
AnnaBridge 145:64910690c574 71 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 145:64910690c574 72 #pragma clang diagnostic pop
AnnaBridge 145:64910690c574 73 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 145:64910690c574 74 #endif
AnnaBridge 145:64910690c574 75 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 145:64910690c574 76 #pragma clang diagnostic push
AnnaBridge 145:64910690c574 77 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 145:64910690c574 78 //lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ
AnnaBridge 145:64910690c574 79 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 145:64910690c574 80 #pragma clang diagnostic pop
AnnaBridge 145:64910690c574 81 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 145:64910690c574 82 #endif
AnnaBridge 145:64910690c574 83 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 145:64910690c574 84 #pragma clang diagnostic push
AnnaBridge 145:64910690c574 85 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 145:64910690c574 86 //lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE
AnnaBridge 145:64910690c574 87 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 145:64910690c574 88 #pragma clang diagnostic pop
AnnaBridge 145:64910690c574 89 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 145:64910690c574 90 #endif
AnnaBridge 145:64910690c574 91 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 145:64910690c574 92 #pragma clang diagnostic push
AnnaBridge 145:64910690c574 93 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 145:64910690c574 94 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 145:64910690c574 95 #pragma clang diagnostic pop
AnnaBridge 145:64910690c574 96 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 145:64910690c574 97 #endif
AnnaBridge 145:64910690c574 98 #ifndef __ALIGNED
AnnaBridge 145:64910690c574 99 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 145:64910690c574 100 #endif
AnnaBridge 145:64910690c574 101
AnnaBridge 145:64910690c574 102
AnnaBridge 145:64910690c574 103 /* ########################### Core Function Access ########################### */
AnnaBridge 145:64910690c574 104 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 105 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 145:64910690c574 106 @{
AnnaBridge 145:64910690c574 107 */
AnnaBridge 145:64910690c574 108
AnnaBridge 145:64910690c574 109 /**
AnnaBridge 145:64910690c574 110 \brief Enable IRQ Interrupts
AnnaBridge 145:64910690c574 111 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 145:64910690c574 112 Can only be executed in Privileged modes.
AnnaBridge 145:64910690c574 113 */
AnnaBridge 145:64910690c574 114 /* intrinsic void __enable_irq(); see arm_compat.h */
AnnaBridge 145:64910690c574 115
AnnaBridge 145:64910690c574 116
AnnaBridge 145:64910690c574 117 /**
AnnaBridge 145:64910690c574 118 \brief Disable IRQ Interrupts
AnnaBridge 145:64910690c574 119 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 145:64910690c574 120 Can only be executed in Privileged modes.
AnnaBridge 145:64910690c574 121 */
AnnaBridge 145:64910690c574 122 /* intrinsic void __disable_irq(); see arm_compat.h */
AnnaBridge 145:64910690c574 123
AnnaBridge 145:64910690c574 124
AnnaBridge 145:64910690c574 125 /**
AnnaBridge 145:64910690c574 126 \brief Get Control Register
AnnaBridge 145:64910690c574 127 \details Returns the content of the Control Register.
AnnaBridge 145:64910690c574 128 \return Control Register value
AnnaBridge 145:64910690c574 129 */
AnnaBridge 145:64910690c574 130 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge 145:64910690c574 131 {
AnnaBridge 145:64910690c574 132 uint32_t result;
AnnaBridge 145:64910690c574 133
AnnaBridge 145:64910690c574 134 __ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge 145:64910690c574 135 return(result);
AnnaBridge 145:64910690c574 136 }
AnnaBridge 145:64910690c574 137
AnnaBridge 145:64910690c574 138
AnnaBridge 145:64910690c574 139 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 140 /**
AnnaBridge 145:64910690c574 141 \brief Get Control Register (non-secure)
AnnaBridge 145:64910690c574 142 \details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge 145:64910690c574 143 \return non-secure Control Register value
AnnaBridge 145:64910690c574 144 */
AnnaBridge 145:64910690c574 145 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge 145:64910690c574 146 {
AnnaBridge 145:64910690c574 147 uint32_t result;
AnnaBridge 145:64910690c574 148
AnnaBridge 145:64910690c574 149 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 150 return(result);
AnnaBridge 145:64910690c574 151 }
AnnaBridge 145:64910690c574 152 #endif
AnnaBridge 145:64910690c574 153
AnnaBridge 145:64910690c574 154
AnnaBridge 145:64910690c574 155 /**
AnnaBridge 145:64910690c574 156 \brief Set Control Register
AnnaBridge 145:64910690c574 157 \details Writes the given value to the Control Register.
AnnaBridge 145:64910690c574 158 \param [in] control Control Register value to set
AnnaBridge 145:64910690c574 159 */
AnnaBridge 145:64910690c574 160 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge 145:64910690c574 161 {
AnnaBridge 145:64910690c574 162 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge 145:64910690c574 163 }
AnnaBridge 145:64910690c574 164
AnnaBridge 145:64910690c574 165
AnnaBridge 145:64910690c574 166 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 167 /**
AnnaBridge 145:64910690c574 168 \brief Set Control Register (non-secure)
AnnaBridge 145:64910690c574 169 \details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge 145:64910690c574 170 \param [in] control Control Register value to set
AnnaBridge 145:64910690c574 171 */
AnnaBridge 145:64910690c574 172 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge 145:64910690c574 173 {
AnnaBridge 145:64910690c574 174 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge 145:64910690c574 175 }
AnnaBridge 145:64910690c574 176 #endif
AnnaBridge 145:64910690c574 177
AnnaBridge 145:64910690c574 178
AnnaBridge 145:64910690c574 179 /**
AnnaBridge 145:64910690c574 180 \brief Get IPSR Register
AnnaBridge 145:64910690c574 181 \details Returns the content of the IPSR Register.
AnnaBridge 145:64910690c574 182 \return IPSR Register value
AnnaBridge 145:64910690c574 183 */
AnnaBridge 145:64910690c574 184 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge 145:64910690c574 185 {
AnnaBridge 145:64910690c574 186 uint32_t result;
AnnaBridge 145:64910690c574 187
AnnaBridge 145:64910690c574 188 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge 145:64910690c574 189 return(result);
AnnaBridge 145:64910690c574 190 }
AnnaBridge 145:64910690c574 191
AnnaBridge 145:64910690c574 192
AnnaBridge 145:64910690c574 193 /**
AnnaBridge 145:64910690c574 194 \brief Get APSR Register
AnnaBridge 145:64910690c574 195 \details Returns the content of the APSR Register.
AnnaBridge 145:64910690c574 196 \return APSR Register value
AnnaBridge 145:64910690c574 197 */
AnnaBridge 145:64910690c574 198 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 145:64910690c574 199 {
AnnaBridge 145:64910690c574 200 uint32_t result;
AnnaBridge 145:64910690c574 201
AnnaBridge 145:64910690c574 202 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge 145:64910690c574 203 return(result);
AnnaBridge 145:64910690c574 204 }
AnnaBridge 145:64910690c574 205
AnnaBridge 145:64910690c574 206
AnnaBridge 145:64910690c574 207 /**
AnnaBridge 145:64910690c574 208 \brief Get xPSR Register
AnnaBridge 145:64910690c574 209 \details Returns the content of the xPSR Register.
AnnaBridge 145:64910690c574 210 \return xPSR Register value
AnnaBridge 145:64910690c574 211 */
AnnaBridge 145:64910690c574 212 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge 145:64910690c574 213 {
AnnaBridge 145:64910690c574 214 uint32_t result;
AnnaBridge 145:64910690c574 215
AnnaBridge 145:64910690c574 216 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge 145:64910690c574 217 return(result);
AnnaBridge 145:64910690c574 218 }
AnnaBridge 145:64910690c574 219
AnnaBridge 145:64910690c574 220
AnnaBridge 145:64910690c574 221 /**
AnnaBridge 145:64910690c574 222 \brief Get Process Stack Pointer
AnnaBridge 145:64910690c574 223 \details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge 145:64910690c574 224 \return PSP Register value
AnnaBridge 145:64910690c574 225 */
AnnaBridge 145:64910690c574 226 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge 145:64910690c574 227 {
AnnaBridge 145:64910690c574 228 register uint32_t result;
AnnaBridge 145:64910690c574 229
AnnaBridge 145:64910690c574 230 __ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge 145:64910690c574 231 return(result);
AnnaBridge 145:64910690c574 232 }
AnnaBridge 145:64910690c574 233
AnnaBridge 145:64910690c574 234
AnnaBridge 145:64910690c574 235 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 236 /**
AnnaBridge 145:64910690c574 237 \brief Get Process Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 238 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 145:64910690c574 239 \return PSP Register value
AnnaBridge 145:64910690c574 240 */
AnnaBridge 145:64910690c574 241 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge 145:64910690c574 242 {
AnnaBridge 145:64910690c574 243 register uint32_t result;
AnnaBridge 145:64910690c574 244
AnnaBridge 145:64910690c574 245 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 246 return(result);
AnnaBridge 145:64910690c574 247 }
AnnaBridge 145:64910690c574 248 #endif
AnnaBridge 145:64910690c574 249
AnnaBridge 145:64910690c574 250
AnnaBridge 145:64910690c574 251 /**
AnnaBridge 145:64910690c574 252 \brief Set Process Stack Pointer
AnnaBridge 145:64910690c574 253 \details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge 145:64910690c574 254 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 145:64910690c574 255 */
AnnaBridge 145:64910690c574 256 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 145:64910690c574 257 {
AnnaBridge 145:64910690c574 258 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge 145:64910690c574 259 }
AnnaBridge 145:64910690c574 260
AnnaBridge 145:64910690c574 261
AnnaBridge 145:64910690c574 262 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 263 /**
AnnaBridge 145:64910690c574 264 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 265 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 145:64910690c574 266 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 145:64910690c574 267 */
AnnaBridge 145:64910690c574 268 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge 145:64910690c574 269 {
AnnaBridge 145:64910690c574 270 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge 145:64910690c574 271 }
AnnaBridge 145:64910690c574 272 #endif
AnnaBridge 145:64910690c574 273
AnnaBridge 145:64910690c574 274
AnnaBridge 145:64910690c574 275 /**
AnnaBridge 145:64910690c574 276 \brief Get Main Stack Pointer
AnnaBridge 145:64910690c574 277 \details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge 145:64910690c574 278 \return MSP Register value
AnnaBridge 145:64910690c574 279 */
AnnaBridge 145:64910690c574 280 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge 145:64910690c574 281 {
AnnaBridge 145:64910690c574 282 register uint32_t result;
AnnaBridge 145:64910690c574 283
AnnaBridge 145:64910690c574 284 __ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge 145:64910690c574 285 return(result);
AnnaBridge 145:64910690c574 286 }
AnnaBridge 145:64910690c574 287
AnnaBridge 145:64910690c574 288
AnnaBridge 145:64910690c574 289 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 290 /**
AnnaBridge 145:64910690c574 291 \brief Get Main Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 292 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 145:64910690c574 293 \return MSP Register value
AnnaBridge 145:64910690c574 294 */
AnnaBridge 145:64910690c574 295 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge 145:64910690c574 296 {
AnnaBridge 145:64910690c574 297 register uint32_t result;
AnnaBridge 145:64910690c574 298
AnnaBridge 145:64910690c574 299 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 300 return(result);
AnnaBridge 145:64910690c574 301 }
AnnaBridge 145:64910690c574 302 #endif
AnnaBridge 145:64910690c574 303
AnnaBridge 145:64910690c574 304
AnnaBridge 145:64910690c574 305 /**
AnnaBridge 145:64910690c574 306 \brief Set Main Stack Pointer
AnnaBridge 145:64910690c574 307 \details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge 145:64910690c574 308 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 145:64910690c574 309 */
AnnaBridge 145:64910690c574 310 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge 145:64910690c574 311 {
AnnaBridge 145:64910690c574 312 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge 145:64910690c574 313 }
AnnaBridge 145:64910690c574 314
AnnaBridge 145:64910690c574 315
AnnaBridge 145:64910690c574 316 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 317 /**
AnnaBridge 145:64910690c574 318 \brief Set Main Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 319 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 145:64910690c574 320 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 145:64910690c574 321 */
AnnaBridge 145:64910690c574 322 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge 145:64910690c574 323 {
AnnaBridge 145:64910690c574 324 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge 145:64910690c574 325 }
AnnaBridge 145:64910690c574 326 #endif
AnnaBridge 145:64910690c574 327
AnnaBridge 145:64910690c574 328
AnnaBridge 145:64910690c574 329 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 330 /**
AnnaBridge 145:64910690c574 331 \brief Get Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 332 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 145:64910690c574 333 \return SP Register value
AnnaBridge 145:64910690c574 334 */
AnnaBridge 145:64910690c574 335 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge 145:64910690c574 336 {
AnnaBridge 145:64910690c574 337 register uint32_t result;
AnnaBridge 145:64910690c574 338
AnnaBridge 145:64910690c574 339 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 340 return(result);
AnnaBridge 145:64910690c574 341 }
AnnaBridge 145:64910690c574 342
AnnaBridge 145:64910690c574 343
AnnaBridge 145:64910690c574 344 /**
AnnaBridge 145:64910690c574 345 \brief Set Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 346 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 145:64910690c574 347 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 145:64910690c574 348 */
AnnaBridge 145:64910690c574 349 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge 145:64910690c574 350 {
AnnaBridge 145:64910690c574 351 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge 145:64910690c574 352 }
AnnaBridge 145:64910690c574 353 #endif
AnnaBridge 145:64910690c574 354
AnnaBridge 145:64910690c574 355
AnnaBridge 145:64910690c574 356 /**
AnnaBridge 145:64910690c574 357 \brief Get Priority Mask
AnnaBridge 145:64910690c574 358 \details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge 145:64910690c574 359 \return Priority Mask value
AnnaBridge 145:64910690c574 360 */
AnnaBridge 145:64910690c574 361 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge 145:64910690c574 362 {
AnnaBridge 145:64910690c574 363 uint32_t result;
AnnaBridge 145:64910690c574 364
AnnaBridge 145:64910690c574 365 __ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge 145:64910690c574 366 return(result);
AnnaBridge 145:64910690c574 367 }
AnnaBridge 145:64910690c574 368
AnnaBridge 145:64910690c574 369
AnnaBridge 145:64910690c574 370 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 371 /**
AnnaBridge 145:64910690c574 372 \brief Get Priority Mask (non-secure)
AnnaBridge 145:64910690c574 373 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge 145:64910690c574 374 \return Priority Mask value
AnnaBridge 145:64910690c574 375 */
AnnaBridge 145:64910690c574 376 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge 145:64910690c574 377 {
AnnaBridge 145:64910690c574 378 uint32_t result;
AnnaBridge 145:64910690c574 379
AnnaBridge 145:64910690c574 380 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 381 return(result);
AnnaBridge 145:64910690c574 382 }
AnnaBridge 145:64910690c574 383 #endif
AnnaBridge 145:64910690c574 384
AnnaBridge 145:64910690c574 385
AnnaBridge 145:64910690c574 386 /**
AnnaBridge 145:64910690c574 387 \brief Set Priority Mask
AnnaBridge 145:64910690c574 388 \details Assigns the given value to the Priority Mask Register.
AnnaBridge 145:64910690c574 389 \param [in] priMask Priority Mask
AnnaBridge 145:64910690c574 390 */
AnnaBridge 145:64910690c574 391 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge 145:64910690c574 392 {
AnnaBridge 145:64910690c574 393 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge 145:64910690c574 394 }
AnnaBridge 145:64910690c574 395
AnnaBridge 145:64910690c574 396
AnnaBridge 145:64910690c574 397 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 398 /**
AnnaBridge 145:64910690c574 399 \brief Set Priority Mask (non-secure)
AnnaBridge 145:64910690c574 400 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge 145:64910690c574 401 \param [in] priMask Priority Mask
AnnaBridge 145:64910690c574 402 */
AnnaBridge 145:64910690c574 403 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge 145:64910690c574 404 {
AnnaBridge 145:64910690c574 405 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge 145:64910690c574 406 }
AnnaBridge 145:64910690c574 407 #endif
AnnaBridge 145:64910690c574 408
AnnaBridge 145:64910690c574 409
AnnaBridge 145:64910690c574 410 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 411 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 412 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 413 /**
AnnaBridge 145:64910690c574 414 \brief Enable FIQ
AnnaBridge 145:64910690c574 415 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 145:64910690c574 416 Can only be executed in Privileged modes.
AnnaBridge 145:64910690c574 417 */
AnnaBridge 145:64910690c574 418 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
AnnaBridge 145:64910690c574 419
AnnaBridge 145:64910690c574 420
AnnaBridge 145:64910690c574 421 /**
AnnaBridge 145:64910690c574 422 \brief Disable FIQ
AnnaBridge 145:64910690c574 423 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 145:64910690c574 424 Can only be executed in Privileged modes.
AnnaBridge 145:64910690c574 425 */
AnnaBridge 145:64910690c574 426 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
AnnaBridge 145:64910690c574 427
AnnaBridge 145:64910690c574 428
AnnaBridge 145:64910690c574 429 /**
AnnaBridge 145:64910690c574 430 \brief Get Base Priority
AnnaBridge 145:64910690c574 431 \details Returns the current value of the Base Priority register.
AnnaBridge 145:64910690c574 432 \return Base Priority register value
AnnaBridge 145:64910690c574 433 */
AnnaBridge 145:64910690c574 434 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge 145:64910690c574 435 {
AnnaBridge 145:64910690c574 436 uint32_t result;
AnnaBridge 145:64910690c574 437
AnnaBridge 145:64910690c574 438 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge 145:64910690c574 439 return(result);
AnnaBridge 145:64910690c574 440 }
AnnaBridge 145:64910690c574 441
AnnaBridge 145:64910690c574 442
AnnaBridge 145:64910690c574 443 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 444 /**
AnnaBridge 145:64910690c574 445 \brief Get Base Priority (non-secure)
AnnaBridge 145:64910690c574 446 \details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge 145:64910690c574 447 \return Base Priority register value
AnnaBridge 145:64910690c574 448 */
AnnaBridge 145:64910690c574 449 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge 145:64910690c574 450 {
AnnaBridge 145:64910690c574 451 uint32_t result;
AnnaBridge 145:64910690c574 452
AnnaBridge 145:64910690c574 453 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 454 return(result);
AnnaBridge 145:64910690c574 455 }
AnnaBridge 145:64910690c574 456 #endif
AnnaBridge 145:64910690c574 457
AnnaBridge 145:64910690c574 458
AnnaBridge 145:64910690c574 459 /**
AnnaBridge 145:64910690c574 460 \brief Set Base Priority
AnnaBridge 145:64910690c574 461 \details Assigns the given value to the Base Priority register.
AnnaBridge 145:64910690c574 462 \param [in] basePri Base Priority value to set
AnnaBridge 145:64910690c574 463 */
AnnaBridge 145:64910690c574 464 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge 145:64910690c574 465 {
AnnaBridge 145:64910690c574 466 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge 145:64910690c574 467 }
AnnaBridge 145:64910690c574 468
AnnaBridge 145:64910690c574 469
AnnaBridge 145:64910690c574 470 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 471 /**
AnnaBridge 145:64910690c574 472 \brief Set Base Priority (non-secure)
AnnaBridge 145:64910690c574 473 \details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge 145:64910690c574 474 \param [in] basePri Base Priority value to set
AnnaBridge 145:64910690c574 475 */
AnnaBridge 145:64910690c574 476 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge 145:64910690c574 477 {
AnnaBridge 145:64910690c574 478 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge 145:64910690c574 479 }
AnnaBridge 145:64910690c574 480 #endif
AnnaBridge 145:64910690c574 481
AnnaBridge 145:64910690c574 482
AnnaBridge 145:64910690c574 483 /**
AnnaBridge 145:64910690c574 484 \brief Set Base Priority with condition
AnnaBridge 145:64910690c574 485 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge 145:64910690c574 486 or the new value increases the BASEPRI priority level.
AnnaBridge 145:64910690c574 487 \param [in] basePri Base Priority value to set
AnnaBridge 145:64910690c574 488 */
AnnaBridge 145:64910690c574 489 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge 145:64910690c574 490 {
AnnaBridge 145:64910690c574 491 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge 145:64910690c574 492 }
AnnaBridge 145:64910690c574 493
AnnaBridge 145:64910690c574 494
AnnaBridge 145:64910690c574 495 /**
AnnaBridge 145:64910690c574 496 \brief Get Fault Mask
AnnaBridge 145:64910690c574 497 \details Returns the current value of the Fault Mask register.
AnnaBridge 145:64910690c574 498 \return Fault Mask register value
AnnaBridge 145:64910690c574 499 */
AnnaBridge 145:64910690c574 500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge 145:64910690c574 501 {
AnnaBridge 145:64910690c574 502 uint32_t result;
AnnaBridge 145:64910690c574 503
AnnaBridge 145:64910690c574 504 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge 145:64910690c574 505 return(result);
AnnaBridge 145:64910690c574 506 }
AnnaBridge 145:64910690c574 507
AnnaBridge 145:64910690c574 508
AnnaBridge 145:64910690c574 509 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 510 /**
AnnaBridge 145:64910690c574 511 \brief Get Fault Mask (non-secure)
AnnaBridge 145:64910690c574 512 \details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge 145:64910690c574 513 \return Fault Mask register value
AnnaBridge 145:64910690c574 514 */
AnnaBridge 145:64910690c574 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge 145:64910690c574 516 {
AnnaBridge 145:64910690c574 517 uint32_t result;
AnnaBridge 145:64910690c574 518
AnnaBridge 145:64910690c574 519 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 520 return(result);
AnnaBridge 145:64910690c574 521 }
AnnaBridge 145:64910690c574 522 #endif
AnnaBridge 145:64910690c574 523
AnnaBridge 145:64910690c574 524
AnnaBridge 145:64910690c574 525 /**
AnnaBridge 145:64910690c574 526 \brief Set Fault Mask
AnnaBridge 145:64910690c574 527 \details Assigns the given value to the Fault Mask register.
AnnaBridge 145:64910690c574 528 \param [in] faultMask Fault Mask value to set
AnnaBridge 145:64910690c574 529 */
AnnaBridge 145:64910690c574 530 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge 145:64910690c574 531 {
AnnaBridge 145:64910690c574 532 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge 145:64910690c574 533 }
AnnaBridge 145:64910690c574 534
AnnaBridge 145:64910690c574 535
AnnaBridge 145:64910690c574 536 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 145:64910690c574 537 /**
AnnaBridge 145:64910690c574 538 \brief Set Fault Mask (non-secure)
AnnaBridge 145:64910690c574 539 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge 145:64910690c574 540 \param [in] faultMask Fault Mask value to set
AnnaBridge 145:64910690c574 541 */
AnnaBridge 145:64910690c574 542 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge 145:64910690c574 543 {
AnnaBridge 145:64910690c574 544 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge 145:64910690c574 545 }
AnnaBridge 145:64910690c574 546 #endif
AnnaBridge 145:64910690c574 547
AnnaBridge 145:64910690c574 548 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 549 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 550 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 145:64910690c574 551
AnnaBridge 145:64910690c574 552
AnnaBridge 145:64910690c574 553 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 554 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 145:64910690c574 555
AnnaBridge 145:64910690c574 556 /**
AnnaBridge 145:64910690c574 557 \brief Get Process Stack Pointer Limit
AnnaBridge 145:64910690c574 558 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 145:64910690c574 559 \return PSPLIM Register value
AnnaBridge 145:64910690c574 560 */
AnnaBridge 145:64910690c574 561 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge 145:64910690c574 562 {
AnnaBridge 145:64910690c574 563 register uint32_t result;
AnnaBridge 145:64910690c574 564
AnnaBridge 145:64910690c574 565 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge 145:64910690c574 566 return(result);
AnnaBridge 145:64910690c574 567 }
AnnaBridge 145:64910690c574 568
AnnaBridge 145:64910690c574 569
AnnaBridge 145:64910690c574 570 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 145:64910690c574 571 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 572 /**
AnnaBridge 145:64910690c574 573 \brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge 145:64910690c574 574 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 145:64910690c574 575 \return PSPLIM Register value
AnnaBridge 145:64910690c574 576 */
AnnaBridge 145:64910690c574 577 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge 145:64910690c574 578 {
AnnaBridge 145:64910690c574 579 register uint32_t result;
AnnaBridge 145:64910690c574 580
AnnaBridge 145:64910690c574 581 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 582 return(result);
AnnaBridge 145:64910690c574 583 }
AnnaBridge 145:64910690c574 584 #endif
AnnaBridge 145:64910690c574 585
AnnaBridge 145:64910690c574 586
AnnaBridge 145:64910690c574 587 /**
AnnaBridge 145:64910690c574 588 \brief Set Process Stack Pointer Limit
AnnaBridge 145:64910690c574 589 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 145:64910690c574 590 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 145:64910690c574 591 */
AnnaBridge 145:64910690c574 592 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge 145:64910690c574 593 {
AnnaBridge 145:64910690c574 594 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge 145:64910690c574 595 }
AnnaBridge 145:64910690c574 596
AnnaBridge 145:64910690c574 597
AnnaBridge 145:64910690c574 598 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 145:64910690c574 599 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 600 /**
AnnaBridge 145:64910690c574 601 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 145:64910690c574 602 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 145:64910690c574 603 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 145:64910690c574 604 */
AnnaBridge 145:64910690c574 605 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge 145:64910690c574 606 {
AnnaBridge 145:64910690c574 607 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge 145:64910690c574 608 }
AnnaBridge 145:64910690c574 609 #endif
AnnaBridge 145:64910690c574 610
AnnaBridge 145:64910690c574 611
AnnaBridge 145:64910690c574 612 /**
AnnaBridge 145:64910690c574 613 \brief Get Main Stack Pointer Limit
AnnaBridge 145:64910690c574 614 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 145:64910690c574 615 \return MSPLIM Register value
AnnaBridge 145:64910690c574 616 */
AnnaBridge 145:64910690c574 617 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge 145:64910690c574 618 {
AnnaBridge 145:64910690c574 619 register uint32_t result;
AnnaBridge 145:64910690c574 620
AnnaBridge 145:64910690c574 621 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge 145:64910690c574 622
AnnaBridge 145:64910690c574 623 return(result);
AnnaBridge 145:64910690c574 624 }
AnnaBridge 145:64910690c574 625
AnnaBridge 145:64910690c574 626
AnnaBridge 145:64910690c574 627 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 145:64910690c574 628 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 629 /**
AnnaBridge 145:64910690c574 630 \brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge 145:64910690c574 631 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge 145:64910690c574 632 \return MSPLIM Register value
AnnaBridge 145:64910690c574 633 */
AnnaBridge 145:64910690c574 634 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge 145:64910690c574 635 {
AnnaBridge 145:64910690c574 636 register uint32_t result;
AnnaBridge 145:64910690c574 637
AnnaBridge 145:64910690c574 638 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge 145:64910690c574 639 return(result);
AnnaBridge 145:64910690c574 640 }
AnnaBridge 145:64910690c574 641 #endif
AnnaBridge 145:64910690c574 642
AnnaBridge 145:64910690c574 643
AnnaBridge 145:64910690c574 644 /**
AnnaBridge 145:64910690c574 645 \brief Set Main Stack Pointer Limit
AnnaBridge 145:64910690c574 646 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 145:64910690c574 647 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge 145:64910690c574 648 */
AnnaBridge 145:64910690c574 649 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge 145:64910690c574 650 {
AnnaBridge 145:64910690c574 651 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 145:64910690c574 652 }
AnnaBridge 145:64910690c574 653
AnnaBridge 145:64910690c574 654
AnnaBridge 145:64910690c574 655 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 145:64910690c574 656 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 657 /**
AnnaBridge 145:64910690c574 658 \brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge 145:64910690c574 659 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge 145:64910690c574 660 \param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge 145:64910690c574 661 */
AnnaBridge 145:64910690c574 662 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge 145:64910690c574 663 {
AnnaBridge 145:64910690c574 664 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 145:64910690c574 665 }
AnnaBridge 145:64910690c574 666 #endif
AnnaBridge 145:64910690c574 667
AnnaBridge 145:64910690c574 668 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 669 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 145:64910690c574 670
AnnaBridge 145:64910690c574 671
AnnaBridge 145:64910690c574 672 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 673 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 674
AnnaBridge 145:64910690c574 675 /**
AnnaBridge 145:64910690c574 676 \brief Get FPSCR
AnnaBridge 145:64910690c574 677 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 145:64910690c574 678 \return Floating Point Status/Control register value
AnnaBridge 145:64910690c574 679 */
AnnaBridge 145:64910690c574 680 /* #define __get_FPSCR __builtin_arm_get_fpscr */
AnnaBridge 145:64910690c574 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 145:64910690c574 682 {
AnnaBridge 145:64910690c574 683 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 684 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 685 uint32_t result;
AnnaBridge 145:64910690c574 686
AnnaBridge 145:64910690c574 687 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 145:64910690c574 688 return(result);
AnnaBridge 145:64910690c574 689 #else
AnnaBridge 145:64910690c574 690 return(0U);
AnnaBridge 145:64910690c574 691 #endif
AnnaBridge 145:64910690c574 692 }
AnnaBridge 145:64910690c574 693
AnnaBridge 145:64910690c574 694
AnnaBridge 145:64910690c574 695 /**
AnnaBridge 145:64910690c574 696 \brief Set FPSCR
AnnaBridge 145:64910690c574 697 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 145:64910690c574 698 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 145:64910690c574 699 */
AnnaBridge 145:64910690c574 700 /* #define __set_FPSCR __builtin_arm_set_fpscr */
AnnaBridge 145:64910690c574 701 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 145:64910690c574 702 {
AnnaBridge 145:64910690c574 703 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 145:64910690c574 704 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 145:64910690c574 705 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
AnnaBridge 145:64910690c574 706 #else
AnnaBridge 145:64910690c574 707 (void)fpscr;
AnnaBridge 145:64910690c574 708 #endif
AnnaBridge 145:64910690c574 709 }
AnnaBridge 145:64910690c574 710
AnnaBridge 145:64910690c574 711 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 712 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 145:64910690c574 713
AnnaBridge 145:64910690c574 714
AnnaBridge 145:64910690c574 715
AnnaBridge 145:64910690c574 716 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 145:64910690c574 717
AnnaBridge 145:64910690c574 718
AnnaBridge 145:64910690c574 719 /* ########################## Core Instruction Access ######################### */
AnnaBridge 145:64910690c574 720 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge 145:64910690c574 721 Access to dedicated instructions
AnnaBridge 145:64910690c574 722 @{
AnnaBridge 145:64910690c574 723 */
AnnaBridge 145:64910690c574 724
AnnaBridge 145:64910690c574 725 /* Define macros for porting to both thumb1 and thumb2.
AnnaBridge 145:64910690c574 726 * For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge 145:64910690c574 727 * Otherwise, use general registers, specified by constraint "r" */
AnnaBridge 145:64910690c574 728 #if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge 145:64910690c574 729 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge 145:64910690c574 730 #define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge 145:64910690c574 731 #else
AnnaBridge 145:64910690c574 732 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge 145:64910690c574 733 #define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge 145:64910690c574 734 #endif
AnnaBridge 145:64910690c574 735
AnnaBridge 145:64910690c574 736 /**
AnnaBridge 145:64910690c574 737 \brief No Operation
AnnaBridge 145:64910690c574 738 \details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge 145:64910690c574 739 */
AnnaBridge 145:64910690c574 740 #define __NOP __builtin_arm_nop
AnnaBridge 145:64910690c574 741
AnnaBridge 145:64910690c574 742 /**
AnnaBridge 145:64910690c574 743 \brief Wait For Interrupt
AnnaBridge 145:64910690c574 744 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge 145:64910690c574 745 */
AnnaBridge 145:64910690c574 746 #define __WFI __builtin_arm_wfi
AnnaBridge 145:64910690c574 747
AnnaBridge 145:64910690c574 748
AnnaBridge 145:64910690c574 749 /**
AnnaBridge 145:64910690c574 750 \brief Wait For Event
AnnaBridge 145:64910690c574 751 \details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge 145:64910690c574 752 a low-power state until one of a number of events occurs.
AnnaBridge 145:64910690c574 753 */
AnnaBridge 145:64910690c574 754 #define __WFE __builtin_arm_wfe
AnnaBridge 145:64910690c574 755
AnnaBridge 145:64910690c574 756
AnnaBridge 145:64910690c574 757 /**
AnnaBridge 145:64910690c574 758 \brief Send Event
AnnaBridge 145:64910690c574 759 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge 145:64910690c574 760 */
AnnaBridge 145:64910690c574 761 #define __SEV __builtin_arm_sev
AnnaBridge 145:64910690c574 762
AnnaBridge 145:64910690c574 763
AnnaBridge 145:64910690c574 764 /**
AnnaBridge 145:64910690c574 765 \brief Instruction Synchronization Barrier
AnnaBridge 145:64910690c574 766 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 145:64910690c574 767 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 145:64910690c574 768 after the instruction has been completed.
AnnaBridge 145:64910690c574 769 */
AnnaBridge 145:64910690c574 770 #define __ISB() __builtin_arm_isb(0xF);
AnnaBridge 145:64910690c574 771
AnnaBridge 145:64910690c574 772 /**
AnnaBridge 145:64910690c574 773 \brief Data Synchronization Barrier
AnnaBridge 145:64910690c574 774 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 145:64910690c574 775 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 145:64910690c574 776 */
AnnaBridge 145:64910690c574 777 #define __DSB() __builtin_arm_dsb(0xF);
AnnaBridge 145:64910690c574 778
AnnaBridge 145:64910690c574 779
AnnaBridge 145:64910690c574 780 /**
AnnaBridge 145:64910690c574 781 \brief Data Memory Barrier
AnnaBridge 145:64910690c574 782 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 145:64910690c574 783 and after the instruction, without ensuring their completion.
AnnaBridge 145:64910690c574 784 */
AnnaBridge 145:64910690c574 785 #define __DMB() __builtin_arm_dmb(0xF);
AnnaBridge 145:64910690c574 786
AnnaBridge 145:64910690c574 787
AnnaBridge 145:64910690c574 788 /**
AnnaBridge 145:64910690c574 789 \brief Reverse byte order (32 bit)
AnnaBridge 145:64910690c574 790 \details Reverses the byte order in integer value.
AnnaBridge 145:64910690c574 791 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 792 \return Reversed value
AnnaBridge 145:64910690c574 793 */
AnnaBridge 145:64910690c574 794 #define __REV __builtin_bswap32
AnnaBridge 145:64910690c574 795
AnnaBridge 145:64910690c574 796
AnnaBridge 145:64910690c574 797 /**
AnnaBridge 145:64910690c574 798 \brief Reverse byte order (16 bit)
AnnaBridge 145:64910690c574 799 \details Reverses the byte order in two unsigned short values.
AnnaBridge 145:64910690c574 800 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 801 \return Reversed value
AnnaBridge 145:64910690c574 802 */
AnnaBridge 145:64910690c574 803 #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
AnnaBridge 145:64910690c574 804 #if 0
AnnaBridge 145:64910690c574 805 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
AnnaBridge 145:64910690c574 806 {
AnnaBridge 145:64910690c574 807 uint32_t result;
AnnaBridge 145:64910690c574 808
AnnaBridge 145:64910690c574 809 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 145:64910690c574 810 return(result);
AnnaBridge 145:64910690c574 811 }
AnnaBridge 145:64910690c574 812 #endif
AnnaBridge 145:64910690c574 813
AnnaBridge 145:64910690c574 814
AnnaBridge 145:64910690c574 815 /**
AnnaBridge 145:64910690c574 816 \brief Reverse byte order in signed short value
AnnaBridge 145:64910690c574 817 \details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge 145:64910690c574 818 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 819 \return Reversed value
AnnaBridge 145:64910690c574 820 */
AnnaBridge 145:64910690c574 821 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
AnnaBridge 145:64910690c574 822 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
AnnaBridge 145:64910690c574 823 {
AnnaBridge 145:64910690c574 824 int32_t result;
AnnaBridge 145:64910690c574 825
AnnaBridge 145:64910690c574 826 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 145:64910690c574 827 return(result);
AnnaBridge 145:64910690c574 828 }
AnnaBridge 145:64910690c574 829
AnnaBridge 145:64910690c574 830
AnnaBridge 145:64910690c574 831 /**
AnnaBridge 145:64910690c574 832 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 145:64910690c574 833 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 145:64910690c574 834 \param [in] op1 Value to rotate
AnnaBridge 145:64910690c574 835 \param [in] op2 Number of Bits to rotate
AnnaBridge 145:64910690c574 836 \return Rotated value
AnnaBridge 145:64910690c574 837 */
AnnaBridge 145:64910690c574 838 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 839 {
AnnaBridge 145:64910690c574 840 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 145:64910690c574 841 }
AnnaBridge 145:64910690c574 842
AnnaBridge 145:64910690c574 843
AnnaBridge 145:64910690c574 844 /**
AnnaBridge 145:64910690c574 845 \brief Breakpoint
AnnaBridge 145:64910690c574 846 \details Causes the processor to enter Debug state.
AnnaBridge 145:64910690c574 847 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge 145:64910690c574 848 \param [in] value is ignored by the processor.
AnnaBridge 145:64910690c574 849 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 145:64910690c574 850 */
AnnaBridge 145:64910690c574 851 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 145:64910690c574 852
AnnaBridge 145:64910690c574 853
AnnaBridge 145:64910690c574 854 /**
AnnaBridge 145:64910690c574 855 \brief Reverse bit order of value
AnnaBridge 145:64910690c574 856 \details Reverses the bit order of the given value.
AnnaBridge 145:64910690c574 857 \param [in] value Value to reverse
AnnaBridge 145:64910690c574 858 \return Reversed value
AnnaBridge 145:64910690c574 859 */
AnnaBridge 145:64910690c574 860 /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
AnnaBridge 145:64910690c574 861 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 145:64910690c574 862 {
AnnaBridge 145:64910690c574 863 uint32_t result;
AnnaBridge 145:64910690c574 864
AnnaBridge 145:64910690c574 865 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 866 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 867 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 868 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 145:64910690c574 869 #else
AnnaBridge 145:64910690c574 870 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
AnnaBridge 145:64910690c574 871
AnnaBridge 145:64910690c574 872 result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge 145:64910690c574 873 for (value >>= 1U; value; value >>= 1U)
AnnaBridge 145:64910690c574 874 {
AnnaBridge 145:64910690c574 875 result <<= 1U;
AnnaBridge 145:64910690c574 876 result |= value & 1U;
AnnaBridge 145:64910690c574 877 s--;
AnnaBridge 145:64910690c574 878 }
AnnaBridge 145:64910690c574 879 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 145:64910690c574 880 #endif
AnnaBridge 145:64910690c574 881 return(result);
AnnaBridge 145:64910690c574 882 }
AnnaBridge 145:64910690c574 883
AnnaBridge 145:64910690c574 884
AnnaBridge 145:64910690c574 885 /**
AnnaBridge 145:64910690c574 886 \brief Count leading zeros
AnnaBridge 145:64910690c574 887 \details Counts the number of leading zeros of a data value.
AnnaBridge 145:64910690c574 888 \param [in] value Value to count the leading zeros
AnnaBridge 145:64910690c574 889 \return number of leading zeros in value
AnnaBridge 145:64910690c574 890 */
AnnaBridge 145:64910690c574 891 #define __CLZ __builtin_clz
AnnaBridge 145:64910690c574 892
AnnaBridge 145:64910690c574 893
AnnaBridge 145:64910690c574 894 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 895 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 896 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 897 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 145:64910690c574 898 /**
AnnaBridge 145:64910690c574 899 \brief LDR Exclusive (8 bit)
AnnaBridge 145:64910690c574 900 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 145:64910690c574 901 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 902 \return value of type uint8_t at (*ptr)
AnnaBridge 145:64910690c574 903 */
AnnaBridge 145:64910690c574 904 #define __LDREXB (uint8_t)__builtin_arm_ldrex
AnnaBridge 145:64910690c574 905
AnnaBridge 145:64910690c574 906
AnnaBridge 145:64910690c574 907 /**
AnnaBridge 145:64910690c574 908 \brief LDR Exclusive (16 bit)
AnnaBridge 145:64910690c574 909 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 145:64910690c574 910 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 911 \return value of type uint16_t at (*ptr)
AnnaBridge 145:64910690c574 912 */
AnnaBridge 145:64910690c574 913 #define __LDREXH (uint16_t)__builtin_arm_ldrex
AnnaBridge 145:64910690c574 914
AnnaBridge 145:64910690c574 915
AnnaBridge 145:64910690c574 916 /**
AnnaBridge 145:64910690c574 917 \brief LDR Exclusive (32 bit)
AnnaBridge 145:64910690c574 918 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 145:64910690c574 919 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 920 \return value of type uint32_t at (*ptr)
AnnaBridge 145:64910690c574 921 */
AnnaBridge 145:64910690c574 922 #define __LDREXW (uint32_t)__builtin_arm_ldrex
AnnaBridge 145:64910690c574 923
AnnaBridge 145:64910690c574 924
AnnaBridge 145:64910690c574 925 /**
AnnaBridge 145:64910690c574 926 \brief STR Exclusive (8 bit)
AnnaBridge 145:64910690c574 927 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 145:64910690c574 928 \param [in] value Value to store
AnnaBridge 145:64910690c574 929 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 930 \return 0 Function succeeded
AnnaBridge 145:64910690c574 931 \return 1 Function failed
AnnaBridge 145:64910690c574 932 */
AnnaBridge 145:64910690c574 933 #define __STREXB (uint32_t)__builtin_arm_strex
AnnaBridge 145:64910690c574 934
AnnaBridge 145:64910690c574 935
AnnaBridge 145:64910690c574 936 /**
AnnaBridge 145:64910690c574 937 \brief STR Exclusive (16 bit)
AnnaBridge 145:64910690c574 938 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 145:64910690c574 939 \param [in] value Value to store
AnnaBridge 145:64910690c574 940 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 941 \return 0 Function succeeded
AnnaBridge 145:64910690c574 942 \return 1 Function failed
AnnaBridge 145:64910690c574 943 */
AnnaBridge 145:64910690c574 944 #define __STREXH (uint32_t)__builtin_arm_strex
AnnaBridge 145:64910690c574 945
AnnaBridge 145:64910690c574 946
AnnaBridge 145:64910690c574 947 /**
AnnaBridge 145:64910690c574 948 \brief STR Exclusive (32 bit)
AnnaBridge 145:64910690c574 949 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 145:64910690c574 950 \param [in] value Value to store
AnnaBridge 145:64910690c574 951 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 952 \return 0 Function succeeded
AnnaBridge 145:64910690c574 953 \return 1 Function failed
AnnaBridge 145:64910690c574 954 */
AnnaBridge 145:64910690c574 955 #define __STREXW (uint32_t)__builtin_arm_strex
AnnaBridge 145:64910690c574 956
AnnaBridge 145:64910690c574 957
AnnaBridge 145:64910690c574 958 /**
AnnaBridge 145:64910690c574 959 \brief Remove the exclusive lock
AnnaBridge 145:64910690c574 960 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 145:64910690c574 961 */
AnnaBridge 145:64910690c574 962 #define __CLREX __builtin_arm_clrex
AnnaBridge 145:64910690c574 963
AnnaBridge 145:64910690c574 964 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 965 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 966 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 967 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 145:64910690c574 968
AnnaBridge 145:64910690c574 969
AnnaBridge 145:64910690c574 970 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 971 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 972 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 145:64910690c574 973 /**
AnnaBridge 145:64910690c574 974 \brief Signed Saturate
AnnaBridge 145:64910690c574 975 \details Saturates a signed value.
AnnaBridge 145:64910690c574 976 \param [in] value Value to be saturated
AnnaBridge 145:64910690c574 977 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 145:64910690c574 978 \return Saturated value
AnnaBridge 145:64910690c574 979 */
AnnaBridge 145:64910690c574 980 #define __SSAT __builtin_arm_ssat
AnnaBridge 145:64910690c574 981
AnnaBridge 145:64910690c574 982
AnnaBridge 145:64910690c574 983 /**
AnnaBridge 145:64910690c574 984 \brief Unsigned Saturate
AnnaBridge 145:64910690c574 985 \details Saturates an unsigned value.
AnnaBridge 145:64910690c574 986 \param [in] value Value to be saturated
AnnaBridge 145:64910690c574 987 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 145:64910690c574 988 \return Saturated value
AnnaBridge 145:64910690c574 989 */
AnnaBridge 145:64910690c574 990 #define __USAT __builtin_arm_usat
AnnaBridge 145:64910690c574 991
AnnaBridge 145:64910690c574 992
AnnaBridge 145:64910690c574 993 /**
AnnaBridge 145:64910690c574 994 \brief Rotate Right with Extend (32 bit)
AnnaBridge 145:64910690c574 995 \details Moves each bit of a bitstring right by one bit.
AnnaBridge 145:64910690c574 996 The carry input is shifted in at the left end of the bitstring.
AnnaBridge 145:64910690c574 997 \param [in] value Value to rotate
AnnaBridge 145:64910690c574 998 \return Rotated value
AnnaBridge 145:64910690c574 999 */
AnnaBridge 145:64910690c574 1000 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge 145:64910690c574 1001 {
AnnaBridge 145:64910690c574 1002 uint32_t result;
AnnaBridge 145:64910690c574 1003
AnnaBridge 145:64910690c574 1004 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 145:64910690c574 1005 return(result);
AnnaBridge 145:64910690c574 1006 }
AnnaBridge 145:64910690c574 1007
AnnaBridge 145:64910690c574 1008
AnnaBridge 145:64910690c574 1009 /**
AnnaBridge 145:64910690c574 1010 \brief LDRT Unprivileged (8 bit)
AnnaBridge 145:64910690c574 1011 \details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge 145:64910690c574 1012 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1013 \return value of type uint8_t at (*ptr)
AnnaBridge 145:64910690c574 1014 */
AnnaBridge 145:64910690c574 1015 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge 145:64910690c574 1016 {
AnnaBridge 145:64910690c574 1017 uint32_t result;
AnnaBridge 145:64910690c574 1018
AnnaBridge 145:64910690c574 1019 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1020 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 145:64910690c574 1021 }
AnnaBridge 145:64910690c574 1022
AnnaBridge 145:64910690c574 1023
AnnaBridge 145:64910690c574 1024 /**
AnnaBridge 145:64910690c574 1025 \brief LDRT Unprivileged (16 bit)
AnnaBridge 145:64910690c574 1026 \details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge 145:64910690c574 1027 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1028 \return value of type uint16_t at (*ptr)
AnnaBridge 145:64910690c574 1029 */
AnnaBridge 145:64910690c574 1030 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge 145:64910690c574 1031 {
AnnaBridge 145:64910690c574 1032 uint32_t result;
AnnaBridge 145:64910690c574 1033
AnnaBridge 145:64910690c574 1034 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1035 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 145:64910690c574 1036 }
AnnaBridge 145:64910690c574 1037
AnnaBridge 145:64910690c574 1038
AnnaBridge 145:64910690c574 1039 /**
AnnaBridge 145:64910690c574 1040 \brief LDRT Unprivileged (32 bit)
AnnaBridge 145:64910690c574 1041 \details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge 145:64910690c574 1042 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1043 \return value of type uint32_t at (*ptr)
AnnaBridge 145:64910690c574 1044 */
AnnaBridge 145:64910690c574 1045 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge 145:64910690c574 1046 {
AnnaBridge 145:64910690c574 1047 uint32_t result;
AnnaBridge 145:64910690c574 1048
AnnaBridge 145:64910690c574 1049 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1050 return(result);
AnnaBridge 145:64910690c574 1051 }
AnnaBridge 145:64910690c574 1052
AnnaBridge 145:64910690c574 1053
AnnaBridge 145:64910690c574 1054 /**
AnnaBridge 145:64910690c574 1055 \brief STRT Unprivileged (8 bit)
AnnaBridge 145:64910690c574 1056 \details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge 145:64910690c574 1057 \param [in] value Value to store
AnnaBridge 145:64910690c574 1058 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1059 */
AnnaBridge 145:64910690c574 1060 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 145:64910690c574 1061 {
AnnaBridge 145:64910690c574 1062 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 145:64910690c574 1063 }
AnnaBridge 145:64910690c574 1064
AnnaBridge 145:64910690c574 1065
AnnaBridge 145:64910690c574 1066 /**
AnnaBridge 145:64910690c574 1067 \brief STRT Unprivileged (16 bit)
AnnaBridge 145:64910690c574 1068 \details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge 145:64910690c574 1069 \param [in] value Value to store
AnnaBridge 145:64910690c574 1070 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1071 */
AnnaBridge 145:64910690c574 1072 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 145:64910690c574 1073 {
AnnaBridge 145:64910690c574 1074 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 145:64910690c574 1075 }
AnnaBridge 145:64910690c574 1076
AnnaBridge 145:64910690c574 1077
AnnaBridge 145:64910690c574 1078 /**
AnnaBridge 145:64910690c574 1079 \brief STRT Unprivileged (32 bit)
AnnaBridge 145:64910690c574 1080 \details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge 145:64910690c574 1081 \param [in] value Value to store
AnnaBridge 145:64910690c574 1082 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1083 */
AnnaBridge 145:64910690c574 1084 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 145:64910690c574 1085 {
AnnaBridge 145:64910690c574 1086 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge 145:64910690c574 1087 }
AnnaBridge 145:64910690c574 1088
AnnaBridge 145:64910690c574 1089 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 145:64910690c574 1090 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 145:64910690c574 1091 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 145:64910690c574 1092
AnnaBridge 145:64910690c574 1093
AnnaBridge 145:64910690c574 1094 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 1095 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 145:64910690c574 1096 /**
AnnaBridge 145:64910690c574 1097 \brief Load-Acquire (8 bit)
AnnaBridge 145:64910690c574 1098 \details Executes a LDAB instruction for 8 bit value.
AnnaBridge 145:64910690c574 1099 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1100 \return value of type uint8_t at (*ptr)
AnnaBridge 145:64910690c574 1101 */
AnnaBridge 145:64910690c574 1102 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge 145:64910690c574 1103 {
AnnaBridge 145:64910690c574 1104 uint32_t result;
AnnaBridge 145:64910690c574 1105
AnnaBridge 145:64910690c574 1106 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1107 return ((uint8_t) result);
AnnaBridge 145:64910690c574 1108 }
AnnaBridge 145:64910690c574 1109
AnnaBridge 145:64910690c574 1110
AnnaBridge 145:64910690c574 1111 /**
AnnaBridge 145:64910690c574 1112 \brief Load-Acquire (16 bit)
AnnaBridge 145:64910690c574 1113 \details Executes a LDAH instruction for 16 bit values.
AnnaBridge 145:64910690c574 1114 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1115 \return value of type uint16_t at (*ptr)
AnnaBridge 145:64910690c574 1116 */
AnnaBridge 145:64910690c574 1117 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge 145:64910690c574 1118 {
AnnaBridge 145:64910690c574 1119 uint32_t result;
AnnaBridge 145:64910690c574 1120
AnnaBridge 145:64910690c574 1121 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1122 return ((uint16_t) result);
AnnaBridge 145:64910690c574 1123 }
AnnaBridge 145:64910690c574 1124
AnnaBridge 145:64910690c574 1125
AnnaBridge 145:64910690c574 1126 /**
AnnaBridge 145:64910690c574 1127 \brief Load-Acquire (32 bit)
AnnaBridge 145:64910690c574 1128 \details Executes a LDA instruction for 32 bit values.
AnnaBridge 145:64910690c574 1129 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1130 \return value of type uint32_t at (*ptr)
AnnaBridge 145:64910690c574 1131 */
AnnaBridge 145:64910690c574 1132 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge 145:64910690c574 1133 {
AnnaBridge 145:64910690c574 1134 uint32_t result;
AnnaBridge 145:64910690c574 1135
AnnaBridge 145:64910690c574 1136 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 145:64910690c574 1137 return(result);
AnnaBridge 145:64910690c574 1138 }
AnnaBridge 145:64910690c574 1139
AnnaBridge 145:64910690c574 1140
AnnaBridge 145:64910690c574 1141 /**
AnnaBridge 145:64910690c574 1142 \brief Store-Release (8 bit)
AnnaBridge 145:64910690c574 1143 \details Executes a STLB instruction for 8 bit values.
AnnaBridge 145:64910690c574 1144 \param [in] value Value to store
AnnaBridge 145:64910690c574 1145 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1146 */
AnnaBridge 145:64910690c574 1147 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 145:64910690c574 1148 {
AnnaBridge 145:64910690c574 1149 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 145:64910690c574 1150 }
AnnaBridge 145:64910690c574 1151
AnnaBridge 145:64910690c574 1152
AnnaBridge 145:64910690c574 1153 /**
AnnaBridge 145:64910690c574 1154 \brief Store-Release (16 bit)
AnnaBridge 145:64910690c574 1155 \details Executes a STLH instruction for 16 bit values.
AnnaBridge 145:64910690c574 1156 \param [in] value Value to store
AnnaBridge 145:64910690c574 1157 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1158 */
AnnaBridge 145:64910690c574 1159 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 145:64910690c574 1160 {
AnnaBridge 145:64910690c574 1161 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 145:64910690c574 1162 }
AnnaBridge 145:64910690c574 1163
AnnaBridge 145:64910690c574 1164
AnnaBridge 145:64910690c574 1165 /**
AnnaBridge 145:64910690c574 1166 \brief Store-Release (32 bit)
AnnaBridge 145:64910690c574 1167 \details Executes a STL instruction for 32 bit values.
AnnaBridge 145:64910690c574 1168 \param [in] value Value to store
AnnaBridge 145:64910690c574 1169 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1170 */
AnnaBridge 145:64910690c574 1171 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 145:64910690c574 1172 {
AnnaBridge 145:64910690c574 1173 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 145:64910690c574 1174 }
AnnaBridge 145:64910690c574 1175
AnnaBridge 145:64910690c574 1176
AnnaBridge 145:64910690c574 1177 /**
AnnaBridge 145:64910690c574 1178 \brief Load-Acquire Exclusive (8 bit)
AnnaBridge 145:64910690c574 1179 \details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge 145:64910690c574 1180 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1181 \return value of type uint8_t at (*ptr)
AnnaBridge 145:64910690c574 1182 */
AnnaBridge 145:64910690c574 1183 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
AnnaBridge 145:64910690c574 1184
AnnaBridge 145:64910690c574 1185
AnnaBridge 145:64910690c574 1186 /**
AnnaBridge 145:64910690c574 1187 \brief Load-Acquire Exclusive (16 bit)
AnnaBridge 145:64910690c574 1188 \details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge 145:64910690c574 1189 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1190 \return value of type uint16_t at (*ptr)
AnnaBridge 145:64910690c574 1191 */
AnnaBridge 145:64910690c574 1192 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
AnnaBridge 145:64910690c574 1193
AnnaBridge 145:64910690c574 1194
AnnaBridge 145:64910690c574 1195 /**
AnnaBridge 145:64910690c574 1196 \brief Load-Acquire Exclusive (32 bit)
AnnaBridge 145:64910690c574 1197 \details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge 145:64910690c574 1198 \param [in] ptr Pointer to data
AnnaBridge 145:64910690c574 1199 \return value of type uint32_t at (*ptr)
AnnaBridge 145:64910690c574 1200 */
AnnaBridge 145:64910690c574 1201 #define __LDAEX (uint32_t)__builtin_arm_ldaex
AnnaBridge 145:64910690c574 1202
AnnaBridge 145:64910690c574 1203
AnnaBridge 145:64910690c574 1204 /**
AnnaBridge 145:64910690c574 1205 \brief Store-Release Exclusive (8 bit)
AnnaBridge 145:64910690c574 1206 \details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge 145:64910690c574 1207 \param [in] value Value to store
AnnaBridge 145:64910690c574 1208 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1209 \return 0 Function succeeded
AnnaBridge 145:64910690c574 1210 \return 1 Function failed
AnnaBridge 145:64910690c574 1211 */
AnnaBridge 145:64910690c574 1212 #define __STLEXB (uint32_t)__builtin_arm_stlex
AnnaBridge 145:64910690c574 1213
AnnaBridge 145:64910690c574 1214
AnnaBridge 145:64910690c574 1215 /**
AnnaBridge 145:64910690c574 1216 \brief Store-Release Exclusive (16 bit)
AnnaBridge 145:64910690c574 1217 \details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge 145:64910690c574 1218 \param [in] value Value to store
AnnaBridge 145:64910690c574 1219 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1220 \return 0 Function succeeded
AnnaBridge 145:64910690c574 1221 \return 1 Function failed
AnnaBridge 145:64910690c574 1222 */
AnnaBridge 145:64910690c574 1223 #define __STLEXH (uint32_t)__builtin_arm_stlex
AnnaBridge 145:64910690c574 1224
AnnaBridge 145:64910690c574 1225
AnnaBridge 145:64910690c574 1226 /**
AnnaBridge 145:64910690c574 1227 \brief Store-Release Exclusive (32 bit)
AnnaBridge 145:64910690c574 1228 \details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge 145:64910690c574 1229 \param [in] value Value to store
AnnaBridge 145:64910690c574 1230 \param [in] ptr Pointer to location
AnnaBridge 145:64910690c574 1231 \return 0 Function succeeded
AnnaBridge 145:64910690c574 1232 \return 1 Function failed
AnnaBridge 145:64910690c574 1233 */
AnnaBridge 145:64910690c574 1234 #define __STLEX (uint32_t)__builtin_arm_stlex
AnnaBridge 145:64910690c574 1235
AnnaBridge 145:64910690c574 1236 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 145:64910690c574 1237 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 145:64910690c574 1238
AnnaBridge 145:64910690c574 1239 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge 145:64910690c574 1240
AnnaBridge 145:64910690c574 1241
AnnaBridge 145:64910690c574 1242 /* ################### Compiler specific Intrinsics ########################### */
AnnaBridge 145:64910690c574 1243 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge 145:64910690c574 1244 Access to dedicated SIMD instructions
AnnaBridge 145:64910690c574 1245 @{
AnnaBridge 145:64910690c574 1246 */
AnnaBridge 145:64910690c574 1247
AnnaBridge 145:64910690c574 1248 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge 145:64910690c574 1249
AnnaBridge 145:64910690c574 1250 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1251 {
AnnaBridge 145:64910690c574 1252 uint32_t result;
AnnaBridge 145:64910690c574 1253
AnnaBridge 145:64910690c574 1254 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1255 return(result);
AnnaBridge 145:64910690c574 1256 }
AnnaBridge 145:64910690c574 1257
AnnaBridge 145:64910690c574 1258 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1259 {
AnnaBridge 145:64910690c574 1260 uint32_t result;
AnnaBridge 145:64910690c574 1261
AnnaBridge 145:64910690c574 1262 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1263 return(result);
AnnaBridge 145:64910690c574 1264 }
AnnaBridge 145:64910690c574 1265
AnnaBridge 145:64910690c574 1266 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1267 {
AnnaBridge 145:64910690c574 1268 uint32_t result;
AnnaBridge 145:64910690c574 1269
AnnaBridge 145:64910690c574 1270 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1271 return(result);
AnnaBridge 145:64910690c574 1272 }
AnnaBridge 145:64910690c574 1273
AnnaBridge 145:64910690c574 1274 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1275 {
AnnaBridge 145:64910690c574 1276 uint32_t result;
AnnaBridge 145:64910690c574 1277
AnnaBridge 145:64910690c574 1278 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1279 return(result);
AnnaBridge 145:64910690c574 1280 }
AnnaBridge 145:64910690c574 1281
AnnaBridge 145:64910690c574 1282 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1283 {
AnnaBridge 145:64910690c574 1284 uint32_t result;
AnnaBridge 145:64910690c574 1285
AnnaBridge 145:64910690c574 1286 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1287 return(result);
AnnaBridge 145:64910690c574 1288 }
AnnaBridge 145:64910690c574 1289
AnnaBridge 145:64910690c574 1290 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1291 {
AnnaBridge 145:64910690c574 1292 uint32_t result;
AnnaBridge 145:64910690c574 1293
AnnaBridge 145:64910690c574 1294 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1295 return(result);
AnnaBridge 145:64910690c574 1296 }
AnnaBridge 145:64910690c574 1297
AnnaBridge 145:64910690c574 1298
AnnaBridge 145:64910690c574 1299 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1300 {
AnnaBridge 145:64910690c574 1301 uint32_t result;
AnnaBridge 145:64910690c574 1302
AnnaBridge 145:64910690c574 1303 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1304 return(result);
AnnaBridge 145:64910690c574 1305 }
AnnaBridge 145:64910690c574 1306
AnnaBridge 145:64910690c574 1307 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1308 {
AnnaBridge 145:64910690c574 1309 uint32_t result;
AnnaBridge 145:64910690c574 1310
AnnaBridge 145:64910690c574 1311 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1312 return(result);
AnnaBridge 145:64910690c574 1313 }
AnnaBridge 145:64910690c574 1314
AnnaBridge 145:64910690c574 1315 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1316 {
AnnaBridge 145:64910690c574 1317 uint32_t result;
AnnaBridge 145:64910690c574 1318
AnnaBridge 145:64910690c574 1319 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1320 return(result);
AnnaBridge 145:64910690c574 1321 }
AnnaBridge 145:64910690c574 1322
AnnaBridge 145:64910690c574 1323 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1324 {
AnnaBridge 145:64910690c574 1325 uint32_t result;
AnnaBridge 145:64910690c574 1326
AnnaBridge 145:64910690c574 1327 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1328 return(result);
AnnaBridge 145:64910690c574 1329 }
AnnaBridge 145:64910690c574 1330
AnnaBridge 145:64910690c574 1331 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1332 {
AnnaBridge 145:64910690c574 1333 uint32_t result;
AnnaBridge 145:64910690c574 1334
AnnaBridge 145:64910690c574 1335 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1336 return(result);
AnnaBridge 145:64910690c574 1337 }
AnnaBridge 145:64910690c574 1338
AnnaBridge 145:64910690c574 1339 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1340 {
AnnaBridge 145:64910690c574 1341 uint32_t result;
AnnaBridge 145:64910690c574 1342
AnnaBridge 145:64910690c574 1343 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1344 return(result);
AnnaBridge 145:64910690c574 1345 }
AnnaBridge 145:64910690c574 1346
AnnaBridge 145:64910690c574 1347
AnnaBridge 145:64910690c574 1348 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1349 {
AnnaBridge 145:64910690c574 1350 uint32_t result;
AnnaBridge 145:64910690c574 1351
AnnaBridge 145:64910690c574 1352 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1353 return(result);
AnnaBridge 145:64910690c574 1354 }
AnnaBridge 145:64910690c574 1355
AnnaBridge 145:64910690c574 1356 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1357 {
AnnaBridge 145:64910690c574 1358 uint32_t result;
AnnaBridge 145:64910690c574 1359
AnnaBridge 145:64910690c574 1360 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1361 return(result);
AnnaBridge 145:64910690c574 1362 }
AnnaBridge 145:64910690c574 1363
AnnaBridge 145:64910690c574 1364 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1365 {
AnnaBridge 145:64910690c574 1366 uint32_t result;
AnnaBridge 145:64910690c574 1367
AnnaBridge 145:64910690c574 1368 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1369 return(result);
AnnaBridge 145:64910690c574 1370 }
AnnaBridge 145:64910690c574 1371
AnnaBridge 145:64910690c574 1372 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1373 {
AnnaBridge 145:64910690c574 1374 uint32_t result;
AnnaBridge 145:64910690c574 1375
AnnaBridge 145:64910690c574 1376 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1377 return(result);
AnnaBridge 145:64910690c574 1378 }
AnnaBridge 145:64910690c574 1379
AnnaBridge 145:64910690c574 1380 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1381 {
AnnaBridge 145:64910690c574 1382 uint32_t result;
AnnaBridge 145:64910690c574 1383
AnnaBridge 145:64910690c574 1384 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1385 return(result);
AnnaBridge 145:64910690c574 1386 }
AnnaBridge 145:64910690c574 1387
AnnaBridge 145:64910690c574 1388 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1389 {
AnnaBridge 145:64910690c574 1390 uint32_t result;
AnnaBridge 145:64910690c574 1391
AnnaBridge 145:64910690c574 1392 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1393 return(result);
AnnaBridge 145:64910690c574 1394 }
AnnaBridge 145:64910690c574 1395
AnnaBridge 145:64910690c574 1396 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1397 {
AnnaBridge 145:64910690c574 1398 uint32_t result;
AnnaBridge 145:64910690c574 1399
AnnaBridge 145:64910690c574 1400 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1401 return(result);
AnnaBridge 145:64910690c574 1402 }
AnnaBridge 145:64910690c574 1403
AnnaBridge 145:64910690c574 1404 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1405 {
AnnaBridge 145:64910690c574 1406 uint32_t result;
AnnaBridge 145:64910690c574 1407
AnnaBridge 145:64910690c574 1408 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1409 return(result);
AnnaBridge 145:64910690c574 1410 }
AnnaBridge 145:64910690c574 1411
AnnaBridge 145:64910690c574 1412 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1413 {
AnnaBridge 145:64910690c574 1414 uint32_t result;
AnnaBridge 145:64910690c574 1415
AnnaBridge 145:64910690c574 1416 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1417 return(result);
AnnaBridge 145:64910690c574 1418 }
AnnaBridge 145:64910690c574 1419
AnnaBridge 145:64910690c574 1420 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1421 {
AnnaBridge 145:64910690c574 1422 uint32_t result;
AnnaBridge 145:64910690c574 1423
AnnaBridge 145:64910690c574 1424 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1425 return(result);
AnnaBridge 145:64910690c574 1426 }
AnnaBridge 145:64910690c574 1427
AnnaBridge 145:64910690c574 1428 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1429 {
AnnaBridge 145:64910690c574 1430 uint32_t result;
AnnaBridge 145:64910690c574 1431
AnnaBridge 145:64910690c574 1432 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1433 return(result);
AnnaBridge 145:64910690c574 1434 }
AnnaBridge 145:64910690c574 1435
AnnaBridge 145:64910690c574 1436 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1437 {
AnnaBridge 145:64910690c574 1438 uint32_t result;
AnnaBridge 145:64910690c574 1439
AnnaBridge 145:64910690c574 1440 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1441 return(result);
AnnaBridge 145:64910690c574 1442 }
AnnaBridge 145:64910690c574 1443
AnnaBridge 145:64910690c574 1444 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1445 {
AnnaBridge 145:64910690c574 1446 uint32_t result;
AnnaBridge 145:64910690c574 1447
AnnaBridge 145:64910690c574 1448 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1449 return(result);
AnnaBridge 145:64910690c574 1450 }
AnnaBridge 145:64910690c574 1451
AnnaBridge 145:64910690c574 1452 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1453 {
AnnaBridge 145:64910690c574 1454 uint32_t result;
AnnaBridge 145:64910690c574 1455
AnnaBridge 145:64910690c574 1456 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1457 return(result);
AnnaBridge 145:64910690c574 1458 }
AnnaBridge 145:64910690c574 1459
AnnaBridge 145:64910690c574 1460 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1461 {
AnnaBridge 145:64910690c574 1462 uint32_t result;
AnnaBridge 145:64910690c574 1463
AnnaBridge 145:64910690c574 1464 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1465 return(result);
AnnaBridge 145:64910690c574 1466 }
AnnaBridge 145:64910690c574 1467
AnnaBridge 145:64910690c574 1468 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1469 {
AnnaBridge 145:64910690c574 1470 uint32_t result;
AnnaBridge 145:64910690c574 1471
AnnaBridge 145:64910690c574 1472 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1473 return(result);
AnnaBridge 145:64910690c574 1474 }
AnnaBridge 145:64910690c574 1475
AnnaBridge 145:64910690c574 1476 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1477 {
AnnaBridge 145:64910690c574 1478 uint32_t result;
AnnaBridge 145:64910690c574 1479
AnnaBridge 145:64910690c574 1480 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1481 return(result);
AnnaBridge 145:64910690c574 1482 }
AnnaBridge 145:64910690c574 1483
AnnaBridge 145:64910690c574 1484 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1485 {
AnnaBridge 145:64910690c574 1486 uint32_t result;
AnnaBridge 145:64910690c574 1487
AnnaBridge 145:64910690c574 1488 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1489 return(result);
AnnaBridge 145:64910690c574 1490 }
AnnaBridge 145:64910690c574 1491
AnnaBridge 145:64910690c574 1492 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1493 {
AnnaBridge 145:64910690c574 1494 uint32_t result;
AnnaBridge 145:64910690c574 1495
AnnaBridge 145:64910690c574 1496 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1497 return(result);
AnnaBridge 145:64910690c574 1498 }
AnnaBridge 145:64910690c574 1499
AnnaBridge 145:64910690c574 1500 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1501 {
AnnaBridge 145:64910690c574 1502 uint32_t result;
AnnaBridge 145:64910690c574 1503
AnnaBridge 145:64910690c574 1504 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1505 return(result);
AnnaBridge 145:64910690c574 1506 }
AnnaBridge 145:64910690c574 1507
AnnaBridge 145:64910690c574 1508 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1509 {
AnnaBridge 145:64910690c574 1510 uint32_t result;
AnnaBridge 145:64910690c574 1511
AnnaBridge 145:64910690c574 1512 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1513 return(result);
AnnaBridge 145:64910690c574 1514 }
AnnaBridge 145:64910690c574 1515
AnnaBridge 145:64910690c574 1516 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1517 {
AnnaBridge 145:64910690c574 1518 uint32_t result;
AnnaBridge 145:64910690c574 1519
AnnaBridge 145:64910690c574 1520 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1521 return(result);
AnnaBridge 145:64910690c574 1522 }
AnnaBridge 145:64910690c574 1523
AnnaBridge 145:64910690c574 1524 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1525 {
AnnaBridge 145:64910690c574 1526 uint32_t result;
AnnaBridge 145:64910690c574 1527
AnnaBridge 145:64910690c574 1528 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1529 return(result);
AnnaBridge 145:64910690c574 1530 }
AnnaBridge 145:64910690c574 1531
AnnaBridge 145:64910690c574 1532 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1533 {
AnnaBridge 145:64910690c574 1534 uint32_t result;
AnnaBridge 145:64910690c574 1535
AnnaBridge 145:64910690c574 1536 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1537 return(result);
AnnaBridge 145:64910690c574 1538 }
AnnaBridge 145:64910690c574 1539
AnnaBridge 145:64910690c574 1540 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1541 {
AnnaBridge 145:64910690c574 1542 uint32_t result;
AnnaBridge 145:64910690c574 1543
AnnaBridge 145:64910690c574 1544 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1545 return(result);
AnnaBridge 145:64910690c574 1546 }
AnnaBridge 145:64910690c574 1547
AnnaBridge 145:64910690c574 1548 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 145:64910690c574 1549 {
AnnaBridge 145:64910690c574 1550 uint32_t result;
AnnaBridge 145:64910690c574 1551
AnnaBridge 145:64910690c574 1552 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1553 return(result);
AnnaBridge 145:64910690c574 1554 }
AnnaBridge 145:64910690c574 1555
AnnaBridge 145:64910690c574 1556 #define __SSAT16(ARG1,ARG2) \
AnnaBridge 145:64910690c574 1557 ({ \
AnnaBridge 145:64910690c574 1558 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 145:64910690c574 1559 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 145:64910690c574 1560 __RES; \
AnnaBridge 145:64910690c574 1561 })
AnnaBridge 145:64910690c574 1562
AnnaBridge 145:64910690c574 1563 #define __USAT16(ARG1,ARG2) \
AnnaBridge 145:64910690c574 1564 ({ \
AnnaBridge 145:64910690c574 1565 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 145:64910690c574 1566 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 145:64910690c574 1567 __RES; \
AnnaBridge 145:64910690c574 1568 })
AnnaBridge 145:64910690c574 1569
AnnaBridge 145:64910690c574 1570 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge 145:64910690c574 1571 {
AnnaBridge 145:64910690c574 1572 uint32_t result;
AnnaBridge 145:64910690c574 1573
AnnaBridge 145:64910690c574 1574 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 145:64910690c574 1575 return(result);
AnnaBridge 145:64910690c574 1576 }
AnnaBridge 145:64910690c574 1577
AnnaBridge 145:64910690c574 1578 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1579 {
AnnaBridge 145:64910690c574 1580 uint32_t result;
AnnaBridge 145:64910690c574 1581
AnnaBridge 145:64910690c574 1582 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1583 return(result);
AnnaBridge 145:64910690c574 1584 }
AnnaBridge 145:64910690c574 1585
AnnaBridge 145:64910690c574 1586 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge 145:64910690c574 1587 {
AnnaBridge 145:64910690c574 1588 uint32_t result;
AnnaBridge 145:64910690c574 1589
AnnaBridge 145:64910690c574 1590 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 145:64910690c574 1591 return(result);
AnnaBridge 145:64910690c574 1592 }
AnnaBridge 145:64910690c574 1593
AnnaBridge 145:64910690c574 1594 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1595 {
AnnaBridge 145:64910690c574 1596 uint32_t result;
AnnaBridge 145:64910690c574 1597
AnnaBridge 145:64910690c574 1598 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1599 return(result);
AnnaBridge 145:64910690c574 1600 }
AnnaBridge 145:64910690c574 1601
AnnaBridge 145:64910690c574 1602 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1603 {
AnnaBridge 145:64910690c574 1604 uint32_t result;
AnnaBridge 145:64910690c574 1605
AnnaBridge 145:64910690c574 1606 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1607 return(result);
AnnaBridge 145:64910690c574 1608 }
AnnaBridge 145:64910690c574 1609
AnnaBridge 145:64910690c574 1610 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1611 {
AnnaBridge 145:64910690c574 1612 uint32_t result;
AnnaBridge 145:64910690c574 1613
AnnaBridge 145:64910690c574 1614 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1615 return(result);
AnnaBridge 145:64910690c574 1616 }
AnnaBridge 145:64910690c574 1617
AnnaBridge 145:64910690c574 1618 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 145:64910690c574 1619 {
AnnaBridge 145:64910690c574 1620 uint32_t result;
AnnaBridge 145:64910690c574 1621
AnnaBridge 145:64910690c574 1622 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1623 return(result);
AnnaBridge 145:64910690c574 1624 }
AnnaBridge 145:64910690c574 1625
AnnaBridge 145:64910690c574 1626 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 145:64910690c574 1627 {
AnnaBridge 145:64910690c574 1628 uint32_t result;
AnnaBridge 145:64910690c574 1629
AnnaBridge 145:64910690c574 1630 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1631 return(result);
AnnaBridge 145:64910690c574 1632 }
AnnaBridge 145:64910690c574 1633
AnnaBridge 145:64910690c574 1634 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 145:64910690c574 1635 {
AnnaBridge 145:64910690c574 1636 union llreg_u{
AnnaBridge 145:64910690c574 1637 uint32_t w32[2];
AnnaBridge 145:64910690c574 1638 uint64_t w64;
AnnaBridge 145:64910690c574 1639 } llr;
AnnaBridge 145:64910690c574 1640 llr.w64 = acc;
AnnaBridge 145:64910690c574 1641
AnnaBridge 145:64910690c574 1642 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 145:64910690c574 1643 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 145:64910690c574 1644 #else /* Big endian */
AnnaBridge 145:64910690c574 1645 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 145:64910690c574 1646 #endif
AnnaBridge 145:64910690c574 1647
AnnaBridge 145:64910690c574 1648 return(llr.w64);
AnnaBridge 145:64910690c574 1649 }
AnnaBridge 145:64910690c574 1650
AnnaBridge 145:64910690c574 1651 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 145:64910690c574 1652 {
AnnaBridge 145:64910690c574 1653 union llreg_u{
AnnaBridge 145:64910690c574 1654 uint32_t w32[2];
AnnaBridge 145:64910690c574 1655 uint64_t w64;
AnnaBridge 145:64910690c574 1656 } llr;
AnnaBridge 145:64910690c574 1657 llr.w64 = acc;
AnnaBridge 145:64910690c574 1658
AnnaBridge 145:64910690c574 1659 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 145:64910690c574 1660 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 145:64910690c574 1661 #else /* Big endian */
AnnaBridge 145:64910690c574 1662 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 145:64910690c574 1663 #endif
AnnaBridge 145:64910690c574 1664
AnnaBridge 145:64910690c574 1665 return(llr.w64);
AnnaBridge 145:64910690c574 1666 }
AnnaBridge 145:64910690c574 1667
AnnaBridge 145:64910690c574 1668 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1669 {
AnnaBridge 145:64910690c574 1670 uint32_t result;
AnnaBridge 145:64910690c574 1671
AnnaBridge 145:64910690c574 1672 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1673 return(result);
AnnaBridge 145:64910690c574 1674 }
AnnaBridge 145:64910690c574 1675
AnnaBridge 145:64910690c574 1676 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1677 {
AnnaBridge 145:64910690c574 1678 uint32_t result;
AnnaBridge 145:64910690c574 1679
AnnaBridge 145:64910690c574 1680 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1681 return(result);
AnnaBridge 145:64910690c574 1682 }
AnnaBridge 145:64910690c574 1683
AnnaBridge 145:64910690c574 1684 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 145:64910690c574 1685 {
AnnaBridge 145:64910690c574 1686 uint32_t result;
AnnaBridge 145:64910690c574 1687
AnnaBridge 145:64910690c574 1688 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1689 return(result);
AnnaBridge 145:64910690c574 1690 }
AnnaBridge 145:64910690c574 1691
AnnaBridge 145:64910690c574 1692 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 145:64910690c574 1693 {
AnnaBridge 145:64910690c574 1694 uint32_t result;
AnnaBridge 145:64910690c574 1695
AnnaBridge 145:64910690c574 1696 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1697 return(result);
AnnaBridge 145:64910690c574 1698 }
AnnaBridge 145:64910690c574 1699
AnnaBridge 145:64910690c574 1700 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 145:64910690c574 1701 {
AnnaBridge 145:64910690c574 1702 union llreg_u{
AnnaBridge 145:64910690c574 1703 uint32_t w32[2];
AnnaBridge 145:64910690c574 1704 uint64_t w64;
AnnaBridge 145:64910690c574 1705 } llr;
AnnaBridge 145:64910690c574 1706 llr.w64 = acc;
AnnaBridge 145:64910690c574 1707
AnnaBridge 145:64910690c574 1708 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 145:64910690c574 1709 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 145:64910690c574 1710 #else /* Big endian */
AnnaBridge 145:64910690c574 1711 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 145:64910690c574 1712 #endif
AnnaBridge 145:64910690c574 1713
AnnaBridge 145:64910690c574 1714 return(llr.w64);
AnnaBridge 145:64910690c574 1715 }
AnnaBridge 145:64910690c574 1716
AnnaBridge 145:64910690c574 1717 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 145:64910690c574 1718 {
AnnaBridge 145:64910690c574 1719 union llreg_u{
AnnaBridge 145:64910690c574 1720 uint32_t w32[2];
AnnaBridge 145:64910690c574 1721 uint64_t w64;
AnnaBridge 145:64910690c574 1722 } llr;
AnnaBridge 145:64910690c574 1723 llr.w64 = acc;
AnnaBridge 145:64910690c574 1724
AnnaBridge 145:64910690c574 1725 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 145:64910690c574 1726 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 145:64910690c574 1727 #else /* Big endian */
AnnaBridge 145:64910690c574 1728 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 145:64910690c574 1729 #endif
AnnaBridge 145:64910690c574 1730
AnnaBridge 145:64910690c574 1731 return(llr.w64);
AnnaBridge 145:64910690c574 1732 }
AnnaBridge 145:64910690c574 1733
AnnaBridge 145:64910690c574 1734 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge 145:64910690c574 1735 {
AnnaBridge 145:64910690c574 1736 uint32_t result;
AnnaBridge 145:64910690c574 1737
AnnaBridge 145:64910690c574 1738 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1739 return(result);
AnnaBridge 145:64910690c574 1740 }
AnnaBridge 145:64910690c574 1741
AnnaBridge 145:64910690c574 1742 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge 145:64910690c574 1743 {
AnnaBridge 145:64910690c574 1744 int32_t result;
AnnaBridge 145:64910690c574 1745
AnnaBridge 145:64910690c574 1746 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1747 return(result);
AnnaBridge 145:64910690c574 1748 }
AnnaBridge 145:64910690c574 1749
AnnaBridge 145:64910690c574 1750 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge 145:64910690c574 1751 {
AnnaBridge 145:64910690c574 1752 int32_t result;
AnnaBridge 145:64910690c574 1753
AnnaBridge 145:64910690c574 1754 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 145:64910690c574 1755 return(result);
AnnaBridge 145:64910690c574 1756 }
AnnaBridge 145:64910690c574 1757
AnnaBridge 145:64910690c574 1758 #if 0
AnnaBridge 145:64910690c574 1759 #define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge 145:64910690c574 1760 ({ \
AnnaBridge 145:64910690c574 1761 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 145:64910690c574 1762 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 145:64910690c574 1763 __RES; \
AnnaBridge 145:64910690c574 1764 })
AnnaBridge 145:64910690c574 1765
AnnaBridge 145:64910690c574 1766 #define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge 145:64910690c574 1767 ({ \
AnnaBridge 145:64910690c574 1768 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 145:64910690c574 1769 if (ARG3 == 0) \
AnnaBridge 145:64910690c574 1770 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge 145:64910690c574 1771 else \
AnnaBridge 145:64910690c574 1772 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 145:64910690c574 1773 __RES; \
AnnaBridge 145:64910690c574 1774 })
AnnaBridge 145:64910690c574 1775 #endif
AnnaBridge 145:64910690c574 1776
AnnaBridge 145:64910690c574 1777 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
AnnaBridge 145:64910690c574 1778 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge 145:64910690c574 1779
AnnaBridge 145:64910690c574 1780 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
AnnaBridge 145:64910690c574 1781 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge 145:64910690c574 1782
AnnaBridge 145:64910690c574 1783 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge 145:64910690c574 1784 {
AnnaBridge 145:64910690c574 1785 int32_t result;
AnnaBridge 145:64910690c574 1786
AnnaBridge 145:64910690c574 1787 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 145:64910690c574 1788 return(result);
AnnaBridge 145:64910690c574 1789 }
AnnaBridge 145:64910690c574 1790
AnnaBridge 145:64910690c574 1791 #endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge 145:64910690c574 1792 /*@} end of group CMSIS_SIMD_intrinsics */
AnnaBridge 145:64910690c574 1793
AnnaBridge 145:64910690c574 1794
AnnaBridge 145:64910690c574 1795 #endif /* __CMSIS_ARMCLANG_H */