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Committer:
Anna Bridge
Date:
Wed Jan 17 16:13:02 2018 +0000
Revision:
160:5571c4ff569f
Child:
169:a7c7b631e539
mbed library. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 160:5571c4ff569f 1 /******************************************************************************
Anna Bridge 160:5571c4ff569f 2 * @file mpu_armv8.h
Anna Bridge 160:5571c4ff569f 3 * @brief CMSIS MPU API for ARMv8 MPU
Anna Bridge 160:5571c4ff569f 4 * @version V5.0.3
Anna Bridge 160:5571c4ff569f 5 * @date 09. August 2017
Anna Bridge 160:5571c4ff569f 6 ******************************************************************************/
Anna Bridge 160:5571c4ff569f 7 /*
Anna Bridge 160:5571c4ff569f 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
Anna Bridge 160:5571c4ff569f 9 *
Anna Bridge 160:5571c4ff569f 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 160:5571c4ff569f 11 *
Anna Bridge 160:5571c4ff569f 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 160:5571c4ff569f 13 * not use this file except in compliance with the License.
Anna Bridge 160:5571c4ff569f 14 * You may obtain a copy of the License at
Anna Bridge 160:5571c4ff569f 15 *
Anna Bridge 160:5571c4ff569f 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 160:5571c4ff569f 17 *
Anna Bridge 160:5571c4ff569f 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 160:5571c4ff569f 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 160:5571c4ff569f 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 160:5571c4ff569f 21 * See the License for the specific language governing permissions and
Anna Bridge 160:5571c4ff569f 22 * limitations under the License.
Anna Bridge 160:5571c4ff569f 23 */
Anna Bridge 160:5571c4ff569f 24
Anna Bridge 160:5571c4ff569f 25 #ifndef ARM_MPU_ARMV8_H
Anna Bridge 160:5571c4ff569f 26 #define ARM_MPU_ARMV8_H
Anna Bridge 160:5571c4ff569f 27
Anna Bridge 160:5571c4ff569f 28 /** \brief Attribute for device memory (outer only) */
Anna Bridge 160:5571c4ff569f 29 #define ARM_MPU_ATTR_DEVICE ( 0U )
Anna Bridge 160:5571c4ff569f 30
Anna Bridge 160:5571c4ff569f 31 /** \brief Attribute for non-cacheable, normal memory */
Anna Bridge 160:5571c4ff569f 32 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
Anna Bridge 160:5571c4ff569f 33
Anna Bridge 160:5571c4ff569f 34 /** \brief Attribute for normal memory (outer and inner)
Anna Bridge 160:5571c4ff569f 35 * \param NT Non-Transient: Set to 1 for non-transient data.
Anna Bridge 160:5571c4ff569f 36 * \param WB Write-Back: Set to 1 to use write-back update policy.
Anna Bridge 160:5571c4ff569f 37 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
Anna Bridge 160:5571c4ff569f 38 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
Anna Bridge 160:5571c4ff569f 39 */
Anna Bridge 160:5571c4ff569f 40 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
Anna Bridge 160:5571c4ff569f 41 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
Anna Bridge 160:5571c4ff569f 42
Anna Bridge 160:5571c4ff569f 43 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
Anna Bridge 160:5571c4ff569f 44 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
Anna Bridge 160:5571c4ff569f 45
Anna Bridge 160:5571c4ff569f 46 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
Anna Bridge 160:5571c4ff569f 47 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
Anna Bridge 160:5571c4ff569f 48
Anna Bridge 160:5571c4ff569f 49 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
Anna Bridge 160:5571c4ff569f 50 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
Anna Bridge 160:5571c4ff569f 51
Anna Bridge 160:5571c4ff569f 52 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
Anna Bridge 160:5571c4ff569f 53 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
Anna Bridge 160:5571c4ff569f 54
Anna Bridge 160:5571c4ff569f 55 /** \brief Memory Attribute
Anna Bridge 160:5571c4ff569f 56 * \param O Outer memory attributes
Anna Bridge 160:5571c4ff569f 57 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
Anna Bridge 160:5571c4ff569f 58 */
Anna Bridge 160:5571c4ff569f 59 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
Anna Bridge 160:5571c4ff569f 60
Anna Bridge 160:5571c4ff569f 61 /** \brief Normal memory non-shareable */
Anna Bridge 160:5571c4ff569f 62 #define ARM_MPU_SH_NON (0U)
Anna Bridge 160:5571c4ff569f 63
Anna Bridge 160:5571c4ff569f 64 /** \brief Normal memory outer shareable */
Anna Bridge 160:5571c4ff569f 65 #define ARM_MPU_SH_OUTER (2U)
Anna Bridge 160:5571c4ff569f 66
Anna Bridge 160:5571c4ff569f 67 /** \brief Normal memory inner shareable */
Anna Bridge 160:5571c4ff569f 68 #define ARM_MPU_SH_INNER (3U)
Anna Bridge 160:5571c4ff569f 69
Anna Bridge 160:5571c4ff569f 70 /** \brief Memory access permissions
Anna Bridge 160:5571c4ff569f 71 * \param RO Read-Only: Set to 1 for read-only memory.
Anna Bridge 160:5571c4ff569f 72 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
Anna Bridge 160:5571c4ff569f 73 */
Anna Bridge 160:5571c4ff569f 74 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
Anna Bridge 160:5571c4ff569f 75
Anna Bridge 160:5571c4ff569f 76 /** \brief Region Base Address Register value
Anna Bridge 160:5571c4ff569f 77 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
Anna Bridge 160:5571c4ff569f 78 * \param SH Defines the Shareability domain for this memory region.
Anna Bridge 160:5571c4ff569f 79 * \param RO Read-Only: Set to 1 for a read-only memory region.
Anna Bridge 160:5571c4ff569f 80 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
Anna Bridge 160:5571c4ff569f 81 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
Anna Bridge 160:5571c4ff569f 82 */
Anna Bridge 160:5571c4ff569f 83 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
Anna Bridge 160:5571c4ff569f 84 ((BASE & MPU_RBAR_BASE_Pos) | \
Anna Bridge 160:5571c4ff569f 85 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
Anna Bridge 160:5571c4ff569f 86 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
Anna Bridge 160:5571c4ff569f 87 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
Anna Bridge 160:5571c4ff569f 88
Anna Bridge 160:5571c4ff569f 89 /** \brief Region Limit Address Register value
Anna Bridge 160:5571c4ff569f 90 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
Anna Bridge 160:5571c4ff569f 91 * \param IDX The attribute index to be associated with this memory region.
Anna Bridge 160:5571c4ff569f 92 */
Anna Bridge 160:5571c4ff569f 93 #define ARM_MPU_RLAR(LIMIT, IDX) \
Anna Bridge 160:5571c4ff569f 94 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
Anna Bridge 160:5571c4ff569f 95 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
Anna Bridge 160:5571c4ff569f 96 (MPU_RLAR_EN_Msk))
Anna Bridge 160:5571c4ff569f 97
Anna Bridge 160:5571c4ff569f 98 /**
Anna Bridge 160:5571c4ff569f 99 * Struct for a single MPU Region
Anna Bridge 160:5571c4ff569f 100 */
Anna Bridge 160:5571c4ff569f 101 typedef struct _ARM_MPU_Region_t {
Anna Bridge 160:5571c4ff569f 102 uint32_t RBAR; /*!< Region Base Address Register value */
Anna Bridge 160:5571c4ff569f 103 uint32_t RLAR; /*!< Region Limit Address Register value */
Anna Bridge 160:5571c4ff569f 104 } ARM_MPU_Region_t;
Anna Bridge 160:5571c4ff569f 105
Anna Bridge 160:5571c4ff569f 106 /** Enable the MPU.
Anna Bridge 160:5571c4ff569f 107 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 160:5571c4ff569f 108 */
Anna Bridge 160:5571c4ff569f 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Anna Bridge 160:5571c4ff569f 110 {
Anna Bridge 160:5571c4ff569f 111 __DSB();
Anna Bridge 160:5571c4ff569f 112 __ISB();
Anna Bridge 160:5571c4ff569f 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 160:5571c4ff569f 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 160:5571c4ff569f 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 160:5571c4ff569f 116 #endif
Anna Bridge 160:5571c4ff569f 117 }
Anna Bridge 160:5571c4ff569f 118
Anna Bridge 160:5571c4ff569f 119 /** Disable the MPU.
Anna Bridge 160:5571c4ff569f 120 */
Anna Bridge 160:5571c4ff569f 121 __STATIC_INLINE void ARM_MPU_Disable(void)
Anna Bridge 160:5571c4ff569f 122 {
Anna Bridge 160:5571c4ff569f 123 __DSB();
Anna Bridge 160:5571c4ff569f 124 __ISB();
Anna Bridge 160:5571c4ff569f 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 160:5571c4ff569f 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 160:5571c4ff569f 127 #endif
Anna Bridge 160:5571c4ff569f 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 160:5571c4ff569f 129 }
Anna Bridge 160:5571c4ff569f 130
Anna Bridge 160:5571c4ff569f 131 #ifdef MPU_NS
Anna Bridge 160:5571c4ff569f 132 /** Enable the Non-secure MPU.
Anna Bridge 160:5571c4ff569f 133 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 160:5571c4ff569f 134 */
Anna Bridge 160:5571c4ff569f 135 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
Anna Bridge 160:5571c4ff569f 136 {
Anna Bridge 160:5571c4ff569f 137 __DSB();
Anna Bridge 160:5571c4ff569f 138 __ISB();
Anna Bridge 160:5571c4ff569f 139 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 160:5571c4ff569f 140 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 160:5571c4ff569f 141 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 160:5571c4ff569f 142 #endif
Anna Bridge 160:5571c4ff569f 143 }
Anna Bridge 160:5571c4ff569f 144
Anna Bridge 160:5571c4ff569f 145 /** Disable the Non-secure MPU.
Anna Bridge 160:5571c4ff569f 146 */
Anna Bridge 160:5571c4ff569f 147 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
Anna Bridge 160:5571c4ff569f 148 {
Anna Bridge 160:5571c4ff569f 149 __DSB();
Anna Bridge 160:5571c4ff569f 150 __ISB();
Anna Bridge 160:5571c4ff569f 151 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 160:5571c4ff569f 152 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 160:5571c4ff569f 153 #endif
Anna Bridge 160:5571c4ff569f 154 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 160:5571c4ff569f 155 }
Anna Bridge 160:5571c4ff569f 156 #endif
Anna Bridge 160:5571c4ff569f 157
Anna Bridge 160:5571c4ff569f 158 /** Set the memory attribute encoding to the given MPU.
Anna Bridge 160:5571c4ff569f 159 * \param mpu Pointer to the MPU to be configured.
Anna Bridge 160:5571c4ff569f 160 * \param idx The attribute index to be set [0-7]
Anna Bridge 160:5571c4ff569f 161 * \param attr The attribute value to be set.
Anna Bridge 160:5571c4ff569f 162 */
Anna Bridge 160:5571c4ff569f 163 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
Anna Bridge 160:5571c4ff569f 164 {
Anna Bridge 160:5571c4ff569f 165 const uint8_t reg = idx / 4U;
Anna Bridge 160:5571c4ff569f 166 const uint32_t pos = ((idx % 4U) * 8U);
Anna Bridge 160:5571c4ff569f 167 const uint32_t mask = 0xFFU << pos;
Anna Bridge 160:5571c4ff569f 168
Anna Bridge 160:5571c4ff569f 169 if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
Anna Bridge 160:5571c4ff569f 170 return; // invalid index
Anna Bridge 160:5571c4ff569f 171 }
Anna Bridge 160:5571c4ff569f 172
Anna Bridge 160:5571c4ff569f 173 MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
Anna Bridge 160:5571c4ff569f 174 }
Anna Bridge 160:5571c4ff569f 175
Anna Bridge 160:5571c4ff569f 176 /** Set the memory attribute encoding.
Anna Bridge 160:5571c4ff569f 177 * \param idx The attribute index to be set [0-7]
Anna Bridge 160:5571c4ff569f 178 * \param attr The attribute value to be set.
Anna Bridge 160:5571c4ff569f 179 */
Anna Bridge 160:5571c4ff569f 180 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
Anna Bridge 160:5571c4ff569f 181 {
Anna Bridge 160:5571c4ff569f 182 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
Anna Bridge 160:5571c4ff569f 183 }
Anna Bridge 160:5571c4ff569f 184
Anna Bridge 160:5571c4ff569f 185 #ifdef MPU_NS
Anna Bridge 160:5571c4ff569f 186 /** Set the memory attribute encoding to the Non-secure MPU.
Anna Bridge 160:5571c4ff569f 187 * \param idx The attribute index to be set [0-7]
Anna Bridge 160:5571c4ff569f 188 * \param attr The attribute value to be set.
Anna Bridge 160:5571c4ff569f 189 */
Anna Bridge 160:5571c4ff569f 190 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
Anna Bridge 160:5571c4ff569f 191 {
Anna Bridge 160:5571c4ff569f 192 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
Anna Bridge 160:5571c4ff569f 193 }
Anna Bridge 160:5571c4ff569f 194 #endif
Anna Bridge 160:5571c4ff569f 195
Anna Bridge 160:5571c4ff569f 196 /** Clear and disable the given MPU region of the given MPU.
Anna Bridge 160:5571c4ff569f 197 * \param mpu Pointer to MPU to be used.
Anna Bridge 160:5571c4ff569f 198 * \param rnr Region number to be cleared.
Anna Bridge 160:5571c4ff569f 199 */
Anna Bridge 160:5571c4ff569f 200 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
Anna Bridge 160:5571c4ff569f 201 {
Anna Bridge 160:5571c4ff569f 202 MPU->RNR = rnr;
Anna Bridge 160:5571c4ff569f 203 MPU->RLAR = 0U;
Anna Bridge 160:5571c4ff569f 204 }
Anna Bridge 160:5571c4ff569f 205
Anna Bridge 160:5571c4ff569f 206 /** Clear and disable the given MPU region.
Anna Bridge 160:5571c4ff569f 207 * \param rnr Region number to be cleared.
Anna Bridge 160:5571c4ff569f 208 */
Anna Bridge 160:5571c4ff569f 209 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Anna Bridge 160:5571c4ff569f 210 {
Anna Bridge 160:5571c4ff569f 211 ARM_MPU_ClrRegionEx(MPU, rnr);
Anna Bridge 160:5571c4ff569f 212 }
Anna Bridge 160:5571c4ff569f 213
Anna Bridge 160:5571c4ff569f 214 #ifdef MPU_NS
Anna Bridge 160:5571c4ff569f 215 /** Clear and disable the given Non-secure MPU region.
Anna Bridge 160:5571c4ff569f 216 * \param rnr Region number to be cleared.
Anna Bridge 160:5571c4ff569f 217 */
Anna Bridge 160:5571c4ff569f 218 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
Anna Bridge 160:5571c4ff569f 219 {
Anna Bridge 160:5571c4ff569f 220 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
Anna Bridge 160:5571c4ff569f 221 }
Anna Bridge 160:5571c4ff569f 222 #endif
Anna Bridge 160:5571c4ff569f 223
Anna Bridge 160:5571c4ff569f 224 /** Configure the given MPU region of the given MPU.
Anna Bridge 160:5571c4ff569f 225 * \param mpu Pointer to MPU to be used.
Anna Bridge 160:5571c4ff569f 226 * \param rnr Region number to be configured.
Anna Bridge 160:5571c4ff569f 227 * \param rbar Value for RBAR register.
Anna Bridge 160:5571c4ff569f 228 * \param rlar Value for RLAR register.
Anna Bridge 160:5571c4ff569f 229 */
Anna Bridge 160:5571c4ff569f 230 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 160:5571c4ff569f 231 {
Anna Bridge 160:5571c4ff569f 232 MPU->RNR = rnr;
Anna Bridge 160:5571c4ff569f 233 MPU->RBAR = rbar;
Anna Bridge 160:5571c4ff569f 234 MPU->RLAR = rlar;
Anna Bridge 160:5571c4ff569f 235 }
Anna Bridge 160:5571c4ff569f 236
Anna Bridge 160:5571c4ff569f 237 /** Configure the given MPU region.
Anna Bridge 160:5571c4ff569f 238 * \param rnr Region number to be configured.
Anna Bridge 160:5571c4ff569f 239 * \param rbar Value for RBAR register.
Anna Bridge 160:5571c4ff569f 240 * \param rlar Value for RLAR register.
Anna Bridge 160:5571c4ff569f 241 */
Anna Bridge 160:5571c4ff569f 242 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 160:5571c4ff569f 243 {
Anna Bridge 160:5571c4ff569f 244 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
Anna Bridge 160:5571c4ff569f 245 }
Anna Bridge 160:5571c4ff569f 246
Anna Bridge 160:5571c4ff569f 247 #ifdef MPU_NS
Anna Bridge 160:5571c4ff569f 248 /** Configure the given Non-secure MPU region.
Anna Bridge 160:5571c4ff569f 249 * \param rnr Region number to be configured.
Anna Bridge 160:5571c4ff569f 250 * \param rbar Value for RBAR register.
Anna Bridge 160:5571c4ff569f 251 * \param rlar Value for RLAR register.
Anna Bridge 160:5571c4ff569f 252 */
Anna Bridge 160:5571c4ff569f 253 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 160:5571c4ff569f 254 {
Anna Bridge 160:5571c4ff569f 255 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
Anna Bridge 160:5571c4ff569f 256 }
Anna Bridge 160:5571c4ff569f 257 #endif
Anna Bridge 160:5571c4ff569f 258
Anna Bridge 160:5571c4ff569f 259 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Anna Bridge 160:5571c4ff569f 260 * \param dst Destination data is copied to.
Anna Bridge 160:5571c4ff569f 261 * \param src Source data is copied from.
Anna Bridge 160:5571c4ff569f 262 * \param len Amount of data words to be copied.
Anna Bridge 160:5571c4ff569f 263 */
Anna Bridge 160:5571c4ff569f 264 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Anna Bridge 160:5571c4ff569f 265 {
Anna Bridge 160:5571c4ff569f 266 uint32_t i;
Anna Bridge 160:5571c4ff569f 267 for (i = 0U; i < len; ++i)
Anna Bridge 160:5571c4ff569f 268 {
Anna Bridge 160:5571c4ff569f 269 dst[i] = src[i];
Anna Bridge 160:5571c4ff569f 270 }
Anna Bridge 160:5571c4ff569f 271 }
Anna Bridge 160:5571c4ff569f 272
Anna Bridge 160:5571c4ff569f 273 /** Load the given number of MPU regions from a table to the given MPU.
Anna Bridge 160:5571c4ff569f 274 * \param mpu Pointer to the MPU registers to be used.
Anna Bridge 160:5571c4ff569f 275 * \param rnr First region number to be configured.
Anna Bridge 160:5571c4ff569f 276 * \param table Pointer to the MPU configuration table.
Anna Bridge 160:5571c4ff569f 277 * \param cnt Amount of regions to be configured.
Anna Bridge 160:5571c4ff569f 278 */
Anna Bridge 160:5571c4ff569f 279 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 160:5571c4ff569f 280 {
Anna Bridge 160:5571c4ff569f 281 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Anna Bridge 160:5571c4ff569f 282 if (cnt == 1U) {
Anna Bridge 160:5571c4ff569f 283 mpu->RNR = rnr;
Anna Bridge 160:5571c4ff569f 284 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
Anna Bridge 160:5571c4ff569f 285 } else {
Anna Bridge 160:5571c4ff569f 286 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
Anna Bridge 160:5571c4ff569f 287 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
Anna Bridge 160:5571c4ff569f 288
Anna Bridge 160:5571c4ff569f 289 mpu->RNR = rnrBase;
Anna Bridge 160:5571c4ff569f 290 if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
Anna Bridge 160:5571c4ff569f 291 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
Anna Bridge 160:5571c4ff569f 292 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
Anna Bridge 160:5571c4ff569f 293 ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
Anna Bridge 160:5571c4ff569f 294 } else {
Anna Bridge 160:5571c4ff569f 295 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
Anna Bridge 160:5571c4ff569f 296 }
Anna Bridge 160:5571c4ff569f 297 }
Anna Bridge 160:5571c4ff569f 298 }
Anna Bridge 160:5571c4ff569f 299
Anna Bridge 160:5571c4ff569f 300 /** Load the given number of MPU regions from a table.
Anna Bridge 160:5571c4ff569f 301 * \param rnr First region number to be configured.
Anna Bridge 160:5571c4ff569f 302 * \param table Pointer to the MPU configuration table.
Anna Bridge 160:5571c4ff569f 303 * \param cnt Amount of regions to be configured.
Anna Bridge 160:5571c4ff569f 304 */
Anna Bridge 160:5571c4ff569f 305 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 160:5571c4ff569f 306 {
Anna Bridge 160:5571c4ff569f 307 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
Anna Bridge 160:5571c4ff569f 308 }
Anna Bridge 160:5571c4ff569f 309
Anna Bridge 160:5571c4ff569f 310 #ifdef MPU_NS
Anna Bridge 160:5571c4ff569f 311 /** Load the given number of MPU regions from a table to the Non-secure MPU.
Anna Bridge 160:5571c4ff569f 312 * \param rnr First region number to be configured.
Anna Bridge 160:5571c4ff569f 313 * \param table Pointer to the MPU configuration table.
Anna Bridge 160:5571c4ff569f 314 * \param cnt Amount of regions to be configured.
Anna Bridge 160:5571c4ff569f 315 */
Anna Bridge 160:5571c4ff569f 316 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 160:5571c4ff569f 317 {
Anna Bridge 160:5571c4ff569f 318 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
Anna Bridge 160:5571c4ff569f 319 }
Anna Bridge 160:5571c4ff569f 320 #endif
Anna Bridge 160:5571c4ff569f 321
Anna Bridge 160:5571c4ff569f 322 #endif
Anna Bridge 160:5571c4ff569f 323