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TARGET_WALLBOT_BLE/nrf51_bitfields.h@97:433970e64889, 2015-04-14 (annotated)

Committer:: Kojto
Date:: Tue Apr 14 10:58:58 2015 +0200
Revision:: 97:433970e64889
Parent:: 92:4fc01daae5a5
Child:: 122:f9eeca106725

Release 97 of the mbed library



Changes:

- NRF51 - Update Softdevice, fix us ticker

- MTS Dragonfly - bugfixes, IAR support

- MTS mdot - bootloader support

- RZ_A1 - nvic wrapper

- STM F3xx, F4xx - hal reorganization

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	97:433970e64889	1	/* Copyright (c) 2013, Nordic Semiconductor ASA
Kojto	97:433970e64889	2	* All rights reserved.
Kojto	97:433970e64889	3	*
Kojto	97:433970e64889	4	* Redistribution and use in source and binary forms, with or without
Kojto	97:433970e64889	5	* modification, are permitted provided that the following conditions are met:
Kojto	97:433970e64889	6	*
Kojto	97:433970e64889	7	* * Redistributions of source code must retain the above copyright notice, this
Kojto	97:433970e64889	8	* list of conditions and the following disclaimer.
Kojto	97:433970e64889	9	*
Kojto	97:433970e64889	10	* * Redistributions in binary form must reproduce the above copyright notice,
Kojto	97:433970e64889	11	* this list of conditions and the following disclaimer in the documentation
Kojto	97:433970e64889	12	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	13	*
Kojto	97:433970e64889	14	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto	97:433970e64889	15	* contributors may be used to endorse or promote products derived from
Kojto	97:433970e64889	16	* this software without specific prior written permission.
bogdanm	92:4fc01daae5a5	17	*
Kojto	97:433970e64889	18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	97:433970e64889	19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	97:433970e64889	20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	97:433970e64889	21	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	97:433970e64889	22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	97:433970e64889	23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	97:433970e64889	24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	97:433970e64889	25	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	97:433970e64889	26	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	97:433970e64889	27	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	28	*
bogdanm	92:4fc01daae5a5	29	*/
bogdanm	92:4fc01daae5a5	30	#ifndef __NRF51_BITS_H
bogdanm	92:4fc01daae5a5	31	#define __NRF51_BITS_H
bogdanm	92:4fc01daae5a5	32
bogdanm	92:4fc01daae5a5	33	/lint ++flb "Enter library region /
bogdanm	92:4fc01daae5a5	34
Kojto	97:433970e64889	35	#include <core_cm0.h>
bogdanm	92:4fc01daae5a5	36
bogdanm	92:4fc01daae5a5	37	/* Peripheral: AAR */
bogdanm	92:4fc01daae5a5	38	/* Description: Accelerated Address Resolver. */
bogdanm	92:4fc01daae5a5	39
bogdanm	92:4fc01daae5a5	40	/* Register: AAR_INTENSET */
bogdanm	92:4fc01daae5a5	41	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	42
bogdanm	92:4fc01daae5a5	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
bogdanm	92:4fc01daae5a5	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	92:4fc01daae5a5	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	92:4fc01daae5a5	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	49
bogdanm	92:4fc01daae5a5	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
bogdanm	92:4fc01daae5a5	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	92:4fc01daae5a5	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	92:4fc01daae5a5	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	56
bogdanm	92:4fc01daae5a5	57	/* Bit 0 : Enable interrupt on END event. */
bogdanm	92:4fc01daae5a5	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	63
bogdanm	92:4fc01daae5a5	64	/* Register: AAR_INTENCLR */
bogdanm	92:4fc01daae5a5	65	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	66
bogdanm	92:4fc01daae5a5	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
bogdanm	92:4fc01daae5a5	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	92:4fc01daae5a5	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	92:4fc01daae5a5	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	73
bogdanm	92:4fc01daae5a5	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
bogdanm	92:4fc01daae5a5	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	92:4fc01daae5a5	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	92:4fc01daae5a5	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	80
bogdanm	92:4fc01daae5a5	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	92:4fc01daae5a5	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	87
bogdanm	92:4fc01daae5a5	88	/* Register: AAR_STATUS */
bogdanm	92:4fc01daae5a5	89	/* Description: Resolution status. */
bogdanm	92:4fc01daae5a5	90
bogdanm	92:4fc01daae5a5	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
bogdanm	92:4fc01daae5a5	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
bogdanm	92:4fc01daae5a5	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
bogdanm	92:4fc01daae5a5	94
bogdanm	92:4fc01daae5a5	95	/* Register: AAR_ENABLE */
bogdanm	92:4fc01daae5a5	96	/* Description: Enable AAR. */
bogdanm	92:4fc01daae5a5	97
bogdanm	92:4fc01daae5a5	98	/* Bits 1..0 : Enable AAR. */
bogdanm	92:4fc01daae5a5	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
bogdanm	92:4fc01daae5a5	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
bogdanm	92:4fc01daae5a5	103
bogdanm	92:4fc01daae5a5	104	/* Register: AAR_NIRK */
bogdanm	92:4fc01daae5a5	105	/* Description: Number of Identity root Keys in the IRK data structure. */
bogdanm	92:4fc01daae5a5	106
bogdanm	92:4fc01daae5a5	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
bogdanm	92:4fc01daae5a5	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
bogdanm	92:4fc01daae5a5	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	/* Register: AAR_POWER */
bogdanm	92:4fc01daae5a5	112	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	113
bogdanm	92:4fc01daae5a5	114	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	119
bogdanm	92:4fc01daae5a5	120
bogdanm	92:4fc01daae5a5	121	/* Peripheral: ADC */
bogdanm	92:4fc01daae5a5	122	/* Description: Analog to digital converter. */
bogdanm	92:4fc01daae5a5	123
bogdanm	92:4fc01daae5a5	124	/* Register: ADC_INTENSET */
bogdanm	92:4fc01daae5a5	125	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	126
bogdanm	92:4fc01daae5a5	127	/* Bit 0 : Enable interrupt on END event. */
bogdanm	92:4fc01daae5a5	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	133
bogdanm	92:4fc01daae5a5	134	/* Register: ADC_INTENCLR */
bogdanm	92:4fc01daae5a5	135	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	136
bogdanm	92:4fc01daae5a5	137	/* Bit 0 : Disable interrupt on END event. */
bogdanm	92:4fc01daae5a5	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	143
bogdanm	92:4fc01daae5a5	144	/* Register: ADC_BUSY */
bogdanm	92:4fc01daae5a5	145	/* Description: ADC busy register. */
bogdanm	92:4fc01daae5a5	146
bogdanm	92:4fc01daae5a5	147	/* Bit 0 : ADC busy register. */
bogdanm	92:4fc01daae5a5	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
bogdanm	92:4fc01daae5a5	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
bogdanm	92:4fc01daae5a5	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
bogdanm	92:4fc01daae5a5	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
bogdanm	92:4fc01daae5a5	152
bogdanm	92:4fc01daae5a5	153	/* Register: ADC_ENABLE */
bogdanm	92:4fc01daae5a5	154	/* Description: ADC enable. */
bogdanm	92:4fc01daae5a5	155
bogdanm	92:4fc01daae5a5	156	/* Bits 1..0 : ADC enable. */
bogdanm	92:4fc01daae5a5	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
bogdanm	92:4fc01daae5a5	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
bogdanm	92:4fc01daae5a5	161
bogdanm	92:4fc01daae5a5	162	/* Register: ADC_CONFIG */
bogdanm	92:4fc01daae5a5	163	/* Description: ADC configuration register. */
bogdanm	92:4fc01daae5a5	164
bogdanm	92:4fc01daae5a5	165	/* Bits 17..16 : ADC external reference pin selection. */
bogdanm	92:4fc01daae5a5	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
bogdanm	92:4fc01daae5a5	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	92:4fc01daae5a5	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
bogdanm	92:4fc01daae5a5	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
bogdanm	92:4fc01daae5a5	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
bogdanm	92:4fc01daae5a5	171
bogdanm	92:4fc01daae5a5	172	/* Bits 15..8 : ADC analog pin selection. */
bogdanm	92:4fc01daae5a5	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	92:4fc01daae5a5	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	92:4fc01daae5a5	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
bogdanm	92:4fc01daae5a5	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
bogdanm	92:4fc01daae5a5	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
bogdanm	92:4fc01daae5a5	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
bogdanm	92:4fc01daae5a5	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
bogdanm	92:4fc01daae5a5	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
bogdanm	92:4fc01daae5a5	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
bogdanm	92:4fc01daae5a5	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
bogdanm	92:4fc01daae5a5	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
bogdanm	92:4fc01daae5a5	184
bogdanm	92:4fc01daae5a5	185	/* Bits 6..5 : ADC reference selection. */
bogdanm	92:4fc01daae5a5	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
bogdanm	92:4fc01daae5a5	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
bogdanm	92:4fc01daae5a5	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
bogdanm	92:4fc01daae5a5	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
bogdanm	92:4fc01daae5a5	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
bogdanm	92:4fc01daae5a5	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
bogdanm	92:4fc01daae5a5	192
bogdanm	92:4fc01daae5a5	193	/* Bits 4..2 : ADC input selection. */
bogdanm	92:4fc01daae5a5	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
bogdanm	92:4fc01daae5a5	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
bogdanm	92:4fc01daae5a5	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
bogdanm	92:4fc01daae5a5	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
bogdanm	92:4fc01daae5a5	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
bogdanm	92:4fc01daae5a5	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
bogdanm	92:4fc01daae5a5	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
bogdanm	92:4fc01daae5a5	201
bogdanm	92:4fc01daae5a5	202	/* Bits 1..0 : ADC resolution. */
bogdanm	92:4fc01daae5a5	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
bogdanm	92:4fc01daae5a5	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
bogdanm	92:4fc01daae5a5	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
bogdanm	92:4fc01daae5a5	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
bogdanm	92:4fc01daae5a5	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
bogdanm	92:4fc01daae5a5	208
bogdanm	92:4fc01daae5a5	209	/* Register: ADC_RESULT */
bogdanm	92:4fc01daae5a5	210	/* Description: Result of ADC conversion. */
bogdanm	92:4fc01daae5a5	211
bogdanm	92:4fc01daae5a5	212	/* Bits 9..0 : Result of ADC conversion. */
bogdanm	92:4fc01daae5a5	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	92:4fc01daae5a5	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	92:4fc01daae5a5	215
bogdanm	92:4fc01daae5a5	216	/* Register: ADC_POWER */
bogdanm	92:4fc01daae5a5	217	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	218
bogdanm	92:4fc01daae5a5	219	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	224
bogdanm	92:4fc01daae5a5	225
bogdanm	92:4fc01daae5a5	226	/* Peripheral: AMLI */
bogdanm	92:4fc01daae5a5	227	/* Description: AHB Multi-Layer Interface. */
bogdanm	92:4fc01daae5a5	228
bogdanm	92:4fc01daae5a5	229	/* Register: AMLI_RAMPRI_CPU0 */
bogdanm	92:4fc01daae5a5	230	/* Description: Configurable priority configuration register for CPU0. */
bogdanm	92:4fc01daae5a5	231
Kojto	97:433970e64889	232	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	243
Kojto	97:433970e64889	244	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	255
Kojto	97:433970e64889	256	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	267
Kojto	97:433970e64889	268	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	279
bogdanm	92:4fc01daae5a5	280	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	291
bogdanm	92:4fc01daae5a5	292	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	303
bogdanm	92:4fc01daae5a5	304	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	315
bogdanm	92:4fc01daae5a5	316	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	327
bogdanm	92:4fc01daae5a5	328	/* Register: AMLI_RAMPRI_SPIS1 */
bogdanm	92:4fc01daae5a5	329	/* Description: Configurable priority configuration register for SPIS1. */
bogdanm	92:4fc01daae5a5	330
Kojto	97:433970e64889	331	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	342
Kojto	97:433970e64889	343	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	354
Kojto	97:433970e64889	355	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	366
Kojto	97:433970e64889	367	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	378
bogdanm	92:4fc01daae5a5	379	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	390
bogdanm	92:4fc01daae5a5	391	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	402
bogdanm	92:4fc01daae5a5	403	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	414
bogdanm	92:4fc01daae5a5	415	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	426
bogdanm	92:4fc01daae5a5	427	/* Register: AMLI_RAMPRI_RADIO */
bogdanm	92:4fc01daae5a5	428	/* Description: Configurable priority configuration register for RADIO. */
bogdanm	92:4fc01daae5a5	429
Kojto	97:433970e64889	430	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	441
Kojto	97:433970e64889	442	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	453
Kojto	97:433970e64889	454	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	465
Kojto	97:433970e64889	466	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	477
bogdanm	92:4fc01daae5a5	478	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	489
bogdanm	92:4fc01daae5a5	490	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	501
bogdanm	92:4fc01daae5a5	502	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	513
bogdanm	92:4fc01daae5a5	514	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	525
bogdanm	92:4fc01daae5a5	526	/* Register: AMLI_RAMPRI_ECB */
bogdanm	92:4fc01daae5a5	527	/* Description: Configurable priority configuration register for ECB. */
bogdanm	92:4fc01daae5a5	528
Kojto	97:433970e64889	529	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	540
Kojto	97:433970e64889	541	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	552
Kojto	97:433970e64889	553	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	564
Kojto	97:433970e64889	565	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	576
bogdanm	92:4fc01daae5a5	577	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	588
bogdanm	92:4fc01daae5a5	589	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	600
bogdanm	92:4fc01daae5a5	601	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	612
bogdanm	92:4fc01daae5a5	613	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	624
bogdanm	92:4fc01daae5a5	625	/* Register: AMLI_RAMPRI_CCM */
bogdanm	92:4fc01daae5a5	626	/* Description: Configurable priority configuration register for CCM. */
bogdanm	92:4fc01daae5a5	627
Kojto	97:433970e64889	628	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	639
Kojto	97:433970e64889	640	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	651
Kojto	97:433970e64889	652	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	675
bogdanm	92:4fc01daae5a5	676	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	687
bogdanm	92:4fc01daae5a5	688	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	699
bogdanm	92:4fc01daae5a5	700	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	711
bogdanm	92:4fc01daae5a5	712	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	723
bogdanm	92:4fc01daae5a5	724	/* Register: AMLI_RAMPRI_AAR */
bogdanm	92:4fc01daae5a5	725	/* Description: Configurable priority configuration register for AAR. */
bogdanm	92:4fc01daae5a5	726
Kojto	97:433970e64889	727	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	738
Kojto	97:433970e64889	739	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	750
Kojto	97:433970e64889	751	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	762
Kojto	97:433970e64889	763	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	774
bogdanm	92:4fc01daae5a5	775	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	92:4fc01daae5a5	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	92:4fc01daae5a5	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	786
bogdanm	92:4fc01daae5a5	787	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	92:4fc01daae5a5	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	92:4fc01daae5a5	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	798
bogdanm	92:4fc01daae5a5	799	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	92:4fc01daae5a5	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	92:4fc01daae5a5	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	810
bogdanm	92:4fc01daae5a5	811	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	92:4fc01daae5a5	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	92:4fc01daae5a5	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	92:4fc01daae5a5	822
bogdanm	92:4fc01daae5a5	823	/* Peripheral: CCM */
bogdanm	92:4fc01daae5a5	824	/* Description: AES CCM Mode Encryption. */
bogdanm	92:4fc01daae5a5	825
bogdanm	92:4fc01daae5a5	826	/* Register: CCM_SHORTS */
Kojto	97:433970e64889	827	/* Description: Shortcuts for the CCM. */
Kojto	97:433970e64889	828
Kojto	97:433970e64889	829	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
bogdanm	92:4fc01daae5a5	830	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
bogdanm	92:4fc01daae5a5	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
bogdanm	92:4fc01daae5a5	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	834
bogdanm	92:4fc01daae5a5	835	/* Register: CCM_INTENSET */
bogdanm	92:4fc01daae5a5	836	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	837
bogdanm	92:4fc01daae5a5	838	/* Bit 2 : Enable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	839	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	840	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	841	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	842	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	843	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	844
bogdanm	92:4fc01daae5a5	845	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
bogdanm	92:4fc01daae5a5	846	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	92:4fc01daae5a5	847	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	92:4fc01daae5a5	848	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	849	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	850	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	851
bogdanm	92:4fc01daae5a5	852	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
bogdanm	92:4fc01daae5a5	853	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	92:4fc01daae5a5	854	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	92:4fc01daae5a5	855	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	856	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	857	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	858
bogdanm	92:4fc01daae5a5	859	/* Register: CCM_INTENCLR */
bogdanm	92:4fc01daae5a5	860	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	861
bogdanm	92:4fc01daae5a5	862	/* Bit 2 : Disable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	863	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	864	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	865	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	866	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	867	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	868
bogdanm	92:4fc01daae5a5	869	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
bogdanm	92:4fc01daae5a5	870	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	92:4fc01daae5a5	871	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	92:4fc01daae5a5	872	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	873	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	874	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	875
bogdanm	92:4fc01daae5a5	876	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	92:4fc01daae5a5	877	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	92:4fc01daae5a5	878	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	92:4fc01daae5a5	879	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	880	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	881	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	882
bogdanm	92:4fc01daae5a5	883	/* Register: CCM_MICSTATUS */
bogdanm	92:4fc01daae5a5	884	/* Description: CCM RX MIC check result. */
bogdanm	92:4fc01daae5a5	885
bogdanm	92:4fc01daae5a5	886	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
bogdanm	92:4fc01daae5a5	887	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
bogdanm	92:4fc01daae5a5	888	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
bogdanm	92:4fc01daae5a5	889	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
bogdanm	92:4fc01daae5a5	890	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
bogdanm	92:4fc01daae5a5	891
bogdanm	92:4fc01daae5a5	892	/* Register: CCM_ENABLE */
bogdanm	92:4fc01daae5a5	893	/* Description: CCM enable. */
bogdanm	92:4fc01daae5a5	894
bogdanm	92:4fc01daae5a5	895	/* Bits 1..0 : CCM enable. */
bogdanm	92:4fc01daae5a5	896	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	897	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	898	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
bogdanm	92:4fc01daae5a5	899	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
bogdanm	92:4fc01daae5a5	900
bogdanm	92:4fc01daae5a5	901	/* Register: CCM_MODE */
bogdanm	92:4fc01daae5a5	902	/* Description: Operation mode. */
bogdanm	92:4fc01daae5a5	903
bogdanm	92:4fc01daae5a5	904	/* Bit 0 : CCM mode operation. */
bogdanm	92:4fc01daae5a5	905	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	92:4fc01daae5a5	906	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	92:4fc01daae5a5	907	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
bogdanm	92:4fc01daae5a5	908	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
bogdanm	92:4fc01daae5a5	909
bogdanm	92:4fc01daae5a5	910	/* Register: CCM_POWER */
bogdanm	92:4fc01daae5a5	911	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	912
bogdanm	92:4fc01daae5a5	913	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	914	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	915	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	916	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	917	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	918
bogdanm	92:4fc01daae5a5	919
bogdanm	92:4fc01daae5a5	920	/* Peripheral: CLOCK */
bogdanm	92:4fc01daae5a5	921	/* Description: Clock control. */
bogdanm	92:4fc01daae5a5	922
bogdanm	92:4fc01daae5a5	923	/* Register: CLOCK_INTENSET */
bogdanm	92:4fc01daae5a5	924	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	925
bogdanm	92:4fc01daae5a5	926	/* Bit 4 : Enable interrupt on CTTO event. */
bogdanm	92:4fc01daae5a5	927	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	92:4fc01daae5a5	928	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	92:4fc01daae5a5	929	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	930	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	931	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	932
bogdanm	92:4fc01daae5a5	933	/* Bit 3 : Enable interrupt on DONE event. */
bogdanm	92:4fc01daae5a5	934	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	92:4fc01daae5a5	935	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	92:4fc01daae5a5	936	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	937	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	938	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	939
bogdanm	92:4fc01daae5a5	940	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
bogdanm	92:4fc01daae5a5	941	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	942	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	943	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	944	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	945	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	946
bogdanm	92:4fc01daae5a5	947	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
bogdanm	92:4fc01daae5a5	948	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	949	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	950	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	951	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	952	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	953
bogdanm	92:4fc01daae5a5	954	/* Register: CLOCK_INTENCLR */
bogdanm	92:4fc01daae5a5	955	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	956
bogdanm	92:4fc01daae5a5	957	/* Bit 4 : Disable interrupt on CTTO event. */
bogdanm	92:4fc01daae5a5	958	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	92:4fc01daae5a5	959	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	92:4fc01daae5a5	960	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	961	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	962	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	963
bogdanm	92:4fc01daae5a5	964	/* Bit 3 : Disable interrupt on DONE event. */
bogdanm	92:4fc01daae5a5	965	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	92:4fc01daae5a5	966	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	92:4fc01daae5a5	967	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	968	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	969	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	970
bogdanm	92:4fc01daae5a5	971	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
bogdanm	92:4fc01daae5a5	972	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	977
bogdanm	92:4fc01daae5a5	978	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
bogdanm	92:4fc01daae5a5	979	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	92:4fc01daae5a5	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	984
Kojto	97:433970e64889	985	/* Register: CLOCK_HFCLKRUN */
Kojto	97:433970e64889	986	/* Description: Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	987
Kojto	97:433970e64889	988	/* Bit 0 : Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	989	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	990	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	991	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
Kojto	97:433970e64889	992	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
Kojto	97:433970e64889	993
bogdanm	92:4fc01daae5a5	994	/* Register: CLOCK_HFCLKSTAT */
bogdanm	92:4fc01daae5a5	995	/* Description: High frequency clock status. */
bogdanm	92:4fc01daae5a5	996
bogdanm	92:4fc01daae5a5	997	/* Bit 16 : State for the HFCLK. */
bogdanm	92:4fc01daae5a5	998	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	92:4fc01daae5a5	999	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	92:4fc01daae5a5	1000	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
bogdanm	92:4fc01daae5a5	1001	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
bogdanm	92:4fc01daae5a5	1002
bogdanm	92:4fc01daae5a5	1003	/* Bit 0 : Active clock source for the HF clock. */
bogdanm	92:4fc01daae5a5	1004	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	92:4fc01daae5a5	1005	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	92:4fc01daae5a5	1006	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
bogdanm	92:4fc01daae5a5	1007	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
bogdanm	92:4fc01daae5a5	1008
Kojto	97:433970e64889	1009	/* Register: CLOCK_LFCLKRUN */
Kojto	97:433970e64889	1010	/* Description: Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1011
Kojto	97:433970e64889	1012	/* Bit 0 : Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1013	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	1014	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	1015	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
Kojto	97:433970e64889	1016	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
Kojto	97:433970e64889	1017
bogdanm	92:4fc01daae5a5	1018	/* Register: CLOCK_LFCLKSTAT */
bogdanm	92:4fc01daae5a5	1019	/* Description: Low frequency clock status. */
bogdanm	92:4fc01daae5a5	1020
bogdanm	92:4fc01daae5a5	1021	/* Bit 16 : State for the LF clock. */
bogdanm	92:4fc01daae5a5	1022	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	92:4fc01daae5a5	1023	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	92:4fc01daae5a5	1024	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
bogdanm	92:4fc01daae5a5	1025	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
bogdanm	92:4fc01daae5a5	1026
bogdanm	92:4fc01daae5a5	1027	/* Bits 1..0 : Active clock source for the LF clock. */
bogdanm	92:4fc01daae5a5	1028	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	92:4fc01daae5a5	1029	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	92:4fc01daae5a5	1030	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
bogdanm	92:4fc01daae5a5	1031	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
bogdanm	92:4fc01daae5a5	1032	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
bogdanm	92:4fc01daae5a5	1033
Kojto	97:433970e64889	1034	/* Register: CLOCK_LFCLKSRCCOPY */
Kojto	97:433970e64889	1035	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1036
Kojto	97:433970e64889	1037	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1038	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	97:433970e64889	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	97:433970e64889	1040	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	97:433970e64889	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	97:433970e64889	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	97:433970e64889	1043
bogdanm	92:4fc01daae5a5	1044	/* Register: CLOCK_LFCLKSRC */
bogdanm	92:4fc01daae5a5	1045	/* Description: Clock source for the LFCLK clock. */
bogdanm	92:4fc01daae5a5	1046
bogdanm	92:4fc01daae5a5	1047	/* Bits 1..0 : Clock source. */
bogdanm	92:4fc01daae5a5	1048	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	92:4fc01daae5a5	1049	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	92:4fc01daae5a5	1050	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
bogdanm	92:4fc01daae5a5	1051	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
bogdanm	92:4fc01daae5a5	1052	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
bogdanm	92:4fc01daae5a5	1053
bogdanm	92:4fc01daae5a5	1054	/* Register: CLOCK_CTIV */
bogdanm	92:4fc01daae5a5	1055	/* Description: Calibration timer interval. */
bogdanm	92:4fc01daae5a5	1056
bogdanm	92:4fc01daae5a5	1057	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
bogdanm	92:4fc01daae5a5	1058	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
bogdanm	92:4fc01daae5a5	1059	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
bogdanm	92:4fc01daae5a5	1060
bogdanm	92:4fc01daae5a5	1061	/* Register: CLOCK_XTALFREQ */
bogdanm	92:4fc01daae5a5	1062	/* Description: Crystal frequency. */
bogdanm	92:4fc01daae5a5	1063
bogdanm	92:4fc01daae5a5	1064	/* Bits 7..0 : External Xtal frequency selection. */
bogdanm	92:4fc01daae5a5	1065	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	92:4fc01daae5a5	1066	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	97:433970e64889	1067	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
Kojto	97:433970e64889	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
bogdanm	92:4fc01daae5a5	1069
bogdanm	92:4fc01daae5a5	1070
bogdanm	92:4fc01daae5a5	1071	/* Peripheral: ECB */
bogdanm	92:4fc01daae5a5	1072	/* Description: AES ECB Mode Encryption. */
bogdanm	92:4fc01daae5a5	1073
bogdanm	92:4fc01daae5a5	1074	/* Register: ECB_INTENSET */
bogdanm	92:4fc01daae5a5	1075	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	1076
bogdanm	92:4fc01daae5a5	1077	/* Bit 1 : Enable interrupt on ERRORECB event. */
bogdanm	92:4fc01daae5a5	1078	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	92:4fc01daae5a5	1079	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	92:4fc01daae5a5	1080	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	1081	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	1082	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	1083
bogdanm	92:4fc01daae5a5	1084	/* Bit 0 : Enable interrupt on ENDECB event. */
bogdanm	92:4fc01daae5a5	1085	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	92:4fc01daae5a5	1086	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	92:4fc01daae5a5	1087	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	1088	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	1089	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	1090
bogdanm	92:4fc01daae5a5	1091	/* Register: ECB_INTENCLR */
bogdanm	92:4fc01daae5a5	1092	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	1093
bogdanm	92:4fc01daae5a5	1094	/* Bit 1 : Disable interrupt on ERRORECB event. */
bogdanm	92:4fc01daae5a5	1095	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	92:4fc01daae5a5	1096	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	92:4fc01daae5a5	1097	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	1098	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	1099	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	1100
bogdanm	92:4fc01daae5a5	1101	/* Bit 0 : Disable interrupt on ENDECB event. */
bogdanm	92:4fc01daae5a5	1102	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	92:4fc01daae5a5	1103	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	92:4fc01daae5a5	1104	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	1105	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	1106	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	1107
bogdanm	92:4fc01daae5a5	1108	/* Register: ECB_POWER */
bogdanm	92:4fc01daae5a5	1109	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	1110
bogdanm	92:4fc01daae5a5	1111	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	1112	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	1113	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	1114	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	1115	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	1116
bogdanm	92:4fc01daae5a5	1117
bogdanm	92:4fc01daae5a5	1118	/* Peripheral: FICR */
bogdanm	92:4fc01daae5a5	1119	/* Description: Factory Information Configuration. */
bogdanm	92:4fc01daae5a5	1120
bogdanm	92:4fc01daae5a5	1121	/* Register: FICR_PPFC */
bogdanm	92:4fc01daae5a5	1122	/* Description: Pre-programmed factory code present. */
bogdanm	92:4fc01daae5a5	1123
bogdanm	92:4fc01daae5a5	1124	/* Bits 7..0 : Pre-programmed factory code present. */
bogdanm	92:4fc01daae5a5	1125	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
bogdanm	92:4fc01daae5a5	1126	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
bogdanm	92:4fc01daae5a5	1127	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
bogdanm	92:4fc01daae5a5	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
bogdanm	92:4fc01daae5a5	1129
bogdanm	92:4fc01daae5a5	1130	/* Register: FICR_CONFIGID */
bogdanm	92:4fc01daae5a5	1131	/* Description: Configuration identifier. */
bogdanm	92:4fc01daae5a5	1132
bogdanm	92:4fc01daae5a5	1133	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
bogdanm	92:4fc01daae5a5	1134	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
bogdanm	92:4fc01daae5a5	1135	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	92:4fc01daae5a5	1136
bogdanm	92:4fc01daae5a5	1137	/* Bits 15..0 : Hardware Identification Number. */
bogdanm	92:4fc01daae5a5	1138	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
bogdanm	92:4fc01daae5a5	1139	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
bogdanm	92:4fc01daae5a5	1140
bogdanm	92:4fc01daae5a5	1141	/* Register: FICR_DEVICEADDRTYPE */
bogdanm	92:4fc01daae5a5	1142	/* Description: Device address type. */
bogdanm	92:4fc01daae5a5	1143
bogdanm	92:4fc01daae5a5	1144	/* Bit 0 : Device address type. */
bogdanm	92:4fc01daae5a5	1145	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
bogdanm	92:4fc01daae5a5	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
bogdanm	92:4fc01daae5a5	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
bogdanm	92:4fc01daae5a5	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
bogdanm	92:4fc01daae5a5	1149
bogdanm	92:4fc01daae5a5	1150	/* Register: FICR_OVERRIDEEN */
bogdanm	92:4fc01daae5a5	1151	/* Description: Radio calibration override enable. */
bogdanm	92:4fc01daae5a5	1152
bogdanm	92:4fc01daae5a5	1153	/* Bit 3 : Override default values for BLE_1Mbit mode. */
bogdanm	92:4fc01daae5a5	1154	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
bogdanm	92:4fc01daae5a5	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
bogdanm	92:4fc01daae5a5	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
bogdanm	92:4fc01daae5a5	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
bogdanm	92:4fc01daae5a5	1158
Kojto	97:433970e64889	1159	/* Bit 0 : Override default values for NRF_1Mbit mode. */
Kojto	97:433970e64889	1160	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
Kojto	97:433970e64889	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
Kojto	97:433970e64889	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1164
Kojto	97:433970e64889	1165	/* Register: FICR_INFO_PART */
Kojto	97:433970e64889	1166	/* Description: Part code */
Kojto	97:433970e64889	1167
Kojto	97:433970e64889	1168	/* Bits 31..0 : Part code */
Kojto	97:433970e64889	1169	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
Kojto	97:433970e64889	1170	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
Kojto	97:433970e64889	1171	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
Kojto	97:433970e64889	1172	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
Kojto	97:433970e64889	1173	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1174
Kojto	97:433970e64889	1175	/* Register: FICR_INFO_VARIANT */
Kojto	97:433970e64889	1176	/* Description: Part variant */
Kojto	97:433970e64889	1177
Kojto	97:433970e64889	1178	/* Bits 31..0 : Part variant */
Kojto	97:433970e64889	1179	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
Kojto	97:433970e64889	1180	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
Kojto	97:433970e64889	1181	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
Kojto	97:433970e64889	1182	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
Kojto	97:433970e64889	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
Kojto	97:433970e64889	1184	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1185
Kojto	97:433970e64889	1186	/* Register: FICR_INFO_PACKAGE */
Kojto	97:433970e64889	1187	/* Description: Package option */
Kojto	97:433970e64889	1188
Kojto	97:433970e64889	1189	/* Bits 31..0 : Package option */
Kojto	97:433970e64889	1190	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
Kojto	97:433970e64889	1191	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
Kojto	97:433970e64889	1192	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
Kojto	97:433970e64889	1193	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
Kojto	97:433970e64889	1194	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
Kojto	97:433970e64889	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
Kojto	97:433970e64889	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
Kojto	97:433970e64889	1197	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1198
Kojto	97:433970e64889	1199	/* Register: FICR_INFO_RAM */
Kojto	97:433970e64889	1200	/* Description: RAM variant */
Kojto	97:433970e64889	1201
Kojto	97:433970e64889	1202	/* Bits 31..0 : RAM variant */
Kojto	97:433970e64889	1203	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
Kojto	97:433970e64889	1204	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
Kojto	97:433970e64889	1205	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1206	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
Kojto	97:433970e64889	1207	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
Kojto	97:433970e64889	1208
Kojto	97:433970e64889	1209	/* Register: FICR_INFO_FLASH */
Kojto	97:433970e64889	1210	/* Description: Flash variant */
Kojto	97:433970e64889	1211
Kojto	97:433970e64889	1212	/* Bits 31..0 : Flash variant */
Kojto	97:433970e64889	1213	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
Kojto	97:433970e64889	1214	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
Kojto	97:433970e64889	1215	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1216	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
Kojto	97:433970e64889	1217	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
Kojto	97:433970e64889	1218
bogdanm	92:4fc01daae5a5	1219
bogdanm	92:4fc01daae5a5	1220	/* Peripheral: GPIO */
bogdanm	92:4fc01daae5a5	1221	/* Description: General purpose input and output. */
bogdanm	92:4fc01daae5a5	1222
bogdanm	92:4fc01daae5a5	1223	/* Register: GPIO_OUT */
bogdanm	92:4fc01daae5a5	1224	/* Description: Write GPIO port. */
bogdanm	92:4fc01daae5a5	1225
bogdanm	92:4fc01daae5a5	1226	/* Bit 31 : Pin 31. */
bogdanm	92:4fc01daae5a5	1227	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	1228	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	1229	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1230	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1231
bogdanm	92:4fc01daae5a5	1232	/* Bit 30 : Pin 30. */
bogdanm	92:4fc01daae5a5	1233	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	1234	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	1235	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1236	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1237
bogdanm	92:4fc01daae5a5	1238	/* Bit 29 : Pin 29. */
bogdanm	92:4fc01daae5a5	1239	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	1240	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	1241	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1242	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1243
bogdanm	92:4fc01daae5a5	1244	/* Bit 28 : Pin 28. */
bogdanm	92:4fc01daae5a5	1245	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	1246	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	1247	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1248	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1249
bogdanm	92:4fc01daae5a5	1250	/* Bit 27 : Pin 27. */
bogdanm	92:4fc01daae5a5	1251	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	1252	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	1253	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1254	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1255
bogdanm	92:4fc01daae5a5	1256	/* Bit 26 : Pin 26. */
bogdanm	92:4fc01daae5a5	1257	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	1258	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	1259	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1260	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1261
bogdanm	92:4fc01daae5a5	1262	/* Bit 25 : Pin 25. */
bogdanm	92:4fc01daae5a5	1263	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	1264	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	1265	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1266	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1267
bogdanm	92:4fc01daae5a5	1268	/* Bit 24 : Pin 24. */
bogdanm	92:4fc01daae5a5	1269	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	1270	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	1271	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1272	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1273
bogdanm	92:4fc01daae5a5	1274	/* Bit 23 : Pin 23. */
bogdanm	92:4fc01daae5a5	1275	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	1276	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	1277	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1278	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1279
bogdanm	92:4fc01daae5a5	1280	/* Bit 22 : Pin 22. */
bogdanm	92:4fc01daae5a5	1281	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	1282	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	1283	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1284	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1285
bogdanm	92:4fc01daae5a5	1286	/* Bit 21 : Pin 21. */
bogdanm	92:4fc01daae5a5	1287	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	1288	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	1289	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1290	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1291
bogdanm	92:4fc01daae5a5	1292	/* Bit 20 : Pin 20. */
bogdanm	92:4fc01daae5a5	1293	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	1294	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	1295	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1296	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1297
bogdanm	92:4fc01daae5a5	1298	/* Bit 19 : Pin 19. */
bogdanm	92:4fc01daae5a5	1299	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	1300	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	1301	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1302	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1303
bogdanm	92:4fc01daae5a5	1304	/* Bit 18 : Pin 18. */
bogdanm	92:4fc01daae5a5	1305	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	1306	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	1307	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1308	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1309
bogdanm	92:4fc01daae5a5	1310	/* Bit 17 : Pin 17. */
bogdanm	92:4fc01daae5a5	1311	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	1312	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	1313	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1314	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1315
bogdanm	92:4fc01daae5a5	1316	/* Bit 16 : Pin 16. */
bogdanm	92:4fc01daae5a5	1317	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	1318	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	1319	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1320	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1321
bogdanm	92:4fc01daae5a5	1322	/* Bit 15 : Pin 15. */
bogdanm	92:4fc01daae5a5	1323	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	1324	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	1325	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1326	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1327
bogdanm	92:4fc01daae5a5	1328	/* Bit 14 : Pin 14. */
bogdanm	92:4fc01daae5a5	1329	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	1330	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	1331	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1332	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1333
bogdanm	92:4fc01daae5a5	1334	/* Bit 13 : Pin 13. */
bogdanm	92:4fc01daae5a5	1335	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	1336	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	1337	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1338	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1339
bogdanm	92:4fc01daae5a5	1340	/* Bit 12 : Pin 12. */
bogdanm	92:4fc01daae5a5	1341	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	1342	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	1343	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1344	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1345
bogdanm	92:4fc01daae5a5	1346	/* Bit 11 : Pin 11. */
bogdanm	92:4fc01daae5a5	1347	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	1348	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	1349	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1350	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1351
bogdanm	92:4fc01daae5a5	1352	/* Bit 10 : Pin 10. */
bogdanm	92:4fc01daae5a5	1353	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	1354	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	1355	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1356	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1357
bogdanm	92:4fc01daae5a5	1358	/* Bit 9 : Pin 9. */
bogdanm	92:4fc01daae5a5	1359	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	1360	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	1361	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1362	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1363
bogdanm	92:4fc01daae5a5	1364	/* Bit 8 : Pin 8. */
bogdanm	92:4fc01daae5a5	1365	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	1366	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	1367	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1368	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1369
bogdanm	92:4fc01daae5a5	1370	/* Bit 7 : Pin 7. */
bogdanm	92:4fc01daae5a5	1371	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	1372	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	1373	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1374	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1375
bogdanm	92:4fc01daae5a5	1376	/* Bit 6 : Pin 6. */
bogdanm	92:4fc01daae5a5	1377	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	1378	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	1379	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1380	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1381
bogdanm	92:4fc01daae5a5	1382	/* Bit 5 : Pin 5. */
bogdanm	92:4fc01daae5a5	1383	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	1384	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	1385	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1386	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1387
bogdanm	92:4fc01daae5a5	1388	/* Bit 4 : Pin 4. */
bogdanm	92:4fc01daae5a5	1389	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	1390	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	1391	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1392	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1393
bogdanm	92:4fc01daae5a5	1394	/* Bit 3 : Pin 3. */
bogdanm	92:4fc01daae5a5	1395	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	1396	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	1397	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1398	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1399
bogdanm	92:4fc01daae5a5	1400	/* Bit 2 : Pin 2. */
bogdanm	92:4fc01daae5a5	1401	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	1402	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	1403	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1404	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1405
bogdanm	92:4fc01daae5a5	1406	/* Bit 1 : Pin 1. */
bogdanm	92:4fc01daae5a5	1407	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	1408	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	1409	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1410	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1411
bogdanm	92:4fc01daae5a5	1412	/* Bit 0 : Pin 0. */
bogdanm	92:4fc01daae5a5	1413	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	1414	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	1415	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1416	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1417
bogdanm	92:4fc01daae5a5	1418	/* Register: GPIO_OUTSET */
bogdanm	92:4fc01daae5a5	1419	/* Description: Set individual bits in GPIO port. */
bogdanm	92:4fc01daae5a5	1420
bogdanm	92:4fc01daae5a5	1421	/* Bit 31 : Pin 31. */
bogdanm	92:4fc01daae5a5	1422	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	1423	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	1424	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1425	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1426	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1427
bogdanm	92:4fc01daae5a5	1428	/* Bit 30 : Pin 30. */
bogdanm	92:4fc01daae5a5	1429	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	1430	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	1431	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1432	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1433	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1434
bogdanm	92:4fc01daae5a5	1435	/* Bit 29 : Pin 29. */
bogdanm	92:4fc01daae5a5	1436	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	1437	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	1438	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1439	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1440	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1441
bogdanm	92:4fc01daae5a5	1442	/* Bit 28 : Pin 28. */
bogdanm	92:4fc01daae5a5	1443	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	1444	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	1445	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1446	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1447	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1448
bogdanm	92:4fc01daae5a5	1449	/* Bit 27 : Pin 27. */
bogdanm	92:4fc01daae5a5	1450	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	1451	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	1452	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1453	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1454	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1455
bogdanm	92:4fc01daae5a5	1456	/* Bit 26 : Pin 26. */
bogdanm	92:4fc01daae5a5	1457	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	1458	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	1459	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1460	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1461	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1462
bogdanm	92:4fc01daae5a5	1463	/* Bit 25 : Pin 25. */
bogdanm	92:4fc01daae5a5	1464	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	1465	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	1466	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1467	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1468	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1469
bogdanm	92:4fc01daae5a5	1470	/* Bit 24 : Pin 24. */
bogdanm	92:4fc01daae5a5	1471	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	1472	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	1473	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1474	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1475	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1476
bogdanm	92:4fc01daae5a5	1477	/* Bit 23 : Pin 23. */
bogdanm	92:4fc01daae5a5	1478	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	1479	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	1480	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1481	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1482	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1483
bogdanm	92:4fc01daae5a5	1484	/* Bit 22 : Pin 22. */
bogdanm	92:4fc01daae5a5	1485	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	1486	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	1487	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1488	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1489	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1490
bogdanm	92:4fc01daae5a5	1491	/* Bit 21 : Pin 21. */
bogdanm	92:4fc01daae5a5	1492	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	1493	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	1494	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1495	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1496	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1497
bogdanm	92:4fc01daae5a5	1498	/* Bit 20 : Pin 20. */
bogdanm	92:4fc01daae5a5	1499	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	1500	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	1501	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1502	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1503	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1504
bogdanm	92:4fc01daae5a5	1505	/* Bit 19 : Pin 19. */
bogdanm	92:4fc01daae5a5	1506	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	1507	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	1508	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1509	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1510	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1511
bogdanm	92:4fc01daae5a5	1512	/* Bit 18 : Pin 18. */
bogdanm	92:4fc01daae5a5	1513	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	1514	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	1515	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1516	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1517	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1518
bogdanm	92:4fc01daae5a5	1519	/* Bit 17 : Pin 17. */
bogdanm	92:4fc01daae5a5	1520	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	1521	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	1522	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1523	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1524	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1525
bogdanm	92:4fc01daae5a5	1526	/* Bit 16 : Pin 16. */
bogdanm	92:4fc01daae5a5	1527	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	1528	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	1529	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1530	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1531	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1532
bogdanm	92:4fc01daae5a5	1533	/* Bit 15 : Pin 15. */
bogdanm	92:4fc01daae5a5	1534	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	1535	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	1536	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1537	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1538	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1539
bogdanm	92:4fc01daae5a5	1540	/* Bit 14 : Pin 14. */
bogdanm	92:4fc01daae5a5	1541	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	1542	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	1543	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1544	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1545	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1546
bogdanm	92:4fc01daae5a5	1547	/* Bit 13 : Pin 13. */
bogdanm	92:4fc01daae5a5	1548	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	1549	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	1550	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1551	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1552	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1553
bogdanm	92:4fc01daae5a5	1554	/* Bit 12 : Pin 12. */
bogdanm	92:4fc01daae5a5	1555	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	1556	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	1557	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1558	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1559	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1560
bogdanm	92:4fc01daae5a5	1561	/* Bit 11 : Pin 11. */
bogdanm	92:4fc01daae5a5	1562	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	1563	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	1564	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1565	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1566	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1567
bogdanm	92:4fc01daae5a5	1568	/* Bit 10 : Pin 10. */
bogdanm	92:4fc01daae5a5	1569	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	1570	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	1571	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1572	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1573	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1574
bogdanm	92:4fc01daae5a5	1575	/* Bit 9 : Pin 9. */
bogdanm	92:4fc01daae5a5	1576	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	1577	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	1578	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1579	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1580	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1581
bogdanm	92:4fc01daae5a5	1582	/* Bit 8 : Pin 8. */
bogdanm	92:4fc01daae5a5	1583	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	1584	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	1585	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1586	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1587	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1588
bogdanm	92:4fc01daae5a5	1589	/* Bit 7 : Pin 7. */
bogdanm	92:4fc01daae5a5	1590	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	1591	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	1592	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1593	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1594	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1595
bogdanm	92:4fc01daae5a5	1596	/* Bit 6 : Pin 6. */
bogdanm	92:4fc01daae5a5	1597	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	1598	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	1599	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1600	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1601	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1602
bogdanm	92:4fc01daae5a5	1603	/* Bit 5 : Pin 5. */
bogdanm	92:4fc01daae5a5	1604	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	1605	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	1606	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1607	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1608	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1609
bogdanm	92:4fc01daae5a5	1610	/* Bit 4 : Pin 4. */
bogdanm	92:4fc01daae5a5	1611	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	1612	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	1613	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1614	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1615	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1616
bogdanm	92:4fc01daae5a5	1617	/* Bit 3 : Pin 3. */
bogdanm	92:4fc01daae5a5	1618	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	1619	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	1620	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1621	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1622	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1623
bogdanm	92:4fc01daae5a5	1624	/* Bit 2 : Pin 2. */
bogdanm	92:4fc01daae5a5	1625	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	1626	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	1627	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1628	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1629	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1630
bogdanm	92:4fc01daae5a5	1631	/* Bit 1 : Pin 1. */
bogdanm	92:4fc01daae5a5	1632	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	1633	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	1634	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1635	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1636	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1637
bogdanm	92:4fc01daae5a5	1638	/* Bit 0 : Pin 0. */
bogdanm	92:4fc01daae5a5	1639	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	1640	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	1641	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1642	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1643	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
bogdanm	92:4fc01daae5a5	1644
bogdanm	92:4fc01daae5a5	1645	/* Register: GPIO_OUTCLR */
bogdanm	92:4fc01daae5a5	1646	/* Description: Clear individual bits in GPIO port. */
bogdanm	92:4fc01daae5a5	1647
bogdanm	92:4fc01daae5a5	1648	/* Bit 31 : Pin 31. */
bogdanm	92:4fc01daae5a5	1649	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	1650	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	1651	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1652	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1653	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1654
bogdanm	92:4fc01daae5a5	1655	/* Bit 30 : Pin 30. */
bogdanm	92:4fc01daae5a5	1656	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	1657	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	1658	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1659	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1660	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1661
bogdanm	92:4fc01daae5a5	1662	/* Bit 29 : Pin 29. */
bogdanm	92:4fc01daae5a5	1663	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	1664	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	1665	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1666	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1667	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1668
bogdanm	92:4fc01daae5a5	1669	/* Bit 28 : Pin 28. */
bogdanm	92:4fc01daae5a5	1670	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	1671	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	1672	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1673	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1674	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1675
bogdanm	92:4fc01daae5a5	1676	/* Bit 27 : Pin 27. */
bogdanm	92:4fc01daae5a5	1677	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	1678	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	1679	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1680	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1681	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1682
bogdanm	92:4fc01daae5a5	1683	/* Bit 26 : Pin 26. */
bogdanm	92:4fc01daae5a5	1684	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	1685	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	1686	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1687	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1688	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1689
bogdanm	92:4fc01daae5a5	1690	/* Bit 25 : Pin 25. */
bogdanm	92:4fc01daae5a5	1691	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	1692	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	1693	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1694	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1695	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1696
bogdanm	92:4fc01daae5a5	1697	/* Bit 24 : Pin 24. */
bogdanm	92:4fc01daae5a5	1698	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	1699	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	1700	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1701	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1702	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1703
bogdanm	92:4fc01daae5a5	1704	/* Bit 23 : Pin 23. */
bogdanm	92:4fc01daae5a5	1705	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	1706	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	1707	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1708	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1709	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1710
bogdanm	92:4fc01daae5a5	1711	/* Bit 22 : Pin 22. */
bogdanm	92:4fc01daae5a5	1712	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	1713	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	1714	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1715	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1716	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1717
bogdanm	92:4fc01daae5a5	1718	/* Bit 21 : Pin 21. */
bogdanm	92:4fc01daae5a5	1719	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	1720	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	1721	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1722	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1723	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1724
bogdanm	92:4fc01daae5a5	1725	/* Bit 20 : Pin 20. */
bogdanm	92:4fc01daae5a5	1726	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	1727	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	1728	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1729	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1730	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1731
bogdanm	92:4fc01daae5a5	1732	/* Bit 19 : Pin 19. */
bogdanm	92:4fc01daae5a5	1733	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	1734	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	1735	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1736	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1737	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1738
bogdanm	92:4fc01daae5a5	1739	/* Bit 18 : Pin 18. */
bogdanm	92:4fc01daae5a5	1740	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	1741	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	1742	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1743	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1744	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1745
bogdanm	92:4fc01daae5a5	1746	/* Bit 17 : Pin 17. */
bogdanm	92:4fc01daae5a5	1747	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	1748	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	1749	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1750	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1751	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1752
bogdanm	92:4fc01daae5a5	1753	/* Bit 16 : Pin 16. */
bogdanm	92:4fc01daae5a5	1754	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	1755	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	1756	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1757	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1758	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1759
bogdanm	92:4fc01daae5a5	1760	/* Bit 15 : Pin 15. */
bogdanm	92:4fc01daae5a5	1761	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	1762	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	1763	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1764	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1765	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1766
bogdanm	92:4fc01daae5a5	1767	/* Bit 14 : Pin 14. */
bogdanm	92:4fc01daae5a5	1768	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	1769	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	1770	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1771	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1772	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1773
bogdanm	92:4fc01daae5a5	1774	/* Bit 13 : Pin 13. */
bogdanm	92:4fc01daae5a5	1775	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	1776	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	1777	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1778	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1779	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1780
bogdanm	92:4fc01daae5a5	1781	/* Bit 12 : Pin 12. */
bogdanm	92:4fc01daae5a5	1782	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	1783	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	1784	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1785	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1786	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1787
bogdanm	92:4fc01daae5a5	1788	/* Bit 11 : Pin 11. */
bogdanm	92:4fc01daae5a5	1789	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	1790	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	1791	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1792	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1793	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1794
bogdanm	92:4fc01daae5a5	1795	/* Bit 10 : Pin 10. */
bogdanm	92:4fc01daae5a5	1796	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	1797	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	1798	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1799	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1800	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1801
bogdanm	92:4fc01daae5a5	1802	/* Bit 9 : Pin 9. */
bogdanm	92:4fc01daae5a5	1803	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	1804	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	1805	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1806	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1807	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1808
bogdanm	92:4fc01daae5a5	1809	/* Bit 8 : Pin 8. */
bogdanm	92:4fc01daae5a5	1810	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	1811	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	1812	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1813	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1814	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1815
bogdanm	92:4fc01daae5a5	1816	/* Bit 7 : Pin 7. */
bogdanm	92:4fc01daae5a5	1817	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	1818	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	1819	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1820	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1821	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1822
bogdanm	92:4fc01daae5a5	1823	/* Bit 6 : Pin 6. */
bogdanm	92:4fc01daae5a5	1824	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	1825	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	1826	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1827	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1828	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1829
bogdanm	92:4fc01daae5a5	1830	/* Bit 5 : Pin 5. */
bogdanm	92:4fc01daae5a5	1831	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	1832	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	1833	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1834	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1835	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1836
bogdanm	92:4fc01daae5a5	1837	/* Bit 4 : Pin 4. */
bogdanm	92:4fc01daae5a5	1838	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	1839	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	1840	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1841	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1842	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1843
bogdanm	92:4fc01daae5a5	1844	/* Bit 3 : Pin 3. */
bogdanm	92:4fc01daae5a5	1845	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	1846	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	1847	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1848	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1849	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1850
bogdanm	92:4fc01daae5a5	1851	/* Bit 2 : Pin 2. */
bogdanm	92:4fc01daae5a5	1852	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	1853	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	1854	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1855	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1856	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1857
bogdanm	92:4fc01daae5a5	1858	/* Bit 1 : Pin 1. */
bogdanm	92:4fc01daae5a5	1859	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	1860	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	1861	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1862	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1863	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1864
bogdanm	92:4fc01daae5a5	1865	/* Bit 0 : Pin 0. */
bogdanm	92:4fc01daae5a5	1866	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	1867	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	1868	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	92:4fc01daae5a5	1869	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	92:4fc01daae5a5	1870	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
bogdanm	92:4fc01daae5a5	1871
bogdanm	92:4fc01daae5a5	1872	/* Register: GPIO_IN */
bogdanm	92:4fc01daae5a5	1873	/* Description: Read GPIO port. */
bogdanm	92:4fc01daae5a5	1874
bogdanm	92:4fc01daae5a5	1875	/* Bit 31 : Pin 31. */
bogdanm	92:4fc01daae5a5	1876	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	1877	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	1878	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1879	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1880
bogdanm	92:4fc01daae5a5	1881	/* Bit 30 : Pin 30. */
bogdanm	92:4fc01daae5a5	1882	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	1883	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	1884	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1885	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1886
bogdanm	92:4fc01daae5a5	1887	/* Bit 29 : Pin 29. */
bogdanm	92:4fc01daae5a5	1888	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	1889	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	1890	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1891	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1892
bogdanm	92:4fc01daae5a5	1893	/* Bit 28 : Pin 28. */
bogdanm	92:4fc01daae5a5	1894	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	1895	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	1896	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1897	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1898
bogdanm	92:4fc01daae5a5	1899	/* Bit 27 : Pin 27. */
bogdanm	92:4fc01daae5a5	1900	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	1901	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	1902	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1903	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1904
bogdanm	92:4fc01daae5a5	1905	/* Bit 26 : Pin 26. */
bogdanm	92:4fc01daae5a5	1906	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	1907	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	1908	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1909	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1910
bogdanm	92:4fc01daae5a5	1911	/* Bit 25 : Pin 25. */
bogdanm	92:4fc01daae5a5	1912	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	1913	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	1914	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1915	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1916
bogdanm	92:4fc01daae5a5	1917	/* Bit 24 : Pin 24. */
bogdanm	92:4fc01daae5a5	1918	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	1919	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	1920	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1921	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1922
bogdanm	92:4fc01daae5a5	1923	/* Bit 23 : Pin 23. */
bogdanm	92:4fc01daae5a5	1924	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	1925	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	1926	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1927	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1928
bogdanm	92:4fc01daae5a5	1929	/* Bit 22 : Pin 22. */
bogdanm	92:4fc01daae5a5	1930	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	1931	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	1932	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1933	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1934
bogdanm	92:4fc01daae5a5	1935	/* Bit 21 : Pin 21. */
bogdanm	92:4fc01daae5a5	1936	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	1937	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	1938	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1939	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1940
bogdanm	92:4fc01daae5a5	1941	/* Bit 20 : Pin 20. */
bogdanm	92:4fc01daae5a5	1942	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	1943	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	1944	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1945	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1946
bogdanm	92:4fc01daae5a5	1947	/* Bit 19 : Pin 19. */
bogdanm	92:4fc01daae5a5	1948	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	1949	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	1950	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1951	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1952
bogdanm	92:4fc01daae5a5	1953	/* Bit 18 : Pin 18. */
bogdanm	92:4fc01daae5a5	1954	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	1955	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	1956	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1957	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1958
bogdanm	92:4fc01daae5a5	1959	/* Bit 17 : Pin 17. */
bogdanm	92:4fc01daae5a5	1960	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	1961	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	1962	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1963	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1964
bogdanm	92:4fc01daae5a5	1965	/* Bit 16 : Pin 16. */
bogdanm	92:4fc01daae5a5	1966	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	1967	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	1968	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1969	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1970
bogdanm	92:4fc01daae5a5	1971	/* Bit 15 : Pin 15. */
bogdanm	92:4fc01daae5a5	1972	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	1973	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	1974	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1975	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1976
bogdanm	92:4fc01daae5a5	1977	/* Bit 14 : Pin 14. */
bogdanm	92:4fc01daae5a5	1978	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	1979	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	1980	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1981	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1982
bogdanm	92:4fc01daae5a5	1983	/* Bit 13 : Pin 13. */
bogdanm	92:4fc01daae5a5	1984	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	1985	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	1986	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1987	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1988
bogdanm	92:4fc01daae5a5	1989	/* Bit 12 : Pin 12. */
bogdanm	92:4fc01daae5a5	1990	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	1991	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	1992	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1993	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	1994
bogdanm	92:4fc01daae5a5	1995	/* Bit 11 : Pin 11. */
bogdanm	92:4fc01daae5a5	1996	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	1997	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	1998	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	1999	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2000
bogdanm	92:4fc01daae5a5	2001	/* Bit 10 : Pin 10. */
bogdanm	92:4fc01daae5a5	2002	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	2003	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	2004	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2005	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2006
bogdanm	92:4fc01daae5a5	2007	/* Bit 9 : Pin 9. */
bogdanm	92:4fc01daae5a5	2008	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	2009	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	2010	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2011	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2012
bogdanm	92:4fc01daae5a5	2013	/* Bit 8 : Pin 8. */
bogdanm	92:4fc01daae5a5	2014	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	2015	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	2016	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2017	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2018
bogdanm	92:4fc01daae5a5	2019	/* Bit 7 : Pin 7. */
bogdanm	92:4fc01daae5a5	2020	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	2021	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	2022	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2023	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2024
bogdanm	92:4fc01daae5a5	2025	/* Bit 6 : Pin 6. */
bogdanm	92:4fc01daae5a5	2026	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	2027	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	2028	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2029	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2030
bogdanm	92:4fc01daae5a5	2031	/* Bit 5 : Pin 5. */
bogdanm	92:4fc01daae5a5	2032	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	2033	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	2034	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2035	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2036
bogdanm	92:4fc01daae5a5	2037	/* Bit 4 : Pin 4. */
bogdanm	92:4fc01daae5a5	2038	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	2039	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	2040	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2041	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2042
bogdanm	92:4fc01daae5a5	2043	/* Bit 3 : Pin 3. */
bogdanm	92:4fc01daae5a5	2044	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	2045	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	2046	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2047	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2048
bogdanm	92:4fc01daae5a5	2049	/* Bit 2 : Pin 2. */
bogdanm	92:4fc01daae5a5	2050	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	2051	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	2052	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2053	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2054
bogdanm	92:4fc01daae5a5	2055	/* Bit 1 : Pin 1. */
bogdanm	92:4fc01daae5a5	2056	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	2057	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	2058	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2059	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2060
bogdanm	92:4fc01daae5a5	2061	/* Bit 0 : Pin 0. */
bogdanm	92:4fc01daae5a5	2062	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	2063	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	2064	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
bogdanm	92:4fc01daae5a5	2065	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
bogdanm	92:4fc01daae5a5	2066
bogdanm	92:4fc01daae5a5	2067	/* Register: GPIO_DIR */
bogdanm	92:4fc01daae5a5	2068	/* Description: Direction of GPIO pins. */
bogdanm	92:4fc01daae5a5	2069
bogdanm	92:4fc01daae5a5	2070	/* Bit 31 : Pin 31. */
bogdanm	92:4fc01daae5a5	2071	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	2072	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	2073	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2074	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2075
bogdanm	92:4fc01daae5a5	2076	/* Bit 30 : Pin 30. */
bogdanm	92:4fc01daae5a5	2077	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	2078	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	2079	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2080	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2081
bogdanm	92:4fc01daae5a5	2082	/* Bit 29 : Pin 29. */
bogdanm	92:4fc01daae5a5	2083	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	2084	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	2085	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2086	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2087
bogdanm	92:4fc01daae5a5	2088	/* Bit 28 : Pin 28. */
bogdanm	92:4fc01daae5a5	2089	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	2090	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	2091	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2092	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2093
bogdanm	92:4fc01daae5a5	2094	/* Bit 27 : Pin 27. */
bogdanm	92:4fc01daae5a5	2095	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	2096	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	2097	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2098	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2099
bogdanm	92:4fc01daae5a5	2100	/* Bit 26 : Pin 26. */
bogdanm	92:4fc01daae5a5	2101	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	2102	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	2103	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2104	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2105
bogdanm	92:4fc01daae5a5	2106	/* Bit 25 : Pin 25. */
bogdanm	92:4fc01daae5a5	2107	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	2108	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	2109	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2110	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2111
bogdanm	92:4fc01daae5a5	2112	/* Bit 24 : Pin 24. */
bogdanm	92:4fc01daae5a5	2113	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	2114	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	2115	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2116	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2117
bogdanm	92:4fc01daae5a5	2118	/* Bit 23 : Pin 23. */
bogdanm	92:4fc01daae5a5	2119	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	2120	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	2121	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2122	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2123
bogdanm	92:4fc01daae5a5	2124	/* Bit 22 : Pin 22. */
bogdanm	92:4fc01daae5a5	2125	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	2126	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	2127	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2128	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2129
bogdanm	92:4fc01daae5a5	2130	/* Bit 21 : Pin 21. */
bogdanm	92:4fc01daae5a5	2131	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	2132	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	2133	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2134	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2135
bogdanm	92:4fc01daae5a5	2136	/* Bit 20 : Pin 20. */
bogdanm	92:4fc01daae5a5	2137	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	2138	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	2139	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2140	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2141
bogdanm	92:4fc01daae5a5	2142	/* Bit 19 : Pin 19. */
bogdanm	92:4fc01daae5a5	2143	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	2144	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	2145	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2146	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2147
bogdanm	92:4fc01daae5a5	2148	/* Bit 18 : Pin 18. */
bogdanm	92:4fc01daae5a5	2149	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	2150	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	2151	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2152	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2153
bogdanm	92:4fc01daae5a5	2154	/* Bit 17 : Pin 17. */
bogdanm	92:4fc01daae5a5	2155	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	2156	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	2157	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2158	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2159
bogdanm	92:4fc01daae5a5	2160	/* Bit 16 : Pin 16. */
bogdanm	92:4fc01daae5a5	2161	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	2162	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	2163	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2164	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2165
bogdanm	92:4fc01daae5a5	2166	/* Bit 15 : Pin 15. */
bogdanm	92:4fc01daae5a5	2167	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	2168	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	2169	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2170	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2171
bogdanm	92:4fc01daae5a5	2172	/* Bit 14 : Pin 14. */
bogdanm	92:4fc01daae5a5	2173	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	2174	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	2175	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2176	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2177
bogdanm	92:4fc01daae5a5	2178	/* Bit 13 : Pin 13. */
bogdanm	92:4fc01daae5a5	2179	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	2180	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	2181	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2182	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2183
bogdanm	92:4fc01daae5a5	2184	/* Bit 12 : Pin 12. */
bogdanm	92:4fc01daae5a5	2185	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	2186	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	2187	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2188	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2189
bogdanm	92:4fc01daae5a5	2190	/* Bit 11 : Pin 11. */
bogdanm	92:4fc01daae5a5	2191	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	2192	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	2193	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2194	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2195
bogdanm	92:4fc01daae5a5	2196	/* Bit 10 : Pin 10. */
bogdanm	92:4fc01daae5a5	2197	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	2198	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	2199	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2200	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2201
bogdanm	92:4fc01daae5a5	2202	/* Bit 9 : Pin 9. */
bogdanm	92:4fc01daae5a5	2203	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	2204	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	2205	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2206	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2207
bogdanm	92:4fc01daae5a5	2208	/* Bit 8 : Pin 8. */
bogdanm	92:4fc01daae5a5	2209	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	2210	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	2211	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2212	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2213
bogdanm	92:4fc01daae5a5	2214	/* Bit 7 : Pin 7. */
bogdanm	92:4fc01daae5a5	2215	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	2216	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	2217	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2218	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2219
bogdanm	92:4fc01daae5a5	2220	/* Bit 6 : Pin 6. */
bogdanm	92:4fc01daae5a5	2221	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	2222	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	2223	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2224	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2225
bogdanm	92:4fc01daae5a5	2226	/* Bit 5 : Pin 5. */
bogdanm	92:4fc01daae5a5	2227	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	2228	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	2229	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2230	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2231
bogdanm	92:4fc01daae5a5	2232	/* Bit 4 : Pin 4. */
bogdanm	92:4fc01daae5a5	2233	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	2234	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	2235	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2236	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2237
bogdanm	92:4fc01daae5a5	2238	/* Bit 3 : Pin 3. */
bogdanm	92:4fc01daae5a5	2239	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	2240	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	2241	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2242	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2243
bogdanm	92:4fc01daae5a5	2244	/* Bit 2 : Pin 2. */
bogdanm	92:4fc01daae5a5	2245	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	2246	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	2247	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2248	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2249
bogdanm	92:4fc01daae5a5	2250	/* Bit 1 : Pin 1. */
bogdanm	92:4fc01daae5a5	2251	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	2252	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	2253	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2254	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2255
bogdanm	92:4fc01daae5a5	2256	/* Bit 0 : Pin 0. */
bogdanm	92:4fc01daae5a5	2257	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	2258	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	2259	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2260	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2261
bogdanm	92:4fc01daae5a5	2262	/* Register: GPIO_DIRSET */
bogdanm	92:4fc01daae5a5	2263	/* Description: DIR set register. */
bogdanm	92:4fc01daae5a5	2264
bogdanm	92:4fc01daae5a5	2265	/* Bit 31 : Set as output pin 31. */
bogdanm	92:4fc01daae5a5	2266	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	2267	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	2268	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2269	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2270	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2271
bogdanm	92:4fc01daae5a5	2272	/* Bit 30 : Set as output pin 30. */
bogdanm	92:4fc01daae5a5	2273	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	2274	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	2275	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2276	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2277	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2278
bogdanm	92:4fc01daae5a5	2279	/* Bit 29 : Set as output pin 29. */
bogdanm	92:4fc01daae5a5	2280	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	2281	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	2282	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2283	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2284	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2285
bogdanm	92:4fc01daae5a5	2286	/* Bit 28 : Set as output pin 28. */
bogdanm	92:4fc01daae5a5	2287	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	2288	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	2289	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2290	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2291	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2292
bogdanm	92:4fc01daae5a5	2293	/* Bit 27 : Set as output pin 27. */
bogdanm	92:4fc01daae5a5	2294	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	2295	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	2296	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2297	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2298	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2299
bogdanm	92:4fc01daae5a5	2300	/* Bit 26 : Set as output pin 26. */
bogdanm	92:4fc01daae5a5	2301	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	2302	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	2303	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2304	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2305	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2306
bogdanm	92:4fc01daae5a5	2307	/* Bit 25 : Set as output pin 25. */
bogdanm	92:4fc01daae5a5	2308	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	2309	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	2310	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2311	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2312	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2313
bogdanm	92:4fc01daae5a5	2314	/* Bit 24 : Set as output pin 24. */
bogdanm	92:4fc01daae5a5	2315	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	2316	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	2317	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2318	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2319	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2320
bogdanm	92:4fc01daae5a5	2321	/* Bit 23 : Set as output pin 23. */
bogdanm	92:4fc01daae5a5	2322	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	2323	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	2324	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2325	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2326	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2327
bogdanm	92:4fc01daae5a5	2328	/* Bit 22 : Set as output pin 22. */
bogdanm	92:4fc01daae5a5	2329	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	2330	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	2331	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2332	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2333	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2334
bogdanm	92:4fc01daae5a5	2335	/* Bit 21 : Set as output pin 21. */
bogdanm	92:4fc01daae5a5	2336	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	2337	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	2338	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2339	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2340	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2341
bogdanm	92:4fc01daae5a5	2342	/* Bit 20 : Set as output pin 20. */
bogdanm	92:4fc01daae5a5	2343	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	2344	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	2345	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2346	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2347	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2348
bogdanm	92:4fc01daae5a5	2349	/* Bit 19 : Set as output pin 19. */
bogdanm	92:4fc01daae5a5	2350	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	2351	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	2352	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2353	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2354	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2355
bogdanm	92:4fc01daae5a5	2356	/* Bit 18 : Set as output pin 18. */
bogdanm	92:4fc01daae5a5	2357	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	2358	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	2359	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2360	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2361	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2362
bogdanm	92:4fc01daae5a5	2363	/* Bit 17 : Set as output pin 17. */
bogdanm	92:4fc01daae5a5	2364	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	2365	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	2366	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2367	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2368	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2369
bogdanm	92:4fc01daae5a5	2370	/* Bit 16 : Set as output pin 16. */
bogdanm	92:4fc01daae5a5	2371	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	2372	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	2373	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2374	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2375	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2376
bogdanm	92:4fc01daae5a5	2377	/* Bit 15 : Set as output pin 15. */
bogdanm	92:4fc01daae5a5	2378	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	2379	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	2380	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2381	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2382	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2383
bogdanm	92:4fc01daae5a5	2384	/* Bit 14 : Set as output pin 14. */
bogdanm	92:4fc01daae5a5	2385	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	2386	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	2387	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2388	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2389	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2390
bogdanm	92:4fc01daae5a5	2391	/* Bit 13 : Set as output pin 13. */
bogdanm	92:4fc01daae5a5	2392	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	2393	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	2394	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2395	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2396	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2397
bogdanm	92:4fc01daae5a5	2398	/* Bit 12 : Set as output pin 12. */
bogdanm	92:4fc01daae5a5	2399	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	2400	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	2401	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2402	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2403	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2404
bogdanm	92:4fc01daae5a5	2405	/* Bit 11 : Set as output pin 11. */
bogdanm	92:4fc01daae5a5	2406	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	2407	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	2408	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2409	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2410	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2411
bogdanm	92:4fc01daae5a5	2412	/* Bit 10 : Set as output pin 10. */
bogdanm	92:4fc01daae5a5	2413	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	2414	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	2415	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2416	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2417	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2418
bogdanm	92:4fc01daae5a5	2419	/* Bit 9 : Set as output pin 9. */
bogdanm	92:4fc01daae5a5	2420	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	2421	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	2422	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2423	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2424	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2425
bogdanm	92:4fc01daae5a5	2426	/* Bit 8 : Set as output pin 8. */
bogdanm	92:4fc01daae5a5	2427	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	2428	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	2429	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2430	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2431	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2432
bogdanm	92:4fc01daae5a5	2433	/* Bit 7 : Set as output pin 7. */
bogdanm	92:4fc01daae5a5	2434	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	2435	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	2436	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2437	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2438	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2439
bogdanm	92:4fc01daae5a5	2440	/* Bit 6 : Set as output pin 6. */
bogdanm	92:4fc01daae5a5	2441	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	2442	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	2443	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2444	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2445	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2446
bogdanm	92:4fc01daae5a5	2447	/* Bit 5 : Set as output pin 5. */
bogdanm	92:4fc01daae5a5	2448	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	2449	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	2450	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2451	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2452	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2453
bogdanm	92:4fc01daae5a5	2454	/* Bit 4 : Set as output pin 4. */
bogdanm	92:4fc01daae5a5	2455	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	2456	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	2457	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2458	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2459	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2460
bogdanm	92:4fc01daae5a5	2461	/* Bit 3 : Set as output pin 3. */
bogdanm	92:4fc01daae5a5	2462	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	2463	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	2464	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2465	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2466	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2467
bogdanm	92:4fc01daae5a5	2468	/* Bit 2 : Set as output pin 2. */
bogdanm	92:4fc01daae5a5	2469	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	2470	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	2471	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2472	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2473	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2474
bogdanm	92:4fc01daae5a5	2475	/* Bit 1 : Set as output pin 1. */
bogdanm	92:4fc01daae5a5	2476	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	2477	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	2478	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2479	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2480	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2481
bogdanm	92:4fc01daae5a5	2482	/* Bit 0 : Set as output pin 0. */
bogdanm	92:4fc01daae5a5	2483	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	2484	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	2485	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2486	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2487	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
bogdanm	92:4fc01daae5a5	2488
bogdanm	92:4fc01daae5a5	2489	/* Register: GPIO_DIRCLR */
bogdanm	92:4fc01daae5a5	2490	/* Description: DIR clear register. */
bogdanm	92:4fc01daae5a5	2491
bogdanm	92:4fc01daae5a5	2492	/* Bit 31 : Set as input pin 31. */
bogdanm	92:4fc01daae5a5	2493	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	92:4fc01daae5a5	2494	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	92:4fc01daae5a5	2495	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2496	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2497	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2498
bogdanm	92:4fc01daae5a5	2499	/* Bit 30 : Set as input pin 30. */
bogdanm	92:4fc01daae5a5	2500	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	92:4fc01daae5a5	2501	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	92:4fc01daae5a5	2502	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2503	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2504	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2505
bogdanm	92:4fc01daae5a5	2506	/* Bit 29 : Set as input pin 29. */
bogdanm	92:4fc01daae5a5	2507	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	92:4fc01daae5a5	2508	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	92:4fc01daae5a5	2509	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2510	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2511	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2512
bogdanm	92:4fc01daae5a5	2513	/* Bit 28 : Set as input pin 28. */
bogdanm	92:4fc01daae5a5	2514	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	92:4fc01daae5a5	2515	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	92:4fc01daae5a5	2516	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2517	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2518	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2519
bogdanm	92:4fc01daae5a5	2520	/* Bit 27 : Set as input pin 27. */
bogdanm	92:4fc01daae5a5	2521	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	92:4fc01daae5a5	2522	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	92:4fc01daae5a5	2523	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2524	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2525	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2526
bogdanm	92:4fc01daae5a5	2527	/* Bit 26 : Set as input pin 26. */
bogdanm	92:4fc01daae5a5	2528	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	92:4fc01daae5a5	2529	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	92:4fc01daae5a5	2530	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2531	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2532	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2533
bogdanm	92:4fc01daae5a5	2534	/* Bit 25 : Set as input pin 25. */
bogdanm	92:4fc01daae5a5	2535	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	92:4fc01daae5a5	2536	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	92:4fc01daae5a5	2537	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2538	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2539	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2540
bogdanm	92:4fc01daae5a5	2541	/* Bit 24 : Set as input pin 24. */
bogdanm	92:4fc01daae5a5	2542	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	92:4fc01daae5a5	2543	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	92:4fc01daae5a5	2544	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2545	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2546	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2547
bogdanm	92:4fc01daae5a5	2548	/* Bit 23 : Set as input pin 23. */
bogdanm	92:4fc01daae5a5	2549	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	92:4fc01daae5a5	2550	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	92:4fc01daae5a5	2551	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2552	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2553	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2554
bogdanm	92:4fc01daae5a5	2555	/* Bit 22 : Set as input pin 22. */
bogdanm	92:4fc01daae5a5	2556	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	92:4fc01daae5a5	2557	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	92:4fc01daae5a5	2558	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2559	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2560	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2561
bogdanm	92:4fc01daae5a5	2562	/* Bit 21 : Set as input pin 21. */
bogdanm	92:4fc01daae5a5	2563	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	92:4fc01daae5a5	2564	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	92:4fc01daae5a5	2565	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2566	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2567	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2568
bogdanm	92:4fc01daae5a5	2569	/* Bit 20 : Set as input pin 20. */
bogdanm	92:4fc01daae5a5	2570	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	92:4fc01daae5a5	2571	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	92:4fc01daae5a5	2572	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2573	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2574	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2575
bogdanm	92:4fc01daae5a5	2576	/* Bit 19 : Set as input pin 19. */
bogdanm	92:4fc01daae5a5	2577	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	92:4fc01daae5a5	2578	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	92:4fc01daae5a5	2579	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2580	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2581	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2582
bogdanm	92:4fc01daae5a5	2583	/* Bit 18 : Set as input pin 18. */
bogdanm	92:4fc01daae5a5	2584	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	92:4fc01daae5a5	2585	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	92:4fc01daae5a5	2586	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2587	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2588	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2589
bogdanm	92:4fc01daae5a5	2590	/* Bit 17 : Set as input pin 17. */
bogdanm	92:4fc01daae5a5	2591	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	92:4fc01daae5a5	2592	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	92:4fc01daae5a5	2593	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2594	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2595	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2596
bogdanm	92:4fc01daae5a5	2597	/* Bit 16 : Set as input pin 16. */
bogdanm	92:4fc01daae5a5	2598	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	92:4fc01daae5a5	2599	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	92:4fc01daae5a5	2600	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2601	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2602	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2603
bogdanm	92:4fc01daae5a5	2604	/* Bit 15 : Set as input pin 15. */
bogdanm	92:4fc01daae5a5	2605	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	92:4fc01daae5a5	2606	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	92:4fc01daae5a5	2607	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2608	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2609	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2610
bogdanm	92:4fc01daae5a5	2611	/* Bit 14 : Set as input pin 14. */
bogdanm	92:4fc01daae5a5	2612	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	92:4fc01daae5a5	2613	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	92:4fc01daae5a5	2614	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2615	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2616	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2617
bogdanm	92:4fc01daae5a5	2618	/* Bit 13 : Set as input pin 13. */
bogdanm	92:4fc01daae5a5	2619	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	92:4fc01daae5a5	2620	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	92:4fc01daae5a5	2621	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2622	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2623	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2624
bogdanm	92:4fc01daae5a5	2625	/* Bit 12 : Set as input pin 12. */
bogdanm	92:4fc01daae5a5	2626	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	92:4fc01daae5a5	2627	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	92:4fc01daae5a5	2628	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2629	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2630	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2631
bogdanm	92:4fc01daae5a5	2632	/* Bit 11 : Set as input pin 11. */
bogdanm	92:4fc01daae5a5	2633	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	92:4fc01daae5a5	2634	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	92:4fc01daae5a5	2635	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2636	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2637	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2638
bogdanm	92:4fc01daae5a5	2639	/* Bit 10 : Set as input pin 10. */
bogdanm	92:4fc01daae5a5	2640	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	92:4fc01daae5a5	2641	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	92:4fc01daae5a5	2642	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2643	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2644	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2645
bogdanm	92:4fc01daae5a5	2646	/* Bit 9 : Set as input pin 9. */
bogdanm	92:4fc01daae5a5	2647	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	92:4fc01daae5a5	2648	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	92:4fc01daae5a5	2649	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2650	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2651	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2652
bogdanm	92:4fc01daae5a5	2653	/* Bit 8 : Set as input pin 8. */
bogdanm	92:4fc01daae5a5	2654	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	92:4fc01daae5a5	2655	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	92:4fc01daae5a5	2656	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2657	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2658	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2659
bogdanm	92:4fc01daae5a5	2660	/* Bit 7 : Set as input pin 7. */
bogdanm	92:4fc01daae5a5	2661	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	92:4fc01daae5a5	2662	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	92:4fc01daae5a5	2663	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2664	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2665	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2666
bogdanm	92:4fc01daae5a5	2667	/* Bit 6 : Set as input pin 6. */
bogdanm	92:4fc01daae5a5	2668	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	92:4fc01daae5a5	2669	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	92:4fc01daae5a5	2670	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2671	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2672	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2673
bogdanm	92:4fc01daae5a5	2674	/* Bit 5 : Set as input pin 5. */
bogdanm	92:4fc01daae5a5	2675	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	92:4fc01daae5a5	2676	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	92:4fc01daae5a5	2677	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2678	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2679	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2680
bogdanm	92:4fc01daae5a5	2681	/* Bit 4 : Set as input pin 4. */
bogdanm	92:4fc01daae5a5	2682	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	92:4fc01daae5a5	2683	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	92:4fc01daae5a5	2684	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2685	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2686	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2687
bogdanm	92:4fc01daae5a5	2688	/* Bit 3 : Set as input pin 3. */
bogdanm	92:4fc01daae5a5	2689	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	92:4fc01daae5a5	2690	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	92:4fc01daae5a5	2691	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2692	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2693	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2694
bogdanm	92:4fc01daae5a5	2695	/* Bit 2 : Set as input pin 2. */
bogdanm	92:4fc01daae5a5	2696	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	92:4fc01daae5a5	2697	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	92:4fc01daae5a5	2698	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2699	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2700	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2701
bogdanm	92:4fc01daae5a5	2702	/* Bit 1 : Set as input pin 1. */
bogdanm	92:4fc01daae5a5	2703	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	92:4fc01daae5a5	2704	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	92:4fc01daae5a5	2705	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2706	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2707	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2708
bogdanm	92:4fc01daae5a5	2709	/* Bit 0 : Set as input pin 0. */
bogdanm	92:4fc01daae5a5	2710	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	92:4fc01daae5a5	2711	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	92:4fc01daae5a5	2712	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	92:4fc01daae5a5	2713	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	92:4fc01daae5a5	2714	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
bogdanm	92:4fc01daae5a5	2715
bogdanm	92:4fc01daae5a5	2716	/* Register: GPIO_PIN_CNF */
bogdanm	92:4fc01daae5a5	2717	/* Description: Configuration of GPIO pins. */
bogdanm	92:4fc01daae5a5	2718
bogdanm	92:4fc01daae5a5	2719	/* Bits 17..16 : Pin sensing mechanism. */
bogdanm	92:4fc01daae5a5	2720	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
bogdanm	92:4fc01daae5a5	2721	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
bogdanm	92:4fc01daae5a5	2722	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	2723	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
bogdanm	92:4fc01daae5a5	2724	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
bogdanm	92:4fc01daae5a5	2725
bogdanm	92:4fc01daae5a5	2726	/* Bits 10..8 : Drive configuration. */
bogdanm	92:4fc01daae5a5	2727	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
bogdanm	92:4fc01daae5a5	2728	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
bogdanm	92:4fc01daae5a5	2729	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
bogdanm	92:4fc01daae5a5	2730	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
bogdanm	92:4fc01daae5a5	2731	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
bogdanm	92:4fc01daae5a5	2732	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
bogdanm	92:4fc01daae5a5	2733	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
bogdanm	92:4fc01daae5a5	2734	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
bogdanm	92:4fc01daae5a5	2735	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
bogdanm	92:4fc01daae5a5	2736	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
bogdanm	92:4fc01daae5a5	2737
bogdanm	92:4fc01daae5a5	2738	/* Bits 3..2 : Pull-up or -down configuration. */
bogdanm	92:4fc01daae5a5	2739	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
bogdanm	92:4fc01daae5a5	2740	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
bogdanm	92:4fc01daae5a5	2741	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
bogdanm	92:4fc01daae5a5	2742	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
bogdanm	92:4fc01daae5a5	2743	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
bogdanm	92:4fc01daae5a5	2744
bogdanm	92:4fc01daae5a5	2745	/* Bit 1 : Connect or disconnect input path. */
bogdanm	92:4fc01daae5a5	2746	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
bogdanm	92:4fc01daae5a5	2747	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
bogdanm	92:4fc01daae5a5	2748	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
bogdanm	92:4fc01daae5a5	2749	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
bogdanm	92:4fc01daae5a5	2750
bogdanm	92:4fc01daae5a5	2751	/* Bit 0 : Pin direction. */
bogdanm	92:4fc01daae5a5	2752	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
bogdanm	92:4fc01daae5a5	2753	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
bogdanm	92:4fc01daae5a5	2754	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
bogdanm	92:4fc01daae5a5	2755	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
bogdanm	92:4fc01daae5a5	2756
bogdanm	92:4fc01daae5a5	2757
bogdanm	92:4fc01daae5a5	2758	/* Peripheral: GPIOTE */
bogdanm	92:4fc01daae5a5	2759	/* Description: GPIO tasks and events. */
bogdanm	92:4fc01daae5a5	2760
bogdanm	92:4fc01daae5a5	2761	/* Register: GPIOTE_INTENSET */
bogdanm	92:4fc01daae5a5	2762	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	2763
bogdanm	92:4fc01daae5a5	2764	/* Bit 31 : Enable interrupt on PORT event. */
bogdanm	92:4fc01daae5a5	2765	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	92:4fc01daae5a5	2766	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	92:4fc01daae5a5	2767	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2768	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2769	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2770
bogdanm	92:4fc01daae5a5	2771	/* Bit 3 : Enable interrupt on IN[3] event. */
bogdanm	92:4fc01daae5a5	2772	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	92:4fc01daae5a5	2773	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	92:4fc01daae5a5	2774	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2775	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2776	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2777
bogdanm	92:4fc01daae5a5	2778	/* Bit 2 : Enable interrupt on IN[2] event. */
bogdanm	92:4fc01daae5a5	2779	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	92:4fc01daae5a5	2780	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	92:4fc01daae5a5	2781	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2782	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2783	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2784
bogdanm	92:4fc01daae5a5	2785	/* Bit 1 : Enable interrupt on IN[1] event. */
bogdanm	92:4fc01daae5a5	2786	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	92:4fc01daae5a5	2787	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	92:4fc01daae5a5	2788	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2789	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2790	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2791
bogdanm	92:4fc01daae5a5	2792	/* Bit 0 : Enable interrupt on IN[0] event. */
bogdanm	92:4fc01daae5a5	2793	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	92:4fc01daae5a5	2794	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	92:4fc01daae5a5	2795	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2796	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2797	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2798
bogdanm	92:4fc01daae5a5	2799	/* Register: GPIOTE_INTENCLR */
bogdanm	92:4fc01daae5a5	2800	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	2801
bogdanm	92:4fc01daae5a5	2802	/* Bit 31 : Disable interrupt on PORT event. */
bogdanm	92:4fc01daae5a5	2803	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	92:4fc01daae5a5	2804	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	92:4fc01daae5a5	2805	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2806	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2807	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2808
bogdanm	92:4fc01daae5a5	2809	/* Bit 3 : Disable interrupt on IN[3] event. */
bogdanm	92:4fc01daae5a5	2810	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	92:4fc01daae5a5	2811	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	92:4fc01daae5a5	2812	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2813	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2814	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2815
bogdanm	92:4fc01daae5a5	2816	/* Bit 2 : Disable interrupt on IN[2] event. */
bogdanm	92:4fc01daae5a5	2817	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	92:4fc01daae5a5	2818	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	92:4fc01daae5a5	2819	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2820	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2821	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2822
bogdanm	92:4fc01daae5a5	2823	/* Bit 1 : Disable interrupt on IN[1] event. */
bogdanm	92:4fc01daae5a5	2824	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	92:4fc01daae5a5	2825	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	92:4fc01daae5a5	2826	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2827	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2828	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2829
bogdanm	92:4fc01daae5a5	2830	/* Bit 0 : Disable interrupt on IN[0] event. */
bogdanm	92:4fc01daae5a5	2831	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	92:4fc01daae5a5	2832	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	92:4fc01daae5a5	2833	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2834	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2835	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2836
bogdanm	92:4fc01daae5a5	2837	/* Register: GPIOTE_CONFIG */
bogdanm	92:4fc01daae5a5	2838	/* Description: Channel configuration registers. */
bogdanm	92:4fc01daae5a5	2839
bogdanm	92:4fc01daae5a5	2840	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
bogdanm	92:4fc01daae5a5	2841	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
bogdanm	92:4fc01daae5a5	2842	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
bogdanm	92:4fc01daae5a5	2843	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
bogdanm	92:4fc01daae5a5	2844	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
bogdanm	92:4fc01daae5a5	2845
bogdanm	92:4fc01daae5a5	2846	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
bogdanm	92:4fc01daae5a5	2847	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
bogdanm	92:4fc01daae5a5	2848	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
bogdanm	92:4fc01daae5a5	2849	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
bogdanm	92:4fc01daae5a5	2850	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
bogdanm	92:4fc01daae5a5	2851	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
bogdanm	92:4fc01daae5a5	2852
bogdanm	92:4fc01daae5a5	2853	/* Bits 12..8 : Pin select. */
bogdanm	92:4fc01daae5a5	2854	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	92:4fc01daae5a5	2855	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	92:4fc01daae5a5	2856
bogdanm	92:4fc01daae5a5	2857	/* Bits 1..0 : Mode */
bogdanm	92:4fc01daae5a5	2858	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	92:4fc01daae5a5	2859	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	92:4fc01daae5a5	2860	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	2861	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
bogdanm	92:4fc01daae5a5	2862	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
bogdanm	92:4fc01daae5a5	2863
bogdanm	92:4fc01daae5a5	2864	/* Register: GPIOTE_POWER */
bogdanm	92:4fc01daae5a5	2865	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	2866
bogdanm	92:4fc01daae5a5	2867	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	2868	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	2869	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	2870	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	2871	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	2872
bogdanm	92:4fc01daae5a5	2873
bogdanm	92:4fc01daae5a5	2874	/* Peripheral: LPCOMP */
Kojto	97:433970e64889	2875	/* Description: Low power comparator. */
bogdanm	92:4fc01daae5a5	2876
bogdanm	92:4fc01daae5a5	2877	/* Register: LPCOMP_SHORTS */
Kojto	97:433970e64889	2878	/* Description: Shortcuts for the LPCOMP. */
Kojto	97:433970e64889	2879
Kojto	97:433970e64889	2880	/* Bit 4 : Shortcut between CROSS event and STOP task. */
bogdanm	92:4fc01daae5a5	2881	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
bogdanm	92:4fc01daae5a5	2882	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
bogdanm	92:4fc01daae5a5	2883	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	2884	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	2885
Kojto	97:433970e64889	2886	/* Bit 3 : Shortcut between UP event and STOP task. */
bogdanm	92:4fc01daae5a5	2887	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
bogdanm	92:4fc01daae5a5	2888	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
bogdanm	92:4fc01daae5a5	2889	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	2890	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	2891
Kojto	97:433970e64889	2892	/* Bit 2 : Shortcut between DOWN event and STOP task. */
bogdanm	92:4fc01daae5a5	2893	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
bogdanm	92:4fc01daae5a5	2894	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
bogdanm	92:4fc01daae5a5	2895	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	2896	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	2897
Kojto	97:433970e64889	2898	/* Bit 1 : Shortcut between RADY event and STOP task. */
bogdanm	92:4fc01daae5a5	2899	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
bogdanm	92:4fc01daae5a5	2900	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
bogdanm	92:4fc01daae5a5	2901	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	2902	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	2903
Kojto	97:433970e64889	2904	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
bogdanm	92:4fc01daae5a5	2905	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
bogdanm	92:4fc01daae5a5	2906	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
bogdanm	92:4fc01daae5a5	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	2909
bogdanm	92:4fc01daae5a5	2910	/* Register: LPCOMP_INTENSET */
bogdanm	92:4fc01daae5a5	2911	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	2912
bogdanm	92:4fc01daae5a5	2913	/* Bit 3 : Enable interrupt on CROSS event. */
bogdanm	92:4fc01daae5a5	2914	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	92:4fc01daae5a5	2915	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	92:4fc01daae5a5	2916	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2917	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2918	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2919
bogdanm	92:4fc01daae5a5	2920	/* Bit 2 : Enable interrupt on UP event. */
bogdanm	92:4fc01daae5a5	2921	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	92:4fc01daae5a5	2922	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
bogdanm	92:4fc01daae5a5	2923	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2924	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2925	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2926
bogdanm	92:4fc01daae5a5	2927	/* Bit 1 : Enable interrupt on DOWN event. */
bogdanm	92:4fc01daae5a5	2928	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	92:4fc01daae5a5	2929	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	92:4fc01daae5a5	2930	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2931	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2932	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2933
bogdanm	92:4fc01daae5a5	2934	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	2935	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	2936	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	2937	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2938	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2939	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	2940
bogdanm	92:4fc01daae5a5	2941	/* Register: LPCOMP_INTENCLR */
bogdanm	92:4fc01daae5a5	2942	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	2943
bogdanm	92:4fc01daae5a5	2944	/* Bit 3 : Disable interrupt on CROSS event. */
bogdanm	92:4fc01daae5a5	2945	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	92:4fc01daae5a5	2946	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	92:4fc01daae5a5	2947	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2948	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2949	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2950
bogdanm	92:4fc01daae5a5	2951	/* Bit 2 : Disable interrupt on UP event. */
bogdanm	92:4fc01daae5a5	2952	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	92:4fc01daae5a5	2953	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
bogdanm	92:4fc01daae5a5	2954	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2955	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2956	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2957
bogdanm	92:4fc01daae5a5	2958	/* Bit 1 : Disable interrupt on DOWN event. */
bogdanm	92:4fc01daae5a5	2959	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	92:4fc01daae5a5	2960	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	92:4fc01daae5a5	2961	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2962	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2963	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2964
bogdanm	92:4fc01daae5a5	2965	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	2966	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	2967	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	2968	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	2969	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	2970	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	2971
bogdanm	92:4fc01daae5a5	2972	/* Register: LPCOMP_RESULT */
bogdanm	92:4fc01daae5a5	2973	/* Description: Result of last compare. */
bogdanm	92:4fc01daae5a5	2974
bogdanm	92:4fc01daae5a5	2975	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
bogdanm	92:4fc01daae5a5	2976	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	92:4fc01daae5a5	2977	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	92:4fc01daae5a5	2978	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
bogdanm	92:4fc01daae5a5	2979	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
bogdanm	92:4fc01daae5a5	2980
bogdanm	92:4fc01daae5a5	2981	/* Register: LPCOMP_ENABLE */
bogdanm	92:4fc01daae5a5	2982	/* Description: Enable the LPCOMP. */
bogdanm	92:4fc01daae5a5	2983
bogdanm	92:4fc01daae5a5	2984	/* Bits 1..0 : Enable or disable LPCOMP. */
bogdanm	92:4fc01daae5a5	2985	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	2986	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	2987	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
bogdanm	92:4fc01daae5a5	2988	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
bogdanm	92:4fc01daae5a5	2989
bogdanm	92:4fc01daae5a5	2990	/* Register: LPCOMP_PSEL */
bogdanm	92:4fc01daae5a5	2991	/* Description: Input pin select. */
bogdanm	92:4fc01daae5a5	2992
bogdanm	92:4fc01daae5a5	2993	/* Bits 2..0 : Analog input pin select. */
bogdanm	92:4fc01daae5a5	2994	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
bogdanm	92:4fc01daae5a5	2995	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	92:4fc01daae5a5	2996	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
bogdanm	92:4fc01daae5a5	2997	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
bogdanm	92:4fc01daae5a5	2998	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
bogdanm	92:4fc01daae5a5	2999	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
bogdanm	92:4fc01daae5a5	3000	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
bogdanm	92:4fc01daae5a5	3001	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
bogdanm	92:4fc01daae5a5	3002	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
bogdanm	92:4fc01daae5a5	3003	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
bogdanm	92:4fc01daae5a5	3004
bogdanm	92:4fc01daae5a5	3005	/* Register: LPCOMP_REFSEL */
bogdanm	92:4fc01daae5a5	3006	/* Description: Reference select. */
bogdanm	92:4fc01daae5a5	3007
bogdanm	92:4fc01daae5a5	3008	/* Bits 2..0 : Reference select. */
bogdanm	92:4fc01daae5a5	3009	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
bogdanm	92:4fc01daae5a5	3010	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	97:433970e64889	3011	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
Kojto	97:433970e64889	3012	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
Kojto	97:433970e64889	3013	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
Kojto	97:433970e64889	3014	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
Kojto	97:433970e64889	3015	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
Kojto	97:433970e64889	3016	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
Kojto	97:433970e64889	3017	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
bogdanm	92:4fc01daae5a5	3018	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
bogdanm	92:4fc01daae5a5	3019
bogdanm	92:4fc01daae5a5	3020	/* Register: LPCOMP_EXTREFSEL */
bogdanm	92:4fc01daae5a5	3021	/* Description: External reference select. */
bogdanm	92:4fc01daae5a5	3022
bogdanm	92:4fc01daae5a5	3023	/* Bit 0 : External analog reference pin selection. */
bogdanm	92:4fc01daae5a5	3024	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
bogdanm	92:4fc01daae5a5	3025	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	92:4fc01daae5a5	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
bogdanm	92:4fc01daae5a5	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
bogdanm	92:4fc01daae5a5	3028
bogdanm	92:4fc01daae5a5	3029	/* Register: LPCOMP_ANADETECT */
bogdanm	92:4fc01daae5a5	3030	/* Description: Analog detect configuration. */
bogdanm	92:4fc01daae5a5	3031
bogdanm	92:4fc01daae5a5	3032	/* Bits 1..0 : Analog detect configuration. */
bogdanm	92:4fc01daae5a5	3033	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
bogdanm	92:4fc01daae5a5	3034	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
bogdanm	92:4fc01daae5a5	3035	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
bogdanm	92:4fc01daae5a5	3036	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
bogdanm	92:4fc01daae5a5	3037	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
bogdanm	92:4fc01daae5a5	3038
bogdanm	92:4fc01daae5a5	3039	/* Register: LPCOMP_POWER */
bogdanm	92:4fc01daae5a5	3040	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	3041
bogdanm	92:4fc01daae5a5	3042	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	3043	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	3044	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	3045	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	3046	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	3047
bogdanm	92:4fc01daae5a5	3048
bogdanm	92:4fc01daae5a5	3049	/* Peripheral: MPU */
bogdanm	92:4fc01daae5a5	3050	/* Description: Memory Protection Unit. */
bogdanm	92:4fc01daae5a5	3051
bogdanm	92:4fc01daae5a5	3052	/* Register: MPU_PERR0 */
bogdanm	92:4fc01daae5a5	3053	/* Description: Configuration of peripherals in mpu regions. */
bogdanm	92:4fc01daae5a5	3054
bogdanm	92:4fc01daae5a5	3055	/* Bit 31 : PPI region configuration. */
bogdanm	92:4fc01daae5a5	3056	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
bogdanm	92:4fc01daae5a5	3057	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
bogdanm	92:4fc01daae5a5	3058	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3059	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3060
bogdanm	92:4fc01daae5a5	3061	/* Bit 30 : NVMC region configuration. */
bogdanm	92:4fc01daae5a5	3062	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
bogdanm	92:4fc01daae5a5	3063	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
bogdanm	92:4fc01daae5a5	3064	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3065	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3066
Kojto	97:433970e64889	3067	/* Bit 19 : LPCOMP region configuration. */
Kojto	97:433970e64889	3068	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
Kojto	97:433970e64889	3069	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	97:433970e64889	3070	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	97:433970e64889	3071	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3072
bogdanm	92:4fc01daae5a5	3073	/* Bit 18 : QDEC region configuration. */
bogdanm	92:4fc01daae5a5	3074	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
bogdanm	92:4fc01daae5a5	3075	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
bogdanm	92:4fc01daae5a5	3076	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3077	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3078
bogdanm	92:4fc01daae5a5	3079	/* Bit 17 : RTC1 region configuration. */
bogdanm	92:4fc01daae5a5	3080	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
bogdanm	92:4fc01daae5a5	3081	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
bogdanm	92:4fc01daae5a5	3082	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3083	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3084
bogdanm	92:4fc01daae5a5	3085	/* Bit 16 : WDT region configuration. */
bogdanm	92:4fc01daae5a5	3086	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
bogdanm	92:4fc01daae5a5	3087	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
bogdanm	92:4fc01daae5a5	3088	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3089	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3090
bogdanm	92:4fc01daae5a5	3091	/* Bit 15 : CCM and AAR region configuration. */
bogdanm	92:4fc01daae5a5	3092	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
bogdanm	92:4fc01daae5a5	3093	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
bogdanm	92:4fc01daae5a5	3094	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3095	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3096
bogdanm	92:4fc01daae5a5	3097	/* Bit 14 : ECB region configuration. */
bogdanm	92:4fc01daae5a5	3098	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
bogdanm	92:4fc01daae5a5	3099	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
bogdanm	92:4fc01daae5a5	3100	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3101	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3102
bogdanm	92:4fc01daae5a5	3103	/* Bit 13 : RNG region configuration. */
bogdanm	92:4fc01daae5a5	3104	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
bogdanm	92:4fc01daae5a5	3105	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
bogdanm	92:4fc01daae5a5	3106	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3107	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3108
bogdanm	92:4fc01daae5a5	3109	/* Bit 12 : TEMP region configuration. */
bogdanm	92:4fc01daae5a5	3110	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
bogdanm	92:4fc01daae5a5	3111	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
bogdanm	92:4fc01daae5a5	3112	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3113	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3114
bogdanm	92:4fc01daae5a5	3115	/* Bit 11 : RTC0 region configuration. */
bogdanm	92:4fc01daae5a5	3116	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
bogdanm	92:4fc01daae5a5	3117	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
bogdanm	92:4fc01daae5a5	3118	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3119	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3120
bogdanm	92:4fc01daae5a5	3121	/* Bit 10 : TIMER2 region configuration. */
bogdanm	92:4fc01daae5a5	3122	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
bogdanm	92:4fc01daae5a5	3123	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
bogdanm	92:4fc01daae5a5	3124	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3125	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3126
bogdanm	92:4fc01daae5a5	3127	/* Bit 9 : TIMER1 region configuration. */
bogdanm	92:4fc01daae5a5	3128	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
bogdanm	92:4fc01daae5a5	3129	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
bogdanm	92:4fc01daae5a5	3130	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3131	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3132
bogdanm	92:4fc01daae5a5	3133	/* Bit 8 : TIMER0 region configuration. */
bogdanm	92:4fc01daae5a5	3134	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
bogdanm	92:4fc01daae5a5	3135	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
bogdanm	92:4fc01daae5a5	3136	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3137	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3138
bogdanm	92:4fc01daae5a5	3139	/* Bit 7 : ADC region configuration. */
bogdanm	92:4fc01daae5a5	3140	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
bogdanm	92:4fc01daae5a5	3141	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
bogdanm	92:4fc01daae5a5	3142	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3143	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3144
bogdanm	92:4fc01daae5a5	3145	/* Bit 6 : GPIOTE region configuration. */
bogdanm	92:4fc01daae5a5	3146	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
bogdanm	92:4fc01daae5a5	3147	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
bogdanm	92:4fc01daae5a5	3148	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3149	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3150
bogdanm	92:4fc01daae5a5	3151	/* Bit 4 : SPI1 and TWI1 region configuration. */
bogdanm	92:4fc01daae5a5	3152	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
bogdanm	92:4fc01daae5a5	3153	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
bogdanm	92:4fc01daae5a5	3154	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3155	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3156
bogdanm	92:4fc01daae5a5	3157	/* Bit 3 : SPI0 and TWI0 region configuration. */
bogdanm	92:4fc01daae5a5	3158	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
bogdanm	92:4fc01daae5a5	3159	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
bogdanm	92:4fc01daae5a5	3160	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3161	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3162
bogdanm	92:4fc01daae5a5	3163	/* Bit 2 : UART0 region configuration. */
bogdanm	92:4fc01daae5a5	3164	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
bogdanm	92:4fc01daae5a5	3165	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
bogdanm	92:4fc01daae5a5	3166	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3167	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3168
bogdanm	92:4fc01daae5a5	3169	/* Bit 1 : RADIO region configuration. */
bogdanm	92:4fc01daae5a5	3170	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
bogdanm	92:4fc01daae5a5	3171	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
bogdanm	92:4fc01daae5a5	3172	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3173	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3174
bogdanm	92:4fc01daae5a5	3175	/* Bit 0 : POWER_CLOCK region configuration. */
bogdanm	92:4fc01daae5a5	3176	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
bogdanm	92:4fc01daae5a5	3177	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
bogdanm	92:4fc01daae5a5	3178	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	92:4fc01daae5a5	3179	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	92:4fc01daae5a5	3180
bogdanm	92:4fc01daae5a5	3181	/* Register: MPU_PROTENSET0 */
Kojto	97:433970e64889	3182	/* Description: Erase and write protection bit enable set register. */
bogdanm	92:4fc01daae5a5	3183
bogdanm	92:4fc01daae5a5	3184	/* Bit 31 : Protection enable for region 31. */
bogdanm	92:4fc01daae5a5	3185	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
bogdanm	92:4fc01daae5a5	3186	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
bogdanm	92:4fc01daae5a5	3187	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3188	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3189	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3190
bogdanm	92:4fc01daae5a5	3191	/* Bit 30 : Protection enable for region 30. */
bogdanm	92:4fc01daae5a5	3192	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
bogdanm	92:4fc01daae5a5	3193	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
bogdanm	92:4fc01daae5a5	3194	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3195	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3196	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3197
bogdanm	92:4fc01daae5a5	3198	/* Bit 29 : Protection enable for region 29. */
bogdanm	92:4fc01daae5a5	3199	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
bogdanm	92:4fc01daae5a5	3200	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
bogdanm	92:4fc01daae5a5	3201	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3202	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3203	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3204
bogdanm	92:4fc01daae5a5	3205	/* Bit 28 : Protection enable for region 28. */
bogdanm	92:4fc01daae5a5	3206	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
bogdanm	92:4fc01daae5a5	3207	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
bogdanm	92:4fc01daae5a5	3208	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3209	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3210	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3211
bogdanm	92:4fc01daae5a5	3212	/* Bit 27 : Protection enable for region 27. */
bogdanm	92:4fc01daae5a5	3213	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
bogdanm	92:4fc01daae5a5	3214	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
bogdanm	92:4fc01daae5a5	3215	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3216	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3217	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3218
bogdanm	92:4fc01daae5a5	3219	/* Bit 26 : Protection enable for region 26. */
bogdanm	92:4fc01daae5a5	3220	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
bogdanm	92:4fc01daae5a5	3221	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
bogdanm	92:4fc01daae5a5	3222	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3223	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3224	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3225
bogdanm	92:4fc01daae5a5	3226	/* Bit 25 : Protection enable for region 25. */
bogdanm	92:4fc01daae5a5	3227	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
bogdanm	92:4fc01daae5a5	3228	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
bogdanm	92:4fc01daae5a5	3229	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3230	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3231	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3232
bogdanm	92:4fc01daae5a5	3233	/* Bit 24 : Protection enable for region 24. */
bogdanm	92:4fc01daae5a5	3234	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
bogdanm	92:4fc01daae5a5	3235	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
bogdanm	92:4fc01daae5a5	3236	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3237	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3238	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3239
bogdanm	92:4fc01daae5a5	3240	/* Bit 23 : Protection enable for region 23. */
bogdanm	92:4fc01daae5a5	3241	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
bogdanm	92:4fc01daae5a5	3242	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
bogdanm	92:4fc01daae5a5	3243	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3244	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3245	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3246
bogdanm	92:4fc01daae5a5	3247	/* Bit 22 : Protection enable for region 22. */
bogdanm	92:4fc01daae5a5	3248	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
bogdanm	92:4fc01daae5a5	3249	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
bogdanm	92:4fc01daae5a5	3250	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3251	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3252	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3253
bogdanm	92:4fc01daae5a5	3254	/* Bit 21 : Protection enable for region 21. */
bogdanm	92:4fc01daae5a5	3255	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
bogdanm	92:4fc01daae5a5	3256	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
bogdanm	92:4fc01daae5a5	3257	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3258	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3259	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3260
bogdanm	92:4fc01daae5a5	3261	/* Bit 20 : Protection enable for region 20. */
bogdanm	92:4fc01daae5a5	3262	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
bogdanm	92:4fc01daae5a5	3263	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
bogdanm	92:4fc01daae5a5	3264	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3265	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3266	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3267
bogdanm	92:4fc01daae5a5	3268	/* Bit 19 : Protection enable for region 19. */
bogdanm	92:4fc01daae5a5	3269	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
bogdanm	92:4fc01daae5a5	3270	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
bogdanm	92:4fc01daae5a5	3271	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3272	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3273	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3274
bogdanm	92:4fc01daae5a5	3275	/* Bit 18 : Protection enable for region 18. */
bogdanm	92:4fc01daae5a5	3276	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
bogdanm	92:4fc01daae5a5	3277	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
bogdanm	92:4fc01daae5a5	3278	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3279	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3280	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3281
bogdanm	92:4fc01daae5a5	3282	/* Bit 17 : Protection enable for region 17. */
bogdanm	92:4fc01daae5a5	3283	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
bogdanm	92:4fc01daae5a5	3284	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
bogdanm	92:4fc01daae5a5	3285	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3286	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3287	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3288
bogdanm	92:4fc01daae5a5	3289	/* Bit 16 : Protection enable for region 16. */
bogdanm	92:4fc01daae5a5	3290	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
bogdanm	92:4fc01daae5a5	3291	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
bogdanm	92:4fc01daae5a5	3292	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3293	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3294	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3295
bogdanm	92:4fc01daae5a5	3296	/* Bit 15 : Protection enable for region 15. */
bogdanm	92:4fc01daae5a5	3297	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
bogdanm	92:4fc01daae5a5	3298	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
bogdanm	92:4fc01daae5a5	3299	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3300	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3301	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3302
bogdanm	92:4fc01daae5a5	3303	/* Bit 14 : Protection enable for region 14. */
bogdanm	92:4fc01daae5a5	3304	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
bogdanm	92:4fc01daae5a5	3305	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
bogdanm	92:4fc01daae5a5	3306	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3307	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3308	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3309
bogdanm	92:4fc01daae5a5	3310	/* Bit 13 : Protection enable for region 13. */
bogdanm	92:4fc01daae5a5	3311	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
bogdanm	92:4fc01daae5a5	3312	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
bogdanm	92:4fc01daae5a5	3313	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3314	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3315	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3316
bogdanm	92:4fc01daae5a5	3317	/* Bit 12 : Protection enable for region 12. */
bogdanm	92:4fc01daae5a5	3318	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
bogdanm	92:4fc01daae5a5	3319	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
bogdanm	92:4fc01daae5a5	3320	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3321	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3322	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3323
bogdanm	92:4fc01daae5a5	3324	/* Bit 11 : Protection enable for region 11. */
bogdanm	92:4fc01daae5a5	3325	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
bogdanm	92:4fc01daae5a5	3326	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
bogdanm	92:4fc01daae5a5	3327	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3328	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3329	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3330
bogdanm	92:4fc01daae5a5	3331	/* Bit 10 : Protection enable for region 10. */
bogdanm	92:4fc01daae5a5	3332	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
bogdanm	92:4fc01daae5a5	3333	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
bogdanm	92:4fc01daae5a5	3334	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3335	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3336	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3337
bogdanm	92:4fc01daae5a5	3338	/* Bit 9 : Protection enable for region 9. */
bogdanm	92:4fc01daae5a5	3339	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
bogdanm	92:4fc01daae5a5	3340	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
bogdanm	92:4fc01daae5a5	3341	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3342	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3343	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3344
bogdanm	92:4fc01daae5a5	3345	/* Bit 8 : Protection enable for region 8. */
bogdanm	92:4fc01daae5a5	3346	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
bogdanm	92:4fc01daae5a5	3347	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
bogdanm	92:4fc01daae5a5	3348	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3349	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3350	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3351
bogdanm	92:4fc01daae5a5	3352	/* Bit 7 : Protection enable for region 7. */
bogdanm	92:4fc01daae5a5	3353	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
bogdanm	92:4fc01daae5a5	3354	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
bogdanm	92:4fc01daae5a5	3355	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3356	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3357	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3358
bogdanm	92:4fc01daae5a5	3359	/* Bit 6 : Protection enable for region 6. */
bogdanm	92:4fc01daae5a5	3360	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
bogdanm	92:4fc01daae5a5	3361	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
bogdanm	92:4fc01daae5a5	3362	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3363	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3364	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3365
bogdanm	92:4fc01daae5a5	3366	/* Bit 5 : Protection enable for region 5. */
bogdanm	92:4fc01daae5a5	3367	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
bogdanm	92:4fc01daae5a5	3368	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
bogdanm	92:4fc01daae5a5	3369	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3370	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3371	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3372
bogdanm	92:4fc01daae5a5	3373	/* Bit 4 : Protection enable for region 4. */
bogdanm	92:4fc01daae5a5	3374	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
bogdanm	92:4fc01daae5a5	3375	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
bogdanm	92:4fc01daae5a5	3376	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3377	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3378	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3379
bogdanm	92:4fc01daae5a5	3380	/* Bit 3 : Protection enable for region 3. */
bogdanm	92:4fc01daae5a5	3381	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
bogdanm	92:4fc01daae5a5	3382	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
bogdanm	92:4fc01daae5a5	3383	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3384	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3385	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3386
bogdanm	92:4fc01daae5a5	3387	/* Bit 2 : Protection enable for region 2. */
bogdanm	92:4fc01daae5a5	3388	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
bogdanm	92:4fc01daae5a5	3389	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
bogdanm	92:4fc01daae5a5	3390	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3391	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3392	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3393
bogdanm	92:4fc01daae5a5	3394	/* Bit 1 : Protection enable for region 1. */
bogdanm	92:4fc01daae5a5	3395	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
bogdanm	92:4fc01daae5a5	3396	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
bogdanm	92:4fc01daae5a5	3397	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3398	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3399	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3400
bogdanm	92:4fc01daae5a5	3401	/* Bit 0 : Protection enable for region 0. */
bogdanm	92:4fc01daae5a5	3402	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
bogdanm	92:4fc01daae5a5	3403	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
bogdanm	92:4fc01daae5a5	3404	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3405	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3406	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3407
bogdanm	92:4fc01daae5a5	3408	/* Register: MPU_PROTENSET1 */
Kojto	97:433970e64889	3409	/* Description: Erase and write protection bit enable set register. */
bogdanm	92:4fc01daae5a5	3410
bogdanm	92:4fc01daae5a5	3411	/* Bit 31 : Protection enable for region 63. */
bogdanm	92:4fc01daae5a5	3412	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
bogdanm	92:4fc01daae5a5	3413	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
bogdanm	92:4fc01daae5a5	3414	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3415	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3416	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3417
bogdanm	92:4fc01daae5a5	3418	/* Bit 30 : Protection enable for region 62. */
bogdanm	92:4fc01daae5a5	3419	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
bogdanm	92:4fc01daae5a5	3420	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
bogdanm	92:4fc01daae5a5	3421	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3422	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3423	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3424
bogdanm	92:4fc01daae5a5	3425	/* Bit 29 : Protection enable for region 61. */
bogdanm	92:4fc01daae5a5	3426	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
bogdanm	92:4fc01daae5a5	3427	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
bogdanm	92:4fc01daae5a5	3428	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3429	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3430	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3431
bogdanm	92:4fc01daae5a5	3432	/* Bit 28 : Protection enable for region 60. */
bogdanm	92:4fc01daae5a5	3433	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
bogdanm	92:4fc01daae5a5	3434	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
bogdanm	92:4fc01daae5a5	3435	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3436	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3437	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3438
bogdanm	92:4fc01daae5a5	3439	/* Bit 27 : Protection enable for region 59. */
bogdanm	92:4fc01daae5a5	3440	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
bogdanm	92:4fc01daae5a5	3441	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
bogdanm	92:4fc01daae5a5	3442	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3443	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3444	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3445
bogdanm	92:4fc01daae5a5	3446	/* Bit 26 : Protection enable for region 58. */
bogdanm	92:4fc01daae5a5	3447	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
bogdanm	92:4fc01daae5a5	3448	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
bogdanm	92:4fc01daae5a5	3449	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3450	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3451	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3452
bogdanm	92:4fc01daae5a5	3453	/* Bit 25 : Protection enable for region 57. */
bogdanm	92:4fc01daae5a5	3454	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
bogdanm	92:4fc01daae5a5	3455	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
bogdanm	92:4fc01daae5a5	3456	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3457	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3458	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3459
bogdanm	92:4fc01daae5a5	3460	/* Bit 24 : Protection enable for region 56. */
bogdanm	92:4fc01daae5a5	3461	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
bogdanm	92:4fc01daae5a5	3462	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
bogdanm	92:4fc01daae5a5	3463	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3464	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3465	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3466
bogdanm	92:4fc01daae5a5	3467	/* Bit 23 : Protection enable for region 55. */
bogdanm	92:4fc01daae5a5	3468	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
bogdanm	92:4fc01daae5a5	3469	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
bogdanm	92:4fc01daae5a5	3470	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3471	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3472	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3473
bogdanm	92:4fc01daae5a5	3474	/* Bit 22 : Protection enable for region 54. */
bogdanm	92:4fc01daae5a5	3475	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
bogdanm	92:4fc01daae5a5	3476	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
bogdanm	92:4fc01daae5a5	3477	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3478	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3479	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3480
bogdanm	92:4fc01daae5a5	3481	/* Bit 21 : Protection enable for region 53. */
bogdanm	92:4fc01daae5a5	3482	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
bogdanm	92:4fc01daae5a5	3483	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
bogdanm	92:4fc01daae5a5	3484	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3485	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3486	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3487
bogdanm	92:4fc01daae5a5	3488	/* Bit 20 : Protection enable for region 52. */
bogdanm	92:4fc01daae5a5	3489	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
bogdanm	92:4fc01daae5a5	3490	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
bogdanm	92:4fc01daae5a5	3491	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3492	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3493	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3494
bogdanm	92:4fc01daae5a5	3495	/* Bit 19 : Protection enable for region 51. */
bogdanm	92:4fc01daae5a5	3496	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
bogdanm	92:4fc01daae5a5	3497	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
bogdanm	92:4fc01daae5a5	3498	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3499	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3500	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3501
bogdanm	92:4fc01daae5a5	3502	/* Bit 18 : Protection enable for region 50. */
bogdanm	92:4fc01daae5a5	3503	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
bogdanm	92:4fc01daae5a5	3504	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
bogdanm	92:4fc01daae5a5	3505	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3506	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3507	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3508
bogdanm	92:4fc01daae5a5	3509	/* Bit 17 : Protection enable for region 49. */
bogdanm	92:4fc01daae5a5	3510	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
bogdanm	92:4fc01daae5a5	3511	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
bogdanm	92:4fc01daae5a5	3512	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3513	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3514	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3515
bogdanm	92:4fc01daae5a5	3516	/* Bit 16 : Protection enable for region 48. */
bogdanm	92:4fc01daae5a5	3517	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
bogdanm	92:4fc01daae5a5	3518	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
bogdanm	92:4fc01daae5a5	3519	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3520	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3521	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3522
bogdanm	92:4fc01daae5a5	3523	/* Bit 15 : Protection enable for region 47. */
bogdanm	92:4fc01daae5a5	3524	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
bogdanm	92:4fc01daae5a5	3525	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
bogdanm	92:4fc01daae5a5	3526	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3527	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3528	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3529
bogdanm	92:4fc01daae5a5	3530	/* Bit 14 : Protection enable for region 46. */
bogdanm	92:4fc01daae5a5	3531	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
bogdanm	92:4fc01daae5a5	3532	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
bogdanm	92:4fc01daae5a5	3533	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3534	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3535	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3536
bogdanm	92:4fc01daae5a5	3537	/* Bit 13 : Protection enable for region 45. */
bogdanm	92:4fc01daae5a5	3538	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
bogdanm	92:4fc01daae5a5	3539	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
bogdanm	92:4fc01daae5a5	3540	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3541	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3542	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3543
bogdanm	92:4fc01daae5a5	3544	/* Bit 12 : Protection enable for region 44. */
bogdanm	92:4fc01daae5a5	3545	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
bogdanm	92:4fc01daae5a5	3546	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
bogdanm	92:4fc01daae5a5	3547	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3548	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3549	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3550
bogdanm	92:4fc01daae5a5	3551	/* Bit 11 : Protection enable for region 43. */
bogdanm	92:4fc01daae5a5	3552	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
bogdanm	92:4fc01daae5a5	3553	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
bogdanm	92:4fc01daae5a5	3554	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3555	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3556	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3557
bogdanm	92:4fc01daae5a5	3558	/* Bit 10 : Protection enable for region 42. */
bogdanm	92:4fc01daae5a5	3559	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
bogdanm	92:4fc01daae5a5	3560	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
bogdanm	92:4fc01daae5a5	3561	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3562	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3563	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3564
bogdanm	92:4fc01daae5a5	3565	/* Bit 9 : Protection enable for region 41. */
bogdanm	92:4fc01daae5a5	3566	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
bogdanm	92:4fc01daae5a5	3567	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
bogdanm	92:4fc01daae5a5	3568	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3569	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3570	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3571
bogdanm	92:4fc01daae5a5	3572	/* Bit 8 : Protection enable for region 40. */
bogdanm	92:4fc01daae5a5	3573	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
bogdanm	92:4fc01daae5a5	3574	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
bogdanm	92:4fc01daae5a5	3575	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3576	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3577	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3578
bogdanm	92:4fc01daae5a5	3579	/* Bit 7 : Protection enable for region 39. */
bogdanm	92:4fc01daae5a5	3580	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
bogdanm	92:4fc01daae5a5	3581	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
bogdanm	92:4fc01daae5a5	3582	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3583	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3584	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3585
bogdanm	92:4fc01daae5a5	3586	/* Bit 6 : Protection enable for region 38. */
bogdanm	92:4fc01daae5a5	3587	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
bogdanm	92:4fc01daae5a5	3588	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
bogdanm	92:4fc01daae5a5	3589	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3590	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3591	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3592
bogdanm	92:4fc01daae5a5	3593	/* Bit 5 : Protection enable for region 37. */
bogdanm	92:4fc01daae5a5	3594	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
bogdanm	92:4fc01daae5a5	3595	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
bogdanm	92:4fc01daae5a5	3596	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3597	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3598	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3599
bogdanm	92:4fc01daae5a5	3600	/* Bit 4 : Protection enable for region 36. */
bogdanm	92:4fc01daae5a5	3601	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
bogdanm	92:4fc01daae5a5	3602	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
bogdanm	92:4fc01daae5a5	3603	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3604	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3605	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3606
bogdanm	92:4fc01daae5a5	3607	/* Bit 3 : Protection enable for region 35. */
bogdanm	92:4fc01daae5a5	3608	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
bogdanm	92:4fc01daae5a5	3609	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
bogdanm	92:4fc01daae5a5	3610	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3611	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3612	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3613
bogdanm	92:4fc01daae5a5	3614	/* Bit 2 : Protection enable for region 34. */
bogdanm	92:4fc01daae5a5	3615	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
bogdanm	92:4fc01daae5a5	3616	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
bogdanm	92:4fc01daae5a5	3617	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3618	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3619	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3620
bogdanm	92:4fc01daae5a5	3621	/* Bit 1 : Protection enable for region 33. */
bogdanm	92:4fc01daae5a5	3622	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
bogdanm	92:4fc01daae5a5	3623	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
bogdanm	92:4fc01daae5a5	3624	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3625	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3626	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3627
bogdanm	92:4fc01daae5a5	3628	/* Bit 0 : Protection enable for region 32. */
bogdanm	92:4fc01daae5a5	3629	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
bogdanm	92:4fc01daae5a5	3630	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
bogdanm	92:4fc01daae5a5	3631	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3632	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3633	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
bogdanm	92:4fc01daae5a5	3634
bogdanm	92:4fc01daae5a5	3635	/* Register: MPU_DISABLEINDEBUG */
Kojto	97:433970e64889	3636	/* Description: Disable erase and write protection mechanism in debug mode. */
bogdanm	92:4fc01daae5a5	3637
bogdanm	92:4fc01daae5a5	3638	/* Bit 0 : Disable protection mechanism in debug mode. */
bogdanm	92:4fc01daae5a5	3639	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
bogdanm	92:4fc01daae5a5	3640	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
bogdanm	92:4fc01daae5a5	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
bogdanm	92:4fc01daae5a5	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
bogdanm	92:4fc01daae5a5	3643
Kojto	97:433970e64889	3644	/* Register: MPU_PROTBLOCKSIZE */
Kojto	97:433970e64889	3645	/* Description: Erase and write protection block size. */
Kojto	97:433970e64889	3646
Kojto	97:433970e64889	3647	/* Bits 1..0 : Erase and write protection block size. */
Kojto	97:433970e64889	3648	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3649	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
Kojto	97:433970e64889	3651
bogdanm	92:4fc01daae5a5	3652
bogdanm	92:4fc01daae5a5	3653	/* Peripheral: NVMC */
bogdanm	92:4fc01daae5a5	3654	/* Description: Non Volatile Memory Controller. */
bogdanm	92:4fc01daae5a5	3655
bogdanm	92:4fc01daae5a5	3656	/* Register: NVMC_READY */
bogdanm	92:4fc01daae5a5	3657	/* Description: Ready flag. */
bogdanm	92:4fc01daae5a5	3658
bogdanm	92:4fc01daae5a5	3659	/* Bit 0 : NVMC ready. */
bogdanm	92:4fc01daae5a5	3660	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	3661	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	3662	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
bogdanm	92:4fc01daae5a5	3663	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
bogdanm	92:4fc01daae5a5	3664
bogdanm	92:4fc01daae5a5	3665	/* Register: NVMC_CONFIG */
bogdanm	92:4fc01daae5a5	3666	/* Description: Configuration register. */
bogdanm	92:4fc01daae5a5	3667
bogdanm	92:4fc01daae5a5	3668	/* Bits 1..0 : Program write enable. */
bogdanm	92:4fc01daae5a5	3669	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
bogdanm	92:4fc01daae5a5	3670	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
bogdanm	92:4fc01daae5a5	3671	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
bogdanm	92:4fc01daae5a5	3672	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
bogdanm	92:4fc01daae5a5	3673	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
bogdanm	92:4fc01daae5a5	3674
bogdanm	92:4fc01daae5a5	3675	/* Register: NVMC_ERASEALL */
bogdanm	92:4fc01daae5a5	3676	/* Description: Register for erasing all non-volatile user memory. */
bogdanm	92:4fc01daae5a5	3677
bogdanm	92:4fc01daae5a5	3678	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
bogdanm	92:4fc01daae5a5	3679	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
bogdanm	92:4fc01daae5a5	3680	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
bogdanm	92:4fc01daae5a5	3681	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
bogdanm	92:4fc01daae5a5	3682	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
bogdanm	92:4fc01daae5a5	3683
bogdanm	92:4fc01daae5a5	3684	/* Register: NVMC_ERASEUICR */
bogdanm	92:4fc01daae5a5	3685	/* Description: Register for start erasing User Information Congfiguration Registers. */
bogdanm	92:4fc01daae5a5	3686
bogdanm	92:4fc01daae5a5	3687	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
bogdanm	92:4fc01daae5a5	3688	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
bogdanm	92:4fc01daae5a5	3689	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
bogdanm	92:4fc01daae5a5	3690	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
bogdanm	92:4fc01daae5a5	3691	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
bogdanm	92:4fc01daae5a5	3692
bogdanm	92:4fc01daae5a5	3693
bogdanm	92:4fc01daae5a5	3694	/* Peripheral: POWER */
bogdanm	92:4fc01daae5a5	3695	/* Description: Power Control. */
bogdanm	92:4fc01daae5a5	3696
bogdanm	92:4fc01daae5a5	3697	/* Register: POWER_INTENSET */
bogdanm	92:4fc01daae5a5	3698	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	3699
bogdanm	92:4fc01daae5a5	3700	/* Bit 2 : Enable interrupt on POFWARN event. */
bogdanm	92:4fc01daae5a5	3701	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	92:4fc01daae5a5	3702	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	92:4fc01daae5a5	3703	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	3704	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	3705	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	3706
bogdanm	92:4fc01daae5a5	3707	/* Register: POWER_INTENCLR */
bogdanm	92:4fc01daae5a5	3708	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	3709
bogdanm	92:4fc01daae5a5	3710	/* Bit 2 : Disable interrupt on POFWARN event. */
bogdanm	92:4fc01daae5a5	3711	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	92:4fc01daae5a5	3712	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	92:4fc01daae5a5	3713	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	3714	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	3715	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	3716
bogdanm	92:4fc01daae5a5	3717	/* Register: POWER_RESETREAS */
bogdanm	92:4fc01daae5a5	3718	/* Description: Reset reason. */
bogdanm	92:4fc01daae5a5	3719
bogdanm	92:4fc01daae5a5	3720	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
bogdanm	92:4fc01daae5a5	3721	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
bogdanm	92:4fc01daae5a5	3722	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
bogdanm	92:4fc01daae5a5	3723
bogdanm	92:4fc01daae5a5	3724	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
bogdanm	92:4fc01daae5a5	3725	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
bogdanm	92:4fc01daae5a5	3726	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
bogdanm	92:4fc01daae5a5	3727
bogdanm	92:4fc01daae5a5	3728	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
bogdanm	92:4fc01daae5a5	3729	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
bogdanm	92:4fc01daae5a5	3730	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
bogdanm	92:4fc01daae5a5	3731
bogdanm	92:4fc01daae5a5	3732	/* Bit 3 : Reset from CPU lock-up detected. */
bogdanm	92:4fc01daae5a5	3733	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
bogdanm	92:4fc01daae5a5	3734	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
bogdanm	92:4fc01daae5a5	3735
bogdanm	92:4fc01daae5a5	3736	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
bogdanm	92:4fc01daae5a5	3737	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
bogdanm	92:4fc01daae5a5	3738	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
bogdanm	92:4fc01daae5a5	3739
bogdanm	92:4fc01daae5a5	3740	/* Bit 1 : Reset from watchdog detected. */
bogdanm	92:4fc01daae5a5	3741	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
bogdanm	92:4fc01daae5a5	3742	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
bogdanm	92:4fc01daae5a5	3743
bogdanm	92:4fc01daae5a5	3744	/* Bit 0 : Reset from pin-reset detected. */
bogdanm	92:4fc01daae5a5	3745	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
bogdanm	92:4fc01daae5a5	3746	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
bogdanm	92:4fc01daae5a5	3747
Kojto	97:433970e64889	3748	/* Register: POWER_RAMSTATUS */
Kojto	97:433970e64889	3749	/* Description: Ram status register. */
Kojto	97:433970e64889	3750
Kojto	97:433970e64889	3751	/* Bit 3 : RAM block 3 status. */
Kojto	97:433970e64889	3752	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
Kojto	97:433970e64889	3753	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
Kojto	97:433970e64889	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
Kojto	97:433970e64889	3755	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
Kojto	97:433970e64889	3756
Kojto	97:433970e64889	3757	/* Bit 2 : RAM block 2 status. */
Kojto	97:433970e64889	3758	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
Kojto	97:433970e64889	3759	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
Kojto	97:433970e64889	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
Kojto	97:433970e64889	3761	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
Kojto	97:433970e64889	3762
Kojto	97:433970e64889	3763	/* Bit 1 : RAM block 1 status. */
Kojto	97:433970e64889	3764	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
Kojto	97:433970e64889	3765	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
Kojto	97:433970e64889	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
Kojto	97:433970e64889	3767	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
Kojto	97:433970e64889	3768
Kojto	97:433970e64889	3769	/* Bit 0 : RAM block 0 status. */
Kojto	97:433970e64889	3770	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
Kojto	97:433970e64889	3771	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
Kojto	97:433970e64889	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
Kojto	97:433970e64889	3773	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
Kojto	97:433970e64889	3774
bogdanm	92:4fc01daae5a5	3775	/* Register: POWER_SYSTEMOFF */
bogdanm	92:4fc01daae5a5	3776	/* Description: System off register. */
bogdanm	92:4fc01daae5a5	3777
bogdanm	92:4fc01daae5a5	3778	/* Bit 0 : Enter system off mode. */
bogdanm	92:4fc01daae5a5	3779	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
bogdanm	92:4fc01daae5a5	3780	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
bogdanm	92:4fc01daae5a5	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
bogdanm	92:4fc01daae5a5	3782
bogdanm	92:4fc01daae5a5	3783	/* Register: POWER_POFCON */
bogdanm	92:4fc01daae5a5	3784	/* Description: Power failure configuration. */
bogdanm	92:4fc01daae5a5	3785
bogdanm	92:4fc01daae5a5	3786	/* Bits 2..1 : Set threshold level. */
bogdanm	92:4fc01daae5a5	3787	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
bogdanm	92:4fc01daae5a5	3788	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
bogdanm	92:4fc01daae5a5	3789	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
bogdanm	92:4fc01daae5a5	3790	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
bogdanm	92:4fc01daae5a5	3791	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
bogdanm	92:4fc01daae5a5	3792	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
bogdanm	92:4fc01daae5a5	3793
bogdanm	92:4fc01daae5a5	3794	/* Bit 0 : Power failure comparator enable. */
bogdanm	92:4fc01daae5a5	3795	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
bogdanm	92:4fc01daae5a5	3796	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
bogdanm	92:4fc01daae5a5	3797	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	3798	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	3799
bogdanm	92:4fc01daae5a5	3800	/* Register: POWER_GPREGRET */
bogdanm	92:4fc01daae5a5	3801	/* Description: General purpose retention register. This register is a retained register. */
bogdanm	92:4fc01daae5a5	3802
bogdanm	92:4fc01daae5a5	3803	/* Bits 7..0 : General purpose retention register. */
bogdanm	92:4fc01daae5a5	3804	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
bogdanm	92:4fc01daae5a5	3805	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
bogdanm	92:4fc01daae5a5	3806
bogdanm	92:4fc01daae5a5	3807	/* Register: POWER_RAMON */
bogdanm	92:4fc01daae5a5	3808	/* Description: Ram on/off. */
bogdanm	92:4fc01daae5a5	3809
bogdanm	92:4fc01daae5a5	3810	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
bogdanm	92:4fc01daae5a5	3811	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
bogdanm	92:4fc01daae5a5	3812	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
bogdanm	92:4fc01daae5a5	3813	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
bogdanm	92:4fc01daae5a5	3814	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
bogdanm	92:4fc01daae5a5	3815
bogdanm	92:4fc01daae5a5	3816	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
bogdanm	92:4fc01daae5a5	3817	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
bogdanm	92:4fc01daae5a5	3818	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
bogdanm	92:4fc01daae5a5	3819	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
bogdanm	92:4fc01daae5a5	3820	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
bogdanm	92:4fc01daae5a5	3821
bogdanm	92:4fc01daae5a5	3822	/* Bit 1 : RAM block 1 behaviour in ON mode. */
bogdanm	92:4fc01daae5a5	3823	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
bogdanm	92:4fc01daae5a5	3824	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
bogdanm	92:4fc01daae5a5	3825	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
bogdanm	92:4fc01daae5a5	3826	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
bogdanm	92:4fc01daae5a5	3827
bogdanm	92:4fc01daae5a5	3828	/* Bit 0 : RAM block 0 behaviour in ON mode. */
bogdanm	92:4fc01daae5a5	3829	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
bogdanm	92:4fc01daae5a5	3830	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
bogdanm	92:4fc01daae5a5	3831	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
bogdanm	92:4fc01daae5a5	3832	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
bogdanm	92:4fc01daae5a5	3833
bogdanm	92:4fc01daae5a5	3834	/* Register: POWER_RESET */
bogdanm	92:4fc01daae5a5	3835	/* Description: Pin reset functionality configuration register. This register is a retained register. */
bogdanm	92:4fc01daae5a5	3836
Kojto	97:433970e64889	3837	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
bogdanm	92:4fc01daae5a5	3838	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
bogdanm	92:4fc01daae5a5	3839	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
bogdanm	92:4fc01daae5a5	3840	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
bogdanm	92:4fc01daae5a5	3841	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
bogdanm	92:4fc01daae5a5	3842
Kojto	97:433970e64889	3843	/* Register: POWER_RAMONB */
Kojto	97:433970e64889	3844	/* Description: Ram on/off. */
Kojto	97:433970e64889	3845
Kojto	97:433970e64889	3846	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
Kojto	97:433970e64889	3847	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
Kojto	97:433970e64889	3848	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
Kojto	97:433970e64889	3849	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
Kojto	97:433970e64889	3850	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
Kojto	97:433970e64889	3851
Kojto	97:433970e64889	3852	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
Kojto	97:433970e64889	3853	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
Kojto	97:433970e64889	3854	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
Kojto	97:433970e64889	3855	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
Kojto	97:433970e64889	3856	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
Kojto	97:433970e64889	3857
Kojto	97:433970e64889	3858	/* Bit 1 : RAM block 3 behaviour in ON mode. */
Kojto	97:433970e64889	3859	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
Kojto	97:433970e64889	3860	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
Kojto	97:433970e64889	3861	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
Kojto	97:433970e64889	3862	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
Kojto	97:433970e64889	3863
Kojto	97:433970e64889	3864	/* Bit 0 : RAM block 2 behaviour in ON mode. */
Kojto	97:433970e64889	3865	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
Kojto	97:433970e64889	3866	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
Kojto	97:433970e64889	3867	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
Kojto	97:433970e64889	3868	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
Kojto	97:433970e64889	3869
bogdanm	92:4fc01daae5a5	3870	/* Register: POWER_DCDCEN */
bogdanm	92:4fc01daae5a5	3871	/* Description: DCDC converter enable configuration register. */
bogdanm	92:4fc01daae5a5	3872
bogdanm	92:4fc01daae5a5	3873	/* Bit 0 : Enable DCDC converter. */
bogdanm	92:4fc01daae5a5	3874	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
bogdanm	92:4fc01daae5a5	3875	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
bogdanm	92:4fc01daae5a5	3876	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
bogdanm	92:4fc01daae5a5	3877	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
bogdanm	92:4fc01daae5a5	3878
Kojto	97:433970e64889	3879	/* Register: POWER_DCDCFORCE */
Kojto	97:433970e64889	3880	/* Description: DCDC power-up force register. */
Kojto	97:433970e64889	3881
Kojto	97:433970e64889	3882	/* Bit 1 : DCDC power-up force on. */
Kojto	97:433970e64889	3883	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
Kojto	97:433970e64889	3884	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
Kojto	97:433970e64889	3885	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3886	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3887
Kojto	97:433970e64889	3888	/* Bit 0 : DCDC power-up force off. */
Kojto	97:433970e64889	3889	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
Kojto	97:433970e64889	3890	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
Kojto	97:433970e64889	3891	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3892	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3893
bogdanm	92:4fc01daae5a5	3894
bogdanm	92:4fc01daae5a5	3895	/* Peripheral: PPI */
bogdanm	92:4fc01daae5a5	3896	/* Description: PPI controller. */
bogdanm	92:4fc01daae5a5	3897
bogdanm	92:4fc01daae5a5	3898	/* Register: PPI_CHEN */
bogdanm	92:4fc01daae5a5	3899	/* Description: Channel enable. */
bogdanm	92:4fc01daae5a5	3900
bogdanm	92:4fc01daae5a5	3901	/* Bit 31 : Enable PPI channel 31. */
bogdanm	92:4fc01daae5a5	3902	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	92:4fc01daae5a5	3903	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	92:4fc01daae5a5	3904	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3905	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3906
bogdanm	92:4fc01daae5a5	3907	/* Bit 30 : Enable PPI channel 30. */
bogdanm	92:4fc01daae5a5	3908	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	92:4fc01daae5a5	3909	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	92:4fc01daae5a5	3910	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3911	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3912
bogdanm	92:4fc01daae5a5	3913	/* Bit 29 : Enable PPI channel 29. */
bogdanm	92:4fc01daae5a5	3914	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	92:4fc01daae5a5	3915	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	92:4fc01daae5a5	3916	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3917	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3918
bogdanm	92:4fc01daae5a5	3919	/* Bit 28 : Enable PPI channel 28. */
bogdanm	92:4fc01daae5a5	3920	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	92:4fc01daae5a5	3921	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	92:4fc01daae5a5	3922	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3923	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3924
bogdanm	92:4fc01daae5a5	3925	/* Bit 27 : Enable PPI channel 27. */
bogdanm	92:4fc01daae5a5	3926	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	92:4fc01daae5a5	3927	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	92:4fc01daae5a5	3928	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3929	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3930
bogdanm	92:4fc01daae5a5	3931	/* Bit 26 : Enable PPI channel 26. */
bogdanm	92:4fc01daae5a5	3932	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	92:4fc01daae5a5	3933	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	92:4fc01daae5a5	3934	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3935	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3936
bogdanm	92:4fc01daae5a5	3937	/* Bit 25 : Enable PPI channel 25. */
bogdanm	92:4fc01daae5a5	3938	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	92:4fc01daae5a5	3939	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	92:4fc01daae5a5	3940	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3941	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3942
bogdanm	92:4fc01daae5a5	3943	/* Bit 24 : Enable PPI channel 24. */
bogdanm	92:4fc01daae5a5	3944	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	92:4fc01daae5a5	3945	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	92:4fc01daae5a5	3946	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3947	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3948
bogdanm	92:4fc01daae5a5	3949	/* Bit 23 : Enable PPI channel 23. */
bogdanm	92:4fc01daae5a5	3950	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	92:4fc01daae5a5	3951	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	92:4fc01daae5a5	3952	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3953	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3954
bogdanm	92:4fc01daae5a5	3955	/* Bit 22 : Enable PPI channel 22. */
bogdanm	92:4fc01daae5a5	3956	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	92:4fc01daae5a5	3957	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	92:4fc01daae5a5	3958	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3959	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3960
bogdanm	92:4fc01daae5a5	3961	/* Bit 21 : Enable PPI channel 21. */
bogdanm	92:4fc01daae5a5	3962	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	92:4fc01daae5a5	3963	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	92:4fc01daae5a5	3964	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3965	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3966
bogdanm	92:4fc01daae5a5	3967	/* Bit 20 : Enable PPI channel 20. */
bogdanm	92:4fc01daae5a5	3968	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	92:4fc01daae5a5	3969	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	92:4fc01daae5a5	3970	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3971	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3972
bogdanm	92:4fc01daae5a5	3973	/* Bit 15 : Enable PPI channel 15. */
bogdanm	92:4fc01daae5a5	3974	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	92:4fc01daae5a5	3975	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	92:4fc01daae5a5	3976	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3977	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3978
bogdanm	92:4fc01daae5a5	3979	/* Bit 14 : Enable PPI channel 14. */
bogdanm	92:4fc01daae5a5	3980	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	92:4fc01daae5a5	3981	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	92:4fc01daae5a5	3982	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3983	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3984
bogdanm	92:4fc01daae5a5	3985	/* Bit 13 : Enable PPI channel 13. */
bogdanm	92:4fc01daae5a5	3986	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	92:4fc01daae5a5	3987	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	92:4fc01daae5a5	3988	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3989	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3990
bogdanm	92:4fc01daae5a5	3991	/* Bit 12 : Enable PPI channel 12. */
bogdanm	92:4fc01daae5a5	3992	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	92:4fc01daae5a5	3993	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	92:4fc01daae5a5	3994	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	3995	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	3996
bogdanm	92:4fc01daae5a5	3997	/* Bit 11 : Enable PPI channel 11. */
bogdanm	92:4fc01daae5a5	3998	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	92:4fc01daae5a5	3999	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	92:4fc01daae5a5	4000	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4001	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4002
bogdanm	92:4fc01daae5a5	4003	/* Bit 10 : Enable PPI channel 10. */
bogdanm	92:4fc01daae5a5	4004	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	92:4fc01daae5a5	4005	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	92:4fc01daae5a5	4006	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4007	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4008
bogdanm	92:4fc01daae5a5	4009	/* Bit 9 : Enable PPI channel 9. */
bogdanm	92:4fc01daae5a5	4010	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	92:4fc01daae5a5	4011	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	92:4fc01daae5a5	4012	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4013	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4014
bogdanm	92:4fc01daae5a5	4015	/* Bit 8 : Enable PPI channel 8. */
bogdanm	92:4fc01daae5a5	4016	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	92:4fc01daae5a5	4017	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	92:4fc01daae5a5	4018	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4019	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4020
bogdanm	92:4fc01daae5a5	4021	/* Bit 7 : Enable PPI channel 7. */
bogdanm	92:4fc01daae5a5	4022	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	92:4fc01daae5a5	4023	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	92:4fc01daae5a5	4024	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4025	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4026
bogdanm	92:4fc01daae5a5	4027	/* Bit 6 : Enable PPI channel 6. */
bogdanm	92:4fc01daae5a5	4028	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	92:4fc01daae5a5	4029	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	92:4fc01daae5a5	4030	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4031	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4032
bogdanm	92:4fc01daae5a5	4033	/* Bit 5 : Enable PPI channel 5. */
bogdanm	92:4fc01daae5a5	4034	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	92:4fc01daae5a5	4035	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	92:4fc01daae5a5	4036	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4037	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4038
bogdanm	92:4fc01daae5a5	4039	/* Bit 4 : Enable PPI channel 4. */
bogdanm	92:4fc01daae5a5	4040	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	92:4fc01daae5a5	4041	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	92:4fc01daae5a5	4042	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4043	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4044
bogdanm	92:4fc01daae5a5	4045	/* Bit 3 : Enable PPI channel 3. */
bogdanm	92:4fc01daae5a5	4046	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	92:4fc01daae5a5	4047	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	92:4fc01daae5a5	4048	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
bogdanm	92:4fc01daae5a5	4049	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
bogdanm	92:4fc01daae5a5	4050
bogdanm	92:4fc01daae5a5	4051	/* Bit 2 : Enable PPI channel 2. */
bogdanm	92:4fc01daae5a5	4052	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	92:4fc01daae5a5	4053	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	92:4fc01daae5a5	4054	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4055	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4056
bogdanm	92:4fc01daae5a5	4057	/* Bit 1 : Enable PPI channel 1. */
bogdanm	92:4fc01daae5a5	4058	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	92:4fc01daae5a5	4059	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	92:4fc01daae5a5	4060	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4061	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4062
bogdanm	92:4fc01daae5a5	4063	/* Bit 0 : Enable PPI channel 0. */
bogdanm	92:4fc01daae5a5	4064	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	92:4fc01daae5a5	4065	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	92:4fc01daae5a5	4066	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4067	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4068
bogdanm	92:4fc01daae5a5	4069	/* Register: PPI_CHENSET */
bogdanm	92:4fc01daae5a5	4070	/* Description: Channel enable set. */
bogdanm	92:4fc01daae5a5	4071
bogdanm	92:4fc01daae5a5	4072	/* Bit 31 : Enable PPI channel 31. */
bogdanm	92:4fc01daae5a5	4073	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	92:4fc01daae5a5	4074	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	92:4fc01daae5a5	4075	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4076	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4077	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4078
bogdanm	92:4fc01daae5a5	4079	/* Bit 30 : Enable PPI channel 30. */
bogdanm	92:4fc01daae5a5	4080	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	92:4fc01daae5a5	4081	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	92:4fc01daae5a5	4082	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4083	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4084	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4085
bogdanm	92:4fc01daae5a5	4086	/* Bit 29 : Enable PPI channel 29. */
bogdanm	92:4fc01daae5a5	4087	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	92:4fc01daae5a5	4088	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	92:4fc01daae5a5	4089	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4090	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4091	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4092
bogdanm	92:4fc01daae5a5	4093	/* Bit 28 : Enable PPI channel 28. */
bogdanm	92:4fc01daae5a5	4094	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	92:4fc01daae5a5	4095	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	92:4fc01daae5a5	4096	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4097	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4098	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4099
bogdanm	92:4fc01daae5a5	4100	/* Bit 27 : Enable PPI channel 27. */
bogdanm	92:4fc01daae5a5	4101	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	92:4fc01daae5a5	4102	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	92:4fc01daae5a5	4103	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4104	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4105	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4106
bogdanm	92:4fc01daae5a5	4107	/* Bit 26 : Enable PPI channel 26. */
bogdanm	92:4fc01daae5a5	4108	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	92:4fc01daae5a5	4109	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	92:4fc01daae5a5	4110	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4111	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4112	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4113
bogdanm	92:4fc01daae5a5	4114	/* Bit 25 : Enable PPI channel 25. */
bogdanm	92:4fc01daae5a5	4115	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	92:4fc01daae5a5	4116	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	92:4fc01daae5a5	4117	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4118	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4119	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4120
bogdanm	92:4fc01daae5a5	4121	/* Bit 24 : Enable PPI channel 24. */
bogdanm	92:4fc01daae5a5	4122	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	92:4fc01daae5a5	4123	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	92:4fc01daae5a5	4124	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4125	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4126	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4127
bogdanm	92:4fc01daae5a5	4128	/* Bit 23 : Enable PPI channel 23. */
bogdanm	92:4fc01daae5a5	4129	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	92:4fc01daae5a5	4130	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	92:4fc01daae5a5	4131	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4132	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4133	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4134
bogdanm	92:4fc01daae5a5	4135	/* Bit 22 : Enable PPI channel 22. */
bogdanm	92:4fc01daae5a5	4136	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	92:4fc01daae5a5	4137	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	92:4fc01daae5a5	4138	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4139	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4140	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4141
bogdanm	92:4fc01daae5a5	4142	/* Bit 21 : Enable PPI channel 21. */
bogdanm	92:4fc01daae5a5	4143	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	92:4fc01daae5a5	4144	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	92:4fc01daae5a5	4145	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4146	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4147	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4148
bogdanm	92:4fc01daae5a5	4149	/* Bit 20 : Enable PPI channel 20. */
bogdanm	92:4fc01daae5a5	4150	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	92:4fc01daae5a5	4151	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	92:4fc01daae5a5	4152	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4153	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4154	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4155
bogdanm	92:4fc01daae5a5	4156	/* Bit 15 : Enable PPI channel 15. */
bogdanm	92:4fc01daae5a5	4157	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	92:4fc01daae5a5	4158	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	92:4fc01daae5a5	4159	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4160	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4161	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4162
bogdanm	92:4fc01daae5a5	4163	/* Bit 14 : Enable PPI channel 14. */
bogdanm	92:4fc01daae5a5	4164	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	92:4fc01daae5a5	4165	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	92:4fc01daae5a5	4166	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4167	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4168	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4169
bogdanm	92:4fc01daae5a5	4170	/* Bit 13 : Enable PPI channel 13. */
bogdanm	92:4fc01daae5a5	4171	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	92:4fc01daae5a5	4172	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	92:4fc01daae5a5	4173	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4174	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4175	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4176
bogdanm	92:4fc01daae5a5	4177	/* Bit 12 : Enable PPI channel 12. */
bogdanm	92:4fc01daae5a5	4178	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	92:4fc01daae5a5	4179	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	92:4fc01daae5a5	4180	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4181	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4182	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4183
bogdanm	92:4fc01daae5a5	4184	/* Bit 11 : Enable PPI channel 11. */
bogdanm	92:4fc01daae5a5	4185	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	92:4fc01daae5a5	4186	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	92:4fc01daae5a5	4187	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4188	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4189	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4190
bogdanm	92:4fc01daae5a5	4191	/* Bit 10 : Enable PPI channel 10. */
bogdanm	92:4fc01daae5a5	4192	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	92:4fc01daae5a5	4193	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	92:4fc01daae5a5	4194	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4195	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4196	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4197
bogdanm	92:4fc01daae5a5	4198	/* Bit 9 : Enable PPI channel 9. */
bogdanm	92:4fc01daae5a5	4199	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	92:4fc01daae5a5	4200	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	92:4fc01daae5a5	4201	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4202	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4203	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4204
bogdanm	92:4fc01daae5a5	4205	/* Bit 8 : Enable PPI channel 8. */
bogdanm	92:4fc01daae5a5	4206	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	92:4fc01daae5a5	4207	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	92:4fc01daae5a5	4208	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4209	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4210	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4211
bogdanm	92:4fc01daae5a5	4212	/* Bit 7 : Enable PPI channel 7. */
bogdanm	92:4fc01daae5a5	4213	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	92:4fc01daae5a5	4214	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	92:4fc01daae5a5	4215	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4216	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4217	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4218
bogdanm	92:4fc01daae5a5	4219	/* Bit 6 : Enable PPI channel 6. */
bogdanm	92:4fc01daae5a5	4220	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	92:4fc01daae5a5	4221	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	92:4fc01daae5a5	4222	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4223	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4224	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4225
bogdanm	92:4fc01daae5a5	4226	/* Bit 5 : Enable PPI channel 5. */
bogdanm	92:4fc01daae5a5	4227	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	92:4fc01daae5a5	4228	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	92:4fc01daae5a5	4229	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4230	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4231	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4232
bogdanm	92:4fc01daae5a5	4233	/* Bit 4 : Enable PPI channel 4. */
bogdanm	92:4fc01daae5a5	4234	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	92:4fc01daae5a5	4235	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	92:4fc01daae5a5	4236	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4237	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4238	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4239
bogdanm	92:4fc01daae5a5	4240	/* Bit 3 : Enable PPI channel 3. */
bogdanm	92:4fc01daae5a5	4241	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	92:4fc01daae5a5	4242	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	92:4fc01daae5a5	4243	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4244	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4245	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4246
bogdanm	92:4fc01daae5a5	4247	/* Bit 2 : Enable PPI channel 2. */
bogdanm	92:4fc01daae5a5	4248	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	92:4fc01daae5a5	4249	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	92:4fc01daae5a5	4250	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4251	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4252	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4253
bogdanm	92:4fc01daae5a5	4254	/* Bit 1 : Enable PPI channel 1. */
bogdanm	92:4fc01daae5a5	4255	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	92:4fc01daae5a5	4256	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	92:4fc01daae5a5	4257	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4258	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4259	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4260
bogdanm	92:4fc01daae5a5	4261	/* Bit 0 : Enable PPI channel 0. */
bogdanm	92:4fc01daae5a5	4262	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	92:4fc01daae5a5	4263	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	92:4fc01daae5a5	4264	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4265	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4266	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
bogdanm	92:4fc01daae5a5	4267
bogdanm	92:4fc01daae5a5	4268	/* Register: PPI_CHENCLR */
bogdanm	92:4fc01daae5a5	4269	/* Description: Channel enable clear. */
bogdanm	92:4fc01daae5a5	4270
bogdanm	92:4fc01daae5a5	4271	/* Bit 31 : Disable PPI channel 31. */
bogdanm	92:4fc01daae5a5	4272	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	92:4fc01daae5a5	4273	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	92:4fc01daae5a5	4274	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4275	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4276	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4277
bogdanm	92:4fc01daae5a5	4278	/* Bit 30 : Disable PPI channel 30. */
bogdanm	92:4fc01daae5a5	4279	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	92:4fc01daae5a5	4280	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	92:4fc01daae5a5	4281	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4282	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4283	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4284
bogdanm	92:4fc01daae5a5	4285	/* Bit 29 : Disable PPI channel 29. */
bogdanm	92:4fc01daae5a5	4286	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	92:4fc01daae5a5	4287	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	92:4fc01daae5a5	4288	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4289	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4290	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4291
bogdanm	92:4fc01daae5a5	4292	/* Bit 28 : Disable PPI channel 28. */
bogdanm	92:4fc01daae5a5	4293	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	92:4fc01daae5a5	4294	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	92:4fc01daae5a5	4295	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4296	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4297	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4298
bogdanm	92:4fc01daae5a5	4299	/* Bit 27 : Disable PPI channel 27. */
bogdanm	92:4fc01daae5a5	4300	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	92:4fc01daae5a5	4301	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	92:4fc01daae5a5	4302	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4303	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4304	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4305
bogdanm	92:4fc01daae5a5	4306	/* Bit 26 : Disable PPI channel 26. */
bogdanm	92:4fc01daae5a5	4307	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	92:4fc01daae5a5	4308	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	92:4fc01daae5a5	4309	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4310	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4311	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4312
bogdanm	92:4fc01daae5a5	4313	/* Bit 25 : Disable PPI channel 25. */
bogdanm	92:4fc01daae5a5	4314	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	92:4fc01daae5a5	4315	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	92:4fc01daae5a5	4316	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4317	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4318	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4319
bogdanm	92:4fc01daae5a5	4320	/* Bit 24 : Disable PPI channel 24. */
bogdanm	92:4fc01daae5a5	4321	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	92:4fc01daae5a5	4322	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	92:4fc01daae5a5	4323	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4324	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4325	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4326
bogdanm	92:4fc01daae5a5	4327	/* Bit 23 : Disable PPI channel 23. */
bogdanm	92:4fc01daae5a5	4328	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	92:4fc01daae5a5	4329	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	92:4fc01daae5a5	4330	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4331	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4332	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4333
bogdanm	92:4fc01daae5a5	4334	/* Bit 22 : Disable PPI channel 22. */
bogdanm	92:4fc01daae5a5	4335	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	92:4fc01daae5a5	4336	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	92:4fc01daae5a5	4337	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4338	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4339	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4340
bogdanm	92:4fc01daae5a5	4341	/* Bit 21 : Disable PPI channel 21. */
bogdanm	92:4fc01daae5a5	4342	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	92:4fc01daae5a5	4343	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	92:4fc01daae5a5	4344	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4345	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4346	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4347
bogdanm	92:4fc01daae5a5	4348	/* Bit 20 : Disable PPI channel 20. */
bogdanm	92:4fc01daae5a5	4349	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	92:4fc01daae5a5	4350	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	92:4fc01daae5a5	4351	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4352	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4353	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4354
bogdanm	92:4fc01daae5a5	4355	/* Bit 15 : Disable PPI channel 15. */
bogdanm	92:4fc01daae5a5	4356	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	92:4fc01daae5a5	4357	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	92:4fc01daae5a5	4358	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4359	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4360	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4361
bogdanm	92:4fc01daae5a5	4362	/* Bit 14 : Disable PPI channel 14. */
bogdanm	92:4fc01daae5a5	4363	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	92:4fc01daae5a5	4364	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	92:4fc01daae5a5	4365	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4366	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4367	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4368
bogdanm	92:4fc01daae5a5	4369	/* Bit 13 : Disable PPI channel 13. */
bogdanm	92:4fc01daae5a5	4370	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	92:4fc01daae5a5	4371	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	92:4fc01daae5a5	4372	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4373	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4374	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4375
bogdanm	92:4fc01daae5a5	4376	/* Bit 12 : Disable PPI channel 12. */
bogdanm	92:4fc01daae5a5	4377	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	92:4fc01daae5a5	4378	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	92:4fc01daae5a5	4379	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4380	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4381	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4382
bogdanm	92:4fc01daae5a5	4383	/* Bit 11 : Disable PPI channel 11. */
bogdanm	92:4fc01daae5a5	4384	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	92:4fc01daae5a5	4385	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	92:4fc01daae5a5	4386	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4387	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4388	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4389
bogdanm	92:4fc01daae5a5	4390	/* Bit 10 : Disable PPI channel 10. */
bogdanm	92:4fc01daae5a5	4391	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	92:4fc01daae5a5	4392	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	92:4fc01daae5a5	4393	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4394	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4395	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4396
bogdanm	92:4fc01daae5a5	4397	/* Bit 9 : Disable PPI channel 9. */
bogdanm	92:4fc01daae5a5	4398	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	92:4fc01daae5a5	4399	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	92:4fc01daae5a5	4400	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4401	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4402	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4403
bogdanm	92:4fc01daae5a5	4404	/* Bit 8 : Disable PPI channel 8. */
bogdanm	92:4fc01daae5a5	4405	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	92:4fc01daae5a5	4406	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	92:4fc01daae5a5	4407	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4408	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4409	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4410
bogdanm	92:4fc01daae5a5	4411	/* Bit 7 : Disable PPI channel 7. */
bogdanm	92:4fc01daae5a5	4412	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	92:4fc01daae5a5	4413	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	92:4fc01daae5a5	4414	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4415	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4416	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4417
bogdanm	92:4fc01daae5a5	4418	/* Bit 6 : Disable PPI channel 6. */
bogdanm	92:4fc01daae5a5	4419	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	92:4fc01daae5a5	4420	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	92:4fc01daae5a5	4421	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4422	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4423	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4424
bogdanm	92:4fc01daae5a5	4425	/* Bit 5 : Disable PPI channel 5. */
bogdanm	92:4fc01daae5a5	4426	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	92:4fc01daae5a5	4427	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	92:4fc01daae5a5	4428	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4429	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4430	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4431
bogdanm	92:4fc01daae5a5	4432	/* Bit 4 : Disable PPI channel 4. */
bogdanm	92:4fc01daae5a5	4433	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	92:4fc01daae5a5	4434	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	92:4fc01daae5a5	4435	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4436	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4437	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4438
bogdanm	92:4fc01daae5a5	4439	/* Bit 3 : Disable PPI channel 3. */
bogdanm	92:4fc01daae5a5	4440	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	92:4fc01daae5a5	4441	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	92:4fc01daae5a5	4442	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4443	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4444	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4445
bogdanm	92:4fc01daae5a5	4446	/* Bit 2 : Disable PPI channel 2. */
bogdanm	92:4fc01daae5a5	4447	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	92:4fc01daae5a5	4448	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	92:4fc01daae5a5	4449	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4450	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4451	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4452
bogdanm	92:4fc01daae5a5	4453	/* Bit 1 : Disable PPI channel 1. */
bogdanm	92:4fc01daae5a5	4454	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	92:4fc01daae5a5	4455	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	92:4fc01daae5a5	4456	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4457	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4458	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4459
bogdanm	92:4fc01daae5a5	4460	/* Bit 0 : Disable PPI channel 0. */
bogdanm	92:4fc01daae5a5	4461	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	92:4fc01daae5a5	4462	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	92:4fc01daae5a5	4463	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	92:4fc01daae5a5	4464	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	92:4fc01daae5a5	4465	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
bogdanm	92:4fc01daae5a5	4466
bogdanm	92:4fc01daae5a5	4467	/* Register: PPI_CHG */
bogdanm	92:4fc01daae5a5	4468	/* Description: Channel group configuration. */
bogdanm	92:4fc01daae5a5	4469
bogdanm	92:4fc01daae5a5	4470	/* Bit 31 : Include CH31 in channel group. */
bogdanm	92:4fc01daae5a5	4471	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	92:4fc01daae5a5	4472	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	92:4fc01daae5a5	4473	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4474	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4475
bogdanm	92:4fc01daae5a5	4476	/* Bit 30 : Include CH30 in channel group. */
bogdanm	92:4fc01daae5a5	4477	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	92:4fc01daae5a5	4478	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	92:4fc01daae5a5	4479	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4480	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4481
bogdanm	92:4fc01daae5a5	4482	/* Bit 29 : Include CH29 in channel group. */
bogdanm	92:4fc01daae5a5	4483	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	92:4fc01daae5a5	4484	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	92:4fc01daae5a5	4485	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4486	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4487
bogdanm	92:4fc01daae5a5	4488	/* Bit 28 : Include CH28 in channel group. */
bogdanm	92:4fc01daae5a5	4489	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	92:4fc01daae5a5	4490	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	92:4fc01daae5a5	4491	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4492	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4493
bogdanm	92:4fc01daae5a5	4494	/* Bit 27 : Include CH27 in channel group. */
bogdanm	92:4fc01daae5a5	4495	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	92:4fc01daae5a5	4496	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	92:4fc01daae5a5	4497	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4498	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4499
bogdanm	92:4fc01daae5a5	4500	/* Bit 26 : Include CH26 in channel group. */
bogdanm	92:4fc01daae5a5	4501	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	92:4fc01daae5a5	4502	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	92:4fc01daae5a5	4503	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4504	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4505
bogdanm	92:4fc01daae5a5	4506	/* Bit 25 : Include CH25 in channel group. */
bogdanm	92:4fc01daae5a5	4507	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	92:4fc01daae5a5	4508	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	92:4fc01daae5a5	4509	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4510	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4511
bogdanm	92:4fc01daae5a5	4512	/* Bit 24 : Include CH24 in channel group. */
bogdanm	92:4fc01daae5a5	4513	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	92:4fc01daae5a5	4514	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	92:4fc01daae5a5	4515	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4516	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4517
bogdanm	92:4fc01daae5a5	4518	/* Bit 23 : Include CH23 in channel group. */
bogdanm	92:4fc01daae5a5	4519	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	92:4fc01daae5a5	4520	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	92:4fc01daae5a5	4521	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4522	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4523
bogdanm	92:4fc01daae5a5	4524	/* Bit 22 : Include CH22 in channel group. */
bogdanm	92:4fc01daae5a5	4525	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	92:4fc01daae5a5	4526	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	92:4fc01daae5a5	4527	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4528	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4529
bogdanm	92:4fc01daae5a5	4530	/* Bit 21 : Include CH21 in channel group. */
bogdanm	92:4fc01daae5a5	4531	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	92:4fc01daae5a5	4532	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	92:4fc01daae5a5	4533	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4534	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4535
bogdanm	92:4fc01daae5a5	4536	/* Bit 20 : Include CH20 in channel group. */
bogdanm	92:4fc01daae5a5	4537	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	92:4fc01daae5a5	4538	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	92:4fc01daae5a5	4539	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4540	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4541
bogdanm	92:4fc01daae5a5	4542	/* Bit 15 : Include CH15 in channel group. */
bogdanm	92:4fc01daae5a5	4543	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	92:4fc01daae5a5	4544	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	92:4fc01daae5a5	4545	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4546	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4547
bogdanm	92:4fc01daae5a5	4548	/* Bit 14 : Include CH14 in channel group. */
bogdanm	92:4fc01daae5a5	4549	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	92:4fc01daae5a5	4550	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	92:4fc01daae5a5	4551	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4552	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4553
bogdanm	92:4fc01daae5a5	4554	/* Bit 13 : Include CH13 in channel group. */
bogdanm	92:4fc01daae5a5	4555	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	92:4fc01daae5a5	4556	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	92:4fc01daae5a5	4557	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4558	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4559
bogdanm	92:4fc01daae5a5	4560	/* Bit 12 : Include CH12 in channel group. */
bogdanm	92:4fc01daae5a5	4561	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	92:4fc01daae5a5	4562	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	92:4fc01daae5a5	4563	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4564	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4565
bogdanm	92:4fc01daae5a5	4566	/* Bit 11 : Include CH11 in channel group. */
bogdanm	92:4fc01daae5a5	4567	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	92:4fc01daae5a5	4568	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	92:4fc01daae5a5	4569	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4570	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4571
bogdanm	92:4fc01daae5a5	4572	/* Bit 10 : Include CH10 in channel group. */
bogdanm	92:4fc01daae5a5	4573	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	92:4fc01daae5a5	4574	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	92:4fc01daae5a5	4575	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4576	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4577
bogdanm	92:4fc01daae5a5	4578	/* Bit 9 : Include CH9 in channel group. */
bogdanm	92:4fc01daae5a5	4579	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	92:4fc01daae5a5	4580	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	92:4fc01daae5a5	4581	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4582	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4583
bogdanm	92:4fc01daae5a5	4584	/* Bit 8 : Include CH8 in channel group. */
bogdanm	92:4fc01daae5a5	4585	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	92:4fc01daae5a5	4586	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	92:4fc01daae5a5	4587	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4588	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4589
bogdanm	92:4fc01daae5a5	4590	/* Bit 7 : Include CH7 in channel group. */
bogdanm	92:4fc01daae5a5	4591	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	92:4fc01daae5a5	4592	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	92:4fc01daae5a5	4593	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4594	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4595
bogdanm	92:4fc01daae5a5	4596	/* Bit 6 : Include CH6 in channel group. */
bogdanm	92:4fc01daae5a5	4597	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	92:4fc01daae5a5	4598	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	92:4fc01daae5a5	4599	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4600	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4601
bogdanm	92:4fc01daae5a5	4602	/* Bit 5 : Include CH5 in channel group. */
bogdanm	92:4fc01daae5a5	4603	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	92:4fc01daae5a5	4604	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	92:4fc01daae5a5	4605	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4606	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4607
bogdanm	92:4fc01daae5a5	4608	/* Bit 4 : Include CH4 in channel group. */
bogdanm	92:4fc01daae5a5	4609	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	92:4fc01daae5a5	4610	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	92:4fc01daae5a5	4611	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4612	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4613
bogdanm	92:4fc01daae5a5	4614	/* Bit 3 : Include CH3 in channel group. */
bogdanm	92:4fc01daae5a5	4615	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	92:4fc01daae5a5	4616	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	92:4fc01daae5a5	4617	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4618	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4619
bogdanm	92:4fc01daae5a5	4620	/* Bit 2 : Include CH2 in channel group. */
bogdanm	92:4fc01daae5a5	4621	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	92:4fc01daae5a5	4622	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	92:4fc01daae5a5	4623	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4624	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4625
bogdanm	92:4fc01daae5a5	4626	/* Bit 1 : Include CH1 in channel group. */
bogdanm	92:4fc01daae5a5	4627	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	92:4fc01daae5a5	4628	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	92:4fc01daae5a5	4629	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4630	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4631
bogdanm	92:4fc01daae5a5	4632	/* Bit 0 : Include CH0 in channel group. */
bogdanm	92:4fc01daae5a5	4633	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	92:4fc01daae5a5	4634	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	92:4fc01daae5a5	4635	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
bogdanm	92:4fc01daae5a5	4636	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
bogdanm	92:4fc01daae5a5	4637
bogdanm	92:4fc01daae5a5	4638
bogdanm	92:4fc01daae5a5	4639	/* Peripheral: PU */
bogdanm	92:4fc01daae5a5	4640	/* Description: Patch unit. */
bogdanm	92:4fc01daae5a5	4641
bogdanm	92:4fc01daae5a5	4642	/* Register: PU_PATCHADDR */
bogdanm	92:4fc01daae5a5	4643	/* Description: Relative address of patch instructions. */
bogdanm	92:4fc01daae5a5	4644
bogdanm	92:4fc01daae5a5	4645	/* Bits 24..0 : Relative address of patch instructions. */
bogdanm	92:4fc01daae5a5	4646	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
bogdanm	92:4fc01daae5a5	4647	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
bogdanm	92:4fc01daae5a5	4648
bogdanm	92:4fc01daae5a5	4649	/* Register: PU_PATCHEN */
bogdanm	92:4fc01daae5a5	4650	/* Description: Patch enable register. */
bogdanm	92:4fc01daae5a5	4651
bogdanm	92:4fc01daae5a5	4652	/* Bit 7 : Patch 7 enabled. */
bogdanm	92:4fc01daae5a5	4653	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4654	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4655	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4656	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4657
bogdanm	92:4fc01daae5a5	4658	/* Bit 6 : Patch 6 enabled. */
bogdanm	92:4fc01daae5a5	4659	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4660	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4661	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4662	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4663
bogdanm	92:4fc01daae5a5	4664	/* Bit 5 : Patch 5 enabled. */
bogdanm	92:4fc01daae5a5	4665	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4666	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4667	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4668	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4669
bogdanm	92:4fc01daae5a5	4670	/* Bit 4 : Patch 4 enabled. */
bogdanm	92:4fc01daae5a5	4671	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4672	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4673	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4674	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4675
bogdanm	92:4fc01daae5a5	4676	/* Bit 3 : Patch 3 enabled. */
bogdanm	92:4fc01daae5a5	4677	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4678	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4679	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4680	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4681
bogdanm	92:4fc01daae5a5	4682	/* Bit 2 : Patch 2 enabled. */
bogdanm	92:4fc01daae5a5	4683	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4684	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4685	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4686	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4687
bogdanm	92:4fc01daae5a5	4688	/* Bit 1 : Patch 1 enabled. */
bogdanm	92:4fc01daae5a5	4689	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4690	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4691	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4692	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4693
bogdanm	92:4fc01daae5a5	4694	/* Bit 0 : Patch 0 enabled. */
bogdanm	92:4fc01daae5a5	4695	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4696	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4697	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4698	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4699
bogdanm	92:4fc01daae5a5	4700	/* Register: PU_PATCHENSET */
bogdanm	92:4fc01daae5a5	4701	/* Description: Patch enable register. */
bogdanm	92:4fc01daae5a5	4702
bogdanm	92:4fc01daae5a5	4703	/* Bit 7 : Patch 7 enabled. */
bogdanm	92:4fc01daae5a5	4704	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4705	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4706	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4707	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4708	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4709
bogdanm	92:4fc01daae5a5	4710	/* Bit 6 : Patch 6 enabled. */
bogdanm	92:4fc01daae5a5	4711	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4712	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4713	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4714	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4715	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4716
bogdanm	92:4fc01daae5a5	4717	/* Bit 5 : Patch 5 enabled. */
bogdanm	92:4fc01daae5a5	4718	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4719	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4720	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4721	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4722	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4723
bogdanm	92:4fc01daae5a5	4724	/* Bit 4 : Patch 4 enabled. */
bogdanm	92:4fc01daae5a5	4725	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4726	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4727	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4728	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4729	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4730
bogdanm	92:4fc01daae5a5	4731	/* Bit 3 : Patch 3 enabled. */
bogdanm	92:4fc01daae5a5	4732	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4733	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4734	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4735	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4736	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4737
bogdanm	92:4fc01daae5a5	4738	/* Bit 2 : Patch 2 enabled. */
bogdanm	92:4fc01daae5a5	4739	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4740	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4741	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4742	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4743	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4744
bogdanm	92:4fc01daae5a5	4745	/* Bit 1 : Patch 1 enabled. */
bogdanm	92:4fc01daae5a5	4746	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4747	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4748	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4749	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4750	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4751
bogdanm	92:4fc01daae5a5	4752	/* Bit 0 : Patch 0 enabled. */
bogdanm	92:4fc01daae5a5	4753	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4754	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4755	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4756	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4757	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
bogdanm	92:4fc01daae5a5	4758
bogdanm	92:4fc01daae5a5	4759	/* Register: PU_PATCHENCLR */
bogdanm	92:4fc01daae5a5	4760	/* Description: Patch disable register. */
bogdanm	92:4fc01daae5a5	4761
bogdanm	92:4fc01daae5a5	4762	/* Bit 7 : Patch 7 enabled. */
bogdanm	92:4fc01daae5a5	4763	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4764	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
bogdanm	92:4fc01daae5a5	4765	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4766	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4767	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4768
bogdanm	92:4fc01daae5a5	4769	/* Bit 6 : Patch 6 enabled. */
bogdanm	92:4fc01daae5a5	4770	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4771	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
bogdanm	92:4fc01daae5a5	4772	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4773	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4774	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4775
bogdanm	92:4fc01daae5a5	4776	/* Bit 5 : Patch 5 enabled. */
bogdanm	92:4fc01daae5a5	4777	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4778	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
bogdanm	92:4fc01daae5a5	4779	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4780	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4781	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4782
bogdanm	92:4fc01daae5a5	4783	/* Bit 4 : Patch 4 enabled. */
bogdanm	92:4fc01daae5a5	4784	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4785	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
bogdanm	92:4fc01daae5a5	4786	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4787	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4788	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4789
bogdanm	92:4fc01daae5a5	4790	/* Bit 3 : Patch 3 enabled. */
bogdanm	92:4fc01daae5a5	4791	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4792	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
bogdanm	92:4fc01daae5a5	4793	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4794	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4795	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4796
bogdanm	92:4fc01daae5a5	4797	/* Bit 2 : Patch 2 enabled. */
bogdanm	92:4fc01daae5a5	4798	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4799	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
bogdanm	92:4fc01daae5a5	4800	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4801	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4802	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4803
bogdanm	92:4fc01daae5a5	4804	/* Bit 1 : Patch 1 enabled. */
bogdanm	92:4fc01daae5a5	4805	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4806	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
bogdanm	92:4fc01daae5a5	4807	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4808	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4809	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4810
bogdanm	92:4fc01daae5a5	4811	/* Bit 0 : Patch 0 enabled. */
bogdanm	92:4fc01daae5a5	4812	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4813	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
bogdanm	92:4fc01daae5a5	4814	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
bogdanm	92:4fc01daae5a5	4815	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
bogdanm	92:4fc01daae5a5	4816	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
bogdanm	92:4fc01daae5a5	4817
bogdanm	92:4fc01daae5a5	4818
bogdanm	92:4fc01daae5a5	4819	/* Peripheral: QDEC */
bogdanm	92:4fc01daae5a5	4820	/* Description: Rotary decoder. */
bogdanm	92:4fc01daae5a5	4821
bogdanm	92:4fc01daae5a5	4822	/* Register: QDEC_SHORTS */
Kojto	97:433970e64889	4823	/* Description: Shortcuts for the QDEC. */
Kojto	97:433970e64889	4824
Kojto	97:433970e64889	4825	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
bogdanm	92:4fc01daae5a5	4826	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
bogdanm	92:4fc01daae5a5	4827	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
bogdanm	92:4fc01daae5a5	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	4830
Kojto	97:433970e64889	4831	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
bogdanm	92:4fc01daae5a5	4832	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
bogdanm	92:4fc01daae5a5	4833	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
bogdanm	92:4fc01daae5a5	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	4836
bogdanm	92:4fc01daae5a5	4837	/* Register: QDEC_INTENSET */
bogdanm	92:4fc01daae5a5	4838	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	4839
bogdanm	92:4fc01daae5a5	4840	/* Bit 2 : Enable interrupt on ACCOF event. */
bogdanm	92:4fc01daae5a5	4841	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	92:4fc01daae5a5	4842	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	92:4fc01daae5a5	4843	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4844	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4845	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	4846
bogdanm	92:4fc01daae5a5	4847	/* Bit 1 : Enable interrupt on REPORTRDY event. */
bogdanm	92:4fc01daae5a5	4848	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	92:4fc01daae5a5	4849	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	92:4fc01daae5a5	4850	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4851	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4852	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	4853
bogdanm	92:4fc01daae5a5	4854	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
bogdanm	92:4fc01daae5a5	4855	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	92:4fc01daae5a5	4856	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	92:4fc01daae5a5	4857	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4858	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4859	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	4860
bogdanm	92:4fc01daae5a5	4861	/* Register: QDEC_INTENCLR */
bogdanm	92:4fc01daae5a5	4862	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	4863
bogdanm	92:4fc01daae5a5	4864	/* Bit 2 : Disable interrupt on ACCOF event. */
bogdanm	92:4fc01daae5a5	4865	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	92:4fc01daae5a5	4866	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	92:4fc01daae5a5	4867	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4868	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4869	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	4870
bogdanm	92:4fc01daae5a5	4871	/* Bit 1 : Disable interrupt on REPORTRDY event. */
bogdanm	92:4fc01daae5a5	4872	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	92:4fc01daae5a5	4873	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	92:4fc01daae5a5	4874	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4875	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4876	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	4877
bogdanm	92:4fc01daae5a5	4878	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
bogdanm	92:4fc01daae5a5	4879	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	92:4fc01daae5a5	4880	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	92:4fc01daae5a5	4881	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	4882	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	4883	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	4884
bogdanm	92:4fc01daae5a5	4885	/* Register: QDEC_ENABLE */
bogdanm	92:4fc01daae5a5	4886	/* Description: Enable the QDEC. */
bogdanm	92:4fc01daae5a5	4887
bogdanm	92:4fc01daae5a5	4888	/* Bit 0 : Enable or disable QDEC. */
bogdanm	92:4fc01daae5a5	4889	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	4890	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	4891	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
bogdanm	92:4fc01daae5a5	4892	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
bogdanm	92:4fc01daae5a5	4893
bogdanm	92:4fc01daae5a5	4894	/* Register: QDEC_LEDPOL */
bogdanm	92:4fc01daae5a5	4895	/* Description: LED output pin polarity. */
bogdanm	92:4fc01daae5a5	4896
bogdanm	92:4fc01daae5a5	4897	/* Bit 0 : LED output pin polarity. */
bogdanm	92:4fc01daae5a5	4898	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
bogdanm	92:4fc01daae5a5	4899	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
bogdanm	92:4fc01daae5a5	4900	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
bogdanm	92:4fc01daae5a5	4901	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
bogdanm	92:4fc01daae5a5	4902
bogdanm	92:4fc01daae5a5	4903	/* Register: QDEC_SAMPLEPER */
bogdanm	92:4fc01daae5a5	4904	/* Description: Sample period. */
bogdanm	92:4fc01daae5a5	4905
bogdanm	92:4fc01daae5a5	4906	/* Bits 2..0 : Sample period. */
bogdanm	92:4fc01daae5a5	4907	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
bogdanm	92:4fc01daae5a5	4908	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
bogdanm	92:4fc01daae5a5	4909	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
bogdanm	92:4fc01daae5a5	4910	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
bogdanm	92:4fc01daae5a5	4911	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
bogdanm	92:4fc01daae5a5	4912	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
bogdanm	92:4fc01daae5a5	4913	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
bogdanm	92:4fc01daae5a5	4914	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
bogdanm	92:4fc01daae5a5	4915	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
bogdanm	92:4fc01daae5a5	4916	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
bogdanm	92:4fc01daae5a5	4917
bogdanm	92:4fc01daae5a5	4918	/* Register: QDEC_SAMPLE */
bogdanm	92:4fc01daae5a5	4919	/* Description: Motion sample value. */
bogdanm	92:4fc01daae5a5	4920
bogdanm	92:4fc01daae5a5	4921	/* Bits 31..0 : Last sample taken in compliment to 2. */
bogdanm	92:4fc01daae5a5	4922	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
bogdanm	92:4fc01daae5a5	4923	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
bogdanm	92:4fc01daae5a5	4924
bogdanm	92:4fc01daae5a5	4925	/* Register: QDEC_REPORTPER */
bogdanm	92:4fc01daae5a5	4926	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	92:4fc01daae5a5	4927
bogdanm	92:4fc01daae5a5	4928	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	92:4fc01daae5a5	4929	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
bogdanm	92:4fc01daae5a5	4930	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
bogdanm	92:4fc01daae5a5	4931	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
bogdanm	92:4fc01daae5a5	4932	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
bogdanm	92:4fc01daae5a5	4933	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
bogdanm	92:4fc01daae5a5	4934	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
bogdanm	92:4fc01daae5a5	4935	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
bogdanm	92:4fc01daae5a5	4936	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
bogdanm	92:4fc01daae5a5	4937	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
bogdanm	92:4fc01daae5a5	4938	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
bogdanm	92:4fc01daae5a5	4939
bogdanm	92:4fc01daae5a5	4940	/* Register: QDEC_DBFEN */
bogdanm	92:4fc01daae5a5	4941	/* Description: Enable debouncer input filters. */
bogdanm	92:4fc01daae5a5	4942
bogdanm	92:4fc01daae5a5	4943	/* Bit 0 : Enable debounce input filters. */
bogdanm	92:4fc01daae5a5	4944	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
bogdanm	92:4fc01daae5a5	4945	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
bogdanm	92:4fc01daae5a5	4946	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
bogdanm	92:4fc01daae5a5	4947	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
bogdanm	92:4fc01daae5a5	4948
bogdanm	92:4fc01daae5a5	4949	/* Register: QDEC_LEDPRE */
bogdanm	92:4fc01daae5a5	4950	/* Description: Time LED is switched ON before the sample. */
bogdanm	92:4fc01daae5a5	4951
Kojto	97:433970e64889	4952	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
bogdanm	92:4fc01daae5a5	4953	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
Kojto	97:433970e64889	4954	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
bogdanm	92:4fc01daae5a5	4955
bogdanm	92:4fc01daae5a5	4956	/* Register: QDEC_ACCDBL */
bogdanm	92:4fc01daae5a5	4957	/* Description: Accumulated double (error) transitions register. */
bogdanm	92:4fc01daae5a5	4958
bogdanm	92:4fc01daae5a5	4959	/* Bits 3..0 : Accumulated double (error) transitions. */
bogdanm	92:4fc01daae5a5	4960	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
bogdanm	92:4fc01daae5a5	4961	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
bogdanm	92:4fc01daae5a5	4962
bogdanm	92:4fc01daae5a5	4963	/* Register: QDEC_ACCDBLREAD */
bogdanm	92:4fc01daae5a5	4964	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
bogdanm	92:4fc01daae5a5	4965
bogdanm	92:4fc01daae5a5	4966	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
bogdanm	92:4fc01daae5a5	4967	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
bogdanm	92:4fc01daae5a5	4968	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
bogdanm	92:4fc01daae5a5	4969
bogdanm	92:4fc01daae5a5	4970	/* Register: QDEC_POWER */
bogdanm	92:4fc01daae5a5	4971	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	4972
bogdanm	92:4fc01daae5a5	4973	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	4974	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	4975	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	4976	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	4977	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	4978
bogdanm	92:4fc01daae5a5	4979
bogdanm	92:4fc01daae5a5	4980	/* Peripheral: RADIO */
bogdanm	92:4fc01daae5a5	4981	/* Description: The radio. */
bogdanm	92:4fc01daae5a5	4982
bogdanm	92:4fc01daae5a5	4983	/* Register: RADIO_SHORTS */
Kojto	97:433970e64889	4984	/* Description: Shortcuts for the radio. */
bogdanm	92:4fc01daae5a5	4985
bogdanm	92:4fc01daae5a5	4986	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
bogdanm	92:4fc01daae5a5	4987	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
bogdanm	92:4fc01daae5a5	4988	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
bogdanm	92:4fc01daae5a5	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	4991
bogdanm	92:4fc01daae5a5	4992	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
bogdanm	92:4fc01daae5a5	4993	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
bogdanm	92:4fc01daae5a5	4994	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
bogdanm	92:4fc01daae5a5	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	4997
bogdanm	92:4fc01daae5a5	4998	/* Bit 5 : Shortcut between END event and START task. */
bogdanm	92:4fc01daae5a5	4999	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
bogdanm	92:4fc01daae5a5	5000	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
bogdanm	92:4fc01daae5a5	5001	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5002	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5003
bogdanm	92:4fc01daae5a5	5004	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
bogdanm	92:4fc01daae5a5	5005	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
bogdanm	92:4fc01daae5a5	5006	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
bogdanm	92:4fc01daae5a5	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5009
bogdanm	92:4fc01daae5a5	5010	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
bogdanm	92:4fc01daae5a5	5011	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
bogdanm	92:4fc01daae5a5	5012	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
bogdanm	92:4fc01daae5a5	5013	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5014	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5015
bogdanm	92:4fc01daae5a5	5016	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
bogdanm	92:4fc01daae5a5	5017	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
bogdanm	92:4fc01daae5a5	5018	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
bogdanm	92:4fc01daae5a5	5019	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5020	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5021
bogdanm	92:4fc01daae5a5	5022	/* Bit 1 : Shortcut between END event and DISABLE task. */
bogdanm	92:4fc01daae5a5	5023	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
bogdanm	92:4fc01daae5a5	5024	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
bogdanm	92:4fc01daae5a5	5025	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5026	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5027
bogdanm	92:4fc01daae5a5	5028	/* Bit 0 : Shortcut between READY event and START task. */
bogdanm	92:4fc01daae5a5	5029	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
bogdanm	92:4fc01daae5a5	5030	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
bogdanm	92:4fc01daae5a5	5031	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5032	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5033
bogdanm	92:4fc01daae5a5	5034	/* Register: RADIO_INTENSET */
bogdanm	92:4fc01daae5a5	5035	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	5036
bogdanm	92:4fc01daae5a5	5037	/* Bit 10 : Enable interrupt on BCMATCH event. */
bogdanm	92:4fc01daae5a5	5038	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	92:4fc01daae5a5	5039	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	92:4fc01daae5a5	5040	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5041	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5042	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5043
bogdanm	92:4fc01daae5a5	5044	/* Bit 7 : Enable interrupt on RSSIEND event. */
bogdanm	92:4fc01daae5a5	5045	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	92:4fc01daae5a5	5046	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	92:4fc01daae5a5	5047	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5048	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5049	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5050
bogdanm	92:4fc01daae5a5	5051	/* Bit 6 : Enable interrupt on DEVMISS event. */
bogdanm	92:4fc01daae5a5	5052	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	92:4fc01daae5a5	5053	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	92:4fc01daae5a5	5054	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5055	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5056	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5057
bogdanm	92:4fc01daae5a5	5058	/* Bit 5 : Enable interrupt on DEVMATCH event. */
bogdanm	92:4fc01daae5a5	5059	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	92:4fc01daae5a5	5060	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	92:4fc01daae5a5	5061	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5062	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5063	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5064
bogdanm	92:4fc01daae5a5	5065	/* Bit 4 : Enable interrupt on DISABLED event. */
bogdanm	92:4fc01daae5a5	5066	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	92:4fc01daae5a5	5067	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	92:4fc01daae5a5	5068	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5069	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5070	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5071
bogdanm	92:4fc01daae5a5	5072	/* Bit 3 : Enable interrupt on END event. */
bogdanm	92:4fc01daae5a5	5073	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	5074	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	5075	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5076	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5077	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5078
bogdanm	92:4fc01daae5a5	5079	/* Bit 2 : Enable interrupt on PAYLOAD event. */
bogdanm	92:4fc01daae5a5	5080	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	92:4fc01daae5a5	5081	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	92:4fc01daae5a5	5082	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5083	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5084	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5085
bogdanm	92:4fc01daae5a5	5086	/* Bit 1 : Enable interrupt on ADDRESS event. */
bogdanm	92:4fc01daae5a5	5087	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	92:4fc01daae5a5	5088	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	92:4fc01daae5a5	5089	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5090	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5091	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5092
bogdanm	92:4fc01daae5a5	5093	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	5094	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	5095	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	5096	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5097	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5098	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5099
bogdanm	92:4fc01daae5a5	5100	/* Register: RADIO_INTENCLR */
bogdanm	92:4fc01daae5a5	5101	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	5102
bogdanm	92:4fc01daae5a5	5103	/* Bit 10 : Disable interrupt on BCMATCH event. */
bogdanm	92:4fc01daae5a5	5104	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	92:4fc01daae5a5	5105	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	92:4fc01daae5a5	5106	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5107	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5108	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5109
bogdanm	92:4fc01daae5a5	5110	/* Bit 7 : Disable interrupt on RSSIEND event. */
bogdanm	92:4fc01daae5a5	5111	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	92:4fc01daae5a5	5112	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	92:4fc01daae5a5	5113	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5114	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5115	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5116
bogdanm	92:4fc01daae5a5	5117	/* Bit 6 : Disable interrupt on DEVMISS event. */
bogdanm	92:4fc01daae5a5	5118	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	92:4fc01daae5a5	5119	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	92:4fc01daae5a5	5120	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5121	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5122	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5123
bogdanm	92:4fc01daae5a5	5124	/* Bit 5 : Disable interrupt on DEVMATCH event. */
bogdanm	92:4fc01daae5a5	5125	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	92:4fc01daae5a5	5126	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	92:4fc01daae5a5	5127	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5128	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5129	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5130
bogdanm	92:4fc01daae5a5	5131	/* Bit 4 : Disable interrupt on DISABLED event. */
bogdanm	92:4fc01daae5a5	5132	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	92:4fc01daae5a5	5133	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	92:4fc01daae5a5	5134	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5135	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5136	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5137
bogdanm	92:4fc01daae5a5	5138	/* Bit 3 : Disable interrupt on END event. */
bogdanm	92:4fc01daae5a5	5139	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	5140	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	5141	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5142	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5143	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5144
bogdanm	92:4fc01daae5a5	5145	/* Bit 2 : Disable interrupt on PAYLOAD event. */
bogdanm	92:4fc01daae5a5	5146	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	92:4fc01daae5a5	5147	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	92:4fc01daae5a5	5148	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5149	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5150	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5151
bogdanm	92:4fc01daae5a5	5152	/* Bit 1 : Disable interrupt on ADDRESS event. */
bogdanm	92:4fc01daae5a5	5153	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	92:4fc01daae5a5	5154	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	92:4fc01daae5a5	5155	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5156	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5157	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5158
bogdanm	92:4fc01daae5a5	5159	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	5160	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	5161	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	5162	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5163	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5164	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5165
bogdanm	92:4fc01daae5a5	5166	/* Register: RADIO_CRCSTATUS */
bogdanm	92:4fc01daae5a5	5167	/* Description: CRC status of received packet. */
bogdanm	92:4fc01daae5a5	5168
bogdanm	92:4fc01daae5a5	5169	/* Bit 0 : CRC status of received packet. */
bogdanm	92:4fc01daae5a5	5170	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
bogdanm	92:4fc01daae5a5	5171	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
bogdanm	92:4fc01daae5a5	5172	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
bogdanm	92:4fc01daae5a5	5173	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
bogdanm	92:4fc01daae5a5	5174
Kojto	97:433970e64889	5175	/* Register: RADIO_CD */
Kojto	97:433970e64889	5176	/* Description: Carrier detect. */
Kojto	97:433970e64889	5177
Kojto	97:433970e64889	5178	/* Bit 0 : Carrier detect. */
Kojto	97:433970e64889	5179	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
Kojto	97:433970e64889	5180	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
Kojto	97:433970e64889	5181
bogdanm	92:4fc01daae5a5	5182	/* Register: RADIO_RXMATCH */
bogdanm	92:4fc01daae5a5	5183	/* Description: Received address. */
bogdanm	92:4fc01daae5a5	5184
bogdanm	92:4fc01daae5a5	5185	/* Bits 2..0 : Logical address in which previous packet was received. */
bogdanm	92:4fc01daae5a5	5186	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
bogdanm	92:4fc01daae5a5	5187	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
bogdanm	92:4fc01daae5a5	5188
bogdanm	92:4fc01daae5a5	5189	/* Register: RADIO_RXCRC */
bogdanm	92:4fc01daae5a5	5190	/* Description: Received CRC. */
bogdanm	92:4fc01daae5a5	5191
bogdanm	92:4fc01daae5a5	5192	/* Bits 23..0 : CRC field of previously received packet. */
bogdanm	92:4fc01daae5a5	5193	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
bogdanm	92:4fc01daae5a5	5194	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
bogdanm	92:4fc01daae5a5	5195
bogdanm	92:4fc01daae5a5	5196	/* Register: RADIO_DAI */
bogdanm	92:4fc01daae5a5	5197	/* Description: Device address match index. */
bogdanm	92:4fc01daae5a5	5198
Kojto	97:433970e64889	5199	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
bogdanm	92:4fc01daae5a5	5200	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
bogdanm	92:4fc01daae5a5	5201	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
bogdanm	92:4fc01daae5a5	5202
bogdanm	92:4fc01daae5a5	5203	/* Register: RADIO_FREQUENCY */
bogdanm	92:4fc01daae5a5	5204	/* Description: Frequency. */
bogdanm	92:4fc01daae5a5	5205
bogdanm	92:4fc01daae5a5	5206	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
bogdanm	92:4fc01daae5a5	5207	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	5208	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	5209
bogdanm	92:4fc01daae5a5	5210	/* Register: RADIO_TXPOWER */
bogdanm	92:4fc01daae5a5	5211	/* Description: Output power. */
bogdanm	92:4fc01daae5a5	5212
bogdanm	92:4fc01daae5a5	5213	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
bogdanm	92:4fc01daae5a5	5214	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
bogdanm	92:4fc01daae5a5	5215	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
bogdanm	92:4fc01daae5a5	5216	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
bogdanm	92:4fc01daae5a5	5217	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
bogdanm	92:4fc01daae5a5	5218	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
bogdanm	92:4fc01daae5a5	5219	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
bogdanm	92:4fc01daae5a5	5220	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
bogdanm	92:4fc01daae5a5	5221	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
bogdanm	92:4fc01daae5a5	5222	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
bogdanm	92:4fc01daae5a5	5223	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
bogdanm	92:4fc01daae5a5	5224
bogdanm	92:4fc01daae5a5	5225	/* Register: RADIO_MODE */
bogdanm	92:4fc01daae5a5	5226	/* Description: Data rate and modulation. */
bogdanm	92:4fc01daae5a5	5227
bogdanm	92:4fc01daae5a5	5228	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
bogdanm	92:4fc01daae5a5	5229	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	92:4fc01daae5a5	5230	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	92:4fc01daae5a5	5231	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
bogdanm	92:4fc01daae5a5	5232	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
bogdanm	92:4fc01daae5a5	5233	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
bogdanm	92:4fc01daae5a5	5234	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
bogdanm	92:4fc01daae5a5	5235
bogdanm	92:4fc01daae5a5	5236	/* Register: RADIO_PCNF0 */
bogdanm	92:4fc01daae5a5	5237	/* Description: Packet configuration 0. */
bogdanm	92:4fc01daae5a5	5238
bogdanm	92:4fc01daae5a5	5239	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5240	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
bogdanm	92:4fc01daae5a5	5241	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
bogdanm	92:4fc01daae5a5	5242
bogdanm	92:4fc01daae5a5	5243	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5244	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
bogdanm	92:4fc01daae5a5	5245	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
bogdanm	92:4fc01daae5a5	5246
bogdanm	92:4fc01daae5a5	5247	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5248	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
bogdanm	92:4fc01daae5a5	5249	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
bogdanm	92:4fc01daae5a5	5250
bogdanm	92:4fc01daae5a5	5251	/* Register: RADIO_PCNF1 */
bogdanm	92:4fc01daae5a5	5252	/* Description: Packet configuration 1. */
bogdanm	92:4fc01daae5a5	5253
bogdanm	92:4fc01daae5a5	5254	/* Bit 25 : Packet whitening enable. */
bogdanm	92:4fc01daae5a5	5255	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
bogdanm	92:4fc01daae5a5	5256	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
bogdanm	92:4fc01daae5a5	5257	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
bogdanm	92:4fc01daae5a5	5258	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
bogdanm	92:4fc01daae5a5	5259
bogdanm	92:4fc01daae5a5	5260	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5261	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
bogdanm	92:4fc01daae5a5	5262	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
bogdanm	92:4fc01daae5a5	5263	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
bogdanm	92:4fc01daae5a5	5264	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
bogdanm	92:4fc01daae5a5	5265
bogdanm	92:4fc01daae5a5	5266	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5267	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
bogdanm	92:4fc01daae5a5	5268	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
bogdanm	92:4fc01daae5a5	5269
bogdanm	92:4fc01daae5a5	5270	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5271	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
bogdanm	92:4fc01daae5a5	5272	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
bogdanm	92:4fc01daae5a5	5273
bogdanm	92:4fc01daae5a5	5274	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
bogdanm	92:4fc01daae5a5	5275	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
bogdanm	92:4fc01daae5a5	5276	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
bogdanm	92:4fc01daae5a5	5277
bogdanm	92:4fc01daae5a5	5278	/* Register: RADIO_PREFIX0 */
bogdanm	92:4fc01daae5a5	5279	/* Description: Prefixes bytes for logical addresses 0 to 3. */
bogdanm	92:4fc01daae5a5	5280
bogdanm	92:4fc01daae5a5	5281	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5282	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
bogdanm	92:4fc01daae5a5	5283	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
bogdanm	92:4fc01daae5a5	5284
bogdanm	92:4fc01daae5a5	5285	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5286	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
bogdanm	92:4fc01daae5a5	5287	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
bogdanm	92:4fc01daae5a5	5288
bogdanm	92:4fc01daae5a5	5289	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5290	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
bogdanm	92:4fc01daae5a5	5291	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
bogdanm	92:4fc01daae5a5	5292
bogdanm	92:4fc01daae5a5	5293	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5294	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
bogdanm	92:4fc01daae5a5	5295	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
bogdanm	92:4fc01daae5a5	5296
bogdanm	92:4fc01daae5a5	5297	/* Register: RADIO_PREFIX1 */
bogdanm	92:4fc01daae5a5	5298	/* Description: Prefixes bytes for logical addresses 4 to 7. */
bogdanm	92:4fc01daae5a5	5299
bogdanm	92:4fc01daae5a5	5300	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5301	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
bogdanm	92:4fc01daae5a5	5302	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
bogdanm	92:4fc01daae5a5	5303
bogdanm	92:4fc01daae5a5	5304	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5305	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
bogdanm	92:4fc01daae5a5	5306	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
bogdanm	92:4fc01daae5a5	5307
bogdanm	92:4fc01daae5a5	5308	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5309	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
bogdanm	92:4fc01daae5a5	5310	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
bogdanm	92:4fc01daae5a5	5311
bogdanm	92:4fc01daae5a5	5312	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5313	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
bogdanm	92:4fc01daae5a5	5314	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
bogdanm	92:4fc01daae5a5	5315
bogdanm	92:4fc01daae5a5	5316	/* Register: RADIO_TXADDRESS */
bogdanm	92:4fc01daae5a5	5317	/* Description: Transmit address select. */
bogdanm	92:4fc01daae5a5	5318
bogdanm	92:4fc01daae5a5	5319	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5320	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
bogdanm	92:4fc01daae5a5	5321	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
bogdanm	92:4fc01daae5a5	5322
bogdanm	92:4fc01daae5a5	5323	/* Register: RADIO_RXADDRESSES */
bogdanm	92:4fc01daae5a5	5324	/* Description: Receive address select. */
bogdanm	92:4fc01daae5a5	5325
bogdanm	92:4fc01daae5a5	5326	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5327	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
bogdanm	92:4fc01daae5a5	5328	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
bogdanm	92:4fc01daae5a5	5329	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5330	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5331
bogdanm	92:4fc01daae5a5	5332	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5333	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
bogdanm	92:4fc01daae5a5	5334	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
bogdanm	92:4fc01daae5a5	5335	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5336	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5337
bogdanm	92:4fc01daae5a5	5338	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5339	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
bogdanm	92:4fc01daae5a5	5340	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
bogdanm	92:4fc01daae5a5	5341	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5342	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5343
bogdanm	92:4fc01daae5a5	5344	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5345	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
bogdanm	92:4fc01daae5a5	5346	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
bogdanm	92:4fc01daae5a5	5347	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5348	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5349
bogdanm	92:4fc01daae5a5	5350	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5351	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
bogdanm	92:4fc01daae5a5	5352	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
bogdanm	92:4fc01daae5a5	5353	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5354	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5355
bogdanm	92:4fc01daae5a5	5356	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5357	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
bogdanm	92:4fc01daae5a5	5358	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
bogdanm	92:4fc01daae5a5	5359	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5360	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5361
bogdanm	92:4fc01daae5a5	5362	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5363	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
bogdanm	92:4fc01daae5a5	5364	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
bogdanm	92:4fc01daae5a5	5365	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5366	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5367
bogdanm	92:4fc01daae5a5	5368	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5369	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
bogdanm	92:4fc01daae5a5	5370	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
bogdanm	92:4fc01daae5a5	5371	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
bogdanm	92:4fc01daae5a5	5372	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
bogdanm	92:4fc01daae5a5	5373
bogdanm	92:4fc01daae5a5	5374	/* Register: RADIO_CRCCNF */
bogdanm	92:4fc01daae5a5	5375	/* Description: CRC configuration. */
bogdanm	92:4fc01daae5a5	5376
bogdanm	92:4fc01daae5a5	5377	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto	97:433970e64889	5378	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
Kojto	97:433970e64889	5379	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
Kojto	97:433970e64889	5380	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
Kojto	97:433970e64889	5381	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
bogdanm	92:4fc01daae5a5	5382
bogdanm	92:4fc01daae5a5	5383	/* Bits 1..0 : CRC length. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5384	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
bogdanm	92:4fc01daae5a5	5385	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
bogdanm	92:4fc01daae5a5	5386	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
bogdanm	92:4fc01daae5a5	5387	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
bogdanm	92:4fc01daae5a5	5388	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
bogdanm	92:4fc01daae5a5	5389	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
bogdanm	92:4fc01daae5a5	5390
bogdanm	92:4fc01daae5a5	5391	/* Register: RADIO_CRCPOLY */
bogdanm	92:4fc01daae5a5	5392	/* Description: CRC polynomial. */
bogdanm	92:4fc01daae5a5	5393
Kojto	97:433970e64889	5394	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
Kojto	97:433970e64889	5395	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
Kojto	97:433970e64889	5396	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
bogdanm	92:4fc01daae5a5	5397
bogdanm	92:4fc01daae5a5	5398	/* Register: RADIO_CRCINIT */
bogdanm	92:4fc01daae5a5	5399	/* Description: CRC initial value. */
bogdanm	92:4fc01daae5a5	5400
bogdanm	92:4fc01daae5a5	5401	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
bogdanm	92:4fc01daae5a5	5402	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
bogdanm	92:4fc01daae5a5	5403	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
bogdanm	92:4fc01daae5a5	5404
bogdanm	92:4fc01daae5a5	5405	/* Register: RADIO_TEST */
bogdanm	92:4fc01daae5a5	5406	/* Description: Test features enable register. */
bogdanm	92:4fc01daae5a5	5407
bogdanm	92:4fc01daae5a5	5408	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto	97:433970e64889	5409	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
Kojto	97:433970e64889	5410	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
Kojto	97:433970e64889	5411	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
Kojto	97:433970e64889	5412	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
bogdanm	92:4fc01daae5a5	5413
bogdanm	92:4fc01daae5a5	5414	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto	97:433970e64889	5415	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
Kojto	97:433970e64889	5416	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
Kojto	97:433970e64889	5417	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
Kojto	97:433970e64889	5418	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
bogdanm	92:4fc01daae5a5	5419
bogdanm	92:4fc01daae5a5	5420	/* Register: RADIO_TIFS */
bogdanm	92:4fc01daae5a5	5421	/* Description: Inter Frame Spacing in microseconds. */
bogdanm	92:4fc01daae5a5	5422
bogdanm	92:4fc01daae5a5	5423	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
bogdanm	92:4fc01daae5a5	5424	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
bogdanm	92:4fc01daae5a5	5425	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
bogdanm	92:4fc01daae5a5	5426
bogdanm	92:4fc01daae5a5	5427	/* Register: RADIO_RSSISAMPLE */
bogdanm	92:4fc01daae5a5	5428	/* Description: RSSI sample. */
bogdanm	92:4fc01daae5a5	5429
bogdanm	92:4fc01daae5a5	5430	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
bogdanm	92:4fc01daae5a5	5431	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
bogdanm	92:4fc01daae5a5	5432	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
bogdanm	92:4fc01daae5a5	5433
bogdanm	92:4fc01daae5a5	5434	/* Register: RADIO_STATE */
bogdanm	92:4fc01daae5a5	5435	/* Description: Current radio state. */
bogdanm	92:4fc01daae5a5	5436
bogdanm	92:4fc01daae5a5	5437	/* Bits 3..0 : Current radio state. */
bogdanm	92:4fc01daae5a5	5438	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
bogdanm	92:4fc01daae5a5	5439	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	92:4fc01daae5a5	5440	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
bogdanm	92:4fc01daae5a5	5441	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
bogdanm	92:4fc01daae5a5	5442	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
bogdanm	92:4fc01daae5a5	5443	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
bogdanm	92:4fc01daae5a5	5444	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
bogdanm	92:4fc01daae5a5	5445	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
bogdanm	92:4fc01daae5a5	5446	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
bogdanm	92:4fc01daae5a5	5447	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
bogdanm	92:4fc01daae5a5	5448	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
bogdanm	92:4fc01daae5a5	5449
bogdanm	92:4fc01daae5a5	5450	/* Register: RADIO_DATAWHITEIV */
bogdanm	92:4fc01daae5a5	5451	/* Description: Data whitening initial value. */
bogdanm	92:4fc01daae5a5	5452
Kojto	97:433970e64889	5453	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
bogdanm	92:4fc01daae5a5	5454	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
Kojto	97:433970e64889	5455	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
bogdanm	92:4fc01daae5a5	5456
bogdanm	92:4fc01daae5a5	5457	/* Register: RADIO_DAP */
bogdanm	92:4fc01daae5a5	5458	/* Description: Device address prefix. */
bogdanm	92:4fc01daae5a5	5459
bogdanm	92:4fc01daae5a5	5460	/* Bits 15..0 : Device address prefix. */
bogdanm	92:4fc01daae5a5	5461	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
bogdanm	92:4fc01daae5a5	5462	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
bogdanm	92:4fc01daae5a5	5463
bogdanm	92:4fc01daae5a5	5464	/* Register: RADIO_DACNF */
bogdanm	92:4fc01daae5a5	5465	/* Description: Device address match configuration. */
bogdanm	92:4fc01daae5a5	5466
bogdanm	92:4fc01daae5a5	5467	/* Bit 15 : TxAdd for device address 7. */
bogdanm	92:4fc01daae5a5	5468	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
bogdanm	92:4fc01daae5a5	5469	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
bogdanm	92:4fc01daae5a5	5470
bogdanm	92:4fc01daae5a5	5471	/* Bit 14 : TxAdd for device address 6. */
bogdanm	92:4fc01daae5a5	5472	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
bogdanm	92:4fc01daae5a5	5473	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
bogdanm	92:4fc01daae5a5	5474
bogdanm	92:4fc01daae5a5	5475	/* Bit 13 : TxAdd for device address 5. */
bogdanm	92:4fc01daae5a5	5476	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
bogdanm	92:4fc01daae5a5	5477	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
bogdanm	92:4fc01daae5a5	5478
bogdanm	92:4fc01daae5a5	5479	/* Bit 12 : TxAdd for device address 4. */
bogdanm	92:4fc01daae5a5	5480	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
bogdanm	92:4fc01daae5a5	5481	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
bogdanm	92:4fc01daae5a5	5482
bogdanm	92:4fc01daae5a5	5483	/* Bit 11 : TxAdd for device address 3. */
bogdanm	92:4fc01daae5a5	5484	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
bogdanm	92:4fc01daae5a5	5485	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
bogdanm	92:4fc01daae5a5	5486
bogdanm	92:4fc01daae5a5	5487	/* Bit 10 : TxAdd for device address 2. */
bogdanm	92:4fc01daae5a5	5488	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
bogdanm	92:4fc01daae5a5	5489	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
bogdanm	92:4fc01daae5a5	5490
bogdanm	92:4fc01daae5a5	5491	/* Bit 9 : TxAdd for device address 1. */
bogdanm	92:4fc01daae5a5	5492	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
bogdanm	92:4fc01daae5a5	5493	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
bogdanm	92:4fc01daae5a5	5494
bogdanm	92:4fc01daae5a5	5495	/* Bit 8 : TxAdd for device address 0. */
bogdanm	92:4fc01daae5a5	5496	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
bogdanm	92:4fc01daae5a5	5497	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
bogdanm	92:4fc01daae5a5	5498
bogdanm	92:4fc01daae5a5	5499	/* Bit 7 : Enable or disable device address matching using device address 7. */
bogdanm	92:4fc01daae5a5	5500	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
bogdanm	92:4fc01daae5a5	5501	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
bogdanm	92:4fc01daae5a5	5502	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5503	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5504
bogdanm	92:4fc01daae5a5	5505	/* Bit 6 : Enable or disable device address matching using device address 6. */
bogdanm	92:4fc01daae5a5	5506	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
bogdanm	92:4fc01daae5a5	5507	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
bogdanm	92:4fc01daae5a5	5508	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5509	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5510
bogdanm	92:4fc01daae5a5	5511	/* Bit 5 : Enable or disable device address matching using device address 5. */
bogdanm	92:4fc01daae5a5	5512	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
bogdanm	92:4fc01daae5a5	5513	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
bogdanm	92:4fc01daae5a5	5514	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5515	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5516
bogdanm	92:4fc01daae5a5	5517	/* Bit 4 : Enable or disable device address matching using device address 4. */
bogdanm	92:4fc01daae5a5	5518	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
bogdanm	92:4fc01daae5a5	5519	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
bogdanm	92:4fc01daae5a5	5520	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5521	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5522
bogdanm	92:4fc01daae5a5	5523	/* Bit 3 : Enable or disable device address matching using device address 3. */
bogdanm	92:4fc01daae5a5	5524	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
bogdanm	92:4fc01daae5a5	5525	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
bogdanm	92:4fc01daae5a5	5526	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5527	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5528
bogdanm	92:4fc01daae5a5	5529	/* Bit 2 : Enable or disable device address matching using device address 2. */
bogdanm	92:4fc01daae5a5	5530	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
bogdanm	92:4fc01daae5a5	5531	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
bogdanm	92:4fc01daae5a5	5532	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5533	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5534
bogdanm	92:4fc01daae5a5	5535	/* Bit 1 : Enable or disable device address matching using device address 1. */
bogdanm	92:4fc01daae5a5	5536	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
bogdanm	92:4fc01daae5a5	5537	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
bogdanm	92:4fc01daae5a5	5538	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5539	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5540
bogdanm	92:4fc01daae5a5	5541	/* Bit 0 : Enable or disable device address matching using device address 0. */
bogdanm	92:4fc01daae5a5	5542	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
bogdanm	92:4fc01daae5a5	5543	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
bogdanm	92:4fc01daae5a5	5544	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	5545	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	5546
bogdanm	92:4fc01daae5a5	5547	/* Register: RADIO_OVERRIDE0 */
bogdanm	92:4fc01daae5a5	5548	/* Description: Trim value override register 0. */
bogdanm	92:4fc01daae5a5	5549
Kojto	97:433970e64889	5550	/* Bits 31..0 : Trim value override 0. */
bogdanm	92:4fc01daae5a5	5551	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
bogdanm	92:4fc01daae5a5	5552	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
bogdanm	92:4fc01daae5a5	5553
bogdanm	92:4fc01daae5a5	5554	/* Register: RADIO_OVERRIDE1 */
bogdanm	92:4fc01daae5a5	5555	/* Description: Trim value override register 1. */
bogdanm	92:4fc01daae5a5	5556
Kojto	97:433970e64889	5557	/* Bits 31..0 : Trim value override 1. */
bogdanm	92:4fc01daae5a5	5558	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
bogdanm	92:4fc01daae5a5	5559	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
bogdanm	92:4fc01daae5a5	5560
bogdanm	92:4fc01daae5a5	5561	/* Register: RADIO_OVERRIDE2 */
bogdanm	92:4fc01daae5a5	5562	/* Description: Trim value override register 2. */
bogdanm	92:4fc01daae5a5	5563
Kojto	97:433970e64889	5564	/* Bits 31..0 : Trim value override 2. */
bogdanm	92:4fc01daae5a5	5565	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
bogdanm	92:4fc01daae5a5	5566	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
bogdanm	92:4fc01daae5a5	5567
bogdanm	92:4fc01daae5a5	5568	/* Register: RADIO_OVERRIDE3 */
bogdanm	92:4fc01daae5a5	5569	/* Description: Trim value override register 3. */
bogdanm	92:4fc01daae5a5	5570
Kojto	97:433970e64889	5571	/* Bits 31..0 : Trim value override 3. */
bogdanm	92:4fc01daae5a5	5572	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
bogdanm	92:4fc01daae5a5	5573	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
bogdanm	92:4fc01daae5a5	5574
bogdanm	92:4fc01daae5a5	5575	/* Register: RADIO_OVERRIDE4 */
bogdanm	92:4fc01daae5a5	5576	/* Description: Trim value override register 4. */
bogdanm	92:4fc01daae5a5	5577
bogdanm	92:4fc01daae5a5	5578	/* Bit 31 : Enable or disable override of default trim values. */
bogdanm	92:4fc01daae5a5	5579	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	5580	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	5581	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
bogdanm	92:4fc01daae5a5	5582	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
bogdanm	92:4fc01daae5a5	5583
Kojto	97:433970e64889	5584	/* Bits 27..0 : Trim value override 4. */
bogdanm	92:4fc01daae5a5	5585	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
bogdanm	92:4fc01daae5a5	5586	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
bogdanm	92:4fc01daae5a5	5587
bogdanm	92:4fc01daae5a5	5588	/* Register: RADIO_POWER */
bogdanm	92:4fc01daae5a5	5589	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	5590
bogdanm	92:4fc01daae5a5	5591	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	5592	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	5593	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	5594	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	5595	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	5596
bogdanm	92:4fc01daae5a5	5597
bogdanm	92:4fc01daae5a5	5598	/* Peripheral: RNG */
bogdanm	92:4fc01daae5a5	5599	/* Description: Random Number Generator. */
bogdanm	92:4fc01daae5a5	5600
bogdanm	92:4fc01daae5a5	5601	/* Register: RNG_SHORTS */
Kojto	97:433970e64889	5602	/* Description: Shortcuts for the RNG. */
Kojto	97:433970e64889	5603
Kojto	97:433970e64889	5604	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
bogdanm	92:4fc01daae5a5	5605	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
bogdanm	92:4fc01daae5a5	5606	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
bogdanm	92:4fc01daae5a5	5607	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	5608	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	5609
bogdanm	92:4fc01daae5a5	5610	/* Register: RNG_INTENSET */
bogdanm	92:4fc01daae5a5	5611	/* Description: Interrupt enable set register */
bogdanm	92:4fc01daae5a5	5612
bogdanm	92:4fc01daae5a5	5613	/* Bit 0 : Enable interrupt on VALRDY event. */
bogdanm	92:4fc01daae5a5	5614	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	92:4fc01daae5a5	5615	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	92:4fc01daae5a5	5616	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5617	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5618	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5619
bogdanm	92:4fc01daae5a5	5620	/* Register: RNG_INTENCLR */
bogdanm	92:4fc01daae5a5	5621	/* Description: Interrupt enable clear register */
bogdanm	92:4fc01daae5a5	5622
bogdanm	92:4fc01daae5a5	5623	/* Bit 0 : Disable interrupt on VALRDY event. */
bogdanm	92:4fc01daae5a5	5624	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	92:4fc01daae5a5	5625	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	92:4fc01daae5a5	5626	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5627	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5628	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5629
bogdanm	92:4fc01daae5a5	5630	/* Register: RNG_CONFIG */
bogdanm	92:4fc01daae5a5	5631	/* Description: Configuration register. */
bogdanm	92:4fc01daae5a5	5632
bogdanm	92:4fc01daae5a5	5633	/* Bit 0 : Digital error correction enable. */
bogdanm	92:4fc01daae5a5	5634	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
bogdanm	92:4fc01daae5a5	5635	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
bogdanm	92:4fc01daae5a5	5636	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
bogdanm	92:4fc01daae5a5	5637	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
bogdanm	92:4fc01daae5a5	5638
bogdanm	92:4fc01daae5a5	5639	/* Register: RNG_VALUE */
bogdanm	92:4fc01daae5a5	5640	/* Description: RNG random number. */
bogdanm	92:4fc01daae5a5	5641
bogdanm	92:4fc01daae5a5	5642	/* Bits 7..0 : Generated random number. */
bogdanm	92:4fc01daae5a5	5643	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
bogdanm	92:4fc01daae5a5	5644	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
bogdanm	92:4fc01daae5a5	5645
bogdanm	92:4fc01daae5a5	5646	/* Register: RNG_POWER */
bogdanm	92:4fc01daae5a5	5647	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	5648
bogdanm	92:4fc01daae5a5	5649	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	5650	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	5651	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	5652	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	5653	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	5654
bogdanm	92:4fc01daae5a5	5655
bogdanm	92:4fc01daae5a5	5656	/* Peripheral: RTC */
bogdanm	92:4fc01daae5a5	5657	/* Description: Real time counter 0. */
bogdanm	92:4fc01daae5a5	5658
bogdanm	92:4fc01daae5a5	5659	/* Register: RTC_INTENSET */
bogdanm	92:4fc01daae5a5	5660	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	5661
bogdanm	92:4fc01daae5a5	5662	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
bogdanm	92:4fc01daae5a5	5663	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5664	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5665	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5666	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5667	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5668
bogdanm	92:4fc01daae5a5	5669	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
bogdanm	92:4fc01daae5a5	5670	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5671	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5672	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5673	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5674	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5675
bogdanm	92:4fc01daae5a5	5676	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
bogdanm	92:4fc01daae5a5	5677	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5678	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5679	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5680	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5681	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5682
bogdanm	92:4fc01daae5a5	5683	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
bogdanm	92:4fc01daae5a5	5684	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5685	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5686	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5687	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5688	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5689
bogdanm	92:4fc01daae5a5	5690	/* Bit 1 : Enable interrupt on OVRFLW event. */
bogdanm	92:4fc01daae5a5	5691	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5692	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5693	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5694	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5695	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5696
bogdanm	92:4fc01daae5a5	5697	/* Bit 0 : Enable interrupt on TICK event. */
bogdanm	92:4fc01daae5a5	5698	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	92:4fc01daae5a5	5699	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	92:4fc01daae5a5	5700	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5701	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5702	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5703
bogdanm	92:4fc01daae5a5	5704	/* Register: RTC_INTENCLR */
bogdanm	92:4fc01daae5a5	5705	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	5706
bogdanm	92:4fc01daae5a5	5707	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
bogdanm	92:4fc01daae5a5	5708	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5709	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5710	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5711	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5712	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5713
bogdanm	92:4fc01daae5a5	5714	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
bogdanm	92:4fc01daae5a5	5715	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5716	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5717	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5718	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5719	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5720
bogdanm	92:4fc01daae5a5	5721	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
bogdanm	92:4fc01daae5a5	5722	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5723	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5724	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5725	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5726	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5727
bogdanm	92:4fc01daae5a5	5728	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
bogdanm	92:4fc01daae5a5	5729	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5730	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5731	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5732	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5733	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5734
bogdanm	92:4fc01daae5a5	5735	/* Bit 1 : Disable interrupt on OVRFLW event. */
bogdanm	92:4fc01daae5a5	5736	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5737	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5738	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5739	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5740	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5741
bogdanm	92:4fc01daae5a5	5742	/* Bit 0 : Disable interrupt on TICK event. */
bogdanm	92:4fc01daae5a5	5743	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	92:4fc01daae5a5	5744	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	92:4fc01daae5a5	5745	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5746	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5747	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5748
bogdanm	92:4fc01daae5a5	5749	/* Register: RTC_EVTEN */
bogdanm	92:4fc01daae5a5	5750	/* Description: Configures event enable routing to PPI for each RTC event. */
bogdanm	92:4fc01daae5a5	5751
bogdanm	92:4fc01daae5a5	5752	/* Bit 19 : COMPARE[3] event enable. */
bogdanm	92:4fc01daae5a5	5753	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5754	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5755	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5756	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5757
bogdanm	92:4fc01daae5a5	5758	/* Bit 18 : COMPARE[2] event enable. */
bogdanm	92:4fc01daae5a5	5759	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5760	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5761	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5762	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5763
bogdanm	92:4fc01daae5a5	5764	/* Bit 17 : COMPARE[1] event enable. */
bogdanm	92:4fc01daae5a5	5765	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5766	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5767	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5768	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5769
bogdanm	92:4fc01daae5a5	5770	/* Bit 16 : COMPARE[0] event enable. */
bogdanm	92:4fc01daae5a5	5771	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5772	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5773	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5774	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5775
bogdanm	92:4fc01daae5a5	5776	/* Bit 1 : OVRFLW event enable. */
bogdanm	92:4fc01daae5a5	5777	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5778	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5779	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5780	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5781
bogdanm	92:4fc01daae5a5	5782	/* Bit 0 : TICK event enable. */
bogdanm	92:4fc01daae5a5	5783	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	92:4fc01daae5a5	5784	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	92:4fc01daae5a5	5785	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5786	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5787
bogdanm	92:4fc01daae5a5	5788	/* Register: RTC_EVTENSET */
bogdanm	92:4fc01daae5a5	5789	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	92:4fc01daae5a5	5790
bogdanm	92:4fc01daae5a5	5791	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
bogdanm	92:4fc01daae5a5	5792	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5793	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5794	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5795	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5796	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5797
bogdanm	92:4fc01daae5a5	5798	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
bogdanm	92:4fc01daae5a5	5799	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5800	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5801	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5802	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5803	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5804
bogdanm	92:4fc01daae5a5	5805	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
bogdanm	92:4fc01daae5a5	5806	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5807	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5808	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5809	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5810	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5811
bogdanm	92:4fc01daae5a5	5812	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
bogdanm	92:4fc01daae5a5	5813	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5814	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5815	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5816	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5817	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5818
bogdanm	92:4fc01daae5a5	5819	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
bogdanm	92:4fc01daae5a5	5820	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5821	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5822	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5823	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5824	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5825
bogdanm	92:4fc01daae5a5	5826	/* Bit 0 : Enable routing to PPI of TICK event. */
bogdanm	92:4fc01daae5a5	5827	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	92:4fc01daae5a5	5828	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	92:4fc01daae5a5	5829	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5830	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5831	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
bogdanm	92:4fc01daae5a5	5832
bogdanm	92:4fc01daae5a5	5833	/* Register: RTC_EVTENCLR */
bogdanm	92:4fc01daae5a5	5834	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	92:4fc01daae5a5	5835
bogdanm	92:4fc01daae5a5	5836	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
bogdanm	92:4fc01daae5a5	5837	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5838	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	5839	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5840	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5841	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5842
bogdanm	92:4fc01daae5a5	5843	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
bogdanm	92:4fc01daae5a5	5844	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5845	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	5846	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5847	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5848	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5849
bogdanm	92:4fc01daae5a5	5850	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
bogdanm	92:4fc01daae5a5	5851	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5852	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	5853	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5854	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5855	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5856
bogdanm	92:4fc01daae5a5	5857	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
bogdanm	92:4fc01daae5a5	5858	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5859	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	5860	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5861	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5862	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5863
bogdanm	92:4fc01daae5a5	5864	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
bogdanm	92:4fc01daae5a5	5865	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5866	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	92:4fc01daae5a5	5867	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5868	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5869	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5870
bogdanm	92:4fc01daae5a5	5871	/* Bit 0 : Disable routing to PPI of TICK event. */
bogdanm	92:4fc01daae5a5	5872	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	92:4fc01daae5a5	5873	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	92:4fc01daae5a5	5874	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	92:4fc01daae5a5	5875	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	92:4fc01daae5a5	5876	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
bogdanm	92:4fc01daae5a5	5877
bogdanm	92:4fc01daae5a5	5878	/* Register: RTC_COUNTER */
bogdanm	92:4fc01daae5a5	5879	/* Description: Current COUNTER value. */
bogdanm	92:4fc01daae5a5	5880
bogdanm	92:4fc01daae5a5	5881	/* Bits 23..0 : Counter value. */
bogdanm	92:4fc01daae5a5	5882	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
bogdanm	92:4fc01daae5a5	5883	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
bogdanm	92:4fc01daae5a5	5884
bogdanm	92:4fc01daae5a5	5885	/* Register: RTC_PRESCALER */
bogdanm	92:4fc01daae5a5	5886	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
bogdanm	92:4fc01daae5a5	5887
bogdanm	92:4fc01daae5a5	5888	/* Bits 11..0 : RTC PRESCALER value. */
bogdanm	92:4fc01daae5a5	5889	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	92:4fc01daae5a5	5890	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	92:4fc01daae5a5	5891
bogdanm	92:4fc01daae5a5	5892	/* Register: RTC_CC */
bogdanm	92:4fc01daae5a5	5893	/* Description: Capture/compare registers. */
bogdanm	92:4fc01daae5a5	5894
bogdanm	92:4fc01daae5a5	5895	/* Bits 23..0 : Compare value. */
bogdanm	92:4fc01daae5a5	5896	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
bogdanm	92:4fc01daae5a5	5897	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
bogdanm	92:4fc01daae5a5	5898
bogdanm	92:4fc01daae5a5	5899	/* Register: RTC_POWER */
bogdanm	92:4fc01daae5a5	5900	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	5901
bogdanm	92:4fc01daae5a5	5902	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	5903	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	5904	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	5905	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	5906	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	5907
bogdanm	92:4fc01daae5a5	5908
bogdanm	92:4fc01daae5a5	5909	/* Peripheral: SPI */
bogdanm	92:4fc01daae5a5	5910	/* Description: SPI master 0. */
bogdanm	92:4fc01daae5a5	5911
bogdanm	92:4fc01daae5a5	5912	/* Register: SPI_INTENSET */
bogdanm	92:4fc01daae5a5	5913	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	5914
bogdanm	92:4fc01daae5a5	5915	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	5916	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	5917	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	5918	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5919	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5920	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	5921
bogdanm	92:4fc01daae5a5	5922	/* Register: SPI_INTENCLR */
bogdanm	92:4fc01daae5a5	5923	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	5924
bogdanm	92:4fc01daae5a5	5925	/* Bit 2 : Disable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	5926	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	92:4fc01daae5a5	5927	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	92:4fc01daae5a5	5928	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	5929	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	5930	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	5931
bogdanm	92:4fc01daae5a5	5932	/* Register: SPI_ENABLE */
bogdanm	92:4fc01daae5a5	5933	/* Description: Enable SPI. */
bogdanm	92:4fc01daae5a5	5934
bogdanm	92:4fc01daae5a5	5935	/* Bits 2..0 : Enable or disable SPI. */
bogdanm	92:4fc01daae5a5	5936	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	5937	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	5938	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
bogdanm	92:4fc01daae5a5	5939	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
bogdanm	92:4fc01daae5a5	5940
bogdanm	92:4fc01daae5a5	5941	/* Register: SPI_RXD */
bogdanm	92:4fc01daae5a5	5942	/* Description: RX data. */
bogdanm	92:4fc01daae5a5	5943
bogdanm	92:4fc01daae5a5	5944	/* Bits 7..0 : RX data from last transfer. */
bogdanm	92:4fc01daae5a5	5945	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	92:4fc01daae5a5	5946	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	92:4fc01daae5a5	5947
bogdanm	92:4fc01daae5a5	5948	/* Register: SPI_TXD */
bogdanm	92:4fc01daae5a5	5949	/* Description: TX data. */
bogdanm	92:4fc01daae5a5	5950
bogdanm	92:4fc01daae5a5	5951	/* Bits 7..0 : TX data for next transfer. */
bogdanm	92:4fc01daae5a5	5952	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	92:4fc01daae5a5	5953	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	92:4fc01daae5a5	5954
bogdanm	92:4fc01daae5a5	5955	/* Register: SPI_FREQUENCY */
bogdanm	92:4fc01daae5a5	5956	/* Description: SPI frequency */
bogdanm	92:4fc01daae5a5	5957
bogdanm	92:4fc01daae5a5	5958	/* Bits 31..0 : SPI data rate. */
bogdanm	92:4fc01daae5a5	5959	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	5960	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	5961	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
bogdanm	92:4fc01daae5a5	5962	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
bogdanm	92:4fc01daae5a5	5963	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
bogdanm	92:4fc01daae5a5	5964	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
bogdanm	92:4fc01daae5a5	5965	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
bogdanm	92:4fc01daae5a5	5966	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
bogdanm	92:4fc01daae5a5	5967	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
bogdanm	92:4fc01daae5a5	5968
bogdanm	92:4fc01daae5a5	5969	/* Register: SPI_CONFIG */
bogdanm	92:4fc01daae5a5	5970	/* Description: Configuration register. */
bogdanm	92:4fc01daae5a5	5971
bogdanm	92:4fc01daae5a5	5972	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	92:4fc01daae5a5	5973	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	92:4fc01daae5a5	5974	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	92:4fc01daae5a5	5975	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	92:4fc01daae5a5	5976	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	92:4fc01daae5a5	5977
bogdanm	92:4fc01daae5a5	5978	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	92:4fc01daae5a5	5979	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	92:4fc01daae5a5	5980	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	92:4fc01daae5a5	5981	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	92:4fc01daae5a5	5982	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	92:4fc01daae5a5	5983
bogdanm	92:4fc01daae5a5	5984	/* Bit 0 : Bit order. */
bogdanm	92:4fc01daae5a5	5985	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	92:4fc01daae5a5	5986	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	92:4fc01daae5a5	5987	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	92:4fc01daae5a5	5988	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	92:4fc01daae5a5	5989
bogdanm	92:4fc01daae5a5	5990	/* Register: SPI_POWER */
bogdanm	92:4fc01daae5a5	5991	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	5992
bogdanm	92:4fc01daae5a5	5993	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	5994	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	5995	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	5996	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	5997	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	5998
bogdanm	92:4fc01daae5a5	5999
Kojto	97:433970e64889	6000	/* Peripheral: SPIM */
Kojto	97:433970e64889	6001	/* Description: SPI master with easyDMA 1. */
Kojto	97:433970e64889	6002
Kojto	97:433970e64889	6003	/* Register: SPIM_SHORTS */
Kojto	97:433970e64889	6004	/* Description: Shortcuts for SPIM. */
Kojto	97:433970e64889	6005
Kojto	97:433970e64889	6006	/* Bit 17 : Shortcut between END event and START task. */
Kojto	97:433970e64889	6007	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
Kojto	97:433970e64889	6008	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
Kojto	97:433970e64889	6009	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	97:433970e64889	6010	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	97:433970e64889	6011
Kojto	97:433970e64889	6012	/* Register: SPIM_INTENSET */
Kojto	97:433970e64889	6013	/* Description: Interrupt enable set register. */
Kojto	97:433970e64889	6014
Kojto	97:433970e64889	6015	/* Bit 19 : Enable interrupt on STARTED event. */
Kojto	97:433970e64889	6016	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	6017	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	6018	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6019	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6020	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6021
Kojto	97:433970e64889	6022	/* Bit 8 : Enable interrupt on ENDTX event. */
Kojto	97:433970e64889	6023	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	6024	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	6025	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6026	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6027	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6028
Kojto	97:433970e64889	6029	/* Bit 6 : Enable interrupt on END event. */
Kojto	97:433970e64889	6030	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
Kojto	97:433970e64889	6031	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	97:433970e64889	6032	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6033	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6034	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6035
Kojto	97:433970e64889	6036	/* Bit 4 : Enable interrupt on ENDRX event. */
Kojto	97:433970e64889	6037	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	6038	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	6039	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6040	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6041	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6042
Kojto	97:433970e64889	6043	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	97:433970e64889	6044	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	6045	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	6046	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6047	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6048	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6049
Kojto	97:433970e64889	6050	/* Register: SPIM_INTENCLR */
Kojto	97:433970e64889	6051	/* Description: Interrupt enable clear register. */
Kojto	97:433970e64889	6052
Kojto	97:433970e64889	6053	/* Bit 19 : Disable interrupt on STARTED event. */
Kojto	97:433970e64889	6054	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	6055	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	6056	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6057	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6058	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6059
Kojto	97:433970e64889	6060	/* Bit 8 : Disable interrupt on ENDTX event. */
Kojto	97:433970e64889	6061	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	6062	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	6063	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6064	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6065	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6066
Kojto	97:433970e64889	6067	/* Bit 6 : Disable interrupt on END event. */
Kojto	97:433970e64889	6068	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
Kojto	97:433970e64889	6069	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	97:433970e64889	6070	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6071	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6072	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6073
Kojto	97:433970e64889	6074	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	97:433970e64889	6075	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	6076	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	6077	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6078	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6079	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6080
Kojto	97:433970e64889	6081	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	97:433970e64889	6082	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	6083	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	6084	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6085	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6086	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6087
Kojto	97:433970e64889	6088	/* Register: SPIM_ENABLE */
Kojto	97:433970e64889	6089	/* Description: Enable SPIM. */
Kojto	97:433970e64889	6090
Kojto	97:433970e64889	6091	/* Bits 3..0 : Enable or disable SPIM. */
Kojto	97:433970e64889	6092	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	97:433970e64889	6093	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	97:433970e64889	6094	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
Kojto	97:433970e64889	6095	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
Kojto	97:433970e64889	6096
Kojto	97:433970e64889	6097	/* Register: SPIM_RXDDATA */
Kojto	97:433970e64889	6098	/* Description: RXD register. */
Kojto	97:433970e64889	6099
Kojto	97:433970e64889	6100	/* Bits 7..0 : RX data received. Double buffered. */
Kojto	97:433970e64889	6101	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	97:433970e64889	6102	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	97:433970e64889	6103
Kojto	97:433970e64889	6104	/* Register: SPIM_TXDDATA */
Kojto	97:433970e64889	6105	/* Description: TXD register. */
Kojto	97:433970e64889	6106
Kojto	97:433970e64889	6107	/* Bits 7..0 : TX data to send. Double buffered. */
Kojto	97:433970e64889	6108	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	97:433970e64889	6109	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	97:433970e64889	6110
Kojto	97:433970e64889	6111	/* Register: SPIM_FREQUENCY */
Kojto	97:433970e64889	6112	/* Description: SPI frequency. */
Kojto	97:433970e64889	6113
Kojto	97:433970e64889	6114	/* Bits 31..0 : SPI master data rate. */
Kojto	97:433970e64889	6115	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	97:433970e64889	6116	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	97:433970e64889	6117	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
Kojto	97:433970e64889	6118	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	97:433970e64889	6119	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
Kojto	97:433970e64889	6120	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
Kojto	97:433970e64889	6121	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
Kojto	97:433970e64889	6122	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
Kojto	97:433970e64889	6123	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
Kojto	97:433970e64889	6124
Kojto	97:433970e64889	6125	/* Register: SPIM_CONFIG */
Kojto	97:433970e64889	6126	/* Description: Configuration register. */
Kojto	97:433970e64889	6127
Kojto	97:433970e64889	6128	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	97:433970e64889	6129	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	97:433970e64889	6130	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	97:433970e64889	6131	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	97:433970e64889	6132	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	97:433970e64889	6133
Kojto	97:433970e64889	6134	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	97:433970e64889	6135	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	97:433970e64889	6136	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	97:433970e64889	6137	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	97:433970e64889	6138	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	97:433970e64889	6139
Kojto	97:433970e64889	6140	/* Bit 0 : Bit order. */
Kojto	97:433970e64889	6141	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	97:433970e64889	6142	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	97:433970e64889	6143	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	97:433970e64889	6144	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	97:433970e64889	6145
Kojto	97:433970e64889	6146	/* Register: SPIM_ORC */
Kojto	97:433970e64889	6147	/* Description: Over-read character. */
Kojto	97:433970e64889	6148
Kojto	97:433970e64889	6149	/* Bits 7..0 : Over-read character. */
Kojto	97:433970e64889	6150	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	97:433970e64889	6151	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	97:433970e64889	6152
Kojto	97:433970e64889	6153	/* Register: SPIM_POWER */
Kojto	97:433970e64889	6154	/* Description: Peripheral power control. */
Kojto	97:433970e64889	6155
Kojto	97:433970e64889	6156	/* Bit 0 : Peripheral power control. */
Kojto	97:433970e64889	6157	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	97:433970e64889	6158	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	97:433970e64889	6159	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	97:433970e64889	6160	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	97:433970e64889	6161
Kojto	97:433970e64889	6162	/* Register: SPIM_RXD_PTR */
Kojto	97:433970e64889	6163	/* Description: Data pointer. */
Kojto	97:433970e64889	6164
Kojto	97:433970e64889	6165	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	6166	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	6167	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	6168
Kojto	97:433970e64889	6169	/* Register: SPIM_RXD_MAXCNT */
Kojto	97:433970e64889	6170	/* Description: Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	6171
Kojto	97:433970e64889	6172	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	6173	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	6174	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	6175
Kojto	97:433970e64889	6176	/* Register: SPIM_RXD_AMOUNT */
Kojto	97:433970e64889	6177	/* Description: Number of bytes received in the last transaction. */
Kojto	97:433970e64889	6178
Kojto	97:433970e64889	6179	/* Bits 7..0 : Number of bytes received in the last transaction. */
Kojto	97:433970e64889	6180	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	6181	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	6182
Kojto	97:433970e64889	6183	/* Register: SPIM_TXD_PTR */
Kojto	97:433970e64889	6184	/* Description: Data pointer. */
Kojto	97:433970e64889	6185
Kojto	97:433970e64889	6186	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	6187	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	6188	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	6189
Kojto	97:433970e64889	6190	/* Register: SPIM_TXD_MAXCNT */
Kojto	97:433970e64889	6191	/* Description: Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	6192
Kojto	97:433970e64889	6193	/* Bits 7..0 : Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	6194	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	6195	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	6196
Kojto	97:433970e64889	6197	/* Register: SPIM_TXD_AMOUNT */
Kojto	97:433970e64889	6198	/* Description: Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	6199
Kojto	97:433970e64889	6200	/* Bits 7..0 : Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	6201	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	6202	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	6203
Kojto	97:433970e64889	6204
bogdanm	92:4fc01daae5a5	6205	/* Peripheral: SPIS */
bogdanm	92:4fc01daae5a5	6206	/* Description: SPI slave 1. */
bogdanm	92:4fc01daae5a5	6207
bogdanm	92:4fc01daae5a5	6208	/* Register: SPIS_SHORTS */
bogdanm	92:4fc01daae5a5	6209	/* Description: Shortcuts for SPIS. */
bogdanm	92:4fc01daae5a5	6210
bogdanm	92:4fc01daae5a5	6211	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
bogdanm	92:4fc01daae5a5	6212	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
bogdanm	92:4fc01daae5a5	6213	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
bogdanm	92:4fc01daae5a5	6214	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6215	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6216
bogdanm	92:4fc01daae5a5	6217	/* Register: SPIS_INTENSET */
bogdanm	92:4fc01daae5a5	6218	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6219
bogdanm	92:4fc01daae5a5	6220	/* Bit 10 : Enable interrupt on ACQUIRED event. */
bogdanm	92:4fc01daae5a5	6221	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	92:4fc01daae5a5	6222	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	92:4fc01daae5a5	6223	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6224	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6225	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6226
bogdanm	92:4fc01daae5a5	6227	/* Bit 1 : Enable interrupt on END event. */
bogdanm	92:4fc01daae5a5	6228	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	6229	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	6230	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6231	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6232	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6233
bogdanm	92:4fc01daae5a5	6234	/* Register: SPIS_INTENCLR */
bogdanm	92:4fc01daae5a5	6235	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6236
bogdanm	92:4fc01daae5a5	6237	/* Bit 10 : Disable interrupt on ACQUIRED event. */
bogdanm	92:4fc01daae5a5	6238	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	92:4fc01daae5a5	6239	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	92:4fc01daae5a5	6240	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6241	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6242	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6243
bogdanm	92:4fc01daae5a5	6244	/* Bit 1 : Disable interrupt on END event. */
bogdanm	92:4fc01daae5a5	6245	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
bogdanm	92:4fc01daae5a5	6246	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	92:4fc01daae5a5	6247	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6248	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6249	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6250
bogdanm	92:4fc01daae5a5	6251	/* Register: SPIS_SEMSTAT */
bogdanm	92:4fc01daae5a5	6252	/* Description: Semaphore status. */
bogdanm	92:4fc01daae5a5	6253
bogdanm	92:4fc01daae5a5	6254	/* Bits 1..0 : Semaphore status. */
bogdanm	92:4fc01daae5a5	6255	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
bogdanm	92:4fc01daae5a5	6256	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
bogdanm	92:4fc01daae5a5	6257	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
bogdanm	92:4fc01daae5a5	6258	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
bogdanm	92:4fc01daae5a5	6259	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
bogdanm	92:4fc01daae5a5	6260	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
bogdanm	92:4fc01daae5a5	6261
bogdanm	92:4fc01daae5a5	6262	/* Register: SPIS_STATUS */
bogdanm	92:4fc01daae5a5	6263	/* Description: Status from last transaction. */
bogdanm	92:4fc01daae5a5	6264
bogdanm	92:4fc01daae5a5	6265	/* Bit 1 : RX buffer overflow detected, and prevented. */
bogdanm	92:4fc01daae5a5	6266	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
bogdanm	92:4fc01daae5a5	6267	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
bogdanm	92:4fc01daae5a5	6268	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6269	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6270	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
bogdanm	92:4fc01daae5a5	6271
bogdanm	92:4fc01daae5a5	6272	/* Bit 0 : TX buffer overread detected, and prevented. */
bogdanm	92:4fc01daae5a5	6273	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
bogdanm	92:4fc01daae5a5	6274	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
bogdanm	92:4fc01daae5a5	6275	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6276	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6277	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
bogdanm	92:4fc01daae5a5	6278
bogdanm	92:4fc01daae5a5	6279	/* Register: SPIS_ENABLE */
bogdanm	92:4fc01daae5a5	6280	/* Description: Enable SPIS. */
bogdanm	92:4fc01daae5a5	6281
bogdanm	92:4fc01daae5a5	6282	/* Bits 2..0 : Enable or disable SPIS. */
bogdanm	92:4fc01daae5a5	6283	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	6284	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	6285	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
bogdanm	92:4fc01daae5a5	6286	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
bogdanm	92:4fc01daae5a5	6287
bogdanm	92:4fc01daae5a5	6288	/* Register: SPIS_MAXRX */
bogdanm	92:4fc01daae5a5	6289	/* Description: Maximum number of bytes in the receive buffer. */
bogdanm	92:4fc01daae5a5	6290
bogdanm	92:4fc01daae5a5	6291	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
bogdanm	92:4fc01daae5a5	6292	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
bogdanm	92:4fc01daae5a5	6293	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
bogdanm	92:4fc01daae5a5	6294
bogdanm	92:4fc01daae5a5	6295	/* Register: SPIS_AMOUNTRX */
bogdanm	92:4fc01daae5a5	6296	/* Description: Number of bytes received in last granted transaction. */
bogdanm	92:4fc01daae5a5	6297
bogdanm	92:4fc01daae5a5	6298	/* Bits 7..0 : Number of bytes received in last granted transaction. */
bogdanm	92:4fc01daae5a5	6299	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
bogdanm	92:4fc01daae5a5	6300	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
bogdanm	92:4fc01daae5a5	6301
bogdanm	92:4fc01daae5a5	6302	/* Register: SPIS_MAXTX */
bogdanm	92:4fc01daae5a5	6303	/* Description: Maximum number of bytes in the transmit buffer. */
bogdanm	92:4fc01daae5a5	6304
bogdanm	92:4fc01daae5a5	6305	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
bogdanm	92:4fc01daae5a5	6306	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
bogdanm	92:4fc01daae5a5	6307	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
bogdanm	92:4fc01daae5a5	6308
bogdanm	92:4fc01daae5a5	6309	/* Register: SPIS_AMOUNTTX */
bogdanm	92:4fc01daae5a5	6310	/* Description: Number of bytes transmitted in last granted transaction. */
bogdanm	92:4fc01daae5a5	6311
bogdanm	92:4fc01daae5a5	6312	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
bogdanm	92:4fc01daae5a5	6313	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
bogdanm	92:4fc01daae5a5	6314	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
bogdanm	92:4fc01daae5a5	6315
bogdanm	92:4fc01daae5a5	6316	/* Register: SPIS_CONFIG */
bogdanm	92:4fc01daae5a5	6317	/* Description: Configuration register. */
bogdanm	92:4fc01daae5a5	6318
bogdanm	92:4fc01daae5a5	6319	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	92:4fc01daae5a5	6320	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	92:4fc01daae5a5	6321	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	92:4fc01daae5a5	6322	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	92:4fc01daae5a5	6323	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	92:4fc01daae5a5	6324
bogdanm	92:4fc01daae5a5	6325	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	92:4fc01daae5a5	6326	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	92:4fc01daae5a5	6327	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	92:4fc01daae5a5	6328	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	92:4fc01daae5a5	6329	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	92:4fc01daae5a5	6330
bogdanm	92:4fc01daae5a5	6331	/* Bit 0 : Bit order. */
bogdanm	92:4fc01daae5a5	6332	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	92:4fc01daae5a5	6333	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	92:4fc01daae5a5	6334	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	92:4fc01daae5a5	6335	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	92:4fc01daae5a5	6336
bogdanm	92:4fc01daae5a5	6337	/* Register: SPIS_DEF */
bogdanm	92:4fc01daae5a5	6338	/* Description: Default character. */
bogdanm	92:4fc01daae5a5	6339
bogdanm	92:4fc01daae5a5	6340	/* Bits 7..0 : Default character. */
bogdanm	92:4fc01daae5a5	6341	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
bogdanm	92:4fc01daae5a5	6342	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
bogdanm	92:4fc01daae5a5	6343
bogdanm	92:4fc01daae5a5	6344	/* Register: SPIS_ORC */
bogdanm	92:4fc01daae5a5	6345	/* Description: Over-read character. */
bogdanm	92:4fc01daae5a5	6346
bogdanm	92:4fc01daae5a5	6347	/* Bits 7..0 : Over-read character. */
bogdanm	92:4fc01daae5a5	6348	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
bogdanm	92:4fc01daae5a5	6349	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
bogdanm	92:4fc01daae5a5	6350
bogdanm	92:4fc01daae5a5	6351	/* Register: SPIS_POWER */
bogdanm	92:4fc01daae5a5	6352	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	6353
bogdanm	92:4fc01daae5a5	6354	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	6355	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	6356	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	6357	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	6358	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	6359
bogdanm	92:4fc01daae5a5	6360
bogdanm	92:4fc01daae5a5	6361	/* Peripheral: TEMP */
bogdanm	92:4fc01daae5a5	6362	/* Description: Temperature Sensor. */
bogdanm	92:4fc01daae5a5	6363
bogdanm	92:4fc01daae5a5	6364	/* Register: TEMP_INTENSET */
bogdanm	92:4fc01daae5a5	6365	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6366
bogdanm	92:4fc01daae5a5	6367	/* Bit 0 : Enable interrupt on DATARDY event. */
bogdanm	92:4fc01daae5a5	6368	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	92:4fc01daae5a5	6369	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	92:4fc01daae5a5	6370	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6371	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6372	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6373
bogdanm	92:4fc01daae5a5	6374	/* Register: TEMP_INTENCLR */
bogdanm	92:4fc01daae5a5	6375	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6376
bogdanm	92:4fc01daae5a5	6377	/* Bit 0 : Disable interrupt on DATARDY event. */
bogdanm	92:4fc01daae5a5	6378	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	92:4fc01daae5a5	6379	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	92:4fc01daae5a5	6380	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6381	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6382	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6383
bogdanm	92:4fc01daae5a5	6384	/* Register: TEMP_POWER */
bogdanm	92:4fc01daae5a5	6385	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	6386
bogdanm	92:4fc01daae5a5	6387	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	6388	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	6389	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	6390	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	6391	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	6392
bogdanm	92:4fc01daae5a5	6393
bogdanm	92:4fc01daae5a5	6394	/* Peripheral: TIMER */
bogdanm	92:4fc01daae5a5	6395	/* Description: Timer 0. */
bogdanm	92:4fc01daae5a5	6396
bogdanm	92:4fc01daae5a5	6397	/* Register: TIMER_SHORTS */
bogdanm	92:4fc01daae5a5	6398	/* Description: Shortcuts for Timer. */
bogdanm	92:4fc01daae5a5	6399
bogdanm	92:4fc01daae5a5	6400	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
bogdanm	92:4fc01daae5a5	6401	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
bogdanm	92:4fc01daae5a5	6402	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
bogdanm	92:4fc01daae5a5	6403	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6404	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6405
bogdanm	92:4fc01daae5a5	6406	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
bogdanm	92:4fc01daae5a5	6407	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
bogdanm	92:4fc01daae5a5	6408	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
bogdanm	92:4fc01daae5a5	6409	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6410	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6411
bogdanm	92:4fc01daae5a5	6412	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
bogdanm	92:4fc01daae5a5	6413	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
bogdanm	92:4fc01daae5a5	6414	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
bogdanm	92:4fc01daae5a5	6415	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6416	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6417
bogdanm	92:4fc01daae5a5	6418	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
bogdanm	92:4fc01daae5a5	6419	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
bogdanm	92:4fc01daae5a5	6420	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
bogdanm	92:4fc01daae5a5	6421	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6422	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6423
bogdanm	92:4fc01daae5a5	6424	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
bogdanm	92:4fc01daae5a5	6425	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
bogdanm	92:4fc01daae5a5	6426	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
bogdanm	92:4fc01daae5a5	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6429
bogdanm	92:4fc01daae5a5	6430	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
bogdanm	92:4fc01daae5a5	6431	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
bogdanm	92:4fc01daae5a5	6432	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
bogdanm	92:4fc01daae5a5	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6435
bogdanm	92:4fc01daae5a5	6436	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
bogdanm	92:4fc01daae5a5	6437	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
bogdanm	92:4fc01daae5a5	6438	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
bogdanm	92:4fc01daae5a5	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6441
bogdanm	92:4fc01daae5a5	6442	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
bogdanm	92:4fc01daae5a5	6443	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
bogdanm	92:4fc01daae5a5	6444	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
bogdanm	92:4fc01daae5a5	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6447
bogdanm	92:4fc01daae5a5	6448	/* Register: TIMER_INTENSET */
bogdanm	92:4fc01daae5a5	6449	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6450
bogdanm	92:4fc01daae5a5	6451	/* Bit 19 : Enable interrupt on COMPARE[3] */
bogdanm	92:4fc01daae5a5	6452	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	6453	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	6454	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6455	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6456	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6457
bogdanm	92:4fc01daae5a5	6458	/* Bit 18 : Enable interrupt on COMPARE[2] */
bogdanm	92:4fc01daae5a5	6459	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	6460	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	6461	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6462	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6463	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6464
bogdanm	92:4fc01daae5a5	6465	/* Bit 17 : Enable interrupt on COMPARE[1] */
bogdanm	92:4fc01daae5a5	6466	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	6467	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	6468	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6469	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6470	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6471
bogdanm	92:4fc01daae5a5	6472	/* Bit 16 : Enable interrupt on COMPARE[0] */
bogdanm	92:4fc01daae5a5	6473	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	6474	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	6475	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6476	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6477	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6478
bogdanm	92:4fc01daae5a5	6479	/* Register: TIMER_INTENCLR */
bogdanm	92:4fc01daae5a5	6480	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6481
bogdanm	92:4fc01daae5a5	6482	/* Bit 19 : Disable interrupt on COMPARE[3] */
bogdanm	92:4fc01daae5a5	6483	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	6484	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	92:4fc01daae5a5	6485	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6486	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6487	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6488
bogdanm	92:4fc01daae5a5	6489	/* Bit 18 : Disable interrupt on COMPARE[2] */
bogdanm	92:4fc01daae5a5	6490	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	6491	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	92:4fc01daae5a5	6492	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6493	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6494	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6495
bogdanm	92:4fc01daae5a5	6496	/* Bit 17 : Disable interrupt on COMPARE[1] */
bogdanm	92:4fc01daae5a5	6497	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	6498	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	92:4fc01daae5a5	6499	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6500	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6501	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6502
bogdanm	92:4fc01daae5a5	6503	/* Bit 16 : Disable interrupt on COMPARE[0] */
bogdanm	92:4fc01daae5a5	6504	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	6505	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	92:4fc01daae5a5	6506	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6507	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6508	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6509
bogdanm	92:4fc01daae5a5	6510	/* Register: TIMER_MODE */
bogdanm	92:4fc01daae5a5	6511	/* Description: Timer Mode selection. */
bogdanm	92:4fc01daae5a5	6512
bogdanm	92:4fc01daae5a5	6513	/* Bit 0 : Select Normal or Counter mode. */
bogdanm	92:4fc01daae5a5	6514	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	92:4fc01daae5a5	6515	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	92:4fc01daae5a5	6516	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
bogdanm	92:4fc01daae5a5	6517	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
bogdanm	92:4fc01daae5a5	6518
bogdanm	92:4fc01daae5a5	6519	/* Register: TIMER_BITMODE */
bogdanm	92:4fc01daae5a5	6520	/* Description: Sets timer behaviour. */
bogdanm	92:4fc01daae5a5	6521
bogdanm	92:4fc01daae5a5	6522	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
bogdanm	92:4fc01daae5a5	6523	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
bogdanm	92:4fc01daae5a5	6524	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
bogdanm	92:4fc01daae5a5	6525	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
bogdanm	92:4fc01daae5a5	6526	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
bogdanm	92:4fc01daae5a5	6527	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
bogdanm	92:4fc01daae5a5	6528	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
bogdanm	92:4fc01daae5a5	6529
bogdanm	92:4fc01daae5a5	6530	/* Register: TIMER_PRESCALER */
bogdanm	92:4fc01daae5a5	6531	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
bogdanm	92:4fc01daae5a5	6532
bogdanm	92:4fc01daae5a5	6533	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
bogdanm	92:4fc01daae5a5	6534	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	92:4fc01daae5a5	6535	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	92:4fc01daae5a5	6536
bogdanm	92:4fc01daae5a5	6537	/* Register: TIMER_POWER */
bogdanm	92:4fc01daae5a5	6538	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	6539
bogdanm	92:4fc01daae5a5	6540	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	6541	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	6542	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	6543	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	6544	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	6545
bogdanm	92:4fc01daae5a5	6546
bogdanm	92:4fc01daae5a5	6547	/* Peripheral: TWI */
bogdanm	92:4fc01daae5a5	6548	/* Description: Two-wire interface master 0. */
bogdanm	92:4fc01daae5a5	6549
bogdanm	92:4fc01daae5a5	6550	/* Register: TWI_SHORTS */
bogdanm	92:4fc01daae5a5	6551	/* Description: Shortcuts for TWI. */
bogdanm	92:4fc01daae5a5	6552
bogdanm	92:4fc01daae5a5	6553	/* Bit 1 : Shortcut between BB event and the STOP task. */
bogdanm	92:4fc01daae5a5	6554	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
bogdanm	92:4fc01daae5a5	6555	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
bogdanm	92:4fc01daae5a5	6556	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6557	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6558
bogdanm	92:4fc01daae5a5	6559	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
bogdanm	92:4fc01daae5a5	6560	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
bogdanm	92:4fc01daae5a5	6561	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
bogdanm	92:4fc01daae5a5	6562	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6563	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6564
bogdanm	92:4fc01daae5a5	6565	/* Register: TWI_INTENSET */
bogdanm	92:4fc01daae5a5	6566	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6567
Kojto	97:433970e64889	6568	/* Bit 18 : Enable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6569	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6570	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6571	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6572	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6573	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6574
bogdanm	92:4fc01daae5a5	6575	/* Bit 14 : Enable interrupt on BB event. */
bogdanm	92:4fc01daae5a5	6576	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	92:4fc01daae5a5	6577	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
bogdanm	92:4fc01daae5a5	6578	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6579	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6580	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6581
bogdanm	92:4fc01daae5a5	6582	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	6583	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	6584	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	6585	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6586	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6587	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6588
bogdanm	92:4fc01daae5a5	6589	/* Bit 7 : Enable interrupt on TXDSENT event. */
bogdanm	92:4fc01daae5a5	6590	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	92:4fc01daae5a5	6591	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	92:4fc01daae5a5	6592	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6593	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6594	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6595
bogdanm	92:4fc01daae5a5	6596	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	92:4fc01daae5a5	6597	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	92:4fc01daae5a5	6598	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	92:4fc01daae5a5	6599	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6600	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6601	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6602
bogdanm	92:4fc01daae5a5	6603	/* Bit 1 : Enable interrupt on STOPPED event. */
bogdanm	92:4fc01daae5a5	6604	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	92:4fc01daae5a5	6605	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	92:4fc01daae5a5	6606	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6607	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6608	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6609
bogdanm	92:4fc01daae5a5	6610	/* Register: TWI_INTENCLR */
bogdanm	92:4fc01daae5a5	6611	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6612
Kojto	97:433970e64889	6613	/* Bit 18 : Disable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6614	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6615	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6616	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6617	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6618	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6619
bogdanm	92:4fc01daae5a5	6620	/* Bit 14 : Disable interrupt on BB event. */
bogdanm	92:4fc01daae5a5	6621	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	92:4fc01daae5a5	6622	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
bogdanm	92:4fc01daae5a5	6623	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6624	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6625	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6626
bogdanm	92:4fc01daae5a5	6627	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	6628	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	6629	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	6630	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6631	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6632	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6633
bogdanm	92:4fc01daae5a5	6634	/* Bit 7 : Disable interrupt on TXDSENT event. */
bogdanm	92:4fc01daae5a5	6635	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	92:4fc01daae5a5	6636	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	92:4fc01daae5a5	6637	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6638	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6639	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6640
bogdanm	92:4fc01daae5a5	6641	/* Bit 2 : Disable interrupt on RXDREADY event. */
bogdanm	92:4fc01daae5a5	6642	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	92:4fc01daae5a5	6643	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	92:4fc01daae5a5	6644	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6645	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6646	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6647
bogdanm	92:4fc01daae5a5	6648	/* Bit 1 : Disable interrupt on STOPPED event. */
bogdanm	92:4fc01daae5a5	6649	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	92:4fc01daae5a5	6650	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	92:4fc01daae5a5	6651	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6652	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6653	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6654
bogdanm	92:4fc01daae5a5	6655	/* Register: TWI_ERRORSRC */
bogdanm	92:4fc01daae5a5	6656	/* Description: Two-wire error source. Write error field to 1 to clear error. */
bogdanm	92:4fc01daae5a5	6657
bogdanm	92:4fc01daae5a5	6658	/* Bit 2 : NACK received after sending a data byte. */
bogdanm	92:4fc01daae5a5	6659	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
bogdanm	92:4fc01daae5a5	6660	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
bogdanm	92:4fc01daae5a5	6661	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6662	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6663	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6664
bogdanm	92:4fc01daae5a5	6665	/* Bit 1 : NACK received after sending the address. */
bogdanm	92:4fc01daae5a5	6666	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
bogdanm	92:4fc01daae5a5	6667	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
bogdanm	92:4fc01daae5a5	6668	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6669	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6670	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6671
bogdanm	92:4fc01daae5a5	6672	/* Register: TWI_ENABLE */
bogdanm	92:4fc01daae5a5	6673	/* Description: Enable two-wire master. */
bogdanm	92:4fc01daae5a5	6674
bogdanm	92:4fc01daae5a5	6675	/* Bits 2..0 : Enable or disable W2M */
bogdanm	92:4fc01daae5a5	6676	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	6677	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	6678	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	6679	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	6680
bogdanm	92:4fc01daae5a5	6681	/* Register: TWI_RXD */
bogdanm	92:4fc01daae5a5	6682	/* Description: RX data register. */
bogdanm	92:4fc01daae5a5	6683
bogdanm	92:4fc01daae5a5	6684	/* Bits 7..0 : RX data from last transfer. */
bogdanm	92:4fc01daae5a5	6685	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	92:4fc01daae5a5	6686	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	92:4fc01daae5a5	6687
bogdanm	92:4fc01daae5a5	6688	/* Register: TWI_TXD */
bogdanm	92:4fc01daae5a5	6689	/* Description: TX data register. */
bogdanm	92:4fc01daae5a5	6690
bogdanm	92:4fc01daae5a5	6691	/* Bits 7..0 : TX data for next transfer. */
bogdanm	92:4fc01daae5a5	6692	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	92:4fc01daae5a5	6693	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	92:4fc01daae5a5	6694
bogdanm	92:4fc01daae5a5	6695	/* Register: TWI_FREQUENCY */
bogdanm	92:4fc01daae5a5	6696	/* Description: Two-wire frequency. */
bogdanm	92:4fc01daae5a5	6697
bogdanm	92:4fc01daae5a5	6698	/* Bits 31..0 : Two-wire master clock frequency. */
bogdanm	92:4fc01daae5a5	6699	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	6700	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	92:4fc01daae5a5	6701	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
bogdanm	92:4fc01daae5a5	6702	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
bogdanm	92:4fc01daae5a5	6703	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
bogdanm	92:4fc01daae5a5	6704
bogdanm	92:4fc01daae5a5	6705	/* Register: TWI_ADDRESS */
bogdanm	92:4fc01daae5a5	6706	/* Description: Address used in the two-wire transfer. */
bogdanm	92:4fc01daae5a5	6707
bogdanm	92:4fc01daae5a5	6708	/* Bits 6..0 : Two-wire address. */
bogdanm	92:4fc01daae5a5	6709	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
bogdanm	92:4fc01daae5a5	6710	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	92:4fc01daae5a5	6711
bogdanm	92:4fc01daae5a5	6712	/* Register: TWI_POWER */
bogdanm	92:4fc01daae5a5	6713	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	6714
bogdanm	92:4fc01daae5a5	6715	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	6716	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	6717	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	6718	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	6719	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	6720
bogdanm	92:4fc01daae5a5	6721
bogdanm	92:4fc01daae5a5	6722	/* Peripheral: UART */
bogdanm	92:4fc01daae5a5	6723	/* Description: Universal Asynchronous Receiver/Transmitter. */
bogdanm	92:4fc01daae5a5	6724
bogdanm	92:4fc01daae5a5	6725	/* Register: UART_SHORTS */
Kojto	97:433970e64889	6726	/* Description: Shortcuts for UART. */
bogdanm	92:4fc01daae5a5	6727
bogdanm	92:4fc01daae5a5	6728	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
bogdanm	92:4fc01daae5a5	6729	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
bogdanm	92:4fc01daae5a5	6730	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
bogdanm	92:4fc01daae5a5	6731	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6732	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6733
bogdanm	92:4fc01daae5a5	6734	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
bogdanm	92:4fc01daae5a5	6735	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
bogdanm	92:4fc01daae5a5	6736	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
bogdanm	92:4fc01daae5a5	6737	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	92:4fc01daae5a5	6738	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	92:4fc01daae5a5	6739
bogdanm	92:4fc01daae5a5	6740	/* Register: UART_INTENSET */
bogdanm	92:4fc01daae5a5	6741	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6742
bogdanm	92:4fc01daae5a5	6743	/* Bit 17 : Enable interrupt on RXTO event. */
bogdanm	92:4fc01daae5a5	6744	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	92:4fc01daae5a5	6745	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	92:4fc01daae5a5	6746	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6747	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6748	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6749
bogdanm	92:4fc01daae5a5	6750	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	6751	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	6752	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	6753	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6754	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6755	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6756
bogdanm	92:4fc01daae5a5	6757	/* Bit 7 : Enable interrupt on TXRDY event. */
bogdanm	92:4fc01daae5a5	6758	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	92:4fc01daae5a5	6759	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	92:4fc01daae5a5	6760	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6761	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6762	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6763
bogdanm	92:4fc01daae5a5	6764	/* Bit 2 : Enable interrupt on RXRDY event. */
bogdanm	92:4fc01daae5a5	6765	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	92:4fc01daae5a5	6766	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	92:4fc01daae5a5	6767	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6768	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6769	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6770
bogdanm	92:4fc01daae5a5	6771	/* Bit 1 : Enable interrupt on NCTS event. */
bogdanm	92:4fc01daae5a5	6772	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	92:4fc01daae5a5	6773	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	92:4fc01daae5a5	6774	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6775	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6776	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6777
bogdanm	92:4fc01daae5a5	6778	/* Bit 0 : Enable interrupt on CTS event. */
bogdanm	92:4fc01daae5a5	6779	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	92:4fc01daae5a5	6780	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	92:4fc01daae5a5	6781	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6782	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6783	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6784
bogdanm	92:4fc01daae5a5	6785	/* Register: UART_INTENCLR */
bogdanm	92:4fc01daae5a5	6786	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6787
bogdanm	92:4fc01daae5a5	6788	/* Bit 17 : Disable interrupt on RXTO event. */
bogdanm	92:4fc01daae5a5	6789	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	92:4fc01daae5a5	6790	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	92:4fc01daae5a5	6791	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6792	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6793	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6794
bogdanm	92:4fc01daae5a5	6795	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	92:4fc01daae5a5	6796	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	92:4fc01daae5a5	6797	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	92:4fc01daae5a5	6798	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6799	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6800	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6801
bogdanm	92:4fc01daae5a5	6802	/* Bit 7 : Disable interrupt on TXRDY event. */
bogdanm	92:4fc01daae5a5	6803	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	92:4fc01daae5a5	6804	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	92:4fc01daae5a5	6805	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6806	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6807	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6808
bogdanm	92:4fc01daae5a5	6809	/* Bit 2 : Disable interrupt on RXRDY event. */
bogdanm	92:4fc01daae5a5	6810	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	92:4fc01daae5a5	6811	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	92:4fc01daae5a5	6812	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6813	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6814	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6815
bogdanm	92:4fc01daae5a5	6816	/* Bit 1 : Disable interrupt on NCTS event. */
bogdanm	92:4fc01daae5a5	6817	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	92:4fc01daae5a5	6818	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	92:4fc01daae5a5	6819	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6820	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6821	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6822
bogdanm	92:4fc01daae5a5	6823	/* Bit 0 : Disable interrupt on CTS event. */
bogdanm	92:4fc01daae5a5	6824	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	92:4fc01daae5a5	6825	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	92:4fc01daae5a5	6826	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6827	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6828	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6829
bogdanm	92:4fc01daae5a5	6830	/* Register: UART_ERRORSRC */
bogdanm	92:4fc01daae5a5	6831	/* Description: Error source. Write error field to 1 to clear error. */
bogdanm	92:4fc01daae5a5	6832
bogdanm	92:4fc01daae5a5	6833	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
bogdanm	92:4fc01daae5a5	6834	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
bogdanm	92:4fc01daae5a5	6835	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
bogdanm	92:4fc01daae5a5	6836	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6837	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6838	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6839
bogdanm	92:4fc01daae5a5	6840	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
bogdanm	92:4fc01daae5a5	6841	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
bogdanm	92:4fc01daae5a5	6842	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
bogdanm	92:4fc01daae5a5	6843	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6844	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6845	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6846
bogdanm	92:4fc01daae5a5	6847	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
bogdanm	92:4fc01daae5a5	6848	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	92:4fc01daae5a5	6849	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	92:4fc01daae5a5	6850	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6851	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6852	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6853
bogdanm	92:4fc01daae5a5	6854	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
bogdanm	92:4fc01daae5a5	6855	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
bogdanm	92:4fc01daae5a5	6856	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
bogdanm	92:4fc01daae5a5	6857	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
bogdanm	92:4fc01daae5a5	6858	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
bogdanm	92:4fc01daae5a5	6859	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
bogdanm	92:4fc01daae5a5	6860
bogdanm	92:4fc01daae5a5	6861	/* Register: UART_ENABLE */
bogdanm	92:4fc01daae5a5	6862	/* Description: Enable UART and acquire IOs. */
bogdanm	92:4fc01daae5a5	6863
bogdanm	92:4fc01daae5a5	6864	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
bogdanm	92:4fc01daae5a5	6865	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	92:4fc01daae5a5	6866	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	92:4fc01daae5a5	6867	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
bogdanm	92:4fc01daae5a5	6868	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
bogdanm	92:4fc01daae5a5	6869
bogdanm	92:4fc01daae5a5	6870	/* Register: UART_RXD */
Kojto	97:433970e64889	6871	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
bogdanm	92:4fc01daae5a5	6872
bogdanm	92:4fc01daae5a5	6873	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
bogdanm	92:4fc01daae5a5	6874	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	92:4fc01daae5a5	6875	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	92:4fc01daae5a5	6876
bogdanm	92:4fc01daae5a5	6877	/* Register: UART_TXD */
bogdanm	92:4fc01daae5a5	6878	/* Description: TXD register. */
bogdanm	92:4fc01daae5a5	6879
bogdanm	92:4fc01daae5a5	6880	/* Bits 7..0 : TX data for transfer. */
bogdanm	92:4fc01daae5a5	6881	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	92:4fc01daae5a5	6882	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	92:4fc01daae5a5	6883
bogdanm	92:4fc01daae5a5	6884	/* Register: UART_BAUDRATE */
bogdanm	92:4fc01daae5a5	6885	/* Description: UART Baudrate. */
bogdanm	92:4fc01daae5a5	6886
bogdanm	92:4fc01daae5a5	6887	/* Bits 31..0 : UART baudrate. */
bogdanm	92:4fc01daae5a5	6888	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
bogdanm	92:4fc01daae5a5	6889	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
bogdanm	92:4fc01daae5a5	6890	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
bogdanm	92:4fc01daae5a5	6891	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
bogdanm	92:4fc01daae5a5	6892	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
bogdanm	92:4fc01daae5a5	6893	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
bogdanm	92:4fc01daae5a5	6894	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
bogdanm	92:4fc01daae5a5	6895	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
bogdanm	92:4fc01daae5a5	6896	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
bogdanm	92:4fc01daae5a5	6897	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
bogdanm	92:4fc01daae5a5	6898	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
bogdanm	92:4fc01daae5a5	6899	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
bogdanm	92:4fc01daae5a5	6900	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
bogdanm	92:4fc01daae5a5	6901	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
bogdanm	92:4fc01daae5a5	6902	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
bogdanm	92:4fc01daae5a5	6903	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
bogdanm	92:4fc01daae5a5	6904	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
bogdanm	92:4fc01daae5a5	6905	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
bogdanm	92:4fc01daae5a5	6906
bogdanm	92:4fc01daae5a5	6907	/* Register: UART_CONFIG */
bogdanm	92:4fc01daae5a5	6908	/* Description: Configuration of parity and hardware flow control register. */
bogdanm	92:4fc01daae5a5	6909
bogdanm	92:4fc01daae5a5	6910	/* Bits 3..1 : Include parity bit. */
bogdanm	92:4fc01daae5a5	6911	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	92:4fc01daae5a5	6912	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	92:4fc01daae5a5	6913	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
bogdanm	92:4fc01daae5a5	6914	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
bogdanm	92:4fc01daae5a5	6915
bogdanm	92:4fc01daae5a5	6916	/* Bit 0 : Hardware flow control. */
bogdanm	92:4fc01daae5a5	6917	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
bogdanm	92:4fc01daae5a5	6918	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
bogdanm	92:4fc01daae5a5	6919	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
bogdanm	92:4fc01daae5a5	6920	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
bogdanm	92:4fc01daae5a5	6921
bogdanm	92:4fc01daae5a5	6922	/* Register: UART_POWER */
bogdanm	92:4fc01daae5a5	6923	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	6924
bogdanm	92:4fc01daae5a5	6925	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	6926	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	6927	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	6928	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	6929	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	6930
bogdanm	92:4fc01daae5a5	6931
bogdanm	92:4fc01daae5a5	6932	/* Peripheral: UICR */
bogdanm	92:4fc01daae5a5	6933	/* Description: User Information Configuration. */
bogdanm	92:4fc01daae5a5	6934
bogdanm	92:4fc01daae5a5	6935	/* Register: UICR_RBPCONF */
bogdanm	92:4fc01daae5a5	6936	/* Description: Readback protection configuration. */
bogdanm	92:4fc01daae5a5	6937
bogdanm	92:4fc01daae5a5	6938	/* Bits 15..8 : Readback protect all code in the device. */
bogdanm	92:4fc01daae5a5	6939	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
bogdanm	92:4fc01daae5a5	6940	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
bogdanm	92:4fc01daae5a5	6941	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	6942	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	6943
bogdanm	92:4fc01daae5a5	6944	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
bogdanm	92:4fc01daae5a5	6945	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
bogdanm	92:4fc01daae5a5	6946	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
bogdanm	92:4fc01daae5a5	6947	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
bogdanm	92:4fc01daae5a5	6948	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
bogdanm	92:4fc01daae5a5	6949
bogdanm	92:4fc01daae5a5	6950	/* Register: UICR_XTALFREQ */
bogdanm	92:4fc01daae5a5	6951	/* Description: Reset value for CLOCK XTALFREQ register. */
bogdanm	92:4fc01daae5a5	6952
bogdanm	92:4fc01daae5a5	6953	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
bogdanm	92:4fc01daae5a5	6954	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	92:4fc01daae5a5	6955	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
bogdanm	92:4fc01daae5a5	6956	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
bogdanm	92:4fc01daae5a5	6957	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
bogdanm	92:4fc01daae5a5	6958
bogdanm	92:4fc01daae5a5	6959	/* Register: UICR_FWID */
bogdanm	92:4fc01daae5a5	6960	/* Description: Firmware ID. */
bogdanm	92:4fc01daae5a5	6961
bogdanm	92:4fc01daae5a5	6962	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
bogdanm	92:4fc01daae5a5	6963	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
bogdanm	92:4fc01daae5a5	6964	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	92:4fc01daae5a5	6965
bogdanm	92:4fc01daae5a5	6966
bogdanm	92:4fc01daae5a5	6967	/* Peripheral: WDT */
bogdanm	92:4fc01daae5a5	6968	/* Description: Watchdog Timer. */
bogdanm	92:4fc01daae5a5	6969
bogdanm	92:4fc01daae5a5	6970	/* Register: WDT_INTENSET */
bogdanm	92:4fc01daae5a5	6971	/* Description: Interrupt enable set register. */
bogdanm	92:4fc01daae5a5	6972
bogdanm	92:4fc01daae5a5	6973	/* Bit 0 : Enable interrupt on TIMEOUT event. */
bogdanm	92:4fc01daae5a5	6974	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	92:4fc01daae5a5	6975	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	92:4fc01daae5a5	6976	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6977	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6978	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	92:4fc01daae5a5	6979
bogdanm	92:4fc01daae5a5	6980	/* Register: WDT_INTENCLR */
bogdanm	92:4fc01daae5a5	6981	/* Description: Interrupt enable clear register. */
bogdanm	92:4fc01daae5a5	6982
bogdanm	92:4fc01daae5a5	6983	/* Bit 0 : Disable interrupt on TIMEOUT event. */
bogdanm	92:4fc01daae5a5	6984	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	92:4fc01daae5a5	6985	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	92:4fc01daae5a5	6986	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	92:4fc01daae5a5	6987	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	92:4fc01daae5a5	6988	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	92:4fc01daae5a5	6989
bogdanm	92:4fc01daae5a5	6990	/* Register: WDT_RUNSTATUS */
bogdanm	92:4fc01daae5a5	6991	/* Description: Watchdog running status. */
bogdanm	92:4fc01daae5a5	6992
bogdanm	92:4fc01daae5a5	6993	/* Bit 0 : Watchdog running status. */
bogdanm	92:4fc01daae5a5	6994	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
bogdanm	92:4fc01daae5a5	6995	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
bogdanm	92:4fc01daae5a5	6996	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
bogdanm	92:4fc01daae5a5	6997	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
bogdanm	92:4fc01daae5a5	6998
bogdanm	92:4fc01daae5a5	6999	/* Register: WDT_REQSTATUS */
bogdanm	92:4fc01daae5a5	7000	/* Description: Request status. */
bogdanm	92:4fc01daae5a5	7001
bogdanm	92:4fc01daae5a5	7002	/* Bit 7 : Request status for RR[7]. */
bogdanm	92:4fc01daae5a5	7003	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	92:4fc01daae5a5	7004	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	92:4fc01daae5a5	7005	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7006	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7007
bogdanm	92:4fc01daae5a5	7008	/* Bit 6 : Request status for RR[6]. */
bogdanm	92:4fc01daae5a5	7009	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	92:4fc01daae5a5	7010	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	92:4fc01daae5a5	7011	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7012	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7013
bogdanm	92:4fc01daae5a5	7014	/* Bit 5 : Request status for RR[5]. */
bogdanm	92:4fc01daae5a5	7015	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	92:4fc01daae5a5	7016	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	92:4fc01daae5a5	7017	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7018	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7019
bogdanm	92:4fc01daae5a5	7020	/* Bit 4 : Request status for RR[4]. */
bogdanm	92:4fc01daae5a5	7021	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	92:4fc01daae5a5	7022	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	92:4fc01daae5a5	7023	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7024	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7025
bogdanm	92:4fc01daae5a5	7026	/* Bit 3 : Request status for RR[3]. */
bogdanm	92:4fc01daae5a5	7027	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	92:4fc01daae5a5	7028	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	92:4fc01daae5a5	7029	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7030	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7031
bogdanm	92:4fc01daae5a5	7032	/* Bit 2 : Request status for RR[2]. */
bogdanm	92:4fc01daae5a5	7033	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	92:4fc01daae5a5	7034	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	92:4fc01daae5a5	7035	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7036	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7037
bogdanm	92:4fc01daae5a5	7038	/* Bit 1 : Request status for RR[1]. */
bogdanm	92:4fc01daae5a5	7039	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	92:4fc01daae5a5	7040	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	92:4fc01daae5a5	7041	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7042	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7043
bogdanm	92:4fc01daae5a5	7044	/* Bit 0 : Request status for RR[0]. */
bogdanm	92:4fc01daae5a5	7045	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	92:4fc01daae5a5	7046	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	92:4fc01daae5a5	7047	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
bogdanm	92:4fc01daae5a5	7048	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
bogdanm	92:4fc01daae5a5	7049
bogdanm	92:4fc01daae5a5	7050	/* Register: WDT_RREN */
bogdanm	92:4fc01daae5a5	7051	/* Description: Reload request enable. */
bogdanm	92:4fc01daae5a5	7052
bogdanm	92:4fc01daae5a5	7053	/* Bit 7 : Enable or disable RR[7] register. */
bogdanm	92:4fc01daae5a5	7054	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	92:4fc01daae5a5	7055	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	92:4fc01daae5a5	7056	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
bogdanm	92:4fc01daae5a5	7057	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
bogdanm	92:4fc01daae5a5	7058
bogdanm	92:4fc01daae5a5	7059	/* Bit 6 : Enable or disable RR[6] register. */
bogdanm	92:4fc01daae5a5	7060	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	92:4fc01daae5a5	7061	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	92:4fc01daae5a5	7062	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
bogdanm	92:4fc01daae5a5	7063	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
bogdanm	92:4fc01daae5a5	7064
bogdanm	92:4fc01daae5a5	7065	/* Bit 5 : Enable or disable RR[5] register. */
bogdanm	92:4fc01daae5a5	7066	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	92:4fc01daae5a5	7067	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	92:4fc01daae5a5	7068	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
bogdanm	92:4fc01daae5a5	7069	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
bogdanm	92:4fc01daae5a5	7070
bogdanm	92:4fc01daae5a5	7071	/* Bit 4 : Enable or disable RR[4] register. */
bogdanm	92:4fc01daae5a5	7072	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	92:4fc01daae5a5	7073	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	92:4fc01daae5a5	7074	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
bogdanm	92:4fc01daae5a5	7075	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
bogdanm	92:4fc01daae5a5	7076
bogdanm	92:4fc01daae5a5	7077	/* Bit 3 : Enable or disable RR[3] register. */
bogdanm	92:4fc01daae5a5	7078	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	92:4fc01daae5a5	7079	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	92:4fc01daae5a5	7080	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
bogdanm	92:4fc01daae5a5	7081	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
bogdanm	92:4fc01daae5a5	7082
bogdanm	92:4fc01daae5a5	7083	/* Bit 2 : Enable or disable RR[2] register. */
bogdanm	92:4fc01daae5a5	7084	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	92:4fc01daae5a5	7085	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	92:4fc01daae5a5	7086	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
bogdanm	92:4fc01daae5a5	7087	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
bogdanm	92:4fc01daae5a5	7088
bogdanm	92:4fc01daae5a5	7089	/* Bit 1 : Enable or disable RR[1] register. */
bogdanm	92:4fc01daae5a5	7090	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	92:4fc01daae5a5	7091	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	92:4fc01daae5a5	7092	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
bogdanm	92:4fc01daae5a5	7093	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
bogdanm	92:4fc01daae5a5	7094
bogdanm	92:4fc01daae5a5	7095	/* Bit 0 : Enable or disable RR[0] register. */
bogdanm	92:4fc01daae5a5	7096	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	92:4fc01daae5a5	7097	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	92:4fc01daae5a5	7098	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
bogdanm	92:4fc01daae5a5	7099	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
bogdanm	92:4fc01daae5a5	7100
bogdanm	92:4fc01daae5a5	7101	/* Register: WDT_CONFIG */
bogdanm	92:4fc01daae5a5	7102	/* Description: Configuration register. */
bogdanm	92:4fc01daae5a5	7103
bogdanm	92:4fc01daae5a5	7104	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
bogdanm	92:4fc01daae5a5	7105	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
bogdanm	92:4fc01daae5a5	7106	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
bogdanm	92:4fc01daae5a5	7107	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
bogdanm	92:4fc01daae5a5	7108	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
bogdanm	92:4fc01daae5a5	7109
bogdanm	92:4fc01daae5a5	7110	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
bogdanm	92:4fc01daae5a5	7111	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
bogdanm	92:4fc01daae5a5	7112	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
bogdanm	92:4fc01daae5a5	7113	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
bogdanm	92:4fc01daae5a5	7114	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
bogdanm	92:4fc01daae5a5	7115
bogdanm	92:4fc01daae5a5	7116	/* Register: WDT_RR */
bogdanm	92:4fc01daae5a5	7117	/* Description: Reload requests registers. */
bogdanm	92:4fc01daae5a5	7118
bogdanm	92:4fc01daae5a5	7119	/* Bits 31..0 : Reload register. */
bogdanm	92:4fc01daae5a5	7120	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
bogdanm	92:4fc01daae5a5	7121	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
bogdanm	92:4fc01daae5a5	7122	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
bogdanm	92:4fc01daae5a5	7123
bogdanm	92:4fc01daae5a5	7124	/* Register: WDT_POWER */
bogdanm	92:4fc01daae5a5	7125	/* Description: Peripheral power control. */
bogdanm	92:4fc01daae5a5	7126
bogdanm	92:4fc01daae5a5	7127	/* Bit 0 : Peripheral power control. */
bogdanm	92:4fc01daae5a5	7128	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	92:4fc01daae5a5	7129	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	92:4fc01daae5a5	7130	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	92:4fc01daae5a5	7131	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	92:4fc01daae5a5	7132
bogdanm	92:4fc01daae5a5	7133
bogdanm	92:4fc01daae5a5	7134	/lint --flb "Leave library region" /
bogdanm	92:4fc01daae5a5	7135	#endif