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TARGET_WIZWIKI_W7500/TOOLCHAIN_IAR/W7500x.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_WIZWIKI_W7500/TARGET_WIZNET/TARGET_W7500x/device/W7500x.h@162:dbaafcfe0e9d 
mbed library. Release version 164

Who changed what in which revision?

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AnnaBridge 162:dbaafcfe0e9d 1 /**************************************************************************//**
AnnaBridge 162:dbaafcfe0e9d 2 * @file W7500x.h
AnnaBridge 162:dbaafcfe0e9d 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
AnnaBridge 162:dbaafcfe0e9d 4 * Device W7500x
AnnaBridge 162:dbaafcfe0e9d 5 * @version V3.01
AnnaBridge 162:dbaafcfe0e9d 6 * @date 06. March 2012
AnnaBridge 162:dbaafcfe0e9d 7 *
AnnaBridge 162:dbaafcfe0e9d 8 * @note
AnnaBridge 162:dbaafcfe0e9d 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
AnnaBridge 162:dbaafcfe0e9d 10 *
AnnaBridge 162:dbaafcfe0e9d 11 * @par
AnnaBridge 162:dbaafcfe0e9d 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
AnnaBridge 162:dbaafcfe0e9d 13 * processor based microcontrollers. This file can be freely distributed
AnnaBridge 162:dbaafcfe0e9d 14 * within development tools that are supporting such ARM based processors.
AnnaBridge 162:dbaafcfe0e9d 15 *
AnnaBridge 162:dbaafcfe0e9d 16 * @par
AnnaBridge 162:dbaafcfe0e9d 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 162:dbaafcfe0e9d 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 162:dbaafcfe0e9d 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 162:dbaafcfe0e9d 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
AnnaBridge 162:dbaafcfe0e9d 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 162:dbaafcfe0e9d 22 *
AnnaBridge 162:dbaafcfe0e9d 23 ******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 24
AnnaBridge 162:dbaafcfe0e9d 25
AnnaBridge 162:dbaafcfe0e9d 26 #ifndef W7500x_H
AnnaBridge 162:dbaafcfe0e9d 27 #define W7500x_H
AnnaBridge 162:dbaafcfe0e9d 28
AnnaBridge 162:dbaafcfe0e9d 29 #ifdef __cplusplus
AnnaBridge 162:dbaafcfe0e9d 30 extern "C" {
AnnaBridge 162:dbaafcfe0e9d 31 #endif
AnnaBridge 162:dbaafcfe0e9d 32
AnnaBridge 162:dbaafcfe0e9d 33 /** @addtogroup W7500x_Definitions W7500x Definitions
AnnaBridge 162:dbaafcfe0e9d 34 This file defines all structures and symbols for W7500x:
AnnaBridge 162:dbaafcfe0e9d 35 - registers and bitfields
AnnaBridge 162:dbaafcfe0e9d 36 - peripheral base address
AnnaBridge 162:dbaafcfe0e9d 37 - peripheral ID
AnnaBridge 162:dbaafcfe0e9d 38 - Peripheral definitions
AnnaBridge 162:dbaafcfe0e9d 39 @{
AnnaBridge 162:dbaafcfe0e9d 40 */
AnnaBridge 162:dbaafcfe0e9d 41
AnnaBridge 162:dbaafcfe0e9d 42
AnnaBridge 162:dbaafcfe0e9d 43 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 44 /* Processor and Core Peripherals */
AnnaBridge 162:dbaafcfe0e9d 45 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
AnnaBridge 162:dbaafcfe0e9d 47 Configuration of the Cortex-M0 Processor and Core Peripherals
AnnaBridge 162:dbaafcfe0e9d 48 @{
AnnaBridge 162:dbaafcfe0e9d 49 */
AnnaBridge 162:dbaafcfe0e9d 50
AnnaBridge 162:dbaafcfe0e9d 51 /*
AnnaBridge 162:dbaafcfe0e9d 52 * ==========================================================================
AnnaBridge 162:dbaafcfe0e9d 53 * ---------- Interrupt Number Definition -----------------------------------
AnnaBridge 162:dbaafcfe0e9d 54 * ==========================================================================
AnnaBridge 162:dbaafcfe0e9d 55 */
AnnaBridge 162:dbaafcfe0e9d 56
AnnaBridge 162:dbaafcfe0e9d 57 typedef enum IRQn
AnnaBridge 162:dbaafcfe0e9d 58 {
AnnaBridge 162:dbaafcfe0e9d 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
AnnaBridge 162:dbaafcfe0e9d 60
AnnaBridge 162:dbaafcfe0e9d 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
AnnaBridge 162:dbaafcfe0e9d 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
AnnaBridge 162:dbaafcfe0e9d 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
AnnaBridge 162:dbaafcfe0e9d 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
AnnaBridge 162:dbaafcfe0e9d 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
AnnaBridge 162:dbaafcfe0e9d 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
AnnaBridge 162:dbaafcfe0e9d 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
AnnaBridge 162:dbaafcfe0e9d 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
AnnaBridge 162:dbaafcfe0e9d 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
AnnaBridge 162:dbaafcfe0e9d 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
AnnaBridge 162:dbaafcfe0e9d 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
AnnaBridge 162:dbaafcfe0e9d 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
AnnaBridge 162:dbaafcfe0e9d 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
AnnaBridge 162:dbaafcfe0e9d 90 RTC_IRQn = 22, /*!< RTC Interrupt */
AnnaBridge 162:dbaafcfe0e9d 91 ADC_IRQn = 23, /*!< ADC Interrupt */
AnnaBridge 162:dbaafcfe0e9d 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
AnnaBridge 162:dbaafcfe0e9d 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
AnnaBridge 162:dbaafcfe0e9d 94 } IRQn_Type;
AnnaBridge 162:dbaafcfe0e9d 95
AnnaBridge 162:dbaafcfe0e9d 96 /*
AnnaBridge 162:dbaafcfe0e9d 97 * ==========================================================================
AnnaBridge 162:dbaafcfe0e9d 98 * ----------- Processor and Core Peripheral Section ------------------------
AnnaBridge 162:dbaafcfe0e9d 99 * ==========================================================================
AnnaBridge 162:dbaafcfe0e9d 100 */
AnnaBridge 162:dbaafcfe0e9d 101
AnnaBridge 162:dbaafcfe0e9d 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
AnnaBridge 162:dbaafcfe0e9d 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
AnnaBridge 162:dbaafcfe0e9d 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
AnnaBridge 162:dbaafcfe0e9d 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 162:dbaafcfe0e9d 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 162:dbaafcfe0e9d 107
AnnaBridge 162:dbaafcfe0e9d 108 /*@}*/ /* end of group W7500x_CMSIS */
AnnaBridge 162:dbaafcfe0e9d 109
AnnaBridge 162:dbaafcfe0e9d 110
AnnaBridge 162:dbaafcfe0e9d 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
AnnaBridge 162:dbaafcfe0e9d 112 #include "system_W7500x.h" /* W7500x System include file */
AnnaBridge 162:dbaafcfe0e9d 113
AnnaBridge 162:dbaafcfe0e9d 114
AnnaBridge 162:dbaafcfe0e9d 115 /** @addtogroup Exported_types
AnnaBridge 162:dbaafcfe0e9d 116 * @{
AnnaBridge 162:dbaafcfe0e9d 117 */
AnnaBridge 162:dbaafcfe0e9d 118
AnnaBridge 162:dbaafcfe0e9d 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
AnnaBridge 162:dbaafcfe0e9d 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
AnnaBridge 162:dbaafcfe0e9d 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
AnnaBridge 162:dbaafcfe0e9d 122
AnnaBridge 162:dbaafcfe0e9d 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
AnnaBridge 162:dbaafcfe0e9d 124
AnnaBridge 162:dbaafcfe0e9d 125
AnnaBridge 162:dbaafcfe0e9d 126
AnnaBridge 162:dbaafcfe0e9d 127
AnnaBridge 162:dbaafcfe0e9d 128 /**
AnnaBridge 162:dbaafcfe0e9d 129 * @}
AnnaBridge 162:dbaafcfe0e9d 130 */
AnnaBridge 162:dbaafcfe0e9d 131
AnnaBridge 162:dbaafcfe0e9d 132
AnnaBridge 162:dbaafcfe0e9d 133
AnnaBridge 162:dbaafcfe0e9d 134
AnnaBridge 162:dbaafcfe0e9d 135 /** @addtogroup Peripheral_registers_structures
AnnaBridge 162:dbaafcfe0e9d 136 * @{
AnnaBridge 162:dbaafcfe0e9d 137 */
AnnaBridge 162:dbaafcfe0e9d 138
AnnaBridge 162:dbaafcfe0e9d 139 /**
AnnaBridge 162:dbaafcfe0e9d 140 * @brief Clock Reset Generator
AnnaBridge 162:dbaafcfe0e9d 141 */
AnnaBridge 162:dbaafcfe0e9d 142 typedef struct
AnnaBridge 162:dbaafcfe0e9d 143 {
AnnaBridge 162:dbaafcfe0e9d 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
AnnaBridge 162:dbaafcfe0e9d 145 uint32_t RESERVED0[3];
AnnaBridge 162:dbaafcfe0e9d 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
AnnaBridge 162:dbaafcfe0e9d 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
AnnaBridge 162:dbaafcfe0e9d 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
AnnaBridge 162:dbaafcfe0e9d 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
AnnaBridge 162:dbaafcfe0e9d 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
AnnaBridge 162:dbaafcfe0e9d 151 uint32_t RESERVED1[3];
AnnaBridge 162:dbaafcfe0e9d 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
AnnaBridge 162:dbaafcfe0e9d 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
AnnaBridge 162:dbaafcfe0e9d 154 uint32_t RESERVED2[2];
AnnaBridge 162:dbaafcfe0e9d 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
AnnaBridge 162:dbaafcfe0e9d 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
AnnaBridge 162:dbaafcfe0e9d 157 uint32_t RESERVED3[6];
AnnaBridge 162:dbaafcfe0e9d 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
AnnaBridge 162:dbaafcfe0e9d 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
AnnaBridge 162:dbaafcfe0e9d 160 uint32_t RESERVED4[2];
AnnaBridge 162:dbaafcfe0e9d 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
AnnaBridge 162:dbaafcfe0e9d 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
AnnaBridge 162:dbaafcfe0e9d 163 uint32_t RESERVED5[2];
AnnaBridge 162:dbaafcfe0e9d 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
AnnaBridge 162:dbaafcfe0e9d 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
AnnaBridge 162:dbaafcfe0e9d 166 uint32_t RESERVED6[10];
AnnaBridge 162:dbaafcfe0e9d 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
AnnaBridge 162:dbaafcfe0e9d 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
AnnaBridge 162:dbaafcfe0e9d 169 uint32_t RESERVED7[2];
AnnaBridge 162:dbaafcfe0e9d 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
AnnaBridge 162:dbaafcfe0e9d 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
AnnaBridge 162:dbaafcfe0e9d 172 uint32_t RESERVED8[2];
AnnaBridge 162:dbaafcfe0e9d 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
AnnaBridge 162:dbaafcfe0e9d 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
AnnaBridge 162:dbaafcfe0e9d 175 uint32_t RESERVED9[2];
AnnaBridge 162:dbaafcfe0e9d 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
AnnaBridge 162:dbaafcfe0e9d 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
AnnaBridge 162:dbaafcfe0e9d 178 uint32_t RESERVED10[2];
AnnaBridge 162:dbaafcfe0e9d 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
AnnaBridge 162:dbaafcfe0e9d 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
AnnaBridge 162:dbaafcfe0e9d 181 uint32_t RESERVED11[2];
AnnaBridge 162:dbaafcfe0e9d 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
AnnaBridge 162:dbaafcfe0e9d 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
AnnaBridge 162:dbaafcfe0e9d 184 uint32_t RESERVED12[2];
AnnaBridge 162:dbaafcfe0e9d 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
AnnaBridge 162:dbaafcfe0e9d 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
AnnaBridge 162:dbaafcfe0e9d 187 uint32_t RESERVED13[2];
AnnaBridge 162:dbaafcfe0e9d 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
AnnaBridge 162:dbaafcfe0e9d 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
AnnaBridge 162:dbaafcfe0e9d 190 uint32_t RESERVED14[2];
AnnaBridge 162:dbaafcfe0e9d 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
AnnaBridge 162:dbaafcfe0e9d 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
AnnaBridge 162:dbaafcfe0e9d 193 uint32_t RESERVED15;
AnnaBridge 162:dbaafcfe0e9d 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
AnnaBridge 162:dbaafcfe0e9d 195
AnnaBridge 162:dbaafcfe0e9d 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
AnnaBridge 162:dbaafcfe0e9d 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
AnnaBridge 162:dbaafcfe0e9d 198 uint32_t RESERVED16;
AnnaBridge 162:dbaafcfe0e9d 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
AnnaBridge 162:dbaafcfe0e9d 200
AnnaBridge 162:dbaafcfe0e9d 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
AnnaBridge 162:dbaafcfe0e9d 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
AnnaBridge 162:dbaafcfe0e9d 203 uint32_t RESERVED17[2];
AnnaBridge 162:dbaafcfe0e9d 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
AnnaBridge 162:dbaafcfe0e9d 205 uint32_t RESERVED18[3];
AnnaBridge 162:dbaafcfe0e9d 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
AnnaBridge 162:dbaafcfe0e9d 207 }CRG_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 208
AnnaBridge 162:dbaafcfe0e9d 209
AnnaBridge 162:dbaafcfe0e9d 210 /**
AnnaBridge 162:dbaafcfe0e9d 211 * @brief UART
AnnaBridge 162:dbaafcfe0e9d 212 */
AnnaBridge 162:dbaafcfe0e9d 213 typedef struct
AnnaBridge 162:dbaafcfe0e9d 214 {
AnnaBridge 162:dbaafcfe0e9d 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
AnnaBridge 162:dbaafcfe0e9d 216 union {
AnnaBridge 162:dbaafcfe0e9d 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
AnnaBridge 162:dbaafcfe0e9d 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
AnnaBridge 162:dbaafcfe0e9d 219 } STATUS;
AnnaBridge 162:dbaafcfe0e9d 220 uint32_t RESERVED0[4];
AnnaBridge 162:dbaafcfe0e9d 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
AnnaBridge 162:dbaafcfe0e9d 222 uint32_t RESERVED1;
AnnaBridge 162:dbaafcfe0e9d 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
AnnaBridge 162:dbaafcfe0e9d 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
AnnaBridge 162:dbaafcfe0e9d 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
AnnaBridge 162:dbaafcfe0e9d 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
AnnaBridge 162:dbaafcfe0e9d 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
AnnaBridge 162:dbaafcfe0e9d 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
AnnaBridge 162:dbaafcfe0e9d 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
AnnaBridge 162:dbaafcfe0e9d 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
AnnaBridge 162:dbaafcfe0e9d 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
AnnaBridge 162:dbaafcfe0e9d 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
AnnaBridge 162:dbaafcfe0e9d 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
AnnaBridge 162:dbaafcfe0e9d 234 } UART_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 235
AnnaBridge 162:dbaafcfe0e9d 236
AnnaBridge 162:dbaafcfe0e9d 237 /**
AnnaBridge 162:dbaafcfe0e9d 238 * @brief Simple UART
AnnaBridge 162:dbaafcfe0e9d 239 */
AnnaBridge 162:dbaafcfe0e9d 240 typedef struct
AnnaBridge 162:dbaafcfe0e9d 241 {
AnnaBridge 162:dbaafcfe0e9d 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
AnnaBridge 162:dbaafcfe0e9d 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
AnnaBridge 162:dbaafcfe0e9d 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
AnnaBridge 162:dbaafcfe0e9d 245 union {
AnnaBridge 162:dbaafcfe0e9d 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
AnnaBridge 162:dbaafcfe0e9d 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
AnnaBridge 162:dbaafcfe0e9d 248 }INT;
AnnaBridge 162:dbaafcfe0e9d 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
AnnaBridge 162:dbaafcfe0e9d 250
AnnaBridge 162:dbaafcfe0e9d 251 } S_UART_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 252
AnnaBridge 162:dbaafcfe0e9d 253 /**
AnnaBridge 162:dbaafcfe0e9d 254 * @brief Analog Digital Converter
AnnaBridge 162:dbaafcfe0e9d 255 */
AnnaBridge 162:dbaafcfe0e9d 256
AnnaBridge 162:dbaafcfe0e9d 257 typedef struct
AnnaBridge 162:dbaafcfe0e9d 258 {
AnnaBridge 162:dbaafcfe0e9d 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
AnnaBridge 162:dbaafcfe0e9d 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
AnnaBridge 162:dbaafcfe0e9d 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
AnnaBridge 162:dbaafcfe0e9d 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
AnnaBridge 162:dbaafcfe0e9d 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
AnnaBridge 162:dbaafcfe0e9d 264 uint32_t RESERVED0[2];
AnnaBridge 162:dbaafcfe0e9d 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
AnnaBridge 162:dbaafcfe0e9d 266 }ADC_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 267
AnnaBridge 162:dbaafcfe0e9d 268 /**
AnnaBridge 162:dbaafcfe0e9d 269 * @brief dualtimer
AnnaBridge 162:dbaafcfe0e9d 270 */
AnnaBridge 162:dbaafcfe0e9d 271 typedef struct
AnnaBridge 162:dbaafcfe0e9d 272 {
AnnaBridge 162:dbaafcfe0e9d 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
AnnaBridge 162:dbaafcfe0e9d 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
AnnaBridge 162:dbaafcfe0e9d 275 __IO uint32_t TimerControl; // <h> Timer Control
AnnaBridge 162:dbaafcfe0e9d 276 // <o.7> TimerEn: Timer Enable
AnnaBridge 162:dbaafcfe0e9d 277 // <o.6> TimerMode: Timer Mode
AnnaBridge 162:dbaafcfe0e9d 278 // <0=> Freerunning-mode
AnnaBridge 162:dbaafcfe0e9d 279 // <1=> Periodic mode
AnnaBridge 162:dbaafcfe0e9d 280 // <o.5> IntEnable: Interrupt Enable
AnnaBridge 162:dbaafcfe0e9d 281 // <o.2..3> TimerPre: Timer Prescale
AnnaBridge 162:dbaafcfe0e9d 282 // <0=> / 1
AnnaBridge 162:dbaafcfe0e9d 283 // <1=> / 16
AnnaBridge 162:dbaafcfe0e9d 284 // <2=> / 256
AnnaBridge 162:dbaafcfe0e9d 285 // <3=> Undefined!
AnnaBridge 162:dbaafcfe0e9d 286 // <o.1> TimerSize: Timer Size
AnnaBridge 162:dbaafcfe0e9d 287 // <0=> 16-bit counter
AnnaBridge 162:dbaafcfe0e9d 288 // <1=> 32-bit counter
AnnaBridge 162:dbaafcfe0e9d 289 // <o.0> OneShot: One-shoot mode
AnnaBridge 162:dbaafcfe0e9d 290 // <0=> Wrapping mode
AnnaBridge 162:dbaafcfe0e9d 291 // <1=> One-shot mode
AnnaBridge 162:dbaafcfe0e9d 292 // </h>
AnnaBridge 162:dbaafcfe0e9d 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
AnnaBridge 162:dbaafcfe0e9d 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
AnnaBridge 162:dbaafcfe0e9d 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
AnnaBridge 162:dbaafcfe0e9d 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
AnnaBridge 162:dbaafcfe0e9d 297 } DUALTIMER_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 298
AnnaBridge 162:dbaafcfe0e9d 299 /**
AnnaBridge 162:dbaafcfe0e9d 300 * @brief GPIO
AnnaBridge 162:dbaafcfe0e9d 301 */
AnnaBridge 162:dbaafcfe0e9d 302 typedef struct
AnnaBridge 162:dbaafcfe0e9d 303 {
AnnaBridge 162:dbaafcfe0e9d 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
AnnaBridge 162:dbaafcfe0e9d 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
AnnaBridge 162:dbaafcfe0e9d 306 uint32_t RESERVED0[2];
AnnaBridge 162:dbaafcfe0e9d 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
AnnaBridge 162:dbaafcfe0e9d 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
AnnaBridge 162:dbaafcfe0e9d 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
AnnaBridge 162:dbaafcfe0e9d 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
AnnaBridge 162:dbaafcfe0e9d 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
AnnaBridge 162:dbaafcfe0e9d 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
AnnaBridge 162:dbaafcfe0e9d 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
AnnaBridge 162:dbaafcfe0e9d 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
AnnaBridge 162:dbaafcfe0e9d 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
AnnaBridge 162:dbaafcfe0e9d 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
AnnaBridge 162:dbaafcfe0e9d 317 union {
AnnaBridge 162:dbaafcfe0e9d 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
AnnaBridge 162:dbaafcfe0e9d 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
AnnaBridge 162:dbaafcfe0e9d 320 }Interrupt;
AnnaBridge 162:dbaafcfe0e9d 321 uint32_t RESERVED3[241];
AnnaBridge 162:dbaafcfe0e9d 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
AnnaBridge 162:dbaafcfe0e9d 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
AnnaBridge 162:dbaafcfe0e9d 324 } GPIO_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 325
AnnaBridge 162:dbaafcfe0e9d 326 typedef struct
AnnaBridge 162:dbaafcfe0e9d 327 {
AnnaBridge 162:dbaafcfe0e9d 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
AnnaBridge 162:dbaafcfe0e9d 329 /* Port_01, offset : 0x04 */
AnnaBridge 162:dbaafcfe0e9d 330 /* Port_02, offset : 0x08 */
AnnaBridge 162:dbaafcfe0e9d 331 /* Port_03, offset : 0x0C */
AnnaBridge 162:dbaafcfe0e9d 332 /* Port_04, offset : 0x10 */
AnnaBridge 162:dbaafcfe0e9d 333 /* Port_05, offset : 0x14 */
AnnaBridge 162:dbaafcfe0e9d 334 /* Port_06, offset : 0x18 */
AnnaBridge 162:dbaafcfe0e9d 335 /* Port_07, offset : 0x1C */
AnnaBridge 162:dbaafcfe0e9d 336 /* Port_08, offset : 0x20 */
AnnaBridge 162:dbaafcfe0e9d 337 /* Port_09, offset : 0x24 */
AnnaBridge 162:dbaafcfe0e9d 338 /* Port_10, offset : 0x28 */
AnnaBridge 162:dbaafcfe0e9d 339 /* Port_11, offset : 0x2C */
AnnaBridge 162:dbaafcfe0e9d 340 /* Port_12, offset : 0x30 */
AnnaBridge 162:dbaafcfe0e9d 341 /* Port_13, offset : 0x34 */
AnnaBridge 162:dbaafcfe0e9d 342 /* Port_14, offset : 0x38 */
AnnaBridge 162:dbaafcfe0e9d 343 /* Port_15, offset : 0x3C */
AnnaBridge 162:dbaafcfe0e9d 344 } P_Port_Def;
AnnaBridge 162:dbaafcfe0e9d 345
AnnaBridge 162:dbaafcfe0e9d 346 typedef struct
AnnaBridge 162:dbaafcfe0e9d 347 {
AnnaBridge 162:dbaafcfe0e9d 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
AnnaBridge 162:dbaafcfe0e9d 349 /* Port_01, offset : 0x04 */
AnnaBridge 162:dbaafcfe0e9d 350 /* Port_02, offset : 0x08 */
AnnaBridge 162:dbaafcfe0e9d 351 /* Port_03, offset : 0x0C */
AnnaBridge 162:dbaafcfe0e9d 352 /* Port_04, offset : 0x10 */
AnnaBridge 162:dbaafcfe0e9d 353 } P_Port_D_Def;
AnnaBridge 162:dbaafcfe0e9d 354
AnnaBridge 162:dbaafcfe0e9d 355 /**
AnnaBridge 162:dbaafcfe0e9d 356 * @brief I2C Register structure definition
AnnaBridge 162:dbaafcfe0e9d 357 */
AnnaBridge 162:dbaafcfe0e9d 358 typedef struct
AnnaBridge 162:dbaafcfe0e9d 359 {
AnnaBridge 162:dbaafcfe0e9d 360 __IO uint32_t PRER; //0x00
AnnaBridge 162:dbaafcfe0e9d 361 __IO uint32_t CTR; //0x04
AnnaBridge 162:dbaafcfe0e9d 362 __IO uint32_t CMDR; //0x08
AnnaBridge 162:dbaafcfe0e9d 363 __I uint32_t SR; //0x0C
AnnaBridge 162:dbaafcfe0e9d 364 __IO uint32_t TSR; //0x10
AnnaBridge 162:dbaafcfe0e9d 365 __IO uint32_t SADDR; //0x14
AnnaBridge 162:dbaafcfe0e9d 366 __IO uint32_t TXR; //0x18
AnnaBridge 162:dbaafcfe0e9d 367 __I uint32_t RXR; //0x1C
AnnaBridge 162:dbaafcfe0e9d 368 __I uint32_t ISR; //0x20
AnnaBridge 162:dbaafcfe0e9d 369 __IO uint32_t ISCR; //0x24
AnnaBridge 162:dbaafcfe0e9d 370 __IO uint32_t ISMR; //0x28
AnnaBridge 162:dbaafcfe0e9d 371 }I2C_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 372
AnnaBridge 162:dbaafcfe0e9d 373 /**
AnnaBridge 162:dbaafcfe0e9d 374 * @brief PWM Register structure definition
AnnaBridge 162:dbaafcfe0e9d 375 */
AnnaBridge 162:dbaafcfe0e9d 376 typedef struct
AnnaBridge 162:dbaafcfe0e9d 377 {
AnnaBridge 162:dbaafcfe0e9d 378 __IO uint32_t IER; //Interrupt enable register
AnnaBridge 162:dbaafcfe0e9d 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 387
AnnaBridge 162:dbaafcfe0e9d 388 __IO uint32_t SSR; //Start Stop register
AnnaBridge 162:dbaafcfe0e9d 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
AnnaBridge 162:dbaafcfe0e9d 397
AnnaBridge 162:dbaafcfe0e9d 398 __IO uint32_t PSR; //Pause register
AnnaBridge 162:dbaafcfe0e9d 399 // <7> PS7 : Channel 7 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 400 // <6> PS6 : Channel 6 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 401 // <5> PS5 : Channel 5 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 402 // <4> PS4 : Channel 4 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 403 // <3> PS3 : Channel 3 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 404 // <2> PS2 : Channel 2 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 405 // <1> PS1 : Channel 1 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 406 // <0> PS0 : Channel 0 TC pasue <R/W>
AnnaBridge 162:dbaafcfe0e9d 407 } PWM_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 408
AnnaBridge 162:dbaafcfe0e9d 409 typedef struct
AnnaBridge 162:dbaafcfe0e9d 410 {
AnnaBridge 162:dbaafcfe0e9d 411 __I uint32_t IR; //Interrupt register
AnnaBridge 162:dbaafcfe0e9d 412 // <2> CI : Capture interrupt <R>
AnnaBridge 162:dbaafcfe0e9d 413 // <1> OI : Overflow interrupt <R>
AnnaBridge 162:dbaafcfe0e9d 414 // <0> MI : Match interrupt <R>
AnnaBridge 162:dbaafcfe0e9d 415
AnnaBridge 162:dbaafcfe0e9d 416 __IO uint32_t IER; //Interrupt enable register
AnnaBridge 162:dbaafcfe0e9d 417 // <2> CIE : Capture interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 418 // <1> OIE : Overflow interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 419 // <0> MIE : Match interrupt enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 420
AnnaBridge 162:dbaafcfe0e9d 421 __O uint32_t ICR; //Interrupt clear register
AnnaBridge 162:dbaafcfe0e9d 422 // <2> CIC : Capture interrupt clear <W>
AnnaBridge 162:dbaafcfe0e9d 423 // <1> OIC : Overflow interrupt clear <W>
AnnaBridge 162:dbaafcfe0e9d 424 // <0> MIC : Match interrupt clear <W>
AnnaBridge 162:dbaafcfe0e9d 425
AnnaBridge 162:dbaafcfe0e9d 426 __I uint32_t TCR; //Timer/Counter register
AnnaBridge 162:dbaafcfe0e9d 427 // <0..31> TCR : Timer/Counter register <R>
AnnaBridge 162:dbaafcfe0e9d 428
AnnaBridge 162:dbaafcfe0e9d 429 __I uint32_t PCR; //Prescale counter register
AnnaBridge 162:dbaafcfe0e9d 430 // <0..5> PCR : Prescale Counter register <R>
AnnaBridge 162:dbaafcfe0e9d 431
AnnaBridge 162:dbaafcfe0e9d 432 __IO uint32_t PR; //Prescale register
AnnaBridge 162:dbaafcfe0e9d 433 // <0..5> PR : prescale register <R/W>
AnnaBridge 162:dbaafcfe0e9d 434
AnnaBridge 162:dbaafcfe0e9d 435 __IO uint32_t MR; //Match register
AnnaBridge 162:dbaafcfe0e9d 436 // <0..31> MR : Match register <R/W>
AnnaBridge 162:dbaafcfe0e9d 437
AnnaBridge 162:dbaafcfe0e9d 438 __IO uint32_t LR; //Limit register
AnnaBridge 162:dbaafcfe0e9d 439 // <0..31> LR : Limit register <R/W>
AnnaBridge 162:dbaafcfe0e9d 440 __IO uint32_t UDMR; //Up-Down mode register
AnnaBridge 162:dbaafcfe0e9d 441 // <0> UDM : Up-down mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 442
AnnaBridge 162:dbaafcfe0e9d 443 __IO uint32_t TCMR; //Timer/Counter mode register
AnnaBridge 162:dbaafcfe0e9d 444 // <0> TCM : Timer/Counter mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 445
AnnaBridge 162:dbaafcfe0e9d 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
AnnaBridge 162:dbaafcfe0e9d 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 448
AnnaBridge 162:dbaafcfe0e9d 449 __IO uint32_t CMR; //Capture mode register
AnnaBridge 162:dbaafcfe0e9d 450 // <0> CM : Capture mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 451
AnnaBridge 162:dbaafcfe0e9d 452 __IO uint32_t CR; //Capture register
AnnaBridge 162:dbaafcfe0e9d 453 // <0..31> CR : Capture register <R>
AnnaBridge 162:dbaafcfe0e9d 454
AnnaBridge 162:dbaafcfe0e9d 455 __IO uint32_t PDMR; //Periodic mode register
AnnaBridge 162:dbaafcfe0e9d 456 // <0> PDM : Periodic mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 457
AnnaBridge 162:dbaafcfe0e9d 458 __IO uint32_t DZER; //Dead-zone enable register
AnnaBridge 162:dbaafcfe0e9d 459 // <0> DZE : Dead-zone enable <R/W>
AnnaBridge 162:dbaafcfe0e9d 460
AnnaBridge 162:dbaafcfe0e9d 461 __IO uint32_t DZCR; //Dead-zone counter register
AnnaBridge 162:dbaafcfe0e9d 462 // <0..9> DZC : Dead-zone counter <R/W>
AnnaBridge 162:dbaafcfe0e9d 463 } PWM_CHn_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 464
AnnaBridge 162:dbaafcfe0e9d 465 typedef struct
AnnaBridge 162:dbaafcfe0e9d 466 {
AnnaBridge 162:dbaafcfe0e9d 467 __IO uint32_t PWM_CHn_PR; //Prescale register
AnnaBridge 162:dbaafcfe0e9d 468 // <0..5> PR : prescale register <R/W>
AnnaBridge 162:dbaafcfe0e9d 469 __IO uint32_t PWM_CHn_MR; //Match register
AnnaBridge 162:dbaafcfe0e9d 470 // <0..31> MR : Match register <R/W>
AnnaBridge 162:dbaafcfe0e9d 471 __IO uint32_t PWM_CHn_LR; //Limit register
AnnaBridge 162:dbaafcfe0e9d 472 // <0..31> LR : Limit register <R/W>
AnnaBridge 162:dbaafcfe0e9d 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
AnnaBridge 162:dbaafcfe0e9d 474 // <0> UDM : Up-down mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
AnnaBridge 162:dbaafcfe0e9d 476 // <0> PDM : Periodic mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 477 }PWM_TimerModeInitTypeDef;
AnnaBridge 162:dbaafcfe0e9d 478
AnnaBridge 162:dbaafcfe0e9d 479 typedef struct
AnnaBridge 162:dbaafcfe0e9d 480 {
AnnaBridge 162:dbaafcfe0e9d 481 __IO uint32_t PWM_CHn_PR; //Prescale register
AnnaBridge 162:dbaafcfe0e9d 482 // <0..5> PR : prescale register <R/W>
AnnaBridge 162:dbaafcfe0e9d 483 __IO uint32_t PWM_CHn_MR; //Match register
AnnaBridge 162:dbaafcfe0e9d 484 // <0..31> MR : Match register <R/W>
AnnaBridge 162:dbaafcfe0e9d 485 __IO uint32_t PWM_CHn_LR; //Limit register
AnnaBridge 162:dbaafcfe0e9d 486 // <0..31> LR : Limit register <R/W>
AnnaBridge 162:dbaafcfe0e9d 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
AnnaBridge 162:dbaafcfe0e9d 488 // <0> UDM : Up-down mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
AnnaBridge 162:dbaafcfe0e9d 490 // <0> PDM : Peiodic mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
AnnaBridge 162:dbaafcfe0e9d 492 // <0> CM : Capture mode <R/W>
AnnaBridge 162:dbaafcfe0e9d 493 }PWM_CaptureModeInitTypeDef;
AnnaBridge 162:dbaafcfe0e9d 494
AnnaBridge 162:dbaafcfe0e9d 495 typedef struct
AnnaBridge 162:dbaafcfe0e9d 496 {
AnnaBridge 162:dbaafcfe0e9d 497 __IO uint32_t PWM_CHn_MR;
AnnaBridge 162:dbaafcfe0e9d 498 __IO uint32_t PWM_CHn_LR;
AnnaBridge 162:dbaafcfe0e9d 499 __IO uint32_t PWM_CHn_UDMR;
AnnaBridge 162:dbaafcfe0e9d 500 __IO uint32_t PWM_CHn_PDMR;
AnnaBridge 162:dbaafcfe0e9d 501 __IO uint32_t PWM_CHn_TCMR;
AnnaBridge 162:dbaafcfe0e9d 502 }PWM_CounterModeInitTypeDef;
AnnaBridge 162:dbaafcfe0e9d 503
AnnaBridge 162:dbaafcfe0e9d 504
AnnaBridge 162:dbaafcfe0e9d 505 /**
AnnaBridge 162:dbaafcfe0e9d 506 * @brief Random Number generator
AnnaBridge 162:dbaafcfe0e9d 507 */
AnnaBridge 162:dbaafcfe0e9d 508 typedef struct
AnnaBridge 162:dbaafcfe0e9d 509 {
AnnaBridge 162:dbaafcfe0e9d 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
AnnaBridge 162:dbaafcfe0e9d 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
AnnaBridge 162:dbaafcfe0e9d 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
AnnaBridge 162:dbaafcfe0e9d 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
AnnaBridge 162:dbaafcfe0e9d 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
AnnaBridge 162:dbaafcfe0e9d 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
AnnaBridge 162:dbaafcfe0e9d 516 }RNG_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 517
AnnaBridge 162:dbaafcfe0e9d 518 /**
AnnaBridge 162:dbaafcfe0e9d 519 * @brief Serial Peripheral Interface
AnnaBridge 162:dbaafcfe0e9d 520 */
AnnaBridge 162:dbaafcfe0e9d 521 typedef struct
AnnaBridge 162:dbaafcfe0e9d 522 {
AnnaBridge 162:dbaafcfe0e9d 523 __IO uint32_t CR0;
AnnaBridge 162:dbaafcfe0e9d 524 __IO uint32_t CR1;
AnnaBridge 162:dbaafcfe0e9d 525 __IO uint32_t DR;
AnnaBridge 162:dbaafcfe0e9d 526 __IO uint32_t SR;
AnnaBridge 162:dbaafcfe0e9d 527 __IO uint32_t CPSR;
AnnaBridge 162:dbaafcfe0e9d 528 __IO uint32_t IMSC;
AnnaBridge 162:dbaafcfe0e9d 529 __IO uint32_t RIS;
AnnaBridge 162:dbaafcfe0e9d 530 __IO uint32_t MIS;
AnnaBridge 162:dbaafcfe0e9d 531 __IO uint32_t ICR;
AnnaBridge 162:dbaafcfe0e9d 532 __IO uint32_t DMACR;
AnnaBridge 162:dbaafcfe0e9d 533 } SSP_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 534
AnnaBridge 162:dbaafcfe0e9d 535 typedef struct
AnnaBridge 162:dbaafcfe0e9d 536 {
AnnaBridge 162:dbaafcfe0e9d 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
AnnaBridge 162:dbaafcfe0e9d 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
AnnaBridge 162:dbaafcfe0e9d 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
AnnaBridge 162:dbaafcfe0e9d 540 // <o.1> RESEN: Reset enable
AnnaBridge 162:dbaafcfe0e9d 541 // <o.0> INTEN: Interrupt enable
AnnaBridge 162:dbaafcfe0e9d 542 // </h>
AnnaBridge 162:dbaafcfe0e9d 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
AnnaBridge 162:dbaafcfe0e9d 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
AnnaBridge 162:dbaafcfe0e9d 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
AnnaBridge 162:dbaafcfe0e9d 546 uint32_t RESERVED[762];
AnnaBridge 162:dbaafcfe0e9d 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
AnnaBridge 162:dbaafcfe0e9d 548 }WATCHDOG_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 549
AnnaBridge 162:dbaafcfe0e9d 550 /** @addtogroup Peripheral_memory_map
AnnaBridge 162:dbaafcfe0e9d 551 * @{
AnnaBridge 162:dbaafcfe0e9d 552 */
AnnaBridge 162:dbaafcfe0e9d 553
AnnaBridge 162:dbaafcfe0e9d 554 /* Peripheral and SRAM base address */
AnnaBridge 162:dbaafcfe0e9d 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
AnnaBridge 162:dbaafcfe0e9d 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
AnnaBridge 162:dbaafcfe0e9d 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
AnnaBridge 162:dbaafcfe0e9d 558
AnnaBridge 162:dbaafcfe0e9d 559 #define W7500x_RAM_BASE (0x20000000UL)
AnnaBridge 162:dbaafcfe0e9d 560 #define W7500x_APB1_BASE (0x40000000UL)
AnnaBridge 162:dbaafcfe0e9d 561 #define W7500x_APB2_BASE (0x41000000UL)
AnnaBridge 162:dbaafcfe0e9d 562 #define W7500x_AHB_BASE (0x42000000UL)
AnnaBridge 162:dbaafcfe0e9d 563
AnnaBridge 162:dbaafcfe0e9d 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
AnnaBridge 162:dbaafcfe0e9d 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
AnnaBridge 162:dbaafcfe0e9d 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
AnnaBridge 162:dbaafcfe0e9d 567
AnnaBridge 162:dbaafcfe0e9d 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
AnnaBridge 162:dbaafcfe0e9d 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
AnnaBridge 162:dbaafcfe0e9d 570
AnnaBridge 162:dbaafcfe0e9d 571 #define W7500x_INFO_BGT (0x0003FDB8)
AnnaBridge 162:dbaafcfe0e9d 572 #define W7500x_INFO_OSC (0x0003FDBC)
AnnaBridge 162:dbaafcfe0e9d 573
AnnaBridge 162:dbaafcfe0e9d 574 #define W7500x_TRIM_BGT (0x41001210)
AnnaBridge 162:dbaafcfe0e9d 575 #define W7500x_TRIM_OSC (0x41001004)
AnnaBridge 162:dbaafcfe0e9d 576
AnnaBridge 162:dbaafcfe0e9d 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
AnnaBridge 162:dbaafcfe0e9d 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
AnnaBridge 162:dbaafcfe0e9d 579
AnnaBridge 162:dbaafcfe0e9d 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
AnnaBridge 162:dbaafcfe0e9d 581
AnnaBridge 162:dbaafcfe0e9d 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
AnnaBridge 162:dbaafcfe0e9d 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
AnnaBridge 162:dbaafcfe0e9d 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
AnnaBridge 162:dbaafcfe0e9d 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
AnnaBridge 162:dbaafcfe0e9d 586
AnnaBridge 162:dbaafcfe0e9d 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
AnnaBridge 162:dbaafcfe0e9d 588
AnnaBridge 162:dbaafcfe0e9d 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
AnnaBridge 162:dbaafcfe0e9d 590
AnnaBridge 162:dbaafcfe0e9d 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
AnnaBridge 162:dbaafcfe0e9d 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
AnnaBridge 162:dbaafcfe0e9d 593
AnnaBridge 162:dbaafcfe0e9d 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
AnnaBridge 162:dbaafcfe0e9d 595
AnnaBridge 162:dbaafcfe0e9d 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
AnnaBridge 162:dbaafcfe0e9d 597
AnnaBridge 162:dbaafcfe0e9d 598 #define SSP0_BASE (0x4000A000)
AnnaBridge 162:dbaafcfe0e9d 599 #define SSP1_BASE (0x4000B000)
AnnaBridge 162:dbaafcfe0e9d 600
AnnaBridge 162:dbaafcfe0e9d 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
AnnaBridge 162:dbaafcfe0e9d 602
AnnaBridge 162:dbaafcfe0e9d 603 /**
AnnaBridge 162:dbaafcfe0e9d 604 * @}
AnnaBridge 162:dbaafcfe0e9d 605 */
AnnaBridge 162:dbaafcfe0e9d 606
AnnaBridge 162:dbaafcfe0e9d 607
AnnaBridge 162:dbaafcfe0e9d 608 /** @addtogroup Peripheral_declaration
AnnaBridge 162:dbaafcfe0e9d 609 * @{
AnnaBridge 162:dbaafcfe0e9d 610 */
AnnaBridge 162:dbaafcfe0e9d 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
AnnaBridge 162:dbaafcfe0e9d 612
AnnaBridge 162:dbaafcfe0e9d 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
AnnaBridge 162:dbaafcfe0e9d 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
AnnaBridge 162:dbaafcfe0e9d 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
AnnaBridge 162:dbaafcfe0e9d 616
AnnaBridge 162:dbaafcfe0e9d 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
AnnaBridge 162:dbaafcfe0e9d 618
AnnaBridge 162:dbaafcfe0e9d 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
AnnaBridge 162:dbaafcfe0e9d 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
AnnaBridge 162:dbaafcfe0e9d 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
AnnaBridge 162:dbaafcfe0e9d 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
AnnaBridge 162:dbaafcfe0e9d 623
AnnaBridge 162:dbaafcfe0e9d 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
AnnaBridge 162:dbaafcfe0e9d 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
AnnaBridge 162:dbaafcfe0e9d 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
AnnaBridge 162:dbaafcfe0e9d 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
AnnaBridge 162:dbaafcfe0e9d 628
AnnaBridge 162:dbaafcfe0e9d 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
AnnaBridge 162:dbaafcfe0e9d 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
AnnaBridge 162:dbaafcfe0e9d 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
AnnaBridge 162:dbaafcfe0e9d 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
AnnaBridge 162:dbaafcfe0e9d 633
AnnaBridge 162:dbaafcfe0e9d 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
AnnaBridge 162:dbaafcfe0e9d 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
AnnaBridge 162:dbaafcfe0e9d 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
AnnaBridge 162:dbaafcfe0e9d 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
AnnaBridge 162:dbaafcfe0e9d 638
AnnaBridge 162:dbaafcfe0e9d 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
AnnaBridge 162:dbaafcfe0e9d 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
AnnaBridge 162:dbaafcfe0e9d 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
AnnaBridge 162:dbaafcfe0e9d 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
AnnaBridge 162:dbaafcfe0e9d 643
AnnaBridge 162:dbaafcfe0e9d 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
AnnaBridge 162:dbaafcfe0e9d 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 162:dbaafcfe0e9d 646
AnnaBridge 162:dbaafcfe0e9d 647
AnnaBridge 162:dbaafcfe0e9d 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
AnnaBridge 162:dbaafcfe0e9d 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
AnnaBridge 162:dbaafcfe0e9d 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
AnnaBridge 162:dbaafcfe0e9d 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
AnnaBridge 162:dbaafcfe0e9d 652
AnnaBridge 162:dbaafcfe0e9d 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
AnnaBridge 162:dbaafcfe0e9d 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
AnnaBridge 162:dbaafcfe0e9d 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
AnnaBridge 162:dbaafcfe0e9d 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
AnnaBridge 162:dbaafcfe0e9d 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
AnnaBridge 162:dbaafcfe0e9d 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
AnnaBridge 162:dbaafcfe0e9d 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
AnnaBridge 162:dbaafcfe0e9d 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
AnnaBridge 162:dbaafcfe0e9d 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
AnnaBridge 162:dbaafcfe0e9d 662
AnnaBridge 162:dbaafcfe0e9d 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
AnnaBridge 162:dbaafcfe0e9d 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
AnnaBridge 162:dbaafcfe0e9d 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
AnnaBridge 162:dbaafcfe0e9d 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
AnnaBridge 162:dbaafcfe0e9d 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
AnnaBridge 162:dbaafcfe0e9d 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
AnnaBridge 162:dbaafcfe0e9d 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
AnnaBridge 162:dbaafcfe0e9d 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
AnnaBridge 162:dbaafcfe0e9d 671
AnnaBridge 162:dbaafcfe0e9d 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
AnnaBridge 162:dbaafcfe0e9d 673
AnnaBridge 162:dbaafcfe0e9d 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
AnnaBridge 162:dbaafcfe0e9d 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
AnnaBridge 162:dbaafcfe0e9d 676
AnnaBridge 162:dbaafcfe0e9d 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
AnnaBridge 162:dbaafcfe0e9d 678
AnnaBridge 162:dbaafcfe0e9d 679 /**
AnnaBridge 162:dbaafcfe0e9d 680 * @}
AnnaBridge 162:dbaafcfe0e9d 681 */
AnnaBridge 162:dbaafcfe0e9d 682
AnnaBridge 162:dbaafcfe0e9d 683
AnnaBridge 162:dbaafcfe0e9d 684
AnnaBridge 162:dbaafcfe0e9d 685 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 686 /* */
AnnaBridge 162:dbaafcfe0e9d 687 /* Clock Reset Generator */
AnnaBridge 162:dbaafcfe0e9d 688 /* */
AnnaBridge 162:dbaafcfe0e9d 689 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 690 /**************** Bit definition for CRG_OSC_PDR **************************/
AnnaBridge 162:dbaafcfe0e9d 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
AnnaBridge 162:dbaafcfe0e9d 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
AnnaBridge 162:dbaafcfe0e9d 693 /**************** Bit definition for CRG_PLL_PDR **************************/
AnnaBridge 162:dbaafcfe0e9d 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
AnnaBridge 162:dbaafcfe0e9d 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
AnnaBridge 162:dbaafcfe0e9d 696 /**************** Bit definition for CRG_PLL_FCR **************************/
AnnaBridge 162:dbaafcfe0e9d 697 //ToDo
AnnaBridge 162:dbaafcfe0e9d 698 /**************** Bit definition for CRG_PLL_OER **************************/
AnnaBridge 162:dbaafcfe0e9d 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
AnnaBridge 162:dbaafcfe0e9d 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
AnnaBridge 162:dbaafcfe0e9d 701 /**************** Bit definition for CRG_PLL_BPR **************************/
AnnaBridge 162:dbaafcfe0e9d 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
AnnaBridge 162:dbaafcfe0e9d 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
AnnaBridge 162:dbaafcfe0e9d 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
AnnaBridge 162:dbaafcfe0e9d 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
AnnaBridge 162:dbaafcfe0e9d 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
AnnaBridge 162:dbaafcfe0e9d 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
AnnaBridge 162:dbaafcfe0e9d 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
AnnaBridge 162:dbaafcfe0e9d 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
AnnaBridge 162:dbaafcfe0e9d 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
AnnaBridge 162:dbaafcfe0e9d 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
AnnaBridge 162:dbaafcfe0e9d 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
AnnaBridge 162:dbaafcfe0e9d 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
AnnaBridge 162:dbaafcfe0e9d 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
AnnaBridge 162:dbaafcfe0e9d 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
AnnaBridge 162:dbaafcfe0e9d 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
AnnaBridge 162:dbaafcfe0e9d 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
AnnaBridge 162:dbaafcfe0e9d 778 /**************** Bit definition for CRG_RTC_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
AnnaBridge 162:dbaafcfe0e9d 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
AnnaBridge 162:dbaafcfe0e9d 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
AnnaBridge 162:dbaafcfe0e9d 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
AnnaBridge 162:dbaafcfe0e9d 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
AnnaBridge 162:dbaafcfe0e9d 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
AnnaBridge 162:dbaafcfe0e9d 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
AnnaBridge 162:dbaafcfe0e9d 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
AnnaBridge 162:dbaafcfe0e9d 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
AnnaBridge 162:dbaafcfe0e9d 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
AnnaBridge 162:dbaafcfe0e9d 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
AnnaBridge 162:dbaafcfe0e9d 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
AnnaBridge 162:dbaafcfe0e9d 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
AnnaBridge 162:dbaafcfe0e9d 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
AnnaBridge 162:dbaafcfe0e9d 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
AnnaBridge 162:dbaafcfe0e9d 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
AnnaBridge 162:dbaafcfe0e9d 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
AnnaBridge 162:dbaafcfe0e9d 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
AnnaBridge 162:dbaafcfe0e9d 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
AnnaBridge 162:dbaafcfe0e9d 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
AnnaBridge 162:dbaafcfe0e9d 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
AnnaBridge 162:dbaafcfe0e9d 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
AnnaBridge 162:dbaafcfe0e9d 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
AnnaBridge 162:dbaafcfe0e9d 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
AnnaBridge 162:dbaafcfe0e9d 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
AnnaBridge 162:dbaafcfe0e9d 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
AnnaBridge 162:dbaafcfe0e9d 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
AnnaBridge 162:dbaafcfe0e9d 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
AnnaBridge 162:dbaafcfe0e9d 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
AnnaBridge 162:dbaafcfe0e9d 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
AnnaBridge 162:dbaafcfe0e9d 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
AnnaBridge 162:dbaafcfe0e9d 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
AnnaBridge 162:dbaafcfe0e9d 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
AnnaBridge 162:dbaafcfe0e9d 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
AnnaBridge 162:dbaafcfe0e9d 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
AnnaBridge 162:dbaafcfe0e9d 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
AnnaBridge 162:dbaafcfe0e9d 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
AnnaBridge 162:dbaafcfe0e9d 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
AnnaBridge 162:dbaafcfe0e9d 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
AnnaBridge 162:dbaafcfe0e9d 832
AnnaBridge 162:dbaafcfe0e9d 833 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 834 /* */
AnnaBridge 162:dbaafcfe0e9d 835 /* UART */
AnnaBridge 162:dbaafcfe0e9d 836 /* */
AnnaBridge 162:dbaafcfe0e9d 837 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
AnnaBridge 162:dbaafcfe0e9d 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
AnnaBridge 162:dbaafcfe0e9d 840 #define UART_DR_BE (0x01ul << 10) // Break Error
AnnaBridge 162:dbaafcfe0e9d 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
AnnaBridge 162:dbaafcfe0e9d 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
AnnaBridge 162:dbaafcfe0e9d 843 //#define UART_DR_DR // ToDo
AnnaBridge 162:dbaafcfe0e9d 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
AnnaBridge 162:dbaafcfe0e9d 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
AnnaBridge 162:dbaafcfe0e9d 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
AnnaBridge 162:dbaafcfe0e9d 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
AnnaBridge 162:dbaafcfe0e9d 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
AnnaBridge 162:dbaafcfe0e9d 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
AnnaBridge 162:dbaafcfe0e9d 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
AnnaBridge 162:dbaafcfe0e9d 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
AnnaBridge 162:dbaafcfe0e9d 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
AnnaBridge 162:dbaafcfe0e9d 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
AnnaBridge 162:dbaafcfe0e9d 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
AnnaBridge 162:dbaafcfe0e9d 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
AnnaBridge 162:dbaafcfe0e9d 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
AnnaBridge 162:dbaafcfe0e9d 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
AnnaBridge 162:dbaafcfe0e9d 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
AnnaBridge 162:dbaafcfe0e9d 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
AnnaBridge 162:dbaafcfe0e9d 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
AnnaBridge 162:dbaafcfe0e9d 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
AnnaBridge 162:dbaafcfe0e9d 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
AnnaBridge 162:dbaafcfe0e9d 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
AnnaBridge 162:dbaafcfe0e9d 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
AnnaBridge 162:dbaafcfe0e9d 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
AnnaBridge 162:dbaafcfe0e9d 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
AnnaBridge 162:dbaafcfe0e9d 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
AnnaBridge 162:dbaafcfe0e9d 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
AnnaBridge 162:dbaafcfe0e9d 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
AnnaBridge 162:dbaafcfe0e9d 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
AnnaBridge 162:dbaafcfe0e9d 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
AnnaBridge 162:dbaafcfe0e9d 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
AnnaBridge 162:dbaafcfe0e9d 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
AnnaBridge 162:dbaafcfe0e9d 874 /********************* Bit definition for Contro(UARTCR) register *************************/
AnnaBridge 162:dbaafcfe0e9d 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
AnnaBridge 162:dbaafcfe0e9d 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
AnnaBridge 162:dbaafcfe0e9d 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
AnnaBridge 162:dbaafcfe0e9d 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
AnnaBridge 162:dbaafcfe0e9d 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
AnnaBridge 162:dbaafcfe0e9d 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
AnnaBridge 162:dbaafcfe0e9d 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
AnnaBridge 162:dbaafcfe0e9d 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
AnnaBridge 162:dbaafcfe0e9d 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
AnnaBridge 162:dbaafcfe0e9d 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
AnnaBridge 162:dbaafcfe0e9d 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
AnnaBridge 162:dbaafcfe0e9d 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
AnnaBridge 162:dbaafcfe0e9d 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
AnnaBridge 162:dbaafcfe0e9d 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
AnnaBridge 162:dbaafcfe0e9d 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
AnnaBridge 162:dbaafcfe0e9d 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
AnnaBridge 162:dbaafcfe0e9d 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
AnnaBridge 162:dbaafcfe0e9d 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
AnnaBridge 162:dbaafcfe0e9d 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
AnnaBridge 162:dbaafcfe0e9d 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
AnnaBridge 162:dbaafcfe0e9d 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
AnnaBridge 162:dbaafcfe0e9d 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
AnnaBridge 162:dbaafcfe0e9d 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
AnnaBridge 162:dbaafcfe0e9d 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
AnnaBridge 162:dbaafcfe0e9d 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
AnnaBridge 162:dbaafcfe0e9d 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
AnnaBridge 162:dbaafcfe0e9d 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
AnnaBridge 162:dbaafcfe0e9d 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
AnnaBridge 162:dbaafcfe0e9d 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
AnnaBridge 162:dbaafcfe0e9d 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
AnnaBridge 162:dbaafcfe0e9d 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
AnnaBridge 162:dbaafcfe0e9d 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
AnnaBridge 162:dbaafcfe0e9d 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
AnnaBridge 162:dbaafcfe0e9d 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
AnnaBridge 162:dbaafcfe0e9d 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
AnnaBridge 162:dbaafcfe0e9d 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
AnnaBridge 162:dbaafcfe0e9d 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
AnnaBridge 162:dbaafcfe0e9d 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
AnnaBridge 162:dbaafcfe0e9d 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
AnnaBridge 162:dbaafcfe0e9d 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
AnnaBridge 162:dbaafcfe0e9d 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
AnnaBridge 162:dbaafcfe0e9d 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
AnnaBridge 162:dbaafcfe0e9d 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
AnnaBridge 162:dbaafcfe0e9d 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
AnnaBridge 162:dbaafcfe0e9d 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
AnnaBridge 162:dbaafcfe0e9d 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
AnnaBridge 162:dbaafcfe0e9d 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
AnnaBridge 162:dbaafcfe0e9d 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
AnnaBridge 162:dbaafcfe0e9d 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
AnnaBridge 162:dbaafcfe0e9d 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
AnnaBridge 162:dbaafcfe0e9d 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
AnnaBridge 162:dbaafcfe0e9d 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
AnnaBridge 162:dbaafcfe0e9d 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
AnnaBridge 162:dbaafcfe0e9d 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
AnnaBridge 162:dbaafcfe0e9d 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
AnnaBridge 162:dbaafcfe0e9d 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
AnnaBridge 162:dbaafcfe0e9d 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
AnnaBridge 162:dbaafcfe0e9d 942
AnnaBridge 162:dbaafcfe0e9d 943 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 944 /* */
AnnaBridge 162:dbaafcfe0e9d 945 /* Simple UART */
AnnaBridge 162:dbaafcfe0e9d 946 /* */
AnnaBridge 162:dbaafcfe0e9d 947 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 948 /***************** Bit definition for S_UART Data () register ************************/
AnnaBridge 162:dbaafcfe0e9d 949 #define S_UART_DATA (0xFFul << 0)
AnnaBridge 162:dbaafcfe0e9d 950 /***************** Bit definition for S_UART State() register ************************/
AnnaBridge 162:dbaafcfe0e9d 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
AnnaBridge 162:dbaafcfe0e9d 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
AnnaBridge 162:dbaafcfe0e9d 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
AnnaBridge 162:dbaafcfe0e9d 954 /***************** Bit definition for S_UART Control() register ************************/
AnnaBridge 162:dbaafcfe0e9d 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
AnnaBridge 162:dbaafcfe0e9d 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
AnnaBridge 162:dbaafcfe0e9d 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
AnnaBridge 162:dbaafcfe0e9d 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
AnnaBridge 162:dbaafcfe0e9d 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
AnnaBridge 162:dbaafcfe0e9d 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
AnnaBridge 162:dbaafcfe0e9d 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
AnnaBridge 162:dbaafcfe0e9d 962 /***************** Bit definition for S_UART Interrupt() register ************************/
AnnaBridge 162:dbaafcfe0e9d 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
AnnaBridge 162:dbaafcfe0e9d 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
AnnaBridge 162:dbaafcfe0e9d 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
AnnaBridge 162:dbaafcfe0e9d 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
AnnaBridge 162:dbaafcfe0e9d 967
AnnaBridge 162:dbaafcfe0e9d 968 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 969 /* */
AnnaBridge 162:dbaafcfe0e9d 970 /* Analog Digital Register */
AnnaBridge 162:dbaafcfe0e9d 971 /* */
AnnaBridge 162:dbaafcfe0e9d 972 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 973
AnnaBridge 162:dbaafcfe0e9d 974 /*********************** Bit definition for ADC_CTR ***********************/
AnnaBridge 162:dbaafcfe0e9d 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
AnnaBridge 162:dbaafcfe0e9d 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
AnnaBridge 162:dbaafcfe0e9d 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
AnnaBridge 162:dbaafcfe0e9d 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
AnnaBridge 162:dbaafcfe0e9d 979 /*********************** Bit definition for ADC_CHSEL ***********************/
AnnaBridge 162:dbaafcfe0e9d 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
AnnaBridge 162:dbaafcfe0e9d 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
AnnaBridge 162:dbaafcfe0e9d 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
AnnaBridge 162:dbaafcfe0e9d 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
AnnaBridge 162:dbaafcfe0e9d 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
AnnaBridge 162:dbaafcfe0e9d 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
AnnaBridge 162:dbaafcfe0e9d 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
AnnaBridge 162:dbaafcfe0e9d 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
AnnaBridge 162:dbaafcfe0e9d 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
AnnaBridge 162:dbaafcfe0e9d 989 /*********************** Bit definition for ADC_START ***********************/
AnnaBridge 162:dbaafcfe0e9d 990 #define ADC_START_START (0x1ul) // ADC conversion start
AnnaBridge 162:dbaafcfe0e9d 991 /*********************** Bit definition for ADC_DATA ***********************/
AnnaBridge 162:dbaafcfe0e9d 992 //ToDo (Readonly)
AnnaBridge 162:dbaafcfe0e9d 993
AnnaBridge 162:dbaafcfe0e9d 994 /*********************** Bit definition for ADC_INT ***********************/
AnnaBridge 162:dbaafcfe0e9d 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
AnnaBridge 162:dbaafcfe0e9d 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
AnnaBridge 162:dbaafcfe0e9d 997 //ToDo (Readonly)
AnnaBridge 162:dbaafcfe0e9d 998
AnnaBridge 162:dbaafcfe0e9d 999 /*********************** Bit definition for ADC_INTCLR ***********************/
AnnaBridge 162:dbaafcfe0e9d 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
AnnaBridge 162:dbaafcfe0e9d 1001
AnnaBridge 162:dbaafcfe0e9d 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
AnnaBridge 162:dbaafcfe0e9d 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
AnnaBridge 162:dbaafcfe0e9d 1004
AnnaBridge 162:dbaafcfe0e9d 1005 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1006 /* */
AnnaBridge 162:dbaafcfe0e9d 1007 /* Dual Timer */
AnnaBridge 162:dbaafcfe0e9d 1008 /* */
AnnaBridge 162:dbaafcfe0e9d 1009 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1010
AnnaBridge 162:dbaafcfe0e9d 1011 /*********************** Bit definition for dualtimer ***********************/
AnnaBridge 162:dbaafcfe0e9d 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
AnnaBridge 162:dbaafcfe0e9d 1015
AnnaBridge 162:dbaafcfe0e9d 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
AnnaBridge 162:dbaafcfe0e9d 1019
AnnaBridge 162:dbaafcfe0e9d 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
AnnaBridge 162:dbaafcfe0e9d 1023
AnnaBridge 162:dbaafcfe0e9d 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
AnnaBridge 162:dbaafcfe0e9d 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
AnnaBridge 162:dbaafcfe0e9d 1028
AnnaBridge 162:dbaafcfe0e9d 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1031 #define DUALTIMER_TimerControl_Size_Pos 1
AnnaBridge 162:dbaafcfe0e9d 1032
AnnaBridge 162:dbaafcfe0e9d 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
AnnaBridge 162:dbaafcfe0e9d 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
AnnaBridge 162:dbaafcfe0e9d 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
AnnaBridge 162:dbaafcfe0e9d 1036
AnnaBridge 162:dbaafcfe0e9d 1037 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1038 /* */
AnnaBridge 162:dbaafcfe0e9d 1039 /* External Interrupt */
AnnaBridge 162:dbaafcfe0e9d 1040 /* */
AnnaBridge 162:dbaafcfe0e9d 1041 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1042
AnnaBridge 162:dbaafcfe0e9d 1043 /**************** Bit definition for Px_IER **************************/
AnnaBridge 162:dbaafcfe0e9d 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
AnnaBridge 162:dbaafcfe0e9d 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
AnnaBridge 162:dbaafcfe0e9d 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
AnnaBridge 162:dbaafcfe0e9d 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
AnnaBridge 162:dbaafcfe0e9d 1048
AnnaBridge 162:dbaafcfe0e9d 1049 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1050 /* */
AnnaBridge 162:dbaafcfe0e9d 1051 /* GPIO */
AnnaBridge 162:dbaafcfe0e9d 1052 /* */
AnnaBridge 162:dbaafcfe0e9d 1053 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1054
AnnaBridge 162:dbaafcfe0e9d 1055 /**************** Bit definition for Px_AFSR **************************/
AnnaBridge 162:dbaafcfe0e9d 1056 #define Px_AFSR_AF0 (0x00ul)
AnnaBridge 162:dbaafcfe0e9d 1057 #define Px_AFSR_AF1 (0x01ul)
AnnaBridge 162:dbaafcfe0e9d 1058 #define Px_AFSR_AF2 (0x02ul)
AnnaBridge 162:dbaafcfe0e9d 1059 #define Px_AFSR_AF3 (0x03ul)
AnnaBridge 162:dbaafcfe0e9d 1060 /**************** Bit definition for Px_PCR **************************/
AnnaBridge 162:dbaafcfe0e9d 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
AnnaBridge 162:dbaafcfe0e9d 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
AnnaBridge 162:dbaafcfe0e9d 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
AnnaBridge 162:dbaafcfe0e9d 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
AnnaBridge 162:dbaafcfe0e9d 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
AnnaBridge 162:dbaafcfe0e9d 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
AnnaBridge 162:dbaafcfe0e9d 1067
AnnaBridge 162:dbaafcfe0e9d 1068 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1069 /* */
AnnaBridge 162:dbaafcfe0e9d 1070 /* I2C */
AnnaBridge 162:dbaafcfe0e9d 1071 /* */
AnnaBridge 162:dbaafcfe0e9d 1072 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1073
AnnaBridge 162:dbaafcfe0e9d 1074 /**************** Bit definition for I2C_CTR **************************/
AnnaBridge 162:dbaafcfe0e9d 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
AnnaBridge 162:dbaafcfe0e9d 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
AnnaBridge 162:dbaafcfe0e9d 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
AnnaBridge 162:dbaafcfe0e9d 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
AnnaBridge 162:dbaafcfe0e9d 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
AnnaBridge 162:dbaafcfe0e9d 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
AnnaBridge 162:dbaafcfe0e9d 1081
AnnaBridge 162:dbaafcfe0e9d 1082 /**************** Bit definition for I2C_CMDR **************************/
AnnaBridge 162:dbaafcfe0e9d 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
AnnaBridge 162:dbaafcfe0e9d 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
AnnaBridge 162:dbaafcfe0e9d 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
AnnaBridge 162:dbaafcfe0e9d 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
AnnaBridge 162:dbaafcfe0e9d 1087
AnnaBridge 162:dbaafcfe0e9d 1088 /**************** Bit definition for I2C_ISCR **************************/
AnnaBridge 162:dbaafcfe0e9d 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
AnnaBridge 162:dbaafcfe0e9d 1090
AnnaBridge 162:dbaafcfe0e9d 1091 /**************** Bit definition for I2C_SR **************************/
AnnaBridge 162:dbaafcfe0e9d 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
AnnaBridge 162:dbaafcfe0e9d 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
AnnaBridge 162:dbaafcfe0e9d 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
AnnaBridge 162:dbaafcfe0e9d 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
AnnaBridge 162:dbaafcfe0e9d 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
AnnaBridge 162:dbaafcfe0e9d 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
AnnaBridge 162:dbaafcfe0e9d 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
AnnaBridge 162:dbaafcfe0e9d 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
AnnaBridge 162:dbaafcfe0e9d 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
AnnaBridge 162:dbaafcfe0e9d 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
AnnaBridge 162:dbaafcfe0e9d 1102
AnnaBridge 162:dbaafcfe0e9d 1103 /**************** Bit definition for I2C_ISR **************************/
AnnaBridge 162:dbaafcfe0e9d 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
AnnaBridge 162:dbaafcfe0e9d 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
AnnaBridge 162:dbaafcfe0e9d 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
AnnaBridge 162:dbaafcfe0e9d 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
AnnaBridge 162:dbaafcfe0e9d 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
AnnaBridge 162:dbaafcfe0e9d 1109
AnnaBridge 162:dbaafcfe0e9d 1110 /**************** Bit definition for I2C_ISMR **************************/
AnnaBridge 162:dbaafcfe0e9d 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
AnnaBridge 162:dbaafcfe0e9d 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
AnnaBridge 162:dbaafcfe0e9d 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
AnnaBridge 162:dbaafcfe0e9d 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
AnnaBridge 162:dbaafcfe0e9d 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
AnnaBridge 162:dbaafcfe0e9d 1116
AnnaBridge 162:dbaafcfe0e9d 1117 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1118 /* */
AnnaBridge 162:dbaafcfe0e9d 1119 /* PWM */
AnnaBridge 162:dbaafcfe0e9d 1120 /* */
AnnaBridge 162:dbaafcfe0e9d 1121 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1122
AnnaBridge 162:dbaafcfe0e9d 1123 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1124 /* */
AnnaBridge 162:dbaafcfe0e9d 1125 /* Random number generator Register */
AnnaBridge 162:dbaafcfe0e9d 1126 /* */
AnnaBridge 162:dbaafcfe0e9d 1127 /******************************************************************************/
AnnaBridge 162:dbaafcfe0e9d 1128
AnnaBridge 162:dbaafcfe0e9d 1129 /*********************** Bit definition for RNG_RUN ***********************/
AnnaBridge 162:dbaafcfe0e9d 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
AnnaBridge 162:dbaafcfe0e9d 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
AnnaBridge 162:dbaafcfe0e9d 1132 /*********************** Bit definition for RNG_SEED ***********************/
AnnaBridge 162:dbaafcfe0e9d 1133 //ToDo
AnnaBridge 162:dbaafcfe0e9d 1134
AnnaBridge 162:dbaafcfe0e9d 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
AnnaBridge 162:dbaafcfe0e9d 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
AnnaBridge 162:dbaafcfe0e9d 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
AnnaBridge 162:dbaafcfe0e9d 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
AnnaBridge 162:dbaafcfe0e9d 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
AnnaBridge 162:dbaafcfe0e9d 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
AnnaBridge 162:dbaafcfe0e9d 1141 /*********************** Bit definition for RNG_RN ***********************/
AnnaBridge 162:dbaafcfe0e9d 1142 //ToDo
AnnaBridge 162:dbaafcfe0e9d 1143
AnnaBridge 162:dbaafcfe0e9d 1144 /*********************** Bit definition for RNG_POLY ***********************/
AnnaBridge 162:dbaafcfe0e9d 1145 //ToDo
AnnaBridge 162:dbaafcfe0e9d 1146
AnnaBridge 162:dbaafcfe0e9d 1147
AnnaBridge 162:dbaafcfe0e9d 1148
AnnaBridge 162:dbaafcfe0e9d 1149 typedef enum
AnnaBridge 162:dbaafcfe0e9d 1150 {
AnnaBridge 162:dbaafcfe0e9d 1151 PAD_PA = 0,
AnnaBridge 162:dbaafcfe0e9d 1152 PAD_PB,
AnnaBridge 162:dbaafcfe0e9d 1153 PAD_PC,
AnnaBridge 162:dbaafcfe0e9d 1154 PAD_PD
AnnaBridge 162:dbaafcfe0e9d 1155 }PAD_Type;
AnnaBridge 162:dbaafcfe0e9d 1156
AnnaBridge 162:dbaafcfe0e9d 1157 typedef enum
AnnaBridge 162:dbaafcfe0e9d 1158 {
AnnaBridge 162:dbaafcfe0e9d 1159 PAD_AF0 = Px_AFSR_AF0,
AnnaBridge 162:dbaafcfe0e9d 1160 PAD_AF1 = Px_AFSR_AF1,
AnnaBridge 162:dbaafcfe0e9d 1161 PAD_AF2 = Px_AFSR_AF2,
AnnaBridge 162:dbaafcfe0e9d 1162 PAD_AF3 = Px_AFSR_AF3
AnnaBridge 162:dbaafcfe0e9d 1163 }PAD_AF_TypeDef;
AnnaBridge 162:dbaafcfe0e9d 1164
AnnaBridge 162:dbaafcfe0e9d 1165
AnnaBridge 162:dbaafcfe0e9d 1166 #if !defined (USE_HAL_DRIVER)
AnnaBridge 162:dbaafcfe0e9d 1167 #define USE_HAL_DRIVER
AnnaBridge 162:dbaafcfe0e9d 1168 #endif /* USE_HAL_DRIVER */
AnnaBridge 162:dbaafcfe0e9d 1169
AnnaBridge 162:dbaafcfe0e9d 1170
AnnaBridge 162:dbaafcfe0e9d 1171
AnnaBridge 162:dbaafcfe0e9d 1172 #if defined (USE_HAL_DRIVER)
AnnaBridge 162:dbaafcfe0e9d 1173 // #include "system_W7500x.h"
AnnaBridge 162:dbaafcfe0e9d 1174 // #include "W7500x_conf.h"
AnnaBridge 162:dbaafcfe0e9d 1175 #endif
AnnaBridge 162:dbaafcfe0e9d 1176
AnnaBridge 162:dbaafcfe0e9d 1177 #ifdef USE_FULL_ASSERT
AnnaBridge 162:dbaafcfe0e9d 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
AnnaBridge 162:dbaafcfe0e9d 1179 #else
AnnaBridge 162:dbaafcfe0e9d 1180 #define assert_param(expr) ((void)0)
AnnaBridge 162:dbaafcfe0e9d 1181 #endif /* USE_FULL_ASSERT */
AnnaBridge 162:dbaafcfe0e9d 1182
AnnaBridge 162:dbaafcfe0e9d 1183 #ifdef __cplusplus
AnnaBridge 162:dbaafcfe0e9d 1184 }
AnnaBridge 162:dbaafcfe0e9d 1185 #endif
AnnaBridge 162:dbaafcfe0e9d 1186
AnnaBridge 162:dbaafcfe0e9d 1187 #endif /* W7500x_H */
AnnaBridge 162:dbaafcfe0e9d 1188
AnnaBridge 162:dbaafcfe0e9d 1189
AnnaBridge 162:dbaafcfe0e9d 1190
AnnaBridge 162:dbaafcfe0e9d 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/