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TARGET_UBRIDGE/TOOLCHAIN_IAR/fsl_clock.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_UBRIDGE/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_clock.h@145:64910690c574
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 145:64910690c574 | 1 | /* |
AnnaBridge | 145:64910690c574 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
AnnaBridge | 145:64910690c574 | 3 | * All rights reserved. |
AnnaBridge | 145:64910690c574 | 4 | * |
AnnaBridge | 145:64910690c574 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 6 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 7 | * |
AnnaBridge | 145:64910690c574 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 145:64910690c574 | 9 | * of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 145:64910690c574 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 145:64910690c574 | 13 | * other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 14 | * |
AnnaBridge | 145:64910690c574 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 145:64910690c574 | 16 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 145:64910690c574 | 17 | * software without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 18 | * |
AnnaBridge | 145:64910690c574 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 145:64910690c574 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 145:64910690c574 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 145:64910690c574 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 145:64910690c574 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 145:64910690c574 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 145:64910690c574 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 145:64910690c574 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 145:64910690c574 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 29 | */ |
AnnaBridge | 145:64910690c574 | 30 | |
AnnaBridge | 145:64910690c574 | 31 | #ifndef _FSL_CLOCK_H_ |
AnnaBridge | 145:64910690c574 | 32 | #define _FSL_CLOCK_H_ |
AnnaBridge | 145:64910690c574 | 33 | |
AnnaBridge | 145:64910690c574 | 34 | #include "fsl_common.h" |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /*! @addtogroup clock */ |
AnnaBridge | 145:64910690c574 | 37 | /*! @{ */ |
AnnaBridge | 145:64910690c574 | 38 | |
AnnaBridge | 145:64910690c574 | 39 | /*! @file */ |
AnnaBridge | 145:64910690c574 | 40 | |
AnnaBridge | 145:64910690c574 | 41 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 42 | * Definitions |
AnnaBridge | 145:64910690c574 | 43 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 44 | |
AnnaBridge | 145:64910690c574 | 45 | /*! @brief Configure whether driver controls clock |
AnnaBridge | 145:64910690c574 | 46 | * |
AnnaBridge | 145:64910690c574 | 47 | * When set to 0, peripheral drivers will enable clock in initialize function |
AnnaBridge | 145:64910690c574 | 48 | * and disable clock in de-initialize function. When set to 1, peripheral |
AnnaBridge | 145:64910690c574 | 49 | * driver will not control the clock, application could contol the clock out of |
AnnaBridge | 145:64910690c574 | 50 | * the driver. |
AnnaBridge | 145:64910690c574 | 51 | * |
AnnaBridge | 145:64910690c574 | 52 | * @note All drivers share this feature switcher. If it is set to 1, application |
AnnaBridge | 145:64910690c574 | 53 | * should handle clock enable and disable for all drivers. |
AnnaBridge | 145:64910690c574 | 54 | */ |
AnnaBridge | 145:64910690c574 | 55 | #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) |
AnnaBridge | 145:64910690c574 | 56 | #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
AnnaBridge | 145:64910690c574 | 57 | #endif |
AnnaBridge | 145:64910690c574 | 58 | |
AnnaBridge | 145:64910690c574 | 59 | /*! @name Driver version */ |
AnnaBridge | 145:64910690c574 | 60 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 61 | /*! @brief CLOCK driver version 2.2.0. */ |
AnnaBridge | 145:64910690c574 | 62 | #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) |
AnnaBridge | 145:64910690c574 | 63 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 64 | |
AnnaBridge | 145:64910690c574 | 65 | /*! @brief External XTAL0 (OSC0) clock frequency. |
AnnaBridge | 145:64910690c574 | 66 | * |
AnnaBridge | 145:64910690c574 | 67 | * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the |
AnnaBridge | 145:64910690c574 | 68 | * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, |
AnnaBridge | 145:64910690c574 | 69 | * if XTAL0 is 8 MHz: |
AnnaBridge | 145:64910690c574 | 70 | * @code |
AnnaBridge | 145:64910690c574 | 71 | * CLOCK_InitOsc0(...); // Set up the OSC0 |
AnnaBridge | 145:64910690c574 | 72 | * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver. |
AnnaBridge | 145:64910690c574 | 73 | * @endcode |
AnnaBridge | 145:64910690c574 | 74 | * |
AnnaBridge | 145:64910690c574 | 75 | * This is important for the multicore platforms where only one core needs to set up the |
AnnaBridge | 145:64910690c574 | 76 | * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq |
AnnaBridge | 145:64910690c574 | 77 | * to get a valid clock frequency. |
AnnaBridge | 145:64910690c574 | 78 | */ |
AnnaBridge | 145:64910690c574 | 79 | extern uint32_t g_xtal0Freq; |
AnnaBridge | 145:64910690c574 | 80 | |
AnnaBridge | 145:64910690c574 | 81 | /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. |
AnnaBridge | 145:64910690c574 | 82 | * |
AnnaBridge | 145:64910690c574 | 83 | * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the |
AnnaBridge | 145:64910690c574 | 84 | * function CLOCK_SetXtal32Freq to set the value in the clock driver. |
AnnaBridge | 145:64910690c574 | 85 | * |
AnnaBridge | 145:64910690c574 | 86 | * This is important for the multicore platforms where only one core needs to set up |
AnnaBridge | 145:64910690c574 | 87 | * the clock. All other cores need to call the CLOCK_SetXtal32Freq |
AnnaBridge | 145:64910690c574 | 88 | * to get a valid clock frequency. |
AnnaBridge | 145:64910690c574 | 89 | */ |
AnnaBridge | 145:64910690c574 | 90 | extern uint32_t g_xtal32Freq; |
AnnaBridge | 145:64910690c574 | 91 | |
AnnaBridge | 145:64910690c574 | 92 | /*! @brief IRC48M clock frequency in Hz. */ |
AnnaBridge | 145:64910690c574 | 93 | #define MCG_INTERNAL_IRC_48M 48000000U |
AnnaBridge | 145:64910690c574 | 94 | |
AnnaBridge | 145:64910690c574 | 95 | #if (defined(OSC) && !(defined(OSC0))) |
AnnaBridge | 145:64910690c574 | 96 | #define OSC0 OSC |
AnnaBridge | 145:64910690c574 | 97 | #endif |
AnnaBridge | 145:64910690c574 | 98 | |
AnnaBridge | 145:64910690c574 | 99 | /*! @brief Clock ip name array for DMAMUX. */ |
AnnaBridge | 145:64910690c574 | 100 | #define DMAMUX_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 101 | { \ |
AnnaBridge | 145:64910690c574 | 102 | kCLOCK_Dmamux0 \ |
AnnaBridge | 145:64910690c574 | 103 | } |
AnnaBridge | 145:64910690c574 | 104 | |
AnnaBridge | 145:64910690c574 | 105 | /*! @brief Clock ip name array for RTC. */ |
AnnaBridge | 145:64910690c574 | 106 | #define RTC_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 107 | { \ |
AnnaBridge | 145:64910690c574 | 108 | kCLOCK_Rtc0 \ |
AnnaBridge | 145:64910690c574 | 109 | } |
AnnaBridge | 145:64910690c574 | 110 | |
AnnaBridge | 145:64910690c574 | 111 | /*! @brief Clock ip name array for SAI. */ |
AnnaBridge | 145:64910690c574 | 112 | #define SAI_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 113 | { \ |
AnnaBridge | 145:64910690c574 | 114 | kCLOCK_Sai0 \ |
AnnaBridge | 145:64910690c574 | 115 | } |
AnnaBridge | 145:64910690c574 | 116 | |
AnnaBridge | 145:64910690c574 | 117 | /*! @brief Clock ip name array for PORT. */ |
AnnaBridge | 145:64910690c574 | 118 | #define PORT_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 119 | { \ |
AnnaBridge | 145:64910690c574 | 120 | kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ |
AnnaBridge | 145:64910690c574 | 121 | } |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | /*! @brief Clock ip name array for FLEXBUS. */ |
AnnaBridge | 145:64910690c574 | 124 | #define FLEXBUS_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 125 | { \ |
AnnaBridge | 145:64910690c574 | 126 | kCLOCK_Flexbus0 \ |
AnnaBridge | 145:64910690c574 | 127 | } |
AnnaBridge | 145:64910690c574 | 128 | |
AnnaBridge | 145:64910690c574 | 129 | /*! @brief Clock ip name array for EWM. */ |
AnnaBridge | 145:64910690c574 | 130 | #define EWM_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 131 | { \ |
AnnaBridge | 145:64910690c574 | 132 | kCLOCK_Ewm0 \ |
AnnaBridge | 145:64910690c574 | 133 | } |
AnnaBridge | 145:64910690c574 | 134 | |
AnnaBridge | 145:64910690c574 | 135 | /*! @brief Clock ip name array for PIT. */ |
AnnaBridge | 145:64910690c574 | 136 | #define PIT_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 137 | { \ |
AnnaBridge | 145:64910690c574 | 138 | kCLOCK_Pit0 \ |
AnnaBridge | 145:64910690c574 | 139 | } |
AnnaBridge | 145:64910690c574 | 140 | |
AnnaBridge | 145:64910690c574 | 141 | /*! @brief Clock ip name array for DSPI. */ |
AnnaBridge | 145:64910690c574 | 142 | #define DSPI_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 143 | { \ |
AnnaBridge | 145:64910690c574 | 144 | kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \ |
AnnaBridge | 145:64910690c574 | 145 | } |
AnnaBridge | 145:64910690c574 | 146 | |
AnnaBridge | 145:64910690c574 | 147 | /*! @brief Clock ip name array for EMVSIM. */ |
AnnaBridge | 145:64910690c574 | 148 | #define EMVSIM_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 149 | { \ |
AnnaBridge | 145:64910690c574 | 150 | kCLOCK_Emvsim0, kCLOCK_Emvsim1 \ |
AnnaBridge | 145:64910690c574 | 151 | } |
AnnaBridge | 145:64910690c574 | 152 | |
AnnaBridge | 145:64910690c574 | 153 | /*! @brief Clock ip name array for QSPI. */ |
AnnaBridge | 145:64910690c574 | 154 | #define QSPI_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 155 | { \ |
AnnaBridge | 145:64910690c574 | 156 | kCLOCK_Qspi0 \ |
AnnaBridge | 145:64910690c574 | 157 | } |
AnnaBridge | 145:64910690c574 | 158 | |
AnnaBridge | 145:64910690c574 | 159 | /*! @brief Clock ip name array for SDHC. */ |
AnnaBridge | 145:64910690c574 | 160 | #define SDHC_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 161 | { \ |
AnnaBridge | 145:64910690c574 | 162 | kCLOCK_Sdhc0 \ |
AnnaBridge | 145:64910690c574 | 163 | } |
AnnaBridge | 145:64910690c574 | 164 | |
AnnaBridge | 145:64910690c574 | 165 | /*! @brief Clock ip name array for FTM. */ |
AnnaBridge | 145:64910690c574 | 166 | #define FTM_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 167 | { \ |
AnnaBridge | 145:64910690c574 | 168 | kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ |
AnnaBridge | 145:64910690c574 | 169 | } |
AnnaBridge | 145:64910690c574 | 170 | |
AnnaBridge | 145:64910690c574 | 171 | /*! @brief Clock ip name array for EDMA. */ |
AnnaBridge | 145:64910690c574 | 172 | #define EDMA_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 173 | { \ |
AnnaBridge | 145:64910690c574 | 174 | kCLOCK_Dma0 \ |
AnnaBridge | 145:64910690c574 | 175 | } |
AnnaBridge | 145:64910690c574 | 176 | |
AnnaBridge | 145:64910690c574 | 177 | /*! @brief Clock ip name array for LPUART. */ |
AnnaBridge | 145:64910690c574 | 178 | #define LPUART_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 179 | { \ |
AnnaBridge | 145:64910690c574 | 180 | kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \ |
AnnaBridge | 145:64910690c574 | 181 | } |
AnnaBridge | 145:64910690c574 | 182 | |
AnnaBridge | 145:64910690c574 | 183 | /*! @brief Clock ip name array for DAC. */ |
AnnaBridge | 145:64910690c574 | 184 | #define DAC_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 185 | { \ |
AnnaBridge | 145:64910690c574 | 186 | kCLOCK_Dac0 \ |
AnnaBridge | 145:64910690c574 | 187 | } |
AnnaBridge | 145:64910690c574 | 188 | |
AnnaBridge | 145:64910690c574 | 189 | /*! @brief Clock ip name array for LPTMR. */ |
AnnaBridge | 145:64910690c574 | 190 | #define LPTMR_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 191 | { \ |
AnnaBridge | 145:64910690c574 | 192 | kCLOCK_Lptmr0, kCLOCK_Lptmr1 \ |
AnnaBridge | 145:64910690c574 | 193 | } |
AnnaBridge | 145:64910690c574 | 194 | |
AnnaBridge | 145:64910690c574 | 195 | /*! @brief Clock ip name array for ADC16. */ |
AnnaBridge | 145:64910690c574 | 196 | #define ADC16_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 197 | { \ |
AnnaBridge | 145:64910690c574 | 198 | kCLOCK_Adc0 \ |
AnnaBridge | 145:64910690c574 | 199 | } |
AnnaBridge | 145:64910690c574 | 200 | |
AnnaBridge | 145:64910690c574 | 201 | /*! @brief Clock ip name array for SDRAM. */ |
AnnaBridge | 145:64910690c574 | 202 | #define SDRAM_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 203 | { \ |
AnnaBridge | 145:64910690c574 | 204 | kCLOCK_Sdramc0 \ |
AnnaBridge | 145:64910690c574 | 205 | } |
AnnaBridge | 145:64910690c574 | 206 | |
AnnaBridge | 145:64910690c574 | 207 | /*! @brief Clock ip name array for TRNG. */ |
AnnaBridge | 145:64910690c574 | 208 | #define TRNG_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 209 | { \ |
AnnaBridge | 145:64910690c574 | 210 | kCLOCK_Trng0 \ |
AnnaBridge | 145:64910690c574 | 211 | } |
AnnaBridge | 145:64910690c574 | 212 | |
AnnaBridge | 145:64910690c574 | 213 | /*! @brief Clock ip name array for MPU. */ |
AnnaBridge | 145:64910690c574 | 214 | #define MPU_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 215 | { \ |
AnnaBridge | 145:64910690c574 | 216 | kCLOCK_Mpu0 \ |
AnnaBridge | 145:64910690c574 | 217 | } |
AnnaBridge | 145:64910690c574 | 218 | |
AnnaBridge | 145:64910690c574 | 219 | /*! @brief Clock ip name array for FLEXIO. */ |
AnnaBridge | 145:64910690c574 | 220 | #define FLEXIO_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 221 | { \ |
AnnaBridge | 145:64910690c574 | 222 | kCLOCK_Flexio0 \ |
AnnaBridge | 145:64910690c574 | 223 | } |
AnnaBridge | 145:64910690c574 | 224 | |
AnnaBridge | 145:64910690c574 | 225 | /*! @brief Clock ip name array for VREF. */ |
AnnaBridge | 145:64910690c574 | 226 | #define VREF_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 227 | { \ |
AnnaBridge | 145:64910690c574 | 228 | kCLOCK_Vref0 \ |
AnnaBridge | 145:64910690c574 | 229 | } |
AnnaBridge | 145:64910690c574 | 230 | |
AnnaBridge | 145:64910690c574 | 231 | /*! @brief Clock ip name array for CMT. */ |
AnnaBridge | 145:64910690c574 | 232 | #define CMT_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 233 | { \ |
AnnaBridge | 145:64910690c574 | 234 | kCLOCK_Cmt0 \ |
AnnaBridge | 145:64910690c574 | 235 | } |
AnnaBridge | 145:64910690c574 | 236 | |
AnnaBridge | 145:64910690c574 | 237 | /*! @brief Clock ip name array for TPM. */ |
AnnaBridge | 145:64910690c574 | 238 | #define TPM_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 239 | { \ |
AnnaBridge | 145:64910690c574 | 240 | kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \ |
AnnaBridge | 145:64910690c574 | 241 | } |
AnnaBridge | 145:64910690c574 | 242 | |
AnnaBridge | 145:64910690c574 | 243 | /*! @brief Clock ip name array for TSI. */ |
AnnaBridge | 145:64910690c574 | 244 | #define TSI_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 245 | { \ |
AnnaBridge | 145:64910690c574 | 246 | kCLOCK_Tsi0 \ |
AnnaBridge | 145:64910690c574 | 247 | } |
AnnaBridge | 145:64910690c574 | 248 | |
AnnaBridge | 145:64910690c574 | 249 | /*! @brief Clock ip name array for LTC. */ |
AnnaBridge | 145:64910690c574 | 250 | #define LTC_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 251 | { \ |
AnnaBridge | 145:64910690c574 | 252 | kCLOCK_Ltc0 \ |
AnnaBridge | 145:64910690c574 | 253 | } |
AnnaBridge | 145:64910690c574 | 254 | |
AnnaBridge | 145:64910690c574 | 255 | /*! @brief Clock ip name array for CRC. */ |
AnnaBridge | 145:64910690c574 | 256 | #define CRC_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 257 | { \ |
AnnaBridge | 145:64910690c574 | 258 | kCLOCK_Crc0 \ |
AnnaBridge | 145:64910690c574 | 259 | } |
AnnaBridge | 145:64910690c574 | 260 | |
AnnaBridge | 145:64910690c574 | 261 | /*! @brief Clock ip name array for I2C. */ |
AnnaBridge | 145:64910690c574 | 262 | #define I2C_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 263 | { \ |
AnnaBridge | 145:64910690c574 | 264 | kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \ |
AnnaBridge | 145:64910690c574 | 265 | } |
AnnaBridge | 145:64910690c574 | 266 | |
AnnaBridge | 145:64910690c574 | 267 | /*! @brief Clock ip name array for PDB. */ |
AnnaBridge | 145:64910690c574 | 268 | #define PDB_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 269 | { \ |
AnnaBridge | 145:64910690c574 | 270 | kCLOCK_Pdb0 \ |
AnnaBridge | 145:64910690c574 | 271 | } |
AnnaBridge | 145:64910690c574 | 272 | |
AnnaBridge | 145:64910690c574 | 273 | /*! @brief Clock ip name array for FTF. */ |
AnnaBridge | 145:64910690c574 | 274 | #define FTF_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 275 | { \ |
AnnaBridge | 145:64910690c574 | 276 | kCLOCK_Ftf0 \ |
AnnaBridge | 145:64910690c574 | 277 | } |
AnnaBridge | 145:64910690c574 | 278 | |
AnnaBridge | 145:64910690c574 | 279 | /*! @brief Clock ip name array for CMP. */ |
AnnaBridge | 145:64910690c574 | 280 | #define CMP_CLOCKS \ |
AnnaBridge | 145:64910690c574 | 281 | { \ |
AnnaBridge | 145:64910690c574 | 282 | kCLOCK_Cmp0, kCLOCK_Cmp1 \ |
AnnaBridge | 145:64910690c574 | 283 | } |
AnnaBridge | 145:64910690c574 | 284 | |
AnnaBridge | 145:64910690c574 | 285 | /*! |
AnnaBridge | 145:64910690c574 | 286 | * @brief LPO clock frequency. |
AnnaBridge | 145:64910690c574 | 287 | */ |
AnnaBridge | 145:64910690c574 | 288 | #define LPO_CLK_FREQ 1000U |
AnnaBridge | 145:64910690c574 | 289 | |
AnnaBridge | 145:64910690c574 | 290 | /*! @brief Peripherals clock source definition. */ |
AnnaBridge | 145:64910690c574 | 291 | #define SYS_CLK kCLOCK_CoreSysClk |
AnnaBridge | 145:64910690c574 | 292 | #define BUS_CLK kCLOCK_BusClk |
AnnaBridge | 145:64910690c574 | 293 | |
AnnaBridge | 145:64910690c574 | 294 | #define I2C0_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 295 | #define I2C1_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 296 | #define I2C2_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 297 | #define I2C3_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 298 | #define DSPI0_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 299 | #define DSPI1_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 300 | #define DSPI2_CLK_SRC BUS_CLK |
AnnaBridge | 145:64910690c574 | 301 | |
AnnaBridge | 145:64910690c574 | 302 | /*! @brief Clock name used to get clock frequency. */ |
AnnaBridge | 145:64910690c574 | 303 | typedef enum _clock_name |
AnnaBridge | 145:64910690c574 | 304 | { |
AnnaBridge | 145:64910690c574 | 305 | |
AnnaBridge | 145:64910690c574 | 306 | /* ----------------------------- System layer clock -------------------------------*/ |
AnnaBridge | 145:64910690c574 | 307 | kCLOCK_CoreSysClk, /*!< Core/system clock */ |
AnnaBridge | 145:64910690c574 | 308 | kCLOCK_PlatClk, /*!< Platform clock */ |
AnnaBridge | 145:64910690c574 | 309 | kCLOCK_BusClk, /*!< Bus clock */ |
AnnaBridge | 145:64910690c574 | 310 | kCLOCK_FlexBusClk, /*!< FlexBus clock */ |
AnnaBridge | 145:64910690c574 | 311 | kCLOCK_FlashClk, /*!< Flash clock */ |
AnnaBridge | 145:64910690c574 | 312 | kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ |
AnnaBridge | 145:64910690c574 | 313 | kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ |
AnnaBridge | 145:64910690c574 | 314 | |
AnnaBridge | 145:64910690c574 | 315 | /* ---------------------------------- OSC clock -----------------------------------*/ |
AnnaBridge | 145:64910690c574 | 316 | kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ |
AnnaBridge | 145:64910690c574 | 317 | kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ |
AnnaBridge | 145:64910690c574 | 318 | kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ |
AnnaBridge | 145:64910690c574 | 319 | kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ |
AnnaBridge | 145:64910690c574 | 320 | |
AnnaBridge | 145:64910690c574 | 321 | /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ |
AnnaBridge | 145:64910690c574 | 322 | kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ |
AnnaBridge | 145:64910690c574 | 323 | kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ |
AnnaBridge | 145:64910690c574 | 324 | kCLOCK_McgFllClk, /*!< MCGFLLCLK */ |
AnnaBridge | 145:64910690c574 | 325 | kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ |
AnnaBridge | 145:64910690c574 | 326 | kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ |
AnnaBridge | 145:64910690c574 | 327 | kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ |
AnnaBridge | 145:64910690c574 | 328 | kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ |
AnnaBridge | 145:64910690c574 | 329 | kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ |
AnnaBridge | 145:64910690c574 | 330 | |
AnnaBridge | 145:64910690c574 | 331 | /* --------------------------------- Other clock ----------------------------------*/ |
AnnaBridge | 145:64910690c574 | 332 | kCLOCK_LpoClk, /*!< LPO clock */ |
AnnaBridge | 145:64910690c574 | 333 | |
AnnaBridge | 145:64910690c574 | 334 | } clock_name_t; |
AnnaBridge | 145:64910690c574 | 335 | |
AnnaBridge | 145:64910690c574 | 336 | /*! @brief USB clock source definition. */ |
AnnaBridge | 145:64910690c574 | 337 | typedef enum _clock_usb_src |
AnnaBridge | 145:64910690c574 | 338 | { |
AnnaBridge | 145:64910690c574 | 339 | kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ |
AnnaBridge | 145:64910690c574 | 340 | kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ |
AnnaBridge | 145:64910690c574 | 341 | kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ |
AnnaBridge | 145:64910690c574 | 342 | } clock_usb_src_t; |
AnnaBridge | 145:64910690c574 | 343 | /*------------------------------------------------------------------------------ |
AnnaBridge | 145:64910690c574 | 344 | |
AnnaBridge | 145:64910690c574 | 345 | clock_gate_t definition: |
AnnaBridge | 145:64910690c574 | 346 | |
AnnaBridge | 145:64910690c574 | 347 | 31 16 0 |
AnnaBridge | 145:64910690c574 | 348 | ----------------------------------------------------------------- |
AnnaBridge | 145:64910690c574 | 349 | | SIM_SCGC register offset | control bit offset in SCGC | |
AnnaBridge | 145:64910690c574 | 350 | ----------------------------------------------------------------- |
AnnaBridge | 145:64910690c574 | 351 | |
AnnaBridge | 145:64910690c574 | 352 | For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the |
AnnaBridge | 145:64910690c574 | 353 | SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as |
AnnaBridge | 145:64910690c574 | 354 | |
AnnaBridge | 145:64910690c574 | 355 | kClockGateSdhc0 = (0x1030 << 16) | 17; |
AnnaBridge | 145:64910690c574 | 356 | |
AnnaBridge | 145:64910690c574 | 357 | ------------------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 358 | |
AnnaBridge | 145:64910690c574 | 359 | #define CLK_GATE_REG_OFFSET_SHIFT 16U |
AnnaBridge | 145:64910690c574 | 360 | #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U |
AnnaBridge | 145:64910690c574 | 361 | #define CLK_GATE_BIT_SHIFT_SHIFT 0U |
AnnaBridge | 145:64910690c574 | 362 | #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU |
AnnaBridge | 145:64910690c574 | 363 | |
AnnaBridge | 145:64910690c574 | 364 | #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ |
AnnaBridge | 145:64910690c574 | 365 | ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ |
AnnaBridge | 145:64910690c574 | 366 | (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) |
AnnaBridge | 145:64910690c574 | 367 | |
AnnaBridge | 145:64910690c574 | 368 | #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) |
AnnaBridge | 145:64910690c574 | 369 | #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) |
AnnaBridge | 145:64910690c574 | 370 | |
AnnaBridge | 145:64910690c574 | 371 | /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ |
AnnaBridge | 145:64910690c574 | 372 | typedef enum _clock_ip_name |
AnnaBridge | 145:64910690c574 | 373 | { |
AnnaBridge | 145:64910690c574 | 374 | kCLOCK_IpInvalid = 0U, |
AnnaBridge | 145:64910690c574 | 375 | kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U), |
AnnaBridge | 145:64910690c574 | 376 | kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U), |
AnnaBridge | 145:64910690c574 | 377 | |
AnnaBridge | 145:64910690c574 | 378 | kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U), |
AnnaBridge | 145:64910690c574 | 379 | kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x102CU, 5U), |
AnnaBridge | 145:64910690c574 | 380 | kCLOCK_Lpuart2 = CLK_GATE_DEFINE(0x102CU, 6U), |
AnnaBridge | 145:64910690c574 | 381 | kCLOCK_Lpuart3 = CLK_GATE_DEFINE(0x102CU, 7U), |
AnnaBridge | 145:64910690c574 | 382 | kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U), |
AnnaBridge | 145:64910690c574 | 383 | kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U), |
AnnaBridge | 145:64910690c574 | 384 | kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U), |
AnnaBridge | 145:64910690c574 | 385 | kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x102CU, 17U), |
AnnaBridge | 145:64910690c574 | 386 | kCLOCK_Emvsim0 = CLK_GATE_DEFINE(0x102CU, 20U), |
AnnaBridge | 145:64910690c574 | 387 | kCLOCK_Emvsim1 = CLK_GATE_DEFINE(0x102CU, 21U), |
AnnaBridge | 145:64910690c574 | 388 | kCLOCK_Lpuart4 = CLK_GATE_DEFINE(0x102CU, 22U), |
AnnaBridge | 145:64910690c574 | 389 | kCLOCK_Qspi0 = CLK_GATE_DEFINE(0x102CU, 26U), |
AnnaBridge | 145:64910690c574 | 390 | kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x102CU, 31U), |
AnnaBridge | 145:64910690c574 | 391 | |
AnnaBridge | 145:64910690c574 | 392 | kCLOCK_Trng0 = CLK_GATE_DEFINE(0x1030U, 0U), |
AnnaBridge | 145:64910690c574 | 393 | kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U), |
AnnaBridge | 145:64910690c574 | 394 | kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U), |
AnnaBridge | 145:64910690c574 | 395 | kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U), |
AnnaBridge | 145:64910690c574 | 396 | |
AnnaBridge | 145:64910690c574 | 397 | kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), |
AnnaBridge | 145:64910690c574 | 398 | kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), |
AnnaBridge | 145:64910690c574 | 399 | kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), |
AnnaBridge | 145:64910690c574 | 400 | kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), |
AnnaBridge | 145:64910690c574 | 401 | kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), |
AnnaBridge | 145:64910690c574 | 402 | kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), |
AnnaBridge | 145:64910690c574 | 403 | kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), |
AnnaBridge | 145:64910690c574 | 404 | kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), |
AnnaBridge | 145:64910690c574 | 405 | |
AnnaBridge | 145:64910690c574 | 406 | kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), |
AnnaBridge | 145:64910690c574 | 407 | kCLOCK_Lptmr1 = CLK_GATE_DEFINE(0x1038U, 4U), |
AnnaBridge | 145:64910690c574 | 408 | kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U), |
AnnaBridge | 145:64910690c574 | 409 | kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), |
AnnaBridge | 145:64910690c574 | 410 | kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), |
AnnaBridge | 145:64910690c574 | 411 | kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), |
AnnaBridge | 145:64910690c574 | 412 | kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), |
AnnaBridge | 145:64910690c574 | 413 | kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), |
AnnaBridge | 145:64910690c574 | 414 | |
AnnaBridge | 145:64910690c574 | 415 | kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), |
AnnaBridge | 145:64910690c574 | 416 | kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), |
AnnaBridge | 145:64910690c574 | 417 | kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), |
AnnaBridge | 145:64910690c574 | 418 | kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), |
AnnaBridge | 145:64910690c574 | 419 | kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), |
AnnaBridge | 145:64910690c574 | 420 | kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), |
AnnaBridge | 145:64910690c574 | 421 | kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), |
AnnaBridge | 145:64910690c574 | 422 | kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), |
AnnaBridge | 145:64910690c574 | 423 | kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), |
AnnaBridge | 145:64910690c574 | 424 | kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), |
AnnaBridge | 145:64910690c574 | 425 | kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), |
AnnaBridge | 145:64910690c574 | 426 | kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), |
AnnaBridge | 145:64910690c574 | 427 | kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), |
AnnaBridge | 145:64910690c574 | 428 | kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), |
AnnaBridge | 145:64910690c574 | 429 | |
AnnaBridge | 145:64910690c574 | 430 | kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), |
AnnaBridge | 145:64910690c574 | 431 | kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), |
AnnaBridge | 145:64910690c574 | 432 | kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U), |
AnnaBridge | 145:64910690c574 | 433 | kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U), |
AnnaBridge | 145:64910690c574 | 434 | } clock_ip_name_t; |
AnnaBridge | 145:64910690c574 | 435 | |
AnnaBridge | 145:64910690c574 | 436 | /*!@brief SIM configuration structure for clock setting. */ |
AnnaBridge | 145:64910690c574 | 437 | typedef struct _sim_clock_config |
AnnaBridge | 145:64910690c574 | 438 | { |
AnnaBridge | 145:64910690c574 | 439 | uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ |
AnnaBridge | 145:64910690c574 | 440 | uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */ |
AnnaBridge | 145:64910690c574 | 441 | uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */ |
AnnaBridge | 145:64910690c574 | 442 | uint8_t er32kSrc; /*!< ERCLK32K source selection. */ |
AnnaBridge | 145:64910690c574 | 443 | uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ |
AnnaBridge | 145:64910690c574 | 444 | } sim_clock_config_t; |
AnnaBridge | 145:64910690c574 | 445 | |
AnnaBridge | 145:64910690c574 | 446 | /*! @brief OSC work mode. */ |
AnnaBridge | 145:64910690c574 | 447 | typedef enum _osc_mode |
AnnaBridge | 145:64910690c574 | 448 | { |
AnnaBridge | 145:64910690c574 | 449 | kOSC_ModeExt = 0U, /*!< Use an external clock. */ |
AnnaBridge | 145:64910690c574 | 450 | #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) |
AnnaBridge | 145:64910690c574 | 451 | kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ |
AnnaBridge | 145:64910690c574 | 452 | #else |
AnnaBridge | 145:64910690c574 | 453 | kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ |
AnnaBridge | 145:64910690c574 | 454 | #endif |
AnnaBridge | 145:64910690c574 | 455 | kOSC_ModeOscHighGain = 0U |
AnnaBridge | 145:64910690c574 | 456 | #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) |
AnnaBridge | 145:64910690c574 | 457 | | |
AnnaBridge | 145:64910690c574 | 458 | MCG_C2_EREFS_MASK |
AnnaBridge | 145:64910690c574 | 459 | #else |
AnnaBridge | 145:64910690c574 | 460 | | |
AnnaBridge | 145:64910690c574 | 461 | MCG_C2_EREFS0_MASK |
AnnaBridge | 145:64910690c574 | 462 | #endif |
AnnaBridge | 145:64910690c574 | 463 | #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) |
AnnaBridge | 145:64910690c574 | 464 | | |
AnnaBridge | 145:64910690c574 | 465 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ |
AnnaBridge | 145:64910690c574 | 466 | #else |
AnnaBridge | 145:64910690c574 | 467 | | |
AnnaBridge | 145:64910690c574 | 468 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ |
AnnaBridge | 145:64910690c574 | 469 | #endif |
AnnaBridge | 145:64910690c574 | 470 | } osc_mode_t; |
AnnaBridge | 145:64910690c574 | 471 | |
AnnaBridge | 145:64910690c574 | 472 | /*! @brief Oscillator capacitor load setting.*/ |
AnnaBridge | 145:64910690c574 | 473 | enum _osc_cap_load |
AnnaBridge | 145:64910690c574 | 474 | { |
AnnaBridge | 145:64910690c574 | 475 | kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ |
AnnaBridge | 145:64910690c574 | 476 | kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ |
AnnaBridge | 145:64910690c574 | 477 | kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ |
AnnaBridge | 145:64910690c574 | 478 | kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ |
AnnaBridge | 145:64910690c574 | 479 | }; |
AnnaBridge | 145:64910690c574 | 480 | |
AnnaBridge | 145:64910690c574 | 481 | /*! @brief OSCERCLK enable mode. */ |
AnnaBridge | 145:64910690c574 | 482 | enum _oscer_enable_mode |
AnnaBridge | 145:64910690c574 | 483 | { |
AnnaBridge | 145:64910690c574 | 484 | kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ |
AnnaBridge | 145:64910690c574 | 485 | kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ |
AnnaBridge | 145:64910690c574 | 486 | }; |
AnnaBridge | 145:64910690c574 | 487 | |
AnnaBridge | 145:64910690c574 | 488 | /*! @brief OSC configuration for OSCERCLK. */ |
AnnaBridge | 145:64910690c574 | 489 | typedef struct _oscer_config |
AnnaBridge | 145:64910690c574 | 490 | { |
AnnaBridge | 145:64910690c574 | 491 | uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ |
AnnaBridge | 145:64910690c574 | 492 | |
AnnaBridge | 145:64910690c574 | 493 | uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/ |
AnnaBridge | 145:64910690c574 | 494 | } oscer_config_t; |
AnnaBridge | 145:64910690c574 | 495 | |
AnnaBridge | 145:64910690c574 | 496 | /*! |
AnnaBridge | 145:64910690c574 | 497 | * @brief OSC Initialization Configuration Structure |
AnnaBridge | 145:64910690c574 | 498 | * |
AnnaBridge | 145:64910690c574 | 499 | * Defines the configuration data structure to initialize the OSC. |
AnnaBridge | 145:64910690c574 | 500 | * When porting to a new board, set the following members |
AnnaBridge | 145:64910690c574 | 501 | * according to the board setting: |
AnnaBridge | 145:64910690c574 | 502 | * 1. freq: The external frequency. |
AnnaBridge | 145:64910690c574 | 503 | * 2. workMode: The OSC module mode. |
AnnaBridge | 145:64910690c574 | 504 | */ |
AnnaBridge | 145:64910690c574 | 505 | typedef struct _osc_config |
AnnaBridge | 145:64910690c574 | 506 | { |
AnnaBridge | 145:64910690c574 | 507 | uint32_t freq; /*!< External clock frequency. */ |
AnnaBridge | 145:64910690c574 | 508 | uint8_t capLoad; /*!< Capacitor load setting. */ |
AnnaBridge | 145:64910690c574 | 509 | osc_mode_t workMode; /*!< OSC work mode setting. */ |
AnnaBridge | 145:64910690c574 | 510 | oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ |
AnnaBridge | 145:64910690c574 | 511 | } osc_config_t; |
AnnaBridge | 145:64910690c574 | 512 | |
AnnaBridge | 145:64910690c574 | 513 | /*! @brief MCG FLL reference clock source select. */ |
AnnaBridge | 145:64910690c574 | 514 | typedef enum _mcg_fll_src |
AnnaBridge | 145:64910690c574 | 515 | { |
AnnaBridge | 145:64910690c574 | 516 | kMCG_FllSrcExternal, /*!< External reference clock is selected */ |
AnnaBridge | 145:64910690c574 | 517 | kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ |
AnnaBridge | 145:64910690c574 | 518 | } mcg_fll_src_t; |
AnnaBridge | 145:64910690c574 | 519 | |
AnnaBridge | 145:64910690c574 | 520 | /*! @brief MCG internal reference clock select */ |
AnnaBridge | 145:64910690c574 | 521 | typedef enum _mcg_irc_mode |
AnnaBridge | 145:64910690c574 | 522 | { |
AnnaBridge | 145:64910690c574 | 523 | kMCG_IrcSlow, /*!< Slow internal reference clock selected */ |
AnnaBridge | 145:64910690c574 | 524 | kMCG_IrcFast /*!< Fast internal reference clock selected */ |
AnnaBridge | 145:64910690c574 | 525 | } mcg_irc_mode_t; |
AnnaBridge | 145:64910690c574 | 526 | |
AnnaBridge | 145:64910690c574 | 527 | /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ |
AnnaBridge | 145:64910690c574 | 528 | typedef enum _mcg_dmx32 |
AnnaBridge | 145:64910690c574 | 529 | { |
AnnaBridge | 145:64910690c574 | 530 | kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ |
AnnaBridge | 145:64910690c574 | 531 | kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ |
AnnaBridge | 145:64910690c574 | 532 | } mcg_dmx32_t; |
AnnaBridge | 145:64910690c574 | 533 | |
AnnaBridge | 145:64910690c574 | 534 | /*! @brief MCG DCO range select */ |
AnnaBridge | 145:64910690c574 | 535 | typedef enum _mcg_drs |
AnnaBridge | 145:64910690c574 | 536 | { |
AnnaBridge | 145:64910690c574 | 537 | kMCG_DrsLow, /*!< Low frequency range */ |
AnnaBridge | 145:64910690c574 | 538 | kMCG_DrsMid, /*!< Mid frequency range */ |
AnnaBridge | 145:64910690c574 | 539 | kMCG_DrsMidHigh, /*!< Mid-High frequency range */ |
AnnaBridge | 145:64910690c574 | 540 | kMCG_DrsHigh /*!< High frequency range */ |
AnnaBridge | 145:64910690c574 | 541 | } mcg_drs_t; |
AnnaBridge | 145:64910690c574 | 542 | |
AnnaBridge | 145:64910690c574 | 543 | /*! @brief MCG PLL reference clock select */ |
AnnaBridge | 145:64910690c574 | 544 | typedef enum _mcg_pll_ref_src |
AnnaBridge | 145:64910690c574 | 545 | { |
AnnaBridge | 145:64910690c574 | 546 | kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ |
AnnaBridge | 145:64910690c574 | 547 | kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ |
AnnaBridge | 145:64910690c574 | 548 | } mcg_pll_ref_src_t; |
AnnaBridge | 145:64910690c574 | 549 | |
AnnaBridge | 145:64910690c574 | 550 | /*! @brief MCGOUT clock source. */ |
AnnaBridge | 145:64910690c574 | 551 | typedef enum _mcg_clkout_src |
AnnaBridge | 145:64910690c574 | 552 | { |
AnnaBridge | 145:64910690c574 | 553 | kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ |
AnnaBridge | 145:64910690c574 | 554 | kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ |
AnnaBridge | 145:64910690c574 | 555 | kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ |
AnnaBridge | 145:64910690c574 | 556 | } mcg_clkout_src_t; |
AnnaBridge | 145:64910690c574 | 557 | |
AnnaBridge | 145:64910690c574 | 558 | /*! @brief MCG Automatic Trim Machine Select */ |
AnnaBridge | 145:64910690c574 | 559 | typedef enum _mcg_atm_select |
AnnaBridge | 145:64910690c574 | 560 | { |
AnnaBridge | 145:64910690c574 | 561 | kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ |
AnnaBridge | 145:64910690c574 | 562 | kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ |
AnnaBridge | 145:64910690c574 | 563 | } mcg_atm_select_t; |
AnnaBridge | 145:64910690c574 | 564 | |
AnnaBridge | 145:64910690c574 | 565 | /*! @brief MCG OSC Clock Select */ |
AnnaBridge | 145:64910690c574 | 566 | typedef enum _mcg_oscsel |
AnnaBridge | 145:64910690c574 | 567 | { |
AnnaBridge | 145:64910690c574 | 568 | kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ |
AnnaBridge | 145:64910690c574 | 569 | kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ |
AnnaBridge | 145:64910690c574 | 570 | kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ |
AnnaBridge | 145:64910690c574 | 571 | } mcg_oscsel_t; |
AnnaBridge | 145:64910690c574 | 572 | |
AnnaBridge | 145:64910690c574 | 573 | /*! @brief MCG PLLCS select */ |
AnnaBridge | 145:64910690c574 | 574 | typedef enum _mcg_pll_clk_select |
AnnaBridge | 145:64910690c574 | 575 | { |
AnnaBridge | 145:64910690c574 | 576 | kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ |
AnnaBridge | 145:64910690c574 | 577 | kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ |
AnnaBridge | 145:64910690c574 | 578 | } mcg_pll_clk_select_t; |
AnnaBridge | 145:64910690c574 | 579 | |
AnnaBridge | 145:64910690c574 | 580 | /*! @brief MCG clock monitor mode. */ |
AnnaBridge | 145:64910690c574 | 581 | typedef enum _mcg_monitor_mode |
AnnaBridge | 145:64910690c574 | 582 | { |
AnnaBridge | 145:64910690c574 | 583 | kMCG_MonitorNone, /*!< Clock monitor is disabled. */ |
AnnaBridge | 145:64910690c574 | 584 | kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ |
AnnaBridge | 145:64910690c574 | 585 | kMCG_MonitorReset /*!< System reset when clock lost. */ |
AnnaBridge | 145:64910690c574 | 586 | } mcg_monitor_mode_t; |
AnnaBridge | 145:64910690c574 | 587 | |
AnnaBridge | 145:64910690c574 | 588 | /*! @brief MCG status. */ |
AnnaBridge | 145:64910690c574 | 589 | enum _mcg_status |
AnnaBridge | 145:64910690c574 | 590 | { |
AnnaBridge | 145:64910690c574 | 591 | kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ |
AnnaBridge | 145:64910690c574 | 592 | kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific |
AnnaBridge | 145:64910690c574 | 593 | function. */ |
AnnaBridge | 145:64910690c574 | 594 | kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ |
AnnaBridge | 145:64910690c574 | 595 | kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ |
AnnaBridge | 145:64910690c574 | 596 | kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ |
AnnaBridge | 145:64910690c574 | 597 | kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ |
AnnaBridge | 145:64910690c574 | 598 | kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because |
AnnaBridge | 145:64910690c574 | 599 | it is in use. */ |
AnnaBridge | 145:64910690c574 | 600 | }; |
AnnaBridge | 145:64910690c574 | 601 | |
AnnaBridge | 145:64910690c574 | 602 | /*! @brief MCG status flags. */ |
AnnaBridge | 145:64910690c574 | 603 | enum _mcg_status_flags_t |
AnnaBridge | 145:64910690c574 | 604 | { |
AnnaBridge | 145:64910690c574 | 605 | kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ |
AnnaBridge | 145:64910690c574 | 606 | kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ |
AnnaBridge | 145:64910690c574 | 607 | kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ |
AnnaBridge | 145:64910690c574 | 608 | kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ |
AnnaBridge | 145:64910690c574 | 609 | kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ |
AnnaBridge | 145:64910690c574 | 610 | }; |
AnnaBridge | 145:64910690c574 | 611 | |
AnnaBridge | 145:64910690c574 | 612 | /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ |
AnnaBridge | 145:64910690c574 | 613 | enum _mcg_irclk_enable_mode |
AnnaBridge | 145:64910690c574 | 614 | { |
AnnaBridge | 145:64910690c574 | 615 | kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ |
AnnaBridge | 145:64910690c574 | 616 | kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ |
AnnaBridge | 145:64910690c574 | 617 | }; |
AnnaBridge | 145:64910690c574 | 618 | |
AnnaBridge | 145:64910690c574 | 619 | /*! @brief MCG PLL clock enable mode definition. */ |
AnnaBridge | 145:64910690c574 | 620 | enum _mcg_pll_enable_mode |
AnnaBridge | 145:64910690c574 | 621 | { |
AnnaBridge | 145:64910690c574 | 622 | kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the |
AnnaBridge | 145:64910690c574 | 623 | MCG clock mode. Generally, the PLL |
AnnaBridge | 145:64910690c574 | 624 | is disabled in FLL modes |
AnnaBridge | 145:64910690c574 | 625 | (FEI/FBI/FEE/FBE). Setting the PLL clock |
AnnaBridge | 145:64910690c574 | 626 | enable independent, enables the |
AnnaBridge | 145:64910690c574 | 627 | PLL in the FLL modes. */ |
AnnaBridge | 145:64910690c574 | 628 | kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ |
AnnaBridge | 145:64910690c574 | 629 | }; |
AnnaBridge | 145:64910690c574 | 630 | |
AnnaBridge | 145:64910690c574 | 631 | /*! @brief MCG mode definitions */ |
AnnaBridge | 145:64910690c574 | 632 | typedef enum _mcg_mode |
AnnaBridge | 145:64910690c574 | 633 | { |
AnnaBridge | 145:64910690c574 | 634 | kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ |
AnnaBridge | 145:64910690c574 | 635 | kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ |
AnnaBridge | 145:64910690c574 | 636 | kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ |
AnnaBridge | 145:64910690c574 | 637 | kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ |
AnnaBridge | 145:64910690c574 | 638 | kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ |
AnnaBridge | 145:64910690c574 | 639 | kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ |
AnnaBridge | 145:64910690c574 | 640 | kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ |
AnnaBridge | 145:64910690c574 | 641 | kMCG_ModePEE, /*!< PEE - PLL Engaged External */ |
AnnaBridge | 145:64910690c574 | 642 | kMCG_ModeError /*!< Unknown mode */ |
AnnaBridge | 145:64910690c574 | 643 | } mcg_mode_t; |
AnnaBridge | 145:64910690c574 | 644 | |
AnnaBridge | 145:64910690c574 | 645 | /*! @brief MCG PLL configuration. */ |
AnnaBridge | 145:64910690c574 | 646 | typedef struct _mcg_pll_config |
AnnaBridge | 145:64910690c574 | 647 | { |
AnnaBridge | 145:64910690c574 | 648 | uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ |
AnnaBridge | 145:64910690c574 | 649 | uint8_t prdiv; /*!< Reference divider PRDIV. */ |
AnnaBridge | 145:64910690c574 | 650 | uint8_t vdiv; /*!< VCO divider VDIV. */ |
AnnaBridge | 145:64910690c574 | 651 | } mcg_pll_config_t; |
AnnaBridge | 145:64910690c574 | 652 | |
AnnaBridge | 145:64910690c574 | 653 | /*! @brief MCG mode change configuration structure |
AnnaBridge | 145:64910690c574 | 654 | * |
AnnaBridge | 145:64910690c574 | 655 | * When porting to a new board, set the following members |
AnnaBridge | 145:64910690c574 | 656 | * according to the board setting: |
AnnaBridge | 145:64910690c574 | 657 | * 1. frdiv: If the FLL uses the external reference clock, set this |
AnnaBridge | 145:64910690c574 | 658 | * value to ensure that the external reference clock divided by frdiv is |
AnnaBridge | 145:64910690c574 | 659 | * in the 31.25 kHz to 39.0625 kHz range. |
AnnaBridge | 145:64910690c574 | 660 | * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after |
AnnaBridge | 145:64910690c574 | 661 | * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to |
AnnaBridge | 145:64910690c574 | 662 | * FSL_FEATURE_MCG_PLL_REF_MAX range. |
AnnaBridge | 145:64910690c574 | 663 | */ |
AnnaBridge | 145:64910690c574 | 664 | typedef struct _mcg_config |
AnnaBridge | 145:64910690c574 | 665 | { |
AnnaBridge | 145:64910690c574 | 666 | mcg_mode_t mcgMode; /*!< MCG mode. */ |
AnnaBridge | 145:64910690c574 | 667 | |
AnnaBridge | 145:64910690c574 | 668 | /* ----------------------- MCGIRCCLK settings ------------------------ */ |
AnnaBridge | 145:64910690c574 | 669 | uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ |
AnnaBridge | 145:64910690c574 | 670 | mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ |
AnnaBridge | 145:64910690c574 | 671 | uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ |
AnnaBridge | 145:64910690c574 | 672 | |
AnnaBridge | 145:64910690c574 | 673 | /* ------------------------ MCG FLL settings ------------------------- */ |
AnnaBridge | 145:64910690c574 | 674 | uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ |
AnnaBridge | 145:64910690c574 | 675 | mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ |
AnnaBridge | 145:64910690c574 | 676 | mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ |
AnnaBridge | 145:64910690c574 | 677 | mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ |
AnnaBridge | 145:64910690c574 | 678 | |
AnnaBridge | 145:64910690c574 | 679 | /* ------------------------ MCG PLL settings ------------------------- */ |
AnnaBridge | 145:64910690c574 | 680 | mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ |
AnnaBridge | 145:64910690c574 | 681 | |
AnnaBridge | 145:64910690c574 | 682 | } mcg_config_t; |
AnnaBridge | 145:64910690c574 | 683 | |
AnnaBridge | 145:64910690c574 | 684 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 685 | * API |
AnnaBridge | 145:64910690c574 | 686 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 687 | |
AnnaBridge | 145:64910690c574 | 688 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 689 | extern "C" { |
AnnaBridge | 145:64910690c574 | 690 | #endif /* __cplusplus */ |
AnnaBridge | 145:64910690c574 | 691 | |
AnnaBridge | 145:64910690c574 | 692 | /*! |
AnnaBridge | 145:64910690c574 | 693 | * @brief Enable the clock for specific IP. |
AnnaBridge | 145:64910690c574 | 694 | * |
AnnaBridge | 145:64910690c574 | 695 | * @param name Which clock to enable, see \ref clock_ip_name_t. |
AnnaBridge | 145:64910690c574 | 696 | */ |
AnnaBridge | 145:64910690c574 | 697 | static inline void CLOCK_EnableClock(clock_ip_name_t name) |
AnnaBridge | 145:64910690c574 | 698 | { |
AnnaBridge | 145:64910690c574 | 699 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
AnnaBridge | 145:64910690c574 | 700 | (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
AnnaBridge | 145:64910690c574 | 701 | } |
AnnaBridge | 145:64910690c574 | 702 | |
AnnaBridge | 145:64910690c574 | 703 | /*! |
AnnaBridge | 145:64910690c574 | 704 | * @brief Disable the clock for specific IP. |
AnnaBridge | 145:64910690c574 | 705 | * |
AnnaBridge | 145:64910690c574 | 706 | * @param name Which clock to disable, see \ref clock_ip_name_t. |
AnnaBridge | 145:64910690c574 | 707 | */ |
AnnaBridge | 145:64910690c574 | 708 | static inline void CLOCK_DisableClock(clock_ip_name_t name) |
AnnaBridge | 145:64910690c574 | 709 | { |
AnnaBridge | 145:64910690c574 | 710 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
AnnaBridge | 145:64910690c574 | 711 | (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
AnnaBridge | 145:64910690c574 | 712 | } |
AnnaBridge | 145:64910690c574 | 713 | |
AnnaBridge | 145:64910690c574 | 714 | /*! |
AnnaBridge | 145:64910690c574 | 715 | * @brief Set ERCLK32K source. |
AnnaBridge | 145:64910690c574 | 716 | * |
AnnaBridge | 145:64910690c574 | 717 | * @param src The value to set ERCLK32K clock source. |
AnnaBridge | 145:64910690c574 | 718 | */ |
AnnaBridge | 145:64910690c574 | 719 | static inline void CLOCK_SetEr32kClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 720 | { |
AnnaBridge | 145:64910690c574 | 721 | SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); |
AnnaBridge | 145:64910690c574 | 722 | } |
AnnaBridge | 145:64910690c574 | 723 | |
AnnaBridge | 145:64910690c574 | 724 | /*! |
AnnaBridge | 145:64910690c574 | 725 | * @brief Set SDHC0 clock source. |
AnnaBridge | 145:64910690c574 | 726 | * |
AnnaBridge | 145:64910690c574 | 727 | * @param src The value to set SDHC0 clock source. |
AnnaBridge | 145:64910690c574 | 728 | */ |
AnnaBridge | 145:64910690c574 | 729 | static inline void CLOCK_SetSdhc0Clock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 730 | { |
AnnaBridge | 145:64910690c574 | 731 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); |
AnnaBridge | 145:64910690c574 | 732 | } |
AnnaBridge | 145:64910690c574 | 733 | |
AnnaBridge | 145:64910690c574 | 734 | /*! |
AnnaBridge | 145:64910690c574 | 735 | * @brief Set EMVSIM clock source. |
AnnaBridge | 145:64910690c574 | 736 | * |
AnnaBridge | 145:64910690c574 | 737 | * @param src The value to set EMVSIM clock source. |
AnnaBridge | 145:64910690c574 | 738 | */ |
AnnaBridge | 145:64910690c574 | 739 | static inline void CLOCK_SetEmvsimClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 740 | { |
AnnaBridge | 145:64910690c574 | 741 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_EMVSIMSRC_MASK) | SIM_SOPT2_EMVSIMSRC(src)); |
AnnaBridge | 145:64910690c574 | 742 | } |
AnnaBridge | 145:64910690c574 | 743 | |
AnnaBridge | 145:64910690c574 | 744 | /*! |
AnnaBridge | 145:64910690c574 | 745 | * @brief Set LPUART clock source. |
AnnaBridge | 145:64910690c574 | 746 | * |
AnnaBridge | 145:64910690c574 | 747 | * @param src The value to set LPUART clock source. |
AnnaBridge | 145:64910690c574 | 748 | */ |
AnnaBridge | 145:64910690c574 | 749 | static inline void CLOCK_SetLpuartClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 750 | { |
AnnaBridge | 145:64910690c574 | 751 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src)); |
AnnaBridge | 145:64910690c574 | 752 | } |
AnnaBridge | 145:64910690c574 | 753 | |
AnnaBridge | 145:64910690c574 | 754 | /*! |
AnnaBridge | 145:64910690c574 | 755 | * @brief Set TPM clock source. |
AnnaBridge | 145:64910690c574 | 756 | * |
AnnaBridge | 145:64910690c574 | 757 | * @param src The value to set TPM clock source. |
AnnaBridge | 145:64910690c574 | 758 | */ |
AnnaBridge | 145:64910690c574 | 759 | static inline void CLOCK_SetTpmClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 760 | { |
AnnaBridge | 145:64910690c574 | 761 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); |
AnnaBridge | 145:64910690c574 | 762 | } |
AnnaBridge | 145:64910690c574 | 763 | |
AnnaBridge | 145:64910690c574 | 764 | /*! |
AnnaBridge | 145:64910690c574 | 765 | * @brief Set FLEXIO clock source. |
AnnaBridge | 145:64910690c574 | 766 | * |
AnnaBridge | 145:64910690c574 | 767 | * @param src The value to set FLEXIO clock source. |
AnnaBridge | 145:64910690c574 | 768 | */ |
AnnaBridge | 145:64910690c574 | 769 | static inline void CLOCK_SetFlexio0Clock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 770 | { |
AnnaBridge | 145:64910690c574 | 771 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src)); |
AnnaBridge | 145:64910690c574 | 772 | } |
AnnaBridge | 145:64910690c574 | 773 | |
AnnaBridge | 145:64910690c574 | 774 | /*! |
AnnaBridge | 145:64910690c574 | 775 | * @brief Set debug trace clock source. |
AnnaBridge | 145:64910690c574 | 776 | * |
AnnaBridge | 145:64910690c574 | 777 | * @param src The value to set debug trace clock source. |
AnnaBridge | 145:64910690c574 | 778 | */ |
AnnaBridge | 145:64910690c574 | 779 | static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue) |
AnnaBridge | 145:64910690c574 | 780 | { |
AnnaBridge | 145:64910690c574 | 781 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); |
AnnaBridge | 145:64910690c574 | 782 | SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue); |
AnnaBridge | 145:64910690c574 | 783 | } |
AnnaBridge | 145:64910690c574 | 784 | |
AnnaBridge | 145:64910690c574 | 785 | /*! |
AnnaBridge | 145:64910690c574 | 786 | * @brief Set PLLFLLSEL clock source. |
AnnaBridge | 145:64910690c574 | 787 | * |
AnnaBridge | 145:64910690c574 | 788 | * @param src The value to set PLLFLLSEL clock source. |
AnnaBridge | 145:64910690c574 | 789 | */ |
AnnaBridge | 145:64910690c574 | 790 | static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue) |
AnnaBridge | 145:64910690c574 | 791 | { |
AnnaBridge | 145:64910690c574 | 792 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); |
AnnaBridge | 145:64910690c574 | 793 | SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue); |
AnnaBridge | 145:64910690c574 | 794 | } |
AnnaBridge | 145:64910690c574 | 795 | |
AnnaBridge | 145:64910690c574 | 796 | /*! |
AnnaBridge | 145:64910690c574 | 797 | * @brief Set CLKOUT source. |
AnnaBridge | 145:64910690c574 | 798 | * |
AnnaBridge | 145:64910690c574 | 799 | * @param src The value to set CLKOUT source. |
AnnaBridge | 145:64910690c574 | 800 | */ |
AnnaBridge | 145:64910690c574 | 801 | static inline void CLOCK_SetClkOutClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 802 | { |
AnnaBridge | 145:64910690c574 | 803 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); |
AnnaBridge | 145:64910690c574 | 804 | } |
AnnaBridge | 145:64910690c574 | 805 | |
AnnaBridge | 145:64910690c574 | 806 | /*! |
AnnaBridge | 145:64910690c574 | 807 | * @brief Set RTC_CLKOUT source. |
AnnaBridge | 145:64910690c574 | 808 | * |
AnnaBridge | 145:64910690c574 | 809 | * @param src The value to set RTC_CLKOUT source. |
AnnaBridge | 145:64910690c574 | 810 | */ |
AnnaBridge | 145:64910690c574 | 811 | static inline void CLOCK_SetRtcClkOutClock(uint32_t src) |
AnnaBridge | 145:64910690c574 | 812 | { |
AnnaBridge | 145:64910690c574 | 813 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); |
AnnaBridge | 145:64910690c574 | 814 | } |
AnnaBridge | 145:64910690c574 | 815 | |
AnnaBridge | 145:64910690c574 | 816 | /*! @brief Enable USB FS clock. |
AnnaBridge | 145:64910690c574 | 817 | * |
AnnaBridge | 145:64910690c574 | 818 | * @param src USB FS clock source. |
AnnaBridge | 145:64910690c574 | 819 | * @param freq The frequency specified by src. |
AnnaBridge | 145:64910690c574 | 820 | * @retval true The clock is set successfully. |
AnnaBridge | 145:64910690c574 | 821 | * @retval false The clock source is invalid to get proper USB FS clock. |
AnnaBridge | 145:64910690c574 | 822 | */ |
AnnaBridge | 145:64910690c574 | 823 | bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); |
AnnaBridge | 145:64910690c574 | 824 | |
AnnaBridge | 145:64910690c574 | 825 | /*! @brief Disable USB FS clock. |
AnnaBridge | 145:64910690c574 | 826 | * |
AnnaBridge | 145:64910690c574 | 827 | * Disable USB FS clock. |
AnnaBridge | 145:64910690c574 | 828 | */ |
AnnaBridge | 145:64910690c574 | 829 | static inline void CLOCK_DisableUsbfs0Clock(void) |
AnnaBridge | 145:64910690c574 | 830 | { |
AnnaBridge | 145:64910690c574 | 831 | CLOCK_DisableClock(kCLOCK_Usbfs0); |
AnnaBridge | 145:64910690c574 | 832 | } |
AnnaBridge | 145:64910690c574 | 833 | |
AnnaBridge | 145:64910690c574 | 834 | /*! |
AnnaBridge | 145:64910690c574 | 835 | * @brief System clock divider |
AnnaBridge | 145:64910690c574 | 836 | * |
AnnaBridge | 145:64910690c574 | 837 | * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. |
AnnaBridge | 145:64910690c574 | 838 | * |
AnnaBridge | 145:64910690c574 | 839 | * @param outdiv1 Clock 1 output divider value. |
AnnaBridge | 145:64910690c574 | 840 | * |
AnnaBridge | 145:64910690c574 | 841 | * @param outdiv2 Clock 2 output divider value. |
AnnaBridge | 145:64910690c574 | 842 | * |
AnnaBridge | 145:64910690c574 | 843 | * @param outdiv3 Clock 3 output divider value. |
AnnaBridge | 145:64910690c574 | 844 | * |
AnnaBridge | 145:64910690c574 | 845 | * @param outdiv4 Clock 4 output divider value. |
AnnaBridge | 145:64910690c574 | 846 | */ |
AnnaBridge | 145:64910690c574 | 847 | static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) |
AnnaBridge | 145:64910690c574 | 848 | { |
AnnaBridge | 145:64910690c574 | 849 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | |
AnnaBridge | 145:64910690c574 | 850 | SIM_CLKDIV1_OUTDIV4(outdiv4); |
AnnaBridge | 145:64910690c574 | 851 | } |
AnnaBridge | 145:64910690c574 | 852 | |
AnnaBridge | 145:64910690c574 | 853 | /*! |
AnnaBridge | 145:64910690c574 | 854 | * @brief Gets the clock frequency for a specific clock name. |
AnnaBridge | 145:64910690c574 | 855 | * |
AnnaBridge | 145:64910690c574 | 856 | * This function checks the current clock configurations and then calculates |
AnnaBridge | 145:64910690c574 | 857 | * the clock frequency for a specific clock name defined in clock_name_t. |
AnnaBridge | 145:64910690c574 | 858 | * The MCG must be properly configured before using this function. |
AnnaBridge | 145:64910690c574 | 859 | * |
AnnaBridge | 145:64910690c574 | 860 | * @param clockName Clock names defined in clock_name_t |
AnnaBridge | 145:64910690c574 | 861 | * @return Clock frequency value in Hertz |
AnnaBridge | 145:64910690c574 | 862 | */ |
AnnaBridge | 145:64910690c574 | 863 | uint32_t CLOCK_GetFreq(clock_name_t clockName); |
AnnaBridge | 145:64910690c574 | 864 | |
AnnaBridge | 145:64910690c574 | 865 | /*! |
AnnaBridge | 145:64910690c574 | 866 | * @brief Get the core clock or system clock frequency. |
AnnaBridge | 145:64910690c574 | 867 | * |
AnnaBridge | 145:64910690c574 | 868 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 869 | */ |
AnnaBridge | 145:64910690c574 | 870 | uint32_t CLOCK_GetCoreSysClkFreq(void); |
AnnaBridge | 145:64910690c574 | 871 | |
AnnaBridge | 145:64910690c574 | 872 | /*! |
AnnaBridge | 145:64910690c574 | 873 | * @brief Get the platform clock frequency. |
AnnaBridge | 145:64910690c574 | 874 | * |
AnnaBridge | 145:64910690c574 | 875 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 876 | */ |
AnnaBridge | 145:64910690c574 | 877 | uint32_t CLOCK_GetPlatClkFreq(void); |
AnnaBridge | 145:64910690c574 | 878 | |
AnnaBridge | 145:64910690c574 | 879 | /*! |
AnnaBridge | 145:64910690c574 | 880 | * @brief Get the bus clock frequency. |
AnnaBridge | 145:64910690c574 | 881 | * |
AnnaBridge | 145:64910690c574 | 882 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 883 | */ |
AnnaBridge | 145:64910690c574 | 884 | uint32_t CLOCK_GetBusClkFreq(void); |
AnnaBridge | 145:64910690c574 | 885 | |
AnnaBridge | 145:64910690c574 | 886 | /*! |
AnnaBridge | 145:64910690c574 | 887 | * @brief Get the flexbus clock frequency. |
AnnaBridge | 145:64910690c574 | 888 | * |
AnnaBridge | 145:64910690c574 | 889 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 890 | */ |
AnnaBridge | 145:64910690c574 | 891 | uint32_t CLOCK_GetFlexBusClkFreq(void); |
AnnaBridge | 145:64910690c574 | 892 | |
AnnaBridge | 145:64910690c574 | 893 | /*! |
AnnaBridge | 145:64910690c574 | 894 | * @brief Get the flash clock frequency. |
AnnaBridge | 145:64910690c574 | 895 | * |
AnnaBridge | 145:64910690c574 | 896 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 897 | */ |
AnnaBridge | 145:64910690c574 | 898 | uint32_t CLOCK_GetFlashClkFreq(void); |
AnnaBridge | 145:64910690c574 | 899 | |
AnnaBridge | 145:64910690c574 | 900 | /*! |
AnnaBridge | 145:64910690c574 | 901 | * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. |
AnnaBridge | 145:64910690c574 | 902 | * |
AnnaBridge | 145:64910690c574 | 903 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 904 | */ |
AnnaBridge | 145:64910690c574 | 905 | uint32_t CLOCK_GetPllFllSelClkFreq(void); |
AnnaBridge | 145:64910690c574 | 906 | |
AnnaBridge | 145:64910690c574 | 907 | /*! |
AnnaBridge | 145:64910690c574 | 908 | * @brief Get the external reference 32K clock frequency (ERCLK32K). |
AnnaBridge | 145:64910690c574 | 909 | * |
AnnaBridge | 145:64910690c574 | 910 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 911 | */ |
AnnaBridge | 145:64910690c574 | 912 | uint32_t CLOCK_GetEr32kClkFreq(void); |
AnnaBridge | 145:64910690c574 | 913 | |
AnnaBridge | 145:64910690c574 | 914 | /*! |
AnnaBridge | 145:64910690c574 | 915 | * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). |
AnnaBridge | 145:64910690c574 | 916 | * |
AnnaBridge | 145:64910690c574 | 917 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 918 | */ |
AnnaBridge | 145:64910690c574 | 919 | uint32_t CLOCK_GetOsc0ErClkUndivFreq(void); |
AnnaBridge | 145:64910690c574 | 920 | |
AnnaBridge | 145:64910690c574 | 921 | /*! |
AnnaBridge | 145:64910690c574 | 922 | * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). |
AnnaBridge | 145:64910690c574 | 923 | * |
AnnaBridge | 145:64910690c574 | 924 | * @return Clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 925 | */ |
AnnaBridge | 145:64910690c574 | 926 | uint32_t CLOCK_GetOsc0ErClkFreq(void); |
AnnaBridge | 145:64910690c574 | 927 | |
AnnaBridge | 145:64910690c574 | 928 | /*! |
AnnaBridge | 145:64910690c574 | 929 | * @brief Set the clock configure in SIM module. |
AnnaBridge | 145:64910690c574 | 930 | * |
AnnaBridge | 145:64910690c574 | 931 | * This function sets system layer clock settings in SIM module. |
AnnaBridge | 145:64910690c574 | 932 | * |
AnnaBridge | 145:64910690c574 | 933 | * @param config Pointer to the configure structure. |
AnnaBridge | 145:64910690c574 | 934 | */ |
AnnaBridge | 145:64910690c574 | 935 | void CLOCK_SetSimConfig(sim_clock_config_t const *config); |
AnnaBridge | 145:64910690c574 | 936 | |
AnnaBridge | 145:64910690c574 | 937 | /*! |
AnnaBridge | 145:64910690c574 | 938 | * @brief Set the system clock dividers in SIM to safe value. |
AnnaBridge | 145:64910690c574 | 939 | * |
AnnaBridge | 145:64910690c574 | 940 | * The system level clocks (core clock, bus clock, flexbus clock and flash clock) |
AnnaBridge | 145:64910690c574 | 941 | * must be in allowed ranges. During MCG clock mode switch, the MCG output clock |
AnnaBridge | 145:64910690c574 | 942 | * changes then the system level clocks may be out of range. This function could |
AnnaBridge | 145:64910690c574 | 943 | * be used before MCG mode change, to make sure system level clocks are in allowed |
AnnaBridge | 145:64910690c574 | 944 | * range. |
AnnaBridge | 145:64910690c574 | 945 | * |
AnnaBridge | 145:64910690c574 | 946 | * @param config Pointer to the configure structure. |
AnnaBridge | 145:64910690c574 | 947 | */ |
AnnaBridge | 145:64910690c574 | 948 | static inline void CLOCK_SetSimSafeDivs(void) |
AnnaBridge | 145:64910690c574 | 949 | { |
AnnaBridge | 145:64910690c574 | 950 | SIM->CLKDIV1 = 0x01140000U; |
AnnaBridge | 145:64910690c574 | 951 | } |
AnnaBridge | 145:64910690c574 | 952 | |
AnnaBridge | 145:64910690c574 | 953 | /*! @name MCG frequency functions. */ |
AnnaBridge | 145:64910690c574 | 954 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 955 | |
AnnaBridge | 145:64910690c574 | 956 | /*! |
AnnaBridge | 145:64910690c574 | 957 | * @brief Gets the MCG output clock (MCGOUTCLK) frequency. |
AnnaBridge | 145:64910690c574 | 958 | * |
AnnaBridge | 145:64910690c574 | 959 | * This function gets the MCG output clock frequency in Hz based on the current MCG |
AnnaBridge | 145:64910690c574 | 960 | * register value. |
AnnaBridge | 145:64910690c574 | 961 | * |
AnnaBridge | 145:64910690c574 | 962 | * @return The frequency of MCGOUTCLK. |
AnnaBridge | 145:64910690c574 | 963 | */ |
AnnaBridge | 145:64910690c574 | 964 | uint32_t CLOCK_GetOutClkFreq(void); |
AnnaBridge | 145:64910690c574 | 965 | |
AnnaBridge | 145:64910690c574 | 966 | /*! |
AnnaBridge | 145:64910690c574 | 967 | * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency. |
AnnaBridge | 145:64910690c574 | 968 | * |
AnnaBridge | 145:64910690c574 | 969 | * This function gets the MCG FLL clock frequency in Hz based on the current MCG |
AnnaBridge | 145:64910690c574 | 970 | * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and |
AnnaBridge | 145:64910690c574 | 971 | * disabled in low power state in other modes. |
AnnaBridge | 145:64910690c574 | 972 | * |
AnnaBridge | 145:64910690c574 | 973 | * @return The frequency of MCGFLLCLK. |
AnnaBridge | 145:64910690c574 | 974 | */ |
AnnaBridge | 145:64910690c574 | 975 | uint32_t CLOCK_GetFllFreq(void); |
AnnaBridge | 145:64910690c574 | 976 | |
AnnaBridge | 145:64910690c574 | 977 | /*! |
AnnaBridge | 145:64910690c574 | 978 | * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. |
AnnaBridge | 145:64910690c574 | 979 | * |
AnnaBridge | 145:64910690c574 | 980 | * This function gets the MCG internal reference clock frequency in Hz based |
AnnaBridge | 145:64910690c574 | 981 | * on the current MCG register value. |
AnnaBridge | 145:64910690c574 | 982 | * |
AnnaBridge | 145:64910690c574 | 983 | * @return The frequency of MCGIRCLK. |
AnnaBridge | 145:64910690c574 | 984 | */ |
AnnaBridge | 145:64910690c574 | 985 | uint32_t CLOCK_GetInternalRefClkFreq(void); |
AnnaBridge | 145:64910690c574 | 986 | |
AnnaBridge | 145:64910690c574 | 987 | /*! |
AnnaBridge | 145:64910690c574 | 988 | * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. |
AnnaBridge | 145:64910690c574 | 989 | * |
AnnaBridge | 145:64910690c574 | 990 | * This function gets the MCG fixed frequency clock frequency in Hz based |
AnnaBridge | 145:64910690c574 | 991 | * on the current MCG register value. |
AnnaBridge | 145:64910690c574 | 992 | * |
AnnaBridge | 145:64910690c574 | 993 | * @return The frequency of MCGFFCLK. |
AnnaBridge | 145:64910690c574 | 994 | */ |
AnnaBridge | 145:64910690c574 | 995 | uint32_t CLOCK_GetFixedFreqClkFreq(void); |
AnnaBridge | 145:64910690c574 | 996 | |
AnnaBridge | 145:64910690c574 | 997 | /*! |
AnnaBridge | 145:64910690c574 | 998 | * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. |
AnnaBridge | 145:64910690c574 | 999 | * |
AnnaBridge | 145:64910690c574 | 1000 | * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG |
AnnaBridge | 145:64910690c574 | 1001 | * register value. |
AnnaBridge | 145:64910690c574 | 1002 | * |
AnnaBridge | 145:64910690c574 | 1003 | * @return The frequency of MCGPLL0CLK. |
AnnaBridge | 145:64910690c574 | 1004 | */ |
AnnaBridge | 145:64910690c574 | 1005 | uint32_t CLOCK_GetPll0Freq(void); |
AnnaBridge | 145:64910690c574 | 1006 | |
AnnaBridge | 145:64910690c574 | 1007 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 1008 | |
AnnaBridge | 145:64910690c574 | 1009 | /*! @name MCG clock configuration. */ |
AnnaBridge | 145:64910690c574 | 1010 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 1011 | |
AnnaBridge | 145:64910690c574 | 1012 | /*! |
AnnaBridge | 145:64910690c574 | 1013 | * @brief Enables or disables the MCG low power. |
AnnaBridge | 145:64910690c574 | 1014 | * |
AnnaBridge | 145:64910690c574 | 1015 | * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, |
AnnaBridge | 145:64910690c574 | 1016 | * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and |
AnnaBridge | 145:64910690c574 | 1017 | * PBI modes, enabling low power sets the MCG to BLPI mode. |
AnnaBridge | 145:64910690c574 | 1018 | * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings. |
AnnaBridge | 145:64910690c574 | 1019 | * |
AnnaBridge | 145:64910690c574 | 1020 | * @param enable True to enable MCG low power, false to disable MCG low power. |
AnnaBridge | 145:64910690c574 | 1021 | */ |
AnnaBridge | 145:64910690c574 | 1022 | static inline void CLOCK_SetLowPowerEnable(bool enable) |
AnnaBridge | 145:64910690c574 | 1023 | { |
AnnaBridge | 145:64910690c574 | 1024 | if (enable) |
AnnaBridge | 145:64910690c574 | 1025 | { |
AnnaBridge | 145:64910690c574 | 1026 | MCG->C2 |= MCG_C2_LP_MASK; |
AnnaBridge | 145:64910690c574 | 1027 | } |
AnnaBridge | 145:64910690c574 | 1028 | else |
AnnaBridge | 145:64910690c574 | 1029 | { |
AnnaBridge | 145:64910690c574 | 1030 | MCG->C2 &= ~MCG_C2_LP_MASK; |
AnnaBridge | 145:64910690c574 | 1031 | } |
AnnaBridge | 145:64910690c574 | 1032 | } |
AnnaBridge | 145:64910690c574 | 1033 | |
AnnaBridge | 145:64910690c574 | 1034 | /*! |
AnnaBridge | 145:64910690c574 | 1035 | * @brief Configures the Internal Reference clock (MCGIRCLK). |
AnnaBridge | 145:64910690c574 | 1036 | * |
AnnaBridge | 145:64910690c574 | 1037 | * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC |
AnnaBridge | 145:64910690c574 | 1038 | * source. If the fast IRC is used, this function sets the fast IRC divider. |
AnnaBridge | 145:64910690c574 | 1039 | * This function also sets whether the \c MCGIRCLK is enabled in stop mode. |
AnnaBridge | 145:64910690c574 | 1040 | * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, |
AnnaBridge | 145:64910690c574 | 1041 | * using the function in these modes it is not allowed. |
AnnaBridge | 145:64910690c574 | 1042 | * |
AnnaBridge | 145:64910690c574 | 1043 | * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. |
AnnaBridge | 145:64910690c574 | 1044 | * @param ircs MCGIRCLK clock source, choose fast or slow. |
AnnaBridge | 145:64910690c574 | 1045 | * @param fcrdiv Fast IRC divider setting (\c FCRDIV). |
AnnaBridge | 145:64910690c574 | 1046 | * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source, |
AnnaBridge | 145:64910690c574 | 1047 | * the confuration should not be changed. Otherwise, a glitch occurs. |
AnnaBridge | 145:64910690c574 | 1048 | * @retval kStatus_Success MCGIRCLK configuration finished successfully. |
AnnaBridge | 145:64910690c574 | 1049 | */ |
AnnaBridge | 145:64910690c574 | 1050 | status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); |
AnnaBridge | 145:64910690c574 | 1051 | |
AnnaBridge | 145:64910690c574 | 1052 | /*! |
AnnaBridge | 145:64910690c574 | 1053 | * @brief Selects the MCG external reference clock. |
AnnaBridge | 145:64910690c574 | 1054 | * |
AnnaBridge | 145:64910690c574 | 1055 | * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], |
AnnaBridge | 145:64910690c574 | 1056 | * and waits for the clock source to be stable. Because the external reference |
AnnaBridge | 145:64910690c574 | 1057 | * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. |
AnnaBridge | 145:64910690c574 | 1058 | * |
AnnaBridge | 145:64910690c574 | 1059 | * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. |
AnnaBridge | 145:64910690c574 | 1060 | * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, |
AnnaBridge | 145:64910690c574 | 1061 | * the confuration should not be changed. Otherwise, a glitch occurs. |
AnnaBridge | 145:64910690c574 | 1062 | * @retval kStatus_Success External reference clock set successfully. |
AnnaBridge | 145:64910690c574 | 1063 | */ |
AnnaBridge | 145:64910690c574 | 1064 | status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); |
AnnaBridge | 145:64910690c574 | 1065 | |
AnnaBridge | 145:64910690c574 | 1066 | /*! |
AnnaBridge | 145:64910690c574 | 1067 | * @brief Set the FLL external reference clock divider value. |
AnnaBridge | 145:64910690c574 | 1068 | * |
AnnaBridge | 145:64910690c574 | 1069 | * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV]. |
AnnaBridge | 145:64910690c574 | 1070 | * |
AnnaBridge | 145:64910690c574 | 1071 | * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV]. |
AnnaBridge | 145:64910690c574 | 1072 | */ |
AnnaBridge | 145:64910690c574 | 1073 | static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) |
AnnaBridge | 145:64910690c574 | 1074 | { |
AnnaBridge | 145:64910690c574 | 1075 | MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv); |
AnnaBridge | 145:64910690c574 | 1076 | } |
AnnaBridge | 145:64910690c574 | 1077 | |
AnnaBridge | 145:64910690c574 | 1078 | /*! |
AnnaBridge | 145:64910690c574 | 1079 | * @brief Enables the PLL0 in FLL mode. |
AnnaBridge | 145:64910690c574 | 1080 | * |
AnnaBridge | 145:64910690c574 | 1081 | * This function sets us the PLL0 in FLL mode and reconfigures |
AnnaBridge | 145:64910690c574 | 1082 | * the PLL0. Ensure that the PLL reference |
AnnaBridge | 145:64910690c574 | 1083 | * clock is enabled before calling this function and that the PLL0 is not used as a clock source. |
AnnaBridge | 145:64910690c574 | 1084 | * The function CLOCK_CalcPllDiv gets the correct PLL |
AnnaBridge | 145:64910690c574 | 1085 | * divider values. |
AnnaBridge | 145:64910690c574 | 1086 | * |
AnnaBridge | 145:64910690c574 | 1087 | * @param config Pointer to the configuration structure. |
AnnaBridge | 145:64910690c574 | 1088 | */ |
AnnaBridge | 145:64910690c574 | 1089 | void CLOCK_EnablePll0(mcg_pll_config_t const *config); |
AnnaBridge | 145:64910690c574 | 1090 | |
AnnaBridge | 145:64910690c574 | 1091 | /*! |
AnnaBridge | 145:64910690c574 | 1092 | * @brief Disables the PLL0 in FLL mode. |
AnnaBridge | 145:64910690c574 | 1093 | * |
AnnaBridge | 145:64910690c574 | 1094 | * This function disables the PLL0 in FLL mode. It should be used together with the |
AnnaBridge | 145:64910690c574 | 1095 | * @ref CLOCK_EnablePll0. |
AnnaBridge | 145:64910690c574 | 1096 | */ |
AnnaBridge | 145:64910690c574 | 1097 | static inline void CLOCK_DisablePll0(void) |
AnnaBridge | 145:64910690c574 | 1098 | { |
AnnaBridge | 145:64910690c574 | 1099 | MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); |
AnnaBridge | 145:64910690c574 | 1100 | } |
AnnaBridge | 145:64910690c574 | 1101 | |
AnnaBridge | 145:64910690c574 | 1102 | /*! |
AnnaBridge | 145:64910690c574 | 1103 | * @brief Calculates the PLL divider setting for a desired output frequency. |
AnnaBridge | 145:64910690c574 | 1104 | * |
AnnaBridge | 145:64910690c574 | 1105 | * This function calculates the correct reference clock divider (\c PRDIV) and |
AnnaBridge | 145:64910690c574 | 1106 | * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the |
AnnaBridge | 145:64910690c574 | 1107 | * closest frequency match with the corresponding \c PRDIV/VDIV |
AnnaBridge | 145:64910690c574 | 1108 | * returned from parameters. If a desired frequency is not valid, this function |
AnnaBridge | 145:64910690c574 | 1109 | * returns 0. |
AnnaBridge | 145:64910690c574 | 1110 | * |
AnnaBridge | 145:64910690c574 | 1111 | * @param refFreq PLL reference clock frequency. |
AnnaBridge | 145:64910690c574 | 1112 | * @param desireFreq Desired PLL output frequency. |
AnnaBridge | 145:64910690c574 | 1113 | * @param prdiv PRDIV value to generate desired PLL frequency. |
AnnaBridge | 145:64910690c574 | 1114 | * @param vdiv VDIV value to generate desired PLL frequency. |
AnnaBridge | 145:64910690c574 | 1115 | * @return Closest frequency match that the PLL was able generate. |
AnnaBridge | 145:64910690c574 | 1116 | */ |
AnnaBridge | 145:64910690c574 | 1117 | uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); |
AnnaBridge | 145:64910690c574 | 1118 | |
AnnaBridge | 145:64910690c574 | 1119 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 1120 | |
AnnaBridge | 145:64910690c574 | 1121 | /*! @name MCG clock lock monitor functions. */ |
AnnaBridge | 145:64910690c574 | 1122 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 1123 | |
AnnaBridge | 145:64910690c574 | 1124 | /*! |
AnnaBridge | 145:64910690c574 | 1125 | * @brief Sets the OSC0 clock monitor mode. |
AnnaBridge | 145:64910690c574 | 1126 | * |
AnnaBridge | 145:64910690c574 | 1127 | * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details. |
AnnaBridge | 145:64910690c574 | 1128 | * |
AnnaBridge | 145:64910690c574 | 1129 | * @param mode Monitor mode to set. |
AnnaBridge | 145:64910690c574 | 1130 | */ |
AnnaBridge | 145:64910690c574 | 1131 | void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); |
AnnaBridge | 145:64910690c574 | 1132 | |
AnnaBridge | 145:64910690c574 | 1133 | /*! |
AnnaBridge | 145:64910690c574 | 1134 | * @brief Sets the RTC OSC clock monitor mode. |
AnnaBridge | 145:64910690c574 | 1135 | * |
AnnaBridge | 145:64910690c574 | 1136 | * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details. |
AnnaBridge | 145:64910690c574 | 1137 | * |
AnnaBridge | 145:64910690c574 | 1138 | * @param mode Monitor mode to set. |
AnnaBridge | 145:64910690c574 | 1139 | */ |
AnnaBridge | 145:64910690c574 | 1140 | void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); |
AnnaBridge | 145:64910690c574 | 1141 | |
AnnaBridge | 145:64910690c574 | 1142 | /*! |
AnnaBridge | 145:64910690c574 | 1143 | * @brief Sets the PLL0 clock monitor mode. |
AnnaBridge | 145:64910690c574 | 1144 | * |
AnnaBridge | 145:64910690c574 | 1145 | * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details. |
AnnaBridge | 145:64910690c574 | 1146 | * |
AnnaBridge | 145:64910690c574 | 1147 | * @param mode Monitor mode to set. |
AnnaBridge | 145:64910690c574 | 1148 | */ |
AnnaBridge | 145:64910690c574 | 1149 | void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); |
AnnaBridge | 145:64910690c574 | 1150 | |
AnnaBridge | 145:64910690c574 | 1151 | /*! |
AnnaBridge | 145:64910690c574 | 1152 | * @brief Gets the MCG status flags. |
AnnaBridge | 145:64910690c574 | 1153 | * |
AnnaBridge | 145:64910690c574 | 1154 | * This function gets the MCG clock status flags. All status flags are |
AnnaBridge | 145:64910690c574 | 1155 | * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To |
AnnaBridge | 145:64910690c574 | 1156 | * check a specific flag, compare the return value with the flag. |
AnnaBridge | 145:64910690c574 | 1157 | * |
AnnaBridge | 145:64910690c574 | 1158 | * Example: |
AnnaBridge | 145:64910690c574 | 1159 | * @code |
AnnaBridge | 145:64910690c574 | 1160 | // To check the clock lost lock status of OSC0 and PLL0. |
AnnaBridge | 145:64910690c574 | 1161 | uint32_t mcgFlags; |
AnnaBridge | 145:64910690c574 | 1162 | |
AnnaBridge | 145:64910690c574 | 1163 | mcgFlags = CLOCK_GetStatusFlags(); |
AnnaBridge | 145:64910690c574 | 1164 | |
AnnaBridge | 145:64910690c574 | 1165 | if (mcgFlags & kMCG_Osc0LostFlag) |
AnnaBridge | 145:64910690c574 | 1166 | { |
AnnaBridge | 145:64910690c574 | 1167 | // OSC0 clock lock lost. Do something. |
AnnaBridge | 145:64910690c574 | 1168 | } |
AnnaBridge | 145:64910690c574 | 1169 | if (mcgFlags & kMCG_Pll0LostFlag) |
AnnaBridge | 145:64910690c574 | 1170 | { |
AnnaBridge | 145:64910690c574 | 1171 | // PLL0 clock lock lost. Do something. |
AnnaBridge | 145:64910690c574 | 1172 | } |
AnnaBridge | 145:64910690c574 | 1173 | @endcode |
AnnaBridge | 145:64910690c574 | 1174 | * |
AnnaBridge | 145:64910690c574 | 1175 | * @return Logical OR value of the @ref _mcg_status_flags_t. |
AnnaBridge | 145:64910690c574 | 1176 | */ |
AnnaBridge | 145:64910690c574 | 1177 | uint32_t CLOCK_GetStatusFlags(void); |
AnnaBridge | 145:64910690c574 | 1178 | |
AnnaBridge | 145:64910690c574 | 1179 | /*! |
AnnaBridge | 145:64910690c574 | 1180 | * @brief Clears the MCG status flags. |
AnnaBridge | 145:64910690c574 | 1181 | * |
AnnaBridge | 145:64910690c574 | 1182 | * This function clears the MCG clock lock lost status. The parameter is a logical |
AnnaBridge | 145:64910690c574 | 1183 | * OR value of the flags to clear. See @ref _mcg_status_flags_t. |
AnnaBridge | 145:64910690c574 | 1184 | * |
AnnaBridge | 145:64910690c574 | 1185 | * Example: |
AnnaBridge | 145:64910690c574 | 1186 | * @code |
AnnaBridge | 145:64910690c574 | 1187 | // To clear the clock lost lock status flags of OSC0 and PLL0. |
AnnaBridge | 145:64910690c574 | 1188 | |
AnnaBridge | 145:64910690c574 | 1189 | CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); |
AnnaBridge | 145:64910690c574 | 1190 | @endcode |
AnnaBridge | 145:64910690c574 | 1191 | * |
AnnaBridge | 145:64910690c574 | 1192 | * @param mask The status flags to clear. This is a logical OR of members of the |
AnnaBridge | 145:64910690c574 | 1193 | * enumeration @ref _mcg_status_flags_t. |
AnnaBridge | 145:64910690c574 | 1194 | */ |
AnnaBridge | 145:64910690c574 | 1195 | void CLOCK_ClearStatusFlags(uint32_t mask); |
AnnaBridge | 145:64910690c574 | 1196 | |
AnnaBridge | 145:64910690c574 | 1197 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 1198 | |
AnnaBridge | 145:64910690c574 | 1199 | /*! |
AnnaBridge | 145:64910690c574 | 1200 | * @name OSC configuration |
AnnaBridge | 145:64910690c574 | 1201 | * @{ |
AnnaBridge | 145:64910690c574 | 1202 | */ |
AnnaBridge | 145:64910690c574 | 1203 | |
AnnaBridge | 145:64910690c574 | 1204 | /*! |
AnnaBridge | 145:64910690c574 | 1205 | * @brief Configures the OSC external reference clock (OSCERCLK). |
AnnaBridge | 145:64910690c574 | 1206 | * |
AnnaBridge | 145:64910690c574 | 1207 | * This function configures the OSC external reference clock (OSCERCLK). |
AnnaBridge | 145:64910690c574 | 1208 | * This is an example to enable the OSCERCLK in normal and stop modes and also set |
AnnaBridge | 145:64910690c574 | 1209 | * the output divider to 1: |
AnnaBridge | 145:64910690c574 | 1210 | * |
AnnaBridge | 145:64910690c574 | 1211 | @code |
AnnaBridge | 145:64910690c574 | 1212 | oscer_config_t config = |
AnnaBridge | 145:64910690c574 | 1213 | { |
AnnaBridge | 145:64910690c574 | 1214 | .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, |
AnnaBridge | 145:64910690c574 | 1215 | .erclkDiv = 1U, |
AnnaBridge | 145:64910690c574 | 1216 | }; |
AnnaBridge | 145:64910690c574 | 1217 | |
AnnaBridge | 145:64910690c574 | 1218 | OSC_SetExtRefClkConfig(OSC, &config); |
AnnaBridge | 145:64910690c574 | 1219 | @endcode |
AnnaBridge | 145:64910690c574 | 1220 | * |
AnnaBridge | 145:64910690c574 | 1221 | * @param base OSC peripheral address. |
AnnaBridge | 145:64910690c574 | 1222 | * @param config Pointer to the configuration structure. |
AnnaBridge | 145:64910690c574 | 1223 | */ |
AnnaBridge | 145:64910690c574 | 1224 | static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) |
AnnaBridge | 145:64910690c574 | 1225 | { |
AnnaBridge | 145:64910690c574 | 1226 | uint8_t reg = base->CR; |
AnnaBridge | 145:64910690c574 | 1227 | |
AnnaBridge | 145:64910690c574 | 1228 | reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); |
AnnaBridge | 145:64910690c574 | 1229 | reg |= config->enableMode; |
AnnaBridge | 145:64910690c574 | 1230 | |
AnnaBridge | 145:64910690c574 | 1231 | base->CR = reg; |
AnnaBridge | 145:64910690c574 | 1232 | |
AnnaBridge | 145:64910690c574 | 1233 | base->DIV = OSC_DIV_ERPS(config->erclkDiv); |
AnnaBridge | 145:64910690c574 | 1234 | } |
AnnaBridge | 145:64910690c574 | 1235 | |
AnnaBridge | 145:64910690c574 | 1236 | /*! |
AnnaBridge | 145:64910690c574 | 1237 | * @brief Sets the capacitor load configuration for the oscillator. |
AnnaBridge | 145:64910690c574 | 1238 | * |
AnnaBridge | 145:64910690c574 | 1239 | * This function sets the specified capacitors configuration for the oscillator. |
AnnaBridge | 145:64910690c574 | 1240 | * This should be done in the early system level initialization function call |
AnnaBridge | 145:64910690c574 | 1241 | * based on the system configuration. |
AnnaBridge | 145:64910690c574 | 1242 | * |
AnnaBridge | 145:64910690c574 | 1243 | * @param base OSC peripheral address. |
AnnaBridge | 145:64910690c574 | 1244 | * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. |
AnnaBridge | 145:64910690c574 | 1245 | * |
AnnaBridge | 145:64910690c574 | 1246 | * Example: |
AnnaBridge | 145:64910690c574 | 1247 | @code |
AnnaBridge | 145:64910690c574 | 1248 | // To enable only 2 pF and 8 pF capacitor load, please use like this. |
AnnaBridge | 145:64910690c574 | 1249 | OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); |
AnnaBridge | 145:64910690c574 | 1250 | @endcode |
AnnaBridge | 145:64910690c574 | 1251 | */ |
AnnaBridge | 145:64910690c574 | 1252 | static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) |
AnnaBridge | 145:64910690c574 | 1253 | { |
AnnaBridge | 145:64910690c574 | 1254 | uint8_t reg = base->CR; |
AnnaBridge | 145:64910690c574 | 1255 | |
AnnaBridge | 145:64910690c574 | 1256 | reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); |
AnnaBridge | 145:64910690c574 | 1257 | reg |= capLoad; |
AnnaBridge | 145:64910690c574 | 1258 | |
AnnaBridge | 145:64910690c574 | 1259 | base->CR = reg; |
AnnaBridge | 145:64910690c574 | 1260 | } |
AnnaBridge | 145:64910690c574 | 1261 | |
AnnaBridge | 145:64910690c574 | 1262 | /*! |
AnnaBridge | 145:64910690c574 | 1263 | * @brief Initializes the OSC0. |
AnnaBridge | 145:64910690c574 | 1264 | * |
AnnaBridge | 145:64910690c574 | 1265 | * This function initializes the OSC0 according to the board configuration. |
AnnaBridge | 145:64910690c574 | 1266 | * |
AnnaBridge | 145:64910690c574 | 1267 | * @param config Pointer to the OSC0 configuration structure. |
AnnaBridge | 145:64910690c574 | 1268 | */ |
AnnaBridge | 145:64910690c574 | 1269 | void CLOCK_InitOsc0(osc_config_t const *config); |
AnnaBridge | 145:64910690c574 | 1270 | |
AnnaBridge | 145:64910690c574 | 1271 | /*! |
AnnaBridge | 145:64910690c574 | 1272 | * @brief Deinitializes the OSC0. |
AnnaBridge | 145:64910690c574 | 1273 | * |
AnnaBridge | 145:64910690c574 | 1274 | * This function deinitializes the OSC0. |
AnnaBridge | 145:64910690c574 | 1275 | */ |
AnnaBridge | 145:64910690c574 | 1276 | void CLOCK_DeinitOsc0(void); |
AnnaBridge | 145:64910690c574 | 1277 | |
AnnaBridge | 145:64910690c574 | 1278 | /* @} */ |
AnnaBridge | 145:64910690c574 | 1279 | |
AnnaBridge | 145:64910690c574 | 1280 | /*! |
AnnaBridge | 145:64910690c574 | 1281 | * @name External clock frequency |
AnnaBridge | 145:64910690c574 | 1282 | * @{ |
AnnaBridge | 145:64910690c574 | 1283 | */ |
AnnaBridge | 145:64910690c574 | 1284 | |
AnnaBridge | 145:64910690c574 | 1285 | /*! |
AnnaBridge | 145:64910690c574 | 1286 | * @brief Sets the XTAL0 frequency based on board settings. |
AnnaBridge | 145:64910690c574 | 1287 | * |
AnnaBridge | 145:64910690c574 | 1288 | * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 1289 | */ |
AnnaBridge | 145:64910690c574 | 1290 | static inline void CLOCK_SetXtal0Freq(uint32_t freq) |
AnnaBridge | 145:64910690c574 | 1291 | { |
AnnaBridge | 145:64910690c574 | 1292 | g_xtal0Freq = freq; |
AnnaBridge | 145:64910690c574 | 1293 | } |
AnnaBridge | 145:64910690c574 | 1294 | |
AnnaBridge | 145:64910690c574 | 1295 | /*! |
AnnaBridge | 145:64910690c574 | 1296 | * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings. |
AnnaBridge | 145:64910690c574 | 1297 | * |
AnnaBridge | 145:64910690c574 | 1298 | * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. |
AnnaBridge | 145:64910690c574 | 1299 | */ |
AnnaBridge | 145:64910690c574 | 1300 | static inline void CLOCK_SetXtal32Freq(uint32_t freq) |
AnnaBridge | 145:64910690c574 | 1301 | { |
AnnaBridge | 145:64910690c574 | 1302 | g_xtal32Freq = freq; |
AnnaBridge | 145:64910690c574 | 1303 | } |
AnnaBridge | 145:64910690c574 | 1304 | /* @} */ |
AnnaBridge | 145:64910690c574 | 1305 | |
AnnaBridge | 145:64910690c574 | 1306 | /*! |
AnnaBridge | 145:64910690c574 | 1307 | * @name MCG auto-trim machine. |
AnnaBridge | 145:64910690c574 | 1308 | * @{ |
AnnaBridge | 145:64910690c574 | 1309 | */ |
AnnaBridge | 145:64910690c574 | 1310 | |
AnnaBridge | 145:64910690c574 | 1311 | /*! |
AnnaBridge | 145:64910690c574 | 1312 | * @brief Auto trims the internal reference clock. |
AnnaBridge | 145:64910690c574 | 1313 | * |
AnnaBridge | 145:64910690c574 | 1314 | * This function trims the internal reference clock by using the external clock. If |
AnnaBridge | 145:64910690c574 | 1315 | * successful, it returns the kStatus_Success and the frequency after |
AnnaBridge | 145:64910690c574 | 1316 | * trimming is received in the parameter @p actualFreq. If an error occurs, |
AnnaBridge | 145:64910690c574 | 1317 | * the error code is returned. |
AnnaBridge | 145:64910690c574 | 1318 | * |
AnnaBridge | 145:64910690c574 | 1319 | * @param extFreq External clock frequency, which should be a bus clock. |
AnnaBridge | 145:64910690c574 | 1320 | * @param desireFreq Frequency to trim to. |
AnnaBridge | 145:64910690c574 | 1321 | * @param actualFreq Actual frequency after trimming. |
AnnaBridge | 145:64910690c574 | 1322 | * @param atms Trim fast or slow internal reference clock. |
AnnaBridge | 145:64910690c574 | 1323 | * @retval kStatus_Success ATM success. |
AnnaBridge | 145:64910690c574 | 1324 | * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. |
AnnaBridge | 145:64910690c574 | 1325 | * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. |
AnnaBridge | 145:64910690c574 | 1326 | * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. |
AnnaBridge | 145:64910690c574 | 1327 | * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. |
AnnaBridge | 145:64910690c574 | 1328 | */ |
AnnaBridge | 145:64910690c574 | 1329 | status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); |
AnnaBridge | 145:64910690c574 | 1330 | /* @} */ |
AnnaBridge | 145:64910690c574 | 1331 | |
AnnaBridge | 145:64910690c574 | 1332 | /*! @name MCG mode functions. */ |
AnnaBridge | 145:64910690c574 | 1333 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 1334 | |
AnnaBridge | 145:64910690c574 | 1335 | /*! |
AnnaBridge | 145:64910690c574 | 1336 | * @brief Gets the current MCG mode. |
AnnaBridge | 145:64910690c574 | 1337 | * |
AnnaBridge | 145:64910690c574 | 1338 | * This function checks the MCG registers and determines the current MCG mode. |
AnnaBridge | 145:64910690c574 | 1339 | * |
AnnaBridge | 145:64910690c574 | 1340 | * @return Current MCG mode or error code; See @ref mcg_mode_t. |
AnnaBridge | 145:64910690c574 | 1341 | */ |
AnnaBridge | 145:64910690c574 | 1342 | mcg_mode_t CLOCK_GetMode(void); |
AnnaBridge | 145:64910690c574 | 1343 | |
AnnaBridge | 145:64910690c574 | 1344 | /*! |
AnnaBridge | 145:64910690c574 | 1345 | * @brief Sets the MCG to FEI mode. |
AnnaBridge | 145:64910690c574 | 1346 | * |
AnnaBridge | 145:64910690c574 | 1347 | * This function sets the MCG to FEI mode. If setting to FEI mode fails |
AnnaBridge | 145:64910690c574 | 1348 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1349 | * |
AnnaBridge | 145:64910690c574 | 1350 | * @param dmx32 DMX32 in FEI mode. |
AnnaBridge | 145:64910690c574 | 1351 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1352 | * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing |
AnnaBridge | 145:64910690c574 | 1353 | * NULL does not cause a delay. |
AnnaBridge | 145:64910690c574 | 1354 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1355 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1356 | * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed |
AnnaBridge | 145:64910690c574 | 1357 | * to a frequency above 32768 Hz. |
AnnaBridge | 145:64910690c574 | 1358 | */ |
AnnaBridge | 145:64910690c574 | 1359 | status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1360 | |
AnnaBridge | 145:64910690c574 | 1361 | /*! |
AnnaBridge | 145:64910690c574 | 1362 | * @brief Sets the MCG to FEE mode. |
AnnaBridge | 145:64910690c574 | 1363 | * |
AnnaBridge | 145:64910690c574 | 1364 | * This function sets the MCG to FEE mode. If setting to FEE mode fails |
AnnaBridge | 145:64910690c574 | 1365 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1366 | * |
AnnaBridge | 145:64910690c574 | 1367 | * @param frdiv FLL reference clock divider setting, FRDIV. |
AnnaBridge | 145:64910690c574 | 1368 | * @param dmx32 DMX32 in FEE mode. |
AnnaBridge | 145:64910690c574 | 1369 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1370 | * @param fllStableDelay Delay function to make sure FLL is stable. Passing |
AnnaBridge | 145:64910690c574 | 1371 | * NULL does not cause a delay. |
AnnaBridge | 145:64910690c574 | 1372 | * |
AnnaBridge | 145:64910690c574 | 1373 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1374 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1375 | */ |
AnnaBridge | 145:64910690c574 | 1376 | status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1377 | |
AnnaBridge | 145:64910690c574 | 1378 | /*! |
AnnaBridge | 145:64910690c574 | 1379 | * @brief Sets the MCG to FBI mode. |
AnnaBridge | 145:64910690c574 | 1380 | * |
AnnaBridge | 145:64910690c574 | 1381 | * This function sets the MCG to FBI mode. If setting to FBI mode fails |
AnnaBridge | 145:64910690c574 | 1382 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1383 | * |
AnnaBridge | 145:64910690c574 | 1384 | * @param dmx32 DMX32 in FBI mode. |
AnnaBridge | 145:64910690c574 | 1385 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1386 | * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL |
AnnaBridge | 145:64910690c574 | 1387 | * is not used in FBI mode, this parameter can be NULL. Passing |
AnnaBridge | 145:64910690c574 | 1388 | * NULL does not cause a delay. |
AnnaBridge | 145:64910690c574 | 1389 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1390 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1391 | * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed |
AnnaBridge | 145:64910690c574 | 1392 | * to frequency above 32768 Hz. |
AnnaBridge | 145:64910690c574 | 1393 | */ |
AnnaBridge | 145:64910690c574 | 1394 | status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1395 | |
AnnaBridge | 145:64910690c574 | 1396 | /*! |
AnnaBridge | 145:64910690c574 | 1397 | * @brief Sets the MCG to FBE mode. |
AnnaBridge | 145:64910690c574 | 1398 | * |
AnnaBridge | 145:64910690c574 | 1399 | * This function sets the MCG to FBE mode. If setting to FBE mode fails |
AnnaBridge | 145:64910690c574 | 1400 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1401 | * |
AnnaBridge | 145:64910690c574 | 1402 | * @param frdiv FLL reference clock divider setting, FRDIV. |
AnnaBridge | 145:64910690c574 | 1403 | * @param dmx32 DMX32 in FBE mode. |
AnnaBridge | 145:64910690c574 | 1404 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1405 | * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL |
AnnaBridge | 145:64910690c574 | 1406 | * is not used in FBE mode, this parameter can be NULL. Passing NULL |
AnnaBridge | 145:64910690c574 | 1407 | * does not cause a delay. |
AnnaBridge | 145:64910690c574 | 1408 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1409 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1410 | */ |
AnnaBridge | 145:64910690c574 | 1411 | status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1412 | |
AnnaBridge | 145:64910690c574 | 1413 | /*! |
AnnaBridge | 145:64910690c574 | 1414 | * @brief Sets the MCG to BLPI mode. |
AnnaBridge | 145:64910690c574 | 1415 | * |
AnnaBridge | 145:64910690c574 | 1416 | * This function sets the MCG to BLPI mode. If setting to BLPI mode fails |
AnnaBridge | 145:64910690c574 | 1417 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1418 | * |
AnnaBridge | 145:64910690c574 | 1419 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1420 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1421 | */ |
AnnaBridge | 145:64910690c574 | 1422 | status_t CLOCK_SetBlpiMode(void); |
AnnaBridge | 145:64910690c574 | 1423 | |
AnnaBridge | 145:64910690c574 | 1424 | /*! |
AnnaBridge | 145:64910690c574 | 1425 | * @brief Sets the MCG to BLPE mode. |
AnnaBridge | 145:64910690c574 | 1426 | * |
AnnaBridge | 145:64910690c574 | 1427 | * This function sets the MCG to BLPE mode. If setting to BLPE mode fails |
AnnaBridge | 145:64910690c574 | 1428 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1429 | * |
AnnaBridge | 145:64910690c574 | 1430 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1431 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1432 | */ |
AnnaBridge | 145:64910690c574 | 1433 | status_t CLOCK_SetBlpeMode(void); |
AnnaBridge | 145:64910690c574 | 1434 | |
AnnaBridge | 145:64910690c574 | 1435 | /*! |
AnnaBridge | 145:64910690c574 | 1436 | * @brief Sets the MCG to PBE mode. |
AnnaBridge | 145:64910690c574 | 1437 | * |
AnnaBridge | 145:64910690c574 | 1438 | * This function sets the MCG to PBE mode. If setting to PBE mode fails |
AnnaBridge | 145:64910690c574 | 1439 | * from the current mode, this function returns an error. |
AnnaBridge | 145:64910690c574 | 1440 | * |
AnnaBridge | 145:64910690c574 | 1441 | * @param pllcs The PLL selection, PLLCS. |
AnnaBridge | 145:64910690c574 | 1442 | * @param config Pointer to the PLL configuration. |
AnnaBridge | 145:64910690c574 | 1443 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1444 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1445 | * |
AnnaBridge | 145:64910690c574 | 1446 | * @note |
AnnaBridge | 145:64910690c574 | 1447 | * 1. The parameter \c pllcs selects the PLL. For platforms with |
AnnaBridge | 145:64910690c574 | 1448 | * only one PLL, the parameter pllcs is kept for interface compatibility. |
AnnaBridge | 145:64910690c574 | 1449 | * 2. The parameter \c config is the PLL configuration structure. On some |
AnnaBridge | 145:64910690c574 | 1450 | * platforms, it is possible to choose the external PLL directly, which renders the |
AnnaBridge | 145:64910690c574 | 1451 | * configuration structure not necessary. In this case, pass in NULL. |
AnnaBridge | 145:64910690c574 | 1452 | * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); |
AnnaBridge | 145:64910690c574 | 1453 | */ |
AnnaBridge | 145:64910690c574 | 1454 | status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); |
AnnaBridge | 145:64910690c574 | 1455 | |
AnnaBridge | 145:64910690c574 | 1456 | /*! |
AnnaBridge | 145:64910690c574 | 1457 | * @brief Sets the MCG to PEE mode. |
AnnaBridge | 145:64910690c574 | 1458 | * |
AnnaBridge | 145:64910690c574 | 1459 | * This function sets the MCG to PEE mode. |
AnnaBridge | 145:64910690c574 | 1460 | * |
AnnaBridge | 145:64910690c574 | 1461 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1462 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1463 | * |
AnnaBridge | 145:64910690c574 | 1464 | * @note This function only changes the CLKS to use the PLL/FLL output. If the |
AnnaBridge | 145:64910690c574 | 1465 | * PRDIV/VDIV are different than in the PBE mode, set them up |
AnnaBridge | 145:64910690c574 | 1466 | * in PBE mode and wait. When the clock is stable, switch to PEE mode. |
AnnaBridge | 145:64910690c574 | 1467 | */ |
AnnaBridge | 145:64910690c574 | 1468 | status_t CLOCK_SetPeeMode(void); |
AnnaBridge | 145:64910690c574 | 1469 | |
AnnaBridge | 145:64910690c574 | 1470 | /*! |
AnnaBridge | 145:64910690c574 | 1471 | * @brief Switches the MCG to FBE mode from the external mode. |
AnnaBridge | 145:64910690c574 | 1472 | * |
AnnaBridge | 145:64910690c574 | 1473 | * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. |
AnnaBridge | 145:64910690c574 | 1474 | * The external clock is used as the system clock souce and PLL is disabled. However, |
AnnaBridge | 145:64910690c574 | 1475 | * the FLL settings are not configured. This is a lite function with a small code size, which is useful |
AnnaBridge | 145:64910690c574 | 1476 | * during the mode switch. For example, to switch from PEE mode to FEI mode: |
AnnaBridge | 145:64910690c574 | 1477 | * |
AnnaBridge | 145:64910690c574 | 1478 | * @code |
AnnaBridge | 145:64910690c574 | 1479 | * CLOCK_ExternalModeToFbeModeQuick(); |
AnnaBridge | 145:64910690c574 | 1480 | * CLOCK_SetFeiMode(...); |
AnnaBridge | 145:64910690c574 | 1481 | * @endcode |
AnnaBridge | 145:64910690c574 | 1482 | * |
AnnaBridge | 145:64910690c574 | 1483 | * @retval kStatus_Success Switched successfully. |
AnnaBridge | 145:64910690c574 | 1484 | * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. |
AnnaBridge | 145:64910690c574 | 1485 | */ |
AnnaBridge | 145:64910690c574 | 1486 | status_t CLOCK_ExternalModeToFbeModeQuick(void); |
AnnaBridge | 145:64910690c574 | 1487 | |
AnnaBridge | 145:64910690c574 | 1488 | /*! |
AnnaBridge | 145:64910690c574 | 1489 | * @brief Switches the MCG to FBI mode from internal modes. |
AnnaBridge | 145:64910690c574 | 1490 | * |
AnnaBridge | 145:64910690c574 | 1491 | * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. |
AnnaBridge | 145:64910690c574 | 1492 | * The MCGIRCLK is used as the system clock souce and PLL is disabled. However, |
AnnaBridge | 145:64910690c574 | 1493 | * FLL settings are not configured. This is a lite function with a small code size, which is useful |
AnnaBridge | 145:64910690c574 | 1494 | * during the mode switch. For example, to switch from PEI mode to FEE mode: |
AnnaBridge | 145:64910690c574 | 1495 | * |
AnnaBridge | 145:64910690c574 | 1496 | * @code |
AnnaBridge | 145:64910690c574 | 1497 | * CLOCK_InternalModeToFbiModeQuick(); |
AnnaBridge | 145:64910690c574 | 1498 | * CLOCK_SetFeeMode(...); |
AnnaBridge | 145:64910690c574 | 1499 | * @endcode |
AnnaBridge | 145:64910690c574 | 1500 | * |
AnnaBridge | 145:64910690c574 | 1501 | * @retval kStatus_Success Switched successfully. |
AnnaBridge | 145:64910690c574 | 1502 | * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. |
AnnaBridge | 145:64910690c574 | 1503 | */ |
AnnaBridge | 145:64910690c574 | 1504 | status_t CLOCK_InternalModeToFbiModeQuick(void); |
AnnaBridge | 145:64910690c574 | 1505 | |
AnnaBridge | 145:64910690c574 | 1506 | /*! |
AnnaBridge | 145:64910690c574 | 1507 | * @brief Sets the MCG to FEI mode during system boot up. |
AnnaBridge | 145:64910690c574 | 1508 | * |
AnnaBridge | 145:64910690c574 | 1509 | * This function sets the MCG to FEI mode from the reset mode. It can also be used to |
AnnaBridge | 145:64910690c574 | 1510 | * set up MCG during system boot up. |
AnnaBridge | 145:64910690c574 | 1511 | * |
AnnaBridge | 145:64910690c574 | 1512 | * @param dmx32 DMX32 in FEI mode. |
AnnaBridge | 145:64910690c574 | 1513 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1514 | * @param fllStableDelay Delay function to ensure that the FLL is stable. |
AnnaBridge | 145:64910690c574 | 1515 | * |
AnnaBridge | 145:64910690c574 | 1516 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1517 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1518 | * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed |
AnnaBridge | 145:64910690c574 | 1519 | * to frequency above 32768 Hz. |
AnnaBridge | 145:64910690c574 | 1520 | */ |
AnnaBridge | 145:64910690c574 | 1521 | status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1522 | |
AnnaBridge | 145:64910690c574 | 1523 | /*! |
AnnaBridge | 145:64910690c574 | 1524 | * @brief Sets the MCG to FEE mode during system bootup. |
AnnaBridge | 145:64910690c574 | 1525 | * |
AnnaBridge | 145:64910690c574 | 1526 | * This function sets MCG to FEE mode from the reset mode. It can also be used to |
AnnaBridge | 145:64910690c574 | 1527 | * set up the MCG during system boot up. |
AnnaBridge | 145:64910690c574 | 1528 | * |
AnnaBridge | 145:64910690c574 | 1529 | * @param oscsel OSC clock select, OSCSEL. |
AnnaBridge | 145:64910690c574 | 1530 | * @param frdiv FLL reference clock divider setting, FRDIV. |
AnnaBridge | 145:64910690c574 | 1531 | * @param dmx32 DMX32 in FEE mode. |
AnnaBridge | 145:64910690c574 | 1532 | * @param drs The DCO range selection. |
AnnaBridge | 145:64910690c574 | 1533 | * @param fllStableDelay Delay function to ensure that the FLL is stable. |
AnnaBridge | 145:64910690c574 | 1534 | * |
AnnaBridge | 145:64910690c574 | 1535 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1536 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1537 | */ |
AnnaBridge | 145:64910690c574 | 1538 | status_t CLOCK_BootToFeeMode( |
AnnaBridge | 145:64910690c574 | 1539 | mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); |
AnnaBridge | 145:64910690c574 | 1540 | |
AnnaBridge | 145:64910690c574 | 1541 | /*! |
AnnaBridge | 145:64910690c574 | 1542 | * @brief Sets the MCG to BLPI mode during system boot up. |
AnnaBridge | 145:64910690c574 | 1543 | * |
AnnaBridge | 145:64910690c574 | 1544 | * This function sets the MCG to BLPI mode from the reset mode. It can also be used to |
AnnaBridge | 145:64910690c574 | 1545 | * set up the MCG during sytem boot up. |
AnnaBridge | 145:64910690c574 | 1546 | * |
AnnaBridge | 145:64910690c574 | 1547 | * @param fcrdiv Fast IRC divider, FCRDIV. |
AnnaBridge | 145:64910690c574 | 1548 | * @param ircs The internal reference clock to select, IRCS. |
AnnaBridge | 145:64910690c574 | 1549 | * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. |
AnnaBridge | 145:64910690c574 | 1550 | * |
AnnaBridge | 145:64910690c574 | 1551 | * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. |
AnnaBridge | 145:64910690c574 | 1552 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1553 | */ |
AnnaBridge | 145:64910690c574 | 1554 | status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); |
AnnaBridge | 145:64910690c574 | 1555 | |
AnnaBridge | 145:64910690c574 | 1556 | /*! |
AnnaBridge | 145:64910690c574 | 1557 | * @brief Sets the MCG to BLPE mode during sytem boot up. |
AnnaBridge | 145:64910690c574 | 1558 | * |
AnnaBridge | 145:64910690c574 | 1559 | * This function sets the MCG to BLPE mode from the reset mode. It can also be used to |
AnnaBridge | 145:64910690c574 | 1560 | * set up the MCG during sytem boot up. |
AnnaBridge | 145:64910690c574 | 1561 | * |
AnnaBridge | 145:64910690c574 | 1562 | * @param oscsel OSC clock select, MCG_C7[OSCSEL]. |
AnnaBridge | 145:64910690c574 | 1563 | * |
AnnaBridge | 145:64910690c574 | 1564 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1565 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1566 | */ |
AnnaBridge | 145:64910690c574 | 1567 | status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); |
AnnaBridge | 145:64910690c574 | 1568 | |
AnnaBridge | 145:64910690c574 | 1569 | /*! |
AnnaBridge | 145:64910690c574 | 1570 | * @brief Sets the MCG to PEE mode during system boot up. |
AnnaBridge | 145:64910690c574 | 1571 | * |
AnnaBridge | 145:64910690c574 | 1572 | * This function sets the MCG to PEE mode from reset mode. It can also be used to |
AnnaBridge | 145:64910690c574 | 1573 | * set up the MCG during system boot up. |
AnnaBridge | 145:64910690c574 | 1574 | * |
AnnaBridge | 145:64910690c574 | 1575 | * @param oscsel OSC clock select, MCG_C7[OSCSEL]. |
AnnaBridge | 145:64910690c574 | 1576 | * @param pllcs The PLL selection, PLLCS. |
AnnaBridge | 145:64910690c574 | 1577 | * @param config Pointer to the PLL configuration. |
AnnaBridge | 145:64910690c574 | 1578 | * |
AnnaBridge | 145:64910690c574 | 1579 | * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. |
AnnaBridge | 145:64910690c574 | 1580 | * @retval kStatus_Success Switched to the target mode successfully. |
AnnaBridge | 145:64910690c574 | 1581 | */ |
AnnaBridge | 145:64910690c574 | 1582 | status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); |
AnnaBridge | 145:64910690c574 | 1583 | |
AnnaBridge | 145:64910690c574 | 1584 | /*! |
AnnaBridge | 145:64910690c574 | 1585 | * @brief Sets the MCG to a target mode. |
AnnaBridge | 145:64910690c574 | 1586 | * |
AnnaBridge | 145:64910690c574 | 1587 | * This function sets MCG to a target mode defined by the configuration |
AnnaBridge | 145:64910690c574 | 1588 | * structure. If switching to the target mode fails, this function |
AnnaBridge | 145:64910690c574 | 1589 | * chooses the correct path. |
AnnaBridge | 145:64910690c574 | 1590 | * |
AnnaBridge | 145:64910690c574 | 1591 | * @param config Pointer to the target MCG mode configuration structure. |
AnnaBridge | 145:64910690c574 | 1592 | * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. |
AnnaBridge | 145:64910690c574 | 1593 | * |
AnnaBridge | 145:64910690c574 | 1594 | * @note If the external clock is used in the target mode, ensure that it is |
AnnaBridge | 145:64910690c574 | 1595 | * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this |
AnnaBridge | 145:64910690c574 | 1596 | * function. |
AnnaBridge | 145:64910690c574 | 1597 | */ |
AnnaBridge | 145:64910690c574 | 1598 | status_t CLOCK_SetMcgConfig(mcg_config_t const *config); |
AnnaBridge | 145:64910690c574 | 1599 | |
AnnaBridge | 145:64910690c574 | 1600 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 1601 | |
AnnaBridge | 145:64910690c574 | 1602 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 1603 | } |
AnnaBridge | 145:64910690c574 | 1604 | #endif /* __cplusplus */ |
AnnaBridge | 145:64910690c574 | 1605 | |
AnnaBridge | 145:64910690c574 | 1606 | /*! @} */ |
AnnaBridge | 145:64910690c574 | 1607 | |
AnnaBridge | 145:64910690c574 | 1608 | #endif /* _FSL_CLOCK_H_ */ |