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mbed 2

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TARGET_SDT51822B/TOOLCHAIN_IAR/mpu_armv8.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * @file mpu_armv8.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS MPU API for Armv8-M MPU
AnnaBridge 171:3a7713b1edbc 4 * @version V5.0.4
AnnaBridge 171:3a7713b1edbc 5 * @date 10. January 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 #if defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 171:3a7713b1edbc 27 #elif defined (__clang__)
AnnaBridge 171:3a7713b1edbc 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 171:3a7713b1edbc 29 #endif
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 171:3a7713b1edbc 32 #define ARM_MPU_ARMV8_H
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 /** \brief Attribute for device memory (outer only) */
AnnaBridge 171:3a7713b1edbc 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 171:3a7713b1edbc 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 171:3a7713b1edbc 41 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 171:3a7713b1edbc 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 171:3a7713b1edbc 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 171:3a7713b1edbc 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 171:3a7713b1edbc 45 */
AnnaBridge 171:3a7713b1edbc 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 171:3a7713b1edbc 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 171:3a7713b1edbc 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 171:3a7713b1edbc 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 171:3a7713b1edbc 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 171:3a7713b1edbc 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /** \brief Memory Attribute
AnnaBridge 171:3a7713b1edbc 62 * \param O Outer memory attributes
AnnaBridge 171:3a7713b1edbc 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /** \brief Normal memory non-shareable */
AnnaBridge 171:3a7713b1edbc 68 #define ARM_MPU_SH_NON (0U)
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /** \brief Normal memory outer shareable */
AnnaBridge 171:3a7713b1edbc 71 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /** \brief Normal memory inner shareable */
AnnaBridge 171:3a7713b1edbc 74 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 /** \brief Memory access permissions
AnnaBridge 171:3a7713b1edbc 77 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 171:3a7713b1edbc 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /** \brief Region Base Address Register value
AnnaBridge 171:3a7713b1edbc 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 171:3a7713b1edbc 84 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 171:3a7713b1edbc 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 171:3a7713b1edbc 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 171:3a7713b1edbc 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 171:3a7713b1edbc 88 */
AnnaBridge 171:3a7713b1edbc 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 171:3a7713b1edbc 90 ((BASE & MPU_RBAR_BASE_Msk) | \
AnnaBridge 171:3a7713b1edbc 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 171:3a7713b1edbc 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 171:3a7713b1edbc 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /** \brief Region Limit Address Register value
AnnaBridge 171:3a7713b1edbc 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 171:3a7713b1edbc 97 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 171:3a7713b1edbc 98 */
AnnaBridge 171:3a7713b1edbc 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 171:3a7713b1edbc 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 171:3a7713b1edbc 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 171:3a7713b1edbc 102 (MPU_RLAR_EN_Msk))
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /**
AnnaBridge 171:3a7713b1edbc 105 * Struct for a single MPU Region
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107 typedef struct {
AnnaBridge 171:3a7713b1edbc 108 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 171:3a7713b1edbc 109 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 171:3a7713b1edbc 110 } ARM_MPU_Region_t;
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /** Enable the MPU.
AnnaBridge 171:3a7713b1edbc 113 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 171:3a7713b1edbc 116 {
AnnaBridge 171:3a7713b1edbc 117 __DSB();
AnnaBridge 171:3a7713b1edbc 118 __ISB();
AnnaBridge 171:3a7713b1edbc 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 171:3a7713b1edbc 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 171:3a7713b1edbc 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 171:3a7713b1edbc 122 #endif
AnnaBridge 171:3a7713b1edbc 123 }
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /** Disable the MPU.
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 171:3a7713b1edbc 128 {
AnnaBridge 171:3a7713b1edbc 129 __DSB();
AnnaBridge 171:3a7713b1edbc 130 __ISB();
AnnaBridge 171:3a7713b1edbc 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 171:3a7713b1edbc 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 171:3a7713b1edbc 133 #endif
AnnaBridge 171:3a7713b1edbc 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 171:3a7713b1edbc 135 }
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 #ifdef MPU_NS
AnnaBridge 171:3a7713b1edbc 138 /** Enable the Non-secure MPU.
AnnaBridge 171:3a7713b1edbc 139 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 171:3a7713b1edbc 140 */
AnnaBridge 171:3a7713b1edbc 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 171:3a7713b1edbc 142 {
AnnaBridge 171:3a7713b1edbc 143 __DSB();
AnnaBridge 171:3a7713b1edbc 144 __ISB();
AnnaBridge 171:3a7713b1edbc 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 171:3a7713b1edbc 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 171:3a7713b1edbc 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 171:3a7713b1edbc 148 #endif
AnnaBridge 171:3a7713b1edbc 149 }
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /** Disable the Non-secure MPU.
AnnaBridge 171:3a7713b1edbc 152 */
AnnaBridge 171:3a7713b1edbc 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 171:3a7713b1edbc 154 {
AnnaBridge 171:3a7713b1edbc 155 __DSB();
AnnaBridge 171:3a7713b1edbc 156 __ISB();
AnnaBridge 171:3a7713b1edbc 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 171:3a7713b1edbc 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 171:3a7713b1edbc 159 #endif
AnnaBridge 171:3a7713b1edbc 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 171:3a7713b1edbc 161 }
AnnaBridge 171:3a7713b1edbc 162 #endif
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 171:3a7713b1edbc 165 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 171:3a7713b1edbc 166 * \param idx The attribute index to be set [0-7]
AnnaBridge 171:3a7713b1edbc 167 * \param attr The attribute value to be set.
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 171:3a7713b1edbc 170 {
AnnaBridge 171:3a7713b1edbc 171 const uint8_t reg = idx / 4U;
AnnaBridge 171:3a7713b1edbc 172 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 171:3a7713b1edbc 173 const uint32_t mask = 0xFFU << pos;
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
AnnaBridge 171:3a7713b1edbc 176 return; // invalid index
AnnaBridge 171:3a7713b1edbc 177 }
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 171:3a7713b1edbc 180 }
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /** Set the memory attribute encoding.
AnnaBridge 171:3a7713b1edbc 183 * \param idx The attribute index to be set [0-7]
AnnaBridge 171:3a7713b1edbc 184 * \param attr The attribute value to be set.
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 171:3a7713b1edbc 187 {
AnnaBridge 171:3a7713b1edbc 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 171:3a7713b1edbc 189 }
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 #ifdef MPU_NS
AnnaBridge 171:3a7713b1edbc 192 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 171:3a7713b1edbc 193 * \param idx The attribute index to be set [0-7]
AnnaBridge 171:3a7713b1edbc 194 * \param attr The attribute value to be set.
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 171:3a7713b1edbc 197 {
AnnaBridge 171:3a7713b1edbc 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 171:3a7713b1edbc 199 }
AnnaBridge 171:3a7713b1edbc 200 #endif
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 171:3a7713b1edbc 203 * \param mpu Pointer to MPU to be used.
AnnaBridge 171:3a7713b1edbc 204 * \param rnr Region number to be cleared.
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208 mpu->RNR = rnr;
AnnaBridge 171:3a7713b1edbc 209 mpu->RLAR = 0U;
AnnaBridge 171:3a7713b1edbc 210 }
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /** Clear and disable the given MPU region.
AnnaBridge 171:3a7713b1edbc 213 * \param rnr Region number to be cleared.
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 171:3a7713b1edbc 216 {
AnnaBridge 171:3a7713b1edbc 217 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 171:3a7713b1edbc 218 }
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 #ifdef MPU_NS
AnnaBridge 171:3a7713b1edbc 221 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 171:3a7713b1edbc 222 * \param rnr Region number to be cleared.
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 171:3a7713b1edbc 225 {
AnnaBridge 171:3a7713b1edbc 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 171:3a7713b1edbc 227 }
AnnaBridge 171:3a7713b1edbc 228 #endif
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /** Configure the given MPU region of the given MPU.
AnnaBridge 171:3a7713b1edbc 231 * \param mpu Pointer to MPU to be used.
AnnaBridge 171:3a7713b1edbc 232 * \param rnr Region number to be configured.
AnnaBridge 171:3a7713b1edbc 233 * \param rbar Value for RBAR register.
AnnaBridge 171:3a7713b1edbc 234 * \param rlar Value for RLAR register.
AnnaBridge 171:3a7713b1edbc 235 */
AnnaBridge 171:3a7713b1edbc 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 171:3a7713b1edbc 237 {
AnnaBridge 171:3a7713b1edbc 238 mpu->RNR = rnr;
AnnaBridge 171:3a7713b1edbc 239 mpu->RBAR = rbar;
AnnaBridge 171:3a7713b1edbc 240 mpu->RLAR = rlar;
AnnaBridge 171:3a7713b1edbc 241 }
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /** Configure the given MPU region.
AnnaBridge 171:3a7713b1edbc 244 * \param rnr Region number to be configured.
AnnaBridge 171:3a7713b1edbc 245 * \param rbar Value for RBAR register.
AnnaBridge 171:3a7713b1edbc 246 * \param rlar Value for RLAR register.
AnnaBridge 171:3a7713b1edbc 247 */
AnnaBridge 171:3a7713b1edbc 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 171:3a7713b1edbc 249 {
AnnaBridge 171:3a7713b1edbc 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 171:3a7713b1edbc 251 }
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 #ifdef MPU_NS
AnnaBridge 171:3a7713b1edbc 254 /** Configure the given Non-secure MPU region.
AnnaBridge 171:3a7713b1edbc 255 * \param rnr Region number to be configured.
AnnaBridge 171:3a7713b1edbc 256 * \param rbar Value for RBAR register.
AnnaBridge 171:3a7713b1edbc 257 * \param rlar Value for RLAR register.
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 171:3a7713b1edbc 260 {
AnnaBridge 171:3a7713b1edbc 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 171:3a7713b1edbc 262 }
AnnaBridge 171:3a7713b1edbc 263 #endif
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 171:3a7713b1edbc 266 * \param dst Destination data is copied to.
AnnaBridge 171:3a7713b1edbc 267 * \param src Source data is copied from.
AnnaBridge 171:3a7713b1edbc 268 * \param len Amount of data words to be copied.
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 171:3a7713b1edbc 271 {
AnnaBridge 171:3a7713b1edbc 272 uint32_t i;
AnnaBridge 171:3a7713b1edbc 273 for (i = 0U; i < len; ++i)
AnnaBridge 171:3a7713b1edbc 274 {
AnnaBridge 171:3a7713b1edbc 275 dst[i] = src[i];
AnnaBridge 171:3a7713b1edbc 276 }
AnnaBridge 171:3a7713b1edbc 277 }
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 171:3a7713b1edbc 280 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 171:3a7713b1edbc 281 * \param rnr First region number to be configured.
AnnaBridge 171:3a7713b1edbc 282 * \param table Pointer to the MPU configuration table.
AnnaBridge 171:3a7713b1edbc 283 * \param cnt Amount of regions to be configured.
AnnaBridge 171:3a7713b1edbc 284 */
AnnaBridge 171:3a7713b1edbc 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 171:3a7713b1edbc 286 {
AnnaBridge 171:3a7713b1edbc 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 171:3a7713b1edbc 288 if (cnt == 1U) {
AnnaBridge 171:3a7713b1edbc 289 mpu->RNR = rnr;
AnnaBridge 171:3a7713b1edbc 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 171:3a7713b1edbc 291 } else {
AnnaBridge 171:3a7713b1edbc 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 171:3a7713b1edbc 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 mpu->RNR = rnrBase;
AnnaBridge 171:3a7713b1edbc 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 171:3a7713b1edbc 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 171:3a7713b1edbc 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
AnnaBridge 171:3a7713b1edbc 299 table += c;
AnnaBridge 171:3a7713b1edbc 300 cnt -= c;
AnnaBridge 171:3a7713b1edbc 301 rnrOffset = 0U;
AnnaBridge 171:3a7713b1edbc 302 rnrBase += MPU_TYPE_RALIASES;
AnnaBridge 171:3a7713b1edbc 303 mpu->RNR = rnrBase;
AnnaBridge 171:3a7713b1edbc 304 }
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 171:3a7713b1edbc 307 }
AnnaBridge 171:3a7713b1edbc 308 }
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /** Load the given number of MPU regions from a table.
AnnaBridge 171:3a7713b1edbc 311 * \param rnr First region number to be configured.
AnnaBridge 171:3a7713b1edbc 312 * \param table Pointer to the MPU configuration table.
AnnaBridge 171:3a7713b1edbc 313 * \param cnt Amount of regions to be configured.
AnnaBridge 171:3a7713b1edbc 314 */
AnnaBridge 171:3a7713b1edbc 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 171:3a7713b1edbc 316 {
AnnaBridge 171:3a7713b1edbc 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 171:3a7713b1edbc 318 }
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #ifdef MPU_NS
AnnaBridge 171:3a7713b1edbc 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 171:3a7713b1edbc 322 * \param rnr First region number to be configured.
AnnaBridge 171:3a7713b1edbc 323 * \param table Pointer to the MPU configuration table.
AnnaBridge 171:3a7713b1edbc 324 * \param cnt Amount of regions to be configured.
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 171:3a7713b1edbc 327 {
AnnaBridge 171:3a7713b1edbc 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 171:3a7713b1edbc 329 }
AnnaBridge 171:3a7713b1edbc 330 #endif
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 #endif
AnnaBridge 171:3a7713b1edbc 333