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TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/stm32f0xx_ll_spi.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_spi.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SPI LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_LL_SPI_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_LL_SPI_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (SPI1) || defined (SPI2) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup SPI_LL SPI |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 60 | |
AnnaBridge | 171:3a7713b1edbc | 61 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 62 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 63 | /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 64 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 65 | */ |
AnnaBridge | 171:3a7713b1edbc | 66 | |
AnnaBridge | 171:3a7713b1edbc | 67 | /** |
AnnaBridge | 171:3a7713b1edbc | 68 | * @brief SPI Init structures definition |
AnnaBridge | 171:3a7713b1edbc | 69 | */ |
AnnaBridge | 171:3a7713b1edbc | 70 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 71 | { |
AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. |
AnnaBridge | 171:3a7713b1edbc | 73 | This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). |
AnnaBridge | 171:3a7713b1edbc | 78 | This parameter can be a value of @ref SPI_LL_EC_MODE. |
AnnaBridge | 171:3a7713b1edbc | 79 | |
AnnaBridge | 171:3a7713b1edbc | 80 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | uint32_t DataWidth; /*!< Specifies the SPI data width. |
AnnaBridge | 171:3a7713b1edbc | 83 | This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. |
AnnaBridge | 171:3a7713b1edbc | 88 | This parameter can be a value of @ref SPI_LL_EC_POLARITY. |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. |
AnnaBridge | 171:3a7713b1edbc | 93 | This parameter can be a value of @ref SPI_LL_EC_PHASE. |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. |
AnnaBridge | 171:3a7713b1edbc | 98 | This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. |
AnnaBridge | 171:3a7713b1edbc | 99 | |
AnnaBridge | 171:3a7713b1edbc | 100 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. |
AnnaBridge | 171:3a7713b1edbc | 103 | This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. |
AnnaBridge | 171:3a7713b1edbc | 104 | @note The communication clock is derived from the master clock. The slave clock does not need to be set. |
AnnaBridge | 171:3a7713b1edbc | 105 | |
AnnaBridge | 171:3a7713b1edbc | 106 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 107 | |
AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. |
AnnaBridge | 171:3a7713b1edbc | 109 | This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 114 | This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. |
AnnaBridge | 171:3a7713b1edbc | 115 | |
AnnaBridge | 171:3a7713b1edbc | 116 | This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ |
AnnaBridge | 171:3a7713b1edbc | 117 | |
AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. |
AnnaBridge | 171:3a7713b1edbc | 119 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. |
AnnaBridge | 171:3a7713b1edbc | 120 | |
AnnaBridge | 171:3a7713b1edbc | 121 | This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | } LL_SPI_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /** |
AnnaBridge | 171:3a7713b1edbc | 126 | * @} |
AnnaBridge | 171:3a7713b1edbc | 127 | */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 131 | /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 132 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 133 | */ |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 136 | * @brief Flags defines which can be used with LL_SPI_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 137 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 138 | */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ |
AnnaBridge | 171:3a7713b1edbc | 146 | /** |
AnnaBridge | 171:3a7713b1edbc | 147 | * @} |
AnnaBridge | 171:3a7713b1edbc | 148 | */ |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | /** @defgroup SPI_LL_EC_IT IT Defines |
AnnaBridge | 171:3a7713b1edbc | 151 | * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions |
AnnaBridge | 171:3a7713b1edbc | 152 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 153 | */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 157 | /** |
AnnaBridge | 171:3a7713b1edbc | 158 | * @} |
AnnaBridge | 171:3a7713b1edbc | 159 | */ |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | /** @defgroup SPI_LL_EC_MODE Operation Mode |
AnnaBridge | 171:3a7713b1edbc | 162 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 163 | */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ |
AnnaBridge | 171:3a7713b1edbc | 166 | /** |
AnnaBridge | 171:3a7713b1edbc | 167 | * @} |
AnnaBridge | 171:3a7713b1edbc | 168 | */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol |
AnnaBridge | 171:3a7713b1edbc | 171 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 172 | */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ |
AnnaBridge | 171:3a7713b1edbc | 174 | #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ |
AnnaBridge | 171:3a7713b1edbc | 175 | /** |
AnnaBridge | 171:3a7713b1edbc | 176 | * @} |
AnnaBridge | 171:3a7713b1edbc | 177 | */ |
AnnaBridge | 171:3a7713b1edbc | 178 | |
AnnaBridge | 171:3a7713b1edbc | 179 | /** @defgroup SPI_LL_EC_PHASE Clock Phase |
AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 181 | */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ |
AnnaBridge | 171:3a7713b1edbc | 184 | /** |
AnnaBridge | 171:3a7713b1edbc | 185 | * @} |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | /** @defgroup SPI_LL_EC_POLARITY Clock Polarity |
AnnaBridge | 171:3a7713b1edbc | 189 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ |
AnnaBridge | 171:3a7713b1edbc | 193 | /** |
AnnaBridge | 171:3a7713b1edbc | 194 | * @} |
AnnaBridge | 171:3a7713b1edbc | 195 | */ |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler |
AnnaBridge | 171:3a7713b1edbc | 198 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 199 | */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ |
AnnaBridge | 171:3a7713b1edbc | 208 | /** |
AnnaBridge | 171:3a7713b1edbc | 209 | * @} |
AnnaBridge | 171:3a7713b1edbc | 210 | */ |
AnnaBridge | 171:3a7713b1edbc | 211 | |
AnnaBridge | 171:3a7713b1edbc | 212 | /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order |
AnnaBridge | 171:3a7713b1edbc | 213 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 214 | */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ |
AnnaBridge | 171:3a7713b1edbc | 217 | /** |
AnnaBridge | 171:3a7713b1edbc | 218 | * @} |
AnnaBridge | 171:3a7713b1edbc | 219 | */ |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode |
AnnaBridge | 171:3a7713b1edbc | 222 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 223 | */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ |
AnnaBridge | 171:3a7713b1edbc | 228 | /** |
AnnaBridge | 171:3a7713b1edbc | 229 | * @} |
AnnaBridge | 171:3a7713b1edbc | 230 | */ |
AnnaBridge | 171:3a7713b1edbc | 231 | |
AnnaBridge | 171:3a7713b1edbc | 232 | /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode |
AnnaBridge | 171:3a7713b1edbc | 233 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 234 | */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ |
AnnaBridge | 171:3a7713b1edbc | 238 | /** |
AnnaBridge | 171:3a7713b1edbc | 239 | * @} |
AnnaBridge | 171:3a7713b1edbc | 240 | */ |
AnnaBridge | 171:3a7713b1edbc | 241 | |
AnnaBridge | 171:3a7713b1edbc | 242 | /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth |
AnnaBridge | 171:3a7713b1edbc | 243 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 244 | */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ |
AnnaBridge | 171:3a7713b1edbc | 258 | /** |
AnnaBridge | 171:3a7713b1edbc | 259 | * @} |
AnnaBridge | 171:3a7713b1edbc | 260 | */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 262 | |
AnnaBridge | 171:3a7713b1edbc | 263 | /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation |
AnnaBridge | 171:3a7713b1edbc | 264 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 265 | */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ |
AnnaBridge | 171:3a7713b1edbc | 268 | /** |
AnnaBridge | 171:3a7713b1edbc | 269 | * @} |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 272 | |
AnnaBridge | 171:3a7713b1edbc | 273 | /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length |
AnnaBridge | 171:3a7713b1edbc | 274 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 275 | */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ |
AnnaBridge | 171:3a7713b1edbc | 278 | /** |
AnnaBridge | 171:3a7713b1edbc | 279 | * @} |
AnnaBridge | 171:3a7713b1edbc | 280 | */ |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold |
AnnaBridge | 171:3a7713b1edbc | 283 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 284 | */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ |
AnnaBridge | 171:3a7713b1edbc | 287 | /** |
AnnaBridge | 171:3a7713b1edbc | 288 | * @} |
AnnaBridge | 171:3a7713b1edbc | 289 | */ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level |
AnnaBridge | 171:3a7713b1edbc | 292 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 293 | */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
AnnaBridge | 171:3a7713b1edbc | 300 | */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level |
AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 304 | */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ |
AnnaBridge | 171:3a7713b1edbc | 309 | /** |
AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity |
AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ |
AnnaBridge | 171:3a7713b1edbc | 318 | |
AnnaBridge | 171:3a7713b1edbc | 319 | /** |
AnnaBridge | 171:3a7713b1edbc | 320 | * @} |
AnnaBridge | 171:3a7713b1edbc | 321 | */ |
AnnaBridge | 171:3a7713b1edbc | 322 | |
AnnaBridge | 171:3a7713b1edbc | 323 | /** |
AnnaBridge | 171:3a7713b1edbc | 324 | * @} |
AnnaBridge | 171:3a7713b1edbc | 325 | */ |
AnnaBridge | 171:3a7713b1edbc | 326 | |
AnnaBridge | 171:3a7713b1edbc | 327 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 328 | /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 329 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 330 | */ |
AnnaBridge | 171:3a7713b1edbc | 331 | |
AnnaBridge | 171:3a7713b1edbc | 332 | /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 171:3a7713b1edbc | 333 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 334 | */ |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | /** |
AnnaBridge | 171:3a7713b1edbc | 337 | * @brief Write a value in SPI register |
AnnaBridge | 171:3a7713b1edbc | 338 | * @param __INSTANCE__ SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 339 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 340 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 341 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 342 | */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 344 | |
AnnaBridge | 171:3a7713b1edbc | 345 | /** |
AnnaBridge | 171:3a7713b1edbc | 346 | * @brief Read a value in SPI register |
AnnaBridge | 171:3a7713b1edbc | 347 | * @param __INSTANCE__ SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 348 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 349 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 350 | */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 352 | /** |
AnnaBridge | 171:3a7713b1edbc | 353 | * @} |
AnnaBridge | 171:3a7713b1edbc | 354 | */ |
AnnaBridge | 171:3a7713b1edbc | 355 | |
AnnaBridge | 171:3a7713b1edbc | 356 | /** |
AnnaBridge | 171:3a7713b1edbc | 357 | * @} |
AnnaBridge | 171:3a7713b1edbc | 358 | */ |
AnnaBridge | 171:3a7713b1edbc | 359 | |
AnnaBridge | 171:3a7713b1edbc | 360 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 361 | /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 362 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 363 | */ |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | /** @defgroup SPI_LL_EF_Configuration Configuration |
AnnaBridge | 171:3a7713b1edbc | 366 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 367 | */ |
AnnaBridge | 171:3a7713b1edbc | 368 | |
AnnaBridge | 171:3a7713b1edbc | 369 | /** |
AnnaBridge | 171:3a7713b1edbc | 370 | * @brief Enable SPI peripheral |
AnnaBridge | 171:3a7713b1edbc | 371 | * @rmtoll CR1 SPE LL_SPI_Enable |
AnnaBridge | 171:3a7713b1edbc | 372 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 373 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 374 | */ |
AnnaBridge | 171:3a7713b1edbc | 375 | __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 376 | { |
AnnaBridge | 171:3a7713b1edbc | 377 | SET_BIT(SPIx->CR1, SPI_CR1_SPE); |
AnnaBridge | 171:3a7713b1edbc | 378 | } |
AnnaBridge | 171:3a7713b1edbc | 379 | |
AnnaBridge | 171:3a7713b1edbc | 380 | /** |
AnnaBridge | 171:3a7713b1edbc | 381 | * @brief Disable SPI peripheral |
AnnaBridge | 171:3a7713b1edbc | 382 | * @note When disabling the SPI, follow the procedure described in the Reference Manual. |
AnnaBridge | 171:3a7713b1edbc | 383 | * @rmtoll CR1 SPE LL_SPI_Disable |
AnnaBridge | 171:3a7713b1edbc | 384 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 385 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 386 | */ |
AnnaBridge | 171:3a7713b1edbc | 387 | __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 388 | { |
AnnaBridge | 171:3a7713b1edbc | 389 | CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); |
AnnaBridge | 171:3a7713b1edbc | 390 | } |
AnnaBridge | 171:3a7713b1edbc | 391 | |
AnnaBridge | 171:3a7713b1edbc | 392 | /** |
AnnaBridge | 171:3a7713b1edbc | 393 | * @brief Check if SPI peripheral is enabled |
AnnaBridge | 171:3a7713b1edbc | 394 | * @rmtoll CR1 SPE LL_SPI_IsEnabled |
AnnaBridge | 171:3a7713b1edbc | 395 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 396 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 397 | */ |
AnnaBridge | 171:3a7713b1edbc | 398 | __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 399 | { |
AnnaBridge | 171:3a7713b1edbc | 400 | return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); |
AnnaBridge | 171:3a7713b1edbc | 401 | } |
AnnaBridge | 171:3a7713b1edbc | 402 | |
AnnaBridge | 171:3a7713b1edbc | 403 | /** |
AnnaBridge | 171:3a7713b1edbc | 404 | * @brief Set SPI operation mode to Master or Slave |
AnnaBridge | 171:3a7713b1edbc | 405 | * @note This bit should not be changed when communication is ongoing. |
AnnaBridge | 171:3a7713b1edbc | 406 | * @rmtoll CR1 MSTR LL_SPI_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 407 | * CR1 SSI LL_SPI_SetMode |
AnnaBridge | 171:3a7713b1edbc | 408 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 409 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 410 | * @arg @ref LL_SPI_MODE_MASTER |
AnnaBridge | 171:3a7713b1edbc | 411 | * @arg @ref LL_SPI_MODE_SLAVE |
AnnaBridge | 171:3a7713b1edbc | 412 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 413 | */ |
AnnaBridge | 171:3a7713b1edbc | 414 | __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) |
AnnaBridge | 171:3a7713b1edbc | 415 | { |
AnnaBridge | 171:3a7713b1edbc | 416 | MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); |
AnnaBridge | 171:3a7713b1edbc | 417 | } |
AnnaBridge | 171:3a7713b1edbc | 418 | |
AnnaBridge | 171:3a7713b1edbc | 419 | /** |
AnnaBridge | 171:3a7713b1edbc | 420 | * @brief Get SPI operation mode (Master or Slave) |
AnnaBridge | 171:3a7713b1edbc | 421 | * @rmtoll CR1 MSTR LL_SPI_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 422 | * CR1 SSI LL_SPI_GetMode |
AnnaBridge | 171:3a7713b1edbc | 423 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 424 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_SPI_MODE_MASTER |
AnnaBridge | 171:3a7713b1edbc | 426 | * @arg @ref LL_SPI_MODE_SLAVE |
AnnaBridge | 171:3a7713b1edbc | 427 | */ |
AnnaBridge | 171:3a7713b1edbc | 428 | __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 429 | { |
AnnaBridge | 171:3a7713b1edbc | 430 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); |
AnnaBridge | 171:3a7713b1edbc | 431 | } |
AnnaBridge | 171:3a7713b1edbc | 432 | |
AnnaBridge | 171:3a7713b1edbc | 433 | /** |
AnnaBridge | 171:3a7713b1edbc | 434 | * @brief Set serial protocol used |
AnnaBridge | 171:3a7713b1edbc | 435 | * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. |
AnnaBridge | 171:3a7713b1edbc | 436 | * @rmtoll CR2 FRF LL_SPI_SetStandard |
AnnaBridge | 171:3a7713b1edbc | 437 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 438 | * @param Standard This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 439 | * @arg @ref LL_SPI_PROTOCOL_MOTOROLA |
AnnaBridge | 171:3a7713b1edbc | 440 | * @arg @ref LL_SPI_PROTOCOL_TI |
AnnaBridge | 171:3a7713b1edbc | 441 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 442 | */ |
AnnaBridge | 171:3a7713b1edbc | 443 | __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) |
AnnaBridge | 171:3a7713b1edbc | 444 | { |
AnnaBridge | 171:3a7713b1edbc | 445 | MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); |
AnnaBridge | 171:3a7713b1edbc | 446 | } |
AnnaBridge | 171:3a7713b1edbc | 447 | |
AnnaBridge | 171:3a7713b1edbc | 448 | /** |
AnnaBridge | 171:3a7713b1edbc | 449 | * @brief Get serial protocol used |
AnnaBridge | 171:3a7713b1edbc | 450 | * @rmtoll CR2 FRF LL_SPI_GetStandard |
AnnaBridge | 171:3a7713b1edbc | 451 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 452 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 453 | * @arg @ref LL_SPI_PROTOCOL_MOTOROLA |
AnnaBridge | 171:3a7713b1edbc | 454 | * @arg @ref LL_SPI_PROTOCOL_TI |
AnnaBridge | 171:3a7713b1edbc | 455 | */ |
AnnaBridge | 171:3a7713b1edbc | 456 | __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 457 | { |
AnnaBridge | 171:3a7713b1edbc | 458 | return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); |
AnnaBridge | 171:3a7713b1edbc | 459 | } |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | /** |
AnnaBridge | 171:3a7713b1edbc | 462 | * @brief Set clock phase |
AnnaBridge | 171:3a7713b1edbc | 463 | * @note This bit should not be changed when communication is ongoing. |
AnnaBridge | 171:3a7713b1edbc | 464 | * This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 465 | * @rmtoll CR1 CPHA LL_SPI_SetClockPhase |
AnnaBridge | 171:3a7713b1edbc | 466 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 467 | * @param ClockPhase This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 468 | * @arg @ref LL_SPI_PHASE_1EDGE |
AnnaBridge | 171:3a7713b1edbc | 469 | * @arg @ref LL_SPI_PHASE_2EDGE |
AnnaBridge | 171:3a7713b1edbc | 470 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 471 | */ |
AnnaBridge | 171:3a7713b1edbc | 472 | __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) |
AnnaBridge | 171:3a7713b1edbc | 473 | { |
AnnaBridge | 171:3a7713b1edbc | 474 | MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); |
AnnaBridge | 171:3a7713b1edbc | 475 | } |
AnnaBridge | 171:3a7713b1edbc | 476 | |
AnnaBridge | 171:3a7713b1edbc | 477 | /** |
AnnaBridge | 171:3a7713b1edbc | 478 | * @brief Get clock phase |
AnnaBridge | 171:3a7713b1edbc | 479 | * @rmtoll CR1 CPHA LL_SPI_GetClockPhase |
AnnaBridge | 171:3a7713b1edbc | 480 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 481 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 482 | * @arg @ref LL_SPI_PHASE_1EDGE |
AnnaBridge | 171:3a7713b1edbc | 483 | * @arg @ref LL_SPI_PHASE_2EDGE |
AnnaBridge | 171:3a7713b1edbc | 484 | */ |
AnnaBridge | 171:3a7713b1edbc | 485 | __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 486 | { |
AnnaBridge | 171:3a7713b1edbc | 487 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); |
AnnaBridge | 171:3a7713b1edbc | 488 | } |
AnnaBridge | 171:3a7713b1edbc | 489 | |
AnnaBridge | 171:3a7713b1edbc | 490 | /** |
AnnaBridge | 171:3a7713b1edbc | 491 | * @brief Set clock polarity |
AnnaBridge | 171:3a7713b1edbc | 492 | * @note This bit should not be changed when communication is ongoing. |
AnnaBridge | 171:3a7713b1edbc | 493 | * This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 494 | * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity |
AnnaBridge | 171:3a7713b1edbc | 495 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 496 | * @param ClockPolarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 497 | * @arg @ref LL_SPI_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 498 | * @arg @ref LL_SPI_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 499 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 500 | */ |
AnnaBridge | 171:3a7713b1edbc | 501 | __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) |
AnnaBridge | 171:3a7713b1edbc | 502 | { |
AnnaBridge | 171:3a7713b1edbc | 503 | MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); |
AnnaBridge | 171:3a7713b1edbc | 504 | } |
AnnaBridge | 171:3a7713b1edbc | 505 | |
AnnaBridge | 171:3a7713b1edbc | 506 | /** |
AnnaBridge | 171:3a7713b1edbc | 507 | * @brief Get clock polarity |
AnnaBridge | 171:3a7713b1edbc | 508 | * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity |
AnnaBridge | 171:3a7713b1edbc | 509 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 510 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 511 | * @arg @ref LL_SPI_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 512 | * @arg @ref LL_SPI_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 513 | */ |
AnnaBridge | 171:3a7713b1edbc | 514 | __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 515 | { |
AnnaBridge | 171:3a7713b1edbc | 516 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); |
AnnaBridge | 171:3a7713b1edbc | 517 | } |
AnnaBridge | 171:3a7713b1edbc | 518 | |
AnnaBridge | 171:3a7713b1edbc | 519 | /** |
AnnaBridge | 171:3a7713b1edbc | 520 | * @brief Set baud rate prescaler |
AnnaBridge | 171:3a7713b1edbc | 521 | * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 522 | * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler |
AnnaBridge | 171:3a7713b1edbc | 523 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 524 | * @param BaudRate This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 |
AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 |
AnnaBridge | 171:3a7713b1edbc | 530 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 |
AnnaBridge | 171:3a7713b1edbc | 531 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 |
AnnaBridge | 171:3a7713b1edbc | 532 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 |
AnnaBridge | 171:3a7713b1edbc | 533 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 534 | */ |
AnnaBridge | 171:3a7713b1edbc | 535 | __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) |
AnnaBridge | 171:3a7713b1edbc | 536 | { |
AnnaBridge | 171:3a7713b1edbc | 537 | MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); |
AnnaBridge | 171:3a7713b1edbc | 538 | } |
AnnaBridge | 171:3a7713b1edbc | 539 | |
AnnaBridge | 171:3a7713b1edbc | 540 | /** |
AnnaBridge | 171:3a7713b1edbc | 541 | * @brief Get baud rate prescaler |
AnnaBridge | 171:3a7713b1edbc | 542 | * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler |
AnnaBridge | 171:3a7713b1edbc | 543 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 544 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 545 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 546 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 547 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 548 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 |
AnnaBridge | 171:3a7713b1edbc | 549 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 |
AnnaBridge | 171:3a7713b1edbc | 550 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 |
AnnaBridge | 171:3a7713b1edbc | 551 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 |
AnnaBridge | 171:3a7713b1edbc | 552 | * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 |
AnnaBridge | 171:3a7713b1edbc | 553 | */ |
AnnaBridge | 171:3a7713b1edbc | 554 | __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 555 | { |
AnnaBridge | 171:3a7713b1edbc | 556 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); |
AnnaBridge | 171:3a7713b1edbc | 557 | } |
AnnaBridge | 171:3a7713b1edbc | 558 | |
AnnaBridge | 171:3a7713b1edbc | 559 | /** |
AnnaBridge | 171:3a7713b1edbc | 560 | * @brief Set transfer bit order |
AnnaBridge | 171:3a7713b1edbc | 561 | * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 562 | * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder |
AnnaBridge | 171:3a7713b1edbc | 563 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 564 | * @param BitOrder This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 565 | * @arg @ref LL_SPI_LSB_FIRST |
AnnaBridge | 171:3a7713b1edbc | 566 | * @arg @ref LL_SPI_MSB_FIRST |
AnnaBridge | 171:3a7713b1edbc | 567 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 568 | */ |
AnnaBridge | 171:3a7713b1edbc | 569 | __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) |
AnnaBridge | 171:3a7713b1edbc | 570 | { |
AnnaBridge | 171:3a7713b1edbc | 571 | MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); |
AnnaBridge | 171:3a7713b1edbc | 572 | } |
AnnaBridge | 171:3a7713b1edbc | 573 | |
AnnaBridge | 171:3a7713b1edbc | 574 | /** |
AnnaBridge | 171:3a7713b1edbc | 575 | * @brief Get transfer bit order |
AnnaBridge | 171:3a7713b1edbc | 576 | * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder |
AnnaBridge | 171:3a7713b1edbc | 577 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 578 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_SPI_LSB_FIRST |
AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_SPI_MSB_FIRST |
AnnaBridge | 171:3a7713b1edbc | 581 | */ |
AnnaBridge | 171:3a7713b1edbc | 582 | __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 583 | { |
AnnaBridge | 171:3a7713b1edbc | 584 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); |
AnnaBridge | 171:3a7713b1edbc | 585 | } |
AnnaBridge | 171:3a7713b1edbc | 586 | |
AnnaBridge | 171:3a7713b1edbc | 587 | /** |
AnnaBridge | 171:3a7713b1edbc | 588 | * @brief Set transfer direction mode |
AnnaBridge | 171:3a7713b1edbc | 589 | * @note For Half-Duplex mode, Rx Direction is set by default. |
AnnaBridge | 171:3a7713b1edbc | 590 | * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. |
AnnaBridge | 171:3a7713b1edbc | 591 | * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 592 | * CR1 BIDIMODE LL_SPI_SetTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 593 | * CR1 BIDIOE LL_SPI_SetTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 594 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 595 | * @param TransferDirection This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 596 | * @arg @ref LL_SPI_FULL_DUPLEX |
AnnaBridge | 171:3a7713b1edbc | 597 | * @arg @ref LL_SPI_SIMPLEX_RX |
AnnaBridge | 171:3a7713b1edbc | 598 | * @arg @ref LL_SPI_HALF_DUPLEX_RX |
AnnaBridge | 171:3a7713b1edbc | 599 | * @arg @ref LL_SPI_HALF_DUPLEX_TX |
AnnaBridge | 171:3a7713b1edbc | 600 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 601 | */ |
AnnaBridge | 171:3a7713b1edbc | 602 | __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) |
AnnaBridge | 171:3a7713b1edbc | 603 | { |
AnnaBridge | 171:3a7713b1edbc | 604 | MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); |
AnnaBridge | 171:3a7713b1edbc | 605 | } |
AnnaBridge | 171:3a7713b1edbc | 606 | |
AnnaBridge | 171:3a7713b1edbc | 607 | /** |
AnnaBridge | 171:3a7713b1edbc | 608 | * @brief Get transfer direction mode |
AnnaBridge | 171:3a7713b1edbc | 609 | * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 610 | * CR1 BIDIMODE LL_SPI_GetTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 611 | * CR1 BIDIOE LL_SPI_GetTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 612 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 613 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 614 | * @arg @ref LL_SPI_FULL_DUPLEX |
AnnaBridge | 171:3a7713b1edbc | 615 | * @arg @ref LL_SPI_SIMPLEX_RX |
AnnaBridge | 171:3a7713b1edbc | 616 | * @arg @ref LL_SPI_HALF_DUPLEX_RX |
AnnaBridge | 171:3a7713b1edbc | 617 | * @arg @ref LL_SPI_HALF_DUPLEX_TX |
AnnaBridge | 171:3a7713b1edbc | 618 | */ |
AnnaBridge | 171:3a7713b1edbc | 619 | __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 620 | { |
AnnaBridge | 171:3a7713b1edbc | 621 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); |
AnnaBridge | 171:3a7713b1edbc | 622 | } |
AnnaBridge | 171:3a7713b1edbc | 623 | |
AnnaBridge | 171:3a7713b1edbc | 624 | /** |
AnnaBridge | 171:3a7713b1edbc | 625 | * @brief Set frame data width |
AnnaBridge | 171:3a7713b1edbc | 626 | * @rmtoll CR2 DS LL_SPI_SetDataWidth |
AnnaBridge | 171:3a7713b1edbc | 627 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 628 | * @param DataWidth This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 629 | * @arg @ref LL_SPI_DATAWIDTH_4BIT |
AnnaBridge | 171:3a7713b1edbc | 630 | * @arg @ref LL_SPI_DATAWIDTH_5BIT |
AnnaBridge | 171:3a7713b1edbc | 631 | * @arg @ref LL_SPI_DATAWIDTH_6BIT |
AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_SPI_DATAWIDTH_7BIT |
AnnaBridge | 171:3a7713b1edbc | 633 | * @arg @ref LL_SPI_DATAWIDTH_8BIT |
AnnaBridge | 171:3a7713b1edbc | 634 | * @arg @ref LL_SPI_DATAWIDTH_9BIT |
AnnaBridge | 171:3a7713b1edbc | 635 | * @arg @ref LL_SPI_DATAWIDTH_10BIT |
AnnaBridge | 171:3a7713b1edbc | 636 | * @arg @ref LL_SPI_DATAWIDTH_11BIT |
AnnaBridge | 171:3a7713b1edbc | 637 | * @arg @ref LL_SPI_DATAWIDTH_12BIT |
AnnaBridge | 171:3a7713b1edbc | 638 | * @arg @ref LL_SPI_DATAWIDTH_13BIT |
AnnaBridge | 171:3a7713b1edbc | 639 | * @arg @ref LL_SPI_DATAWIDTH_14BIT |
AnnaBridge | 171:3a7713b1edbc | 640 | * @arg @ref LL_SPI_DATAWIDTH_15BIT |
AnnaBridge | 171:3a7713b1edbc | 641 | * @arg @ref LL_SPI_DATAWIDTH_16BIT |
AnnaBridge | 171:3a7713b1edbc | 642 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 643 | */ |
AnnaBridge | 171:3a7713b1edbc | 644 | __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) |
AnnaBridge | 171:3a7713b1edbc | 645 | { |
AnnaBridge | 171:3a7713b1edbc | 646 | MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); |
AnnaBridge | 171:3a7713b1edbc | 647 | } |
AnnaBridge | 171:3a7713b1edbc | 648 | |
AnnaBridge | 171:3a7713b1edbc | 649 | /** |
AnnaBridge | 171:3a7713b1edbc | 650 | * @brief Get frame data width |
AnnaBridge | 171:3a7713b1edbc | 651 | * @rmtoll CR2 DS LL_SPI_GetDataWidth |
AnnaBridge | 171:3a7713b1edbc | 652 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 653 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 654 | * @arg @ref LL_SPI_DATAWIDTH_4BIT |
AnnaBridge | 171:3a7713b1edbc | 655 | * @arg @ref LL_SPI_DATAWIDTH_5BIT |
AnnaBridge | 171:3a7713b1edbc | 656 | * @arg @ref LL_SPI_DATAWIDTH_6BIT |
AnnaBridge | 171:3a7713b1edbc | 657 | * @arg @ref LL_SPI_DATAWIDTH_7BIT |
AnnaBridge | 171:3a7713b1edbc | 658 | * @arg @ref LL_SPI_DATAWIDTH_8BIT |
AnnaBridge | 171:3a7713b1edbc | 659 | * @arg @ref LL_SPI_DATAWIDTH_9BIT |
AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref LL_SPI_DATAWIDTH_10BIT |
AnnaBridge | 171:3a7713b1edbc | 661 | * @arg @ref LL_SPI_DATAWIDTH_11BIT |
AnnaBridge | 171:3a7713b1edbc | 662 | * @arg @ref LL_SPI_DATAWIDTH_12BIT |
AnnaBridge | 171:3a7713b1edbc | 663 | * @arg @ref LL_SPI_DATAWIDTH_13BIT |
AnnaBridge | 171:3a7713b1edbc | 664 | * @arg @ref LL_SPI_DATAWIDTH_14BIT |
AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref LL_SPI_DATAWIDTH_15BIT |
AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref LL_SPI_DATAWIDTH_16BIT |
AnnaBridge | 171:3a7713b1edbc | 667 | */ |
AnnaBridge | 171:3a7713b1edbc | 668 | __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 669 | { |
AnnaBridge | 171:3a7713b1edbc | 670 | return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); |
AnnaBridge | 171:3a7713b1edbc | 671 | } |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | /** |
AnnaBridge | 171:3a7713b1edbc | 674 | * @brief Set threshold of RXFIFO that triggers an RXNE event |
AnnaBridge | 171:3a7713b1edbc | 675 | * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold |
AnnaBridge | 171:3a7713b1edbc | 676 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 677 | * @param Threshold This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 678 | * @arg @ref LL_SPI_RX_FIFO_TH_HALF |
AnnaBridge | 171:3a7713b1edbc | 679 | * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER |
AnnaBridge | 171:3a7713b1edbc | 680 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 681 | */ |
AnnaBridge | 171:3a7713b1edbc | 682 | __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) |
AnnaBridge | 171:3a7713b1edbc | 683 | { |
AnnaBridge | 171:3a7713b1edbc | 684 | MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); |
AnnaBridge | 171:3a7713b1edbc | 685 | } |
AnnaBridge | 171:3a7713b1edbc | 686 | |
AnnaBridge | 171:3a7713b1edbc | 687 | /** |
AnnaBridge | 171:3a7713b1edbc | 688 | * @brief Get threshold of RXFIFO that triggers an RXNE event |
AnnaBridge | 171:3a7713b1edbc | 689 | * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold |
AnnaBridge | 171:3a7713b1edbc | 690 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 691 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 692 | * @arg @ref LL_SPI_RX_FIFO_TH_HALF |
AnnaBridge | 171:3a7713b1edbc | 693 | * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER |
AnnaBridge | 171:3a7713b1edbc | 694 | */ |
AnnaBridge | 171:3a7713b1edbc | 695 | __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 696 | { |
AnnaBridge | 171:3a7713b1edbc | 697 | return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); |
AnnaBridge | 171:3a7713b1edbc | 698 | } |
AnnaBridge | 171:3a7713b1edbc | 699 | |
AnnaBridge | 171:3a7713b1edbc | 700 | /** |
AnnaBridge | 171:3a7713b1edbc | 701 | * @} |
AnnaBridge | 171:3a7713b1edbc | 702 | */ |
AnnaBridge | 171:3a7713b1edbc | 703 | |
AnnaBridge | 171:3a7713b1edbc | 704 | /** @defgroup SPI_LL_EF_CRC_Management CRC Management |
AnnaBridge | 171:3a7713b1edbc | 705 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 706 | */ |
AnnaBridge | 171:3a7713b1edbc | 707 | |
AnnaBridge | 171:3a7713b1edbc | 708 | /** |
AnnaBridge | 171:3a7713b1edbc | 709 | * @brief Enable CRC |
AnnaBridge | 171:3a7713b1edbc | 710 | * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. |
AnnaBridge | 171:3a7713b1edbc | 711 | * @rmtoll CR1 CRCEN LL_SPI_EnableCRC |
AnnaBridge | 171:3a7713b1edbc | 712 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 713 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 714 | */ |
AnnaBridge | 171:3a7713b1edbc | 715 | __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 716 | { |
AnnaBridge | 171:3a7713b1edbc | 717 | SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); |
AnnaBridge | 171:3a7713b1edbc | 718 | } |
AnnaBridge | 171:3a7713b1edbc | 719 | |
AnnaBridge | 171:3a7713b1edbc | 720 | /** |
AnnaBridge | 171:3a7713b1edbc | 721 | * @brief Disable CRC |
AnnaBridge | 171:3a7713b1edbc | 722 | * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. |
AnnaBridge | 171:3a7713b1edbc | 723 | * @rmtoll CR1 CRCEN LL_SPI_DisableCRC |
AnnaBridge | 171:3a7713b1edbc | 724 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 725 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 726 | */ |
AnnaBridge | 171:3a7713b1edbc | 727 | __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 728 | { |
AnnaBridge | 171:3a7713b1edbc | 729 | CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); |
AnnaBridge | 171:3a7713b1edbc | 730 | } |
AnnaBridge | 171:3a7713b1edbc | 731 | |
AnnaBridge | 171:3a7713b1edbc | 732 | /** |
AnnaBridge | 171:3a7713b1edbc | 733 | * @brief Check if CRC is enabled |
AnnaBridge | 171:3a7713b1edbc | 734 | * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. |
AnnaBridge | 171:3a7713b1edbc | 735 | * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC |
AnnaBridge | 171:3a7713b1edbc | 736 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 737 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 738 | */ |
AnnaBridge | 171:3a7713b1edbc | 739 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 740 | { |
AnnaBridge | 171:3a7713b1edbc | 741 | return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); |
AnnaBridge | 171:3a7713b1edbc | 742 | } |
AnnaBridge | 171:3a7713b1edbc | 743 | |
AnnaBridge | 171:3a7713b1edbc | 744 | /** |
AnnaBridge | 171:3a7713b1edbc | 745 | * @brief Set CRC Length |
AnnaBridge | 171:3a7713b1edbc | 746 | * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. |
AnnaBridge | 171:3a7713b1edbc | 747 | * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth |
AnnaBridge | 171:3a7713b1edbc | 748 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 749 | * @param CRCLength This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 750 | * @arg @ref LL_SPI_CRC_8BIT |
AnnaBridge | 171:3a7713b1edbc | 751 | * @arg @ref LL_SPI_CRC_16BIT |
AnnaBridge | 171:3a7713b1edbc | 752 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 753 | */ |
AnnaBridge | 171:3a7713b1edbc | 754 | __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) |
AnnaBridge | 171:3a7713b1edbc | 755 | { |
AnnaBridge | 171:3a7713b1edbc | 756 | MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); |
AnnaBridge | 171:3a7713b1edbc | 757 | } |
AnnaBridge | 171:3a7713b1edbc | 758 | |
AnnaBridge | 171:3a7713b1edbc | 759 | /** |
AnnaBridge | 171:3a7713b1edbc | 760 | * @brief Get CRC Length |
AnnaBridge | 171:3a7713b1edbc | 761 | * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth |
AnnaBridge | 171:3a7713b1edbc | 762 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 763 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 764 | * @arg @ref LL_SPI_CRC_8BIT |
AnnaBridge | 171:3a7713b1edbc | 765 | * @arg @ref LL_SPI_CRC_16BIT |
AnnaBridge | 171:3a7713b1edbc | 766 | */ |
AnnaBridge | 171:3a7713b1edbc | 767 | __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 768 | { |
AnnaBridge | 171:3a7713b1edbc | 769 | return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); |
AnnaBridge | 171:3a7713b1edbc | 770 | } |
AnnaBridge | 171:3a7713b1edbc | 771 | |
AnnaBridge | 171:3a7713b1edbc | 772 | /** |
AnnaBridge | 171:3a7713b1edbc | 773 | * @brief Set CRCNext to transfer CRC on the line |
AnnaBridge | 171:3a7713b1edbc | 774 | * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. |
AnnaBridge | 171:3a7713b1edbc | 775 | * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext |
AnnaBridge | 171:3a7713b1edbc | 776 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 777 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 778 | */ |
AnnaBridge | 171:3a7713b1edbc | 779 | __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 780 | { |
AnnaBridge | 171:3a7713b1edbc | 781 | SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); |
AnnaBridge | 171:3a7713b1edbc | 782 | } |
AnnaBridge | 171:3a7713b1edbc | 783 | |
AnnaBridge | 171:3a7713b1edbc | 784 | /** |
AnnaBridge | 171:3a7713b1edbc | 785 | * @brief Set polynomial for CRC calculation |
AnnaBridge | 171:3a7713b1edbc | 786 | * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial |
AnnaBridge | 171:3a7713b1edbc | 787 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 788 | * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 789 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 790 | */ |
AnnaBridge | 171:3a7713b1edbc | 791 | __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) |
AnnaBridge | 171:3a7713b1edbc | 792 | { |
AnnaBridge | 171:3a7713b1edbc | 793 | WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); |
AnnaBridge | 171:3a7713b1edbc | 794 | } |
AnnaBridge | 171:3a7713b1edbc | 795 | |
AnnaBridge | 171:3a7713b1edbc | 796 | /** |
AnnaBridge | 171:3a7713b1edbc | 797 | * @brief Get polynomial for CRC calculation |
AnnaBridge | 171:3a7713b1edbc | 798 | * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial |
AnnaBridge | 171:3a7713b1edbc | 799 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 800 | * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 801 | */ |
AnnaBridge | 171:3a7713b1edbc | 802 | __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 803 | { |
AnnaBridge | 171:3a7713b1edbc | 804 | return (uint32_t)(READ_REG(SPIx->CRCPR)); |
AnnaBridge | 171:3a7713b1edbc | 805 | } |
AnnaBridge | 171:3a7713b1edbc | 806 | |
AnnaBridge | 171:3a7713b1edbc | 807 | /** |
AnnaBridge | 171:3a7713b1edbc | 808 | * @brief Get Rx CRC |
AnnaBridge | 171:3a7713b1edbc | 809 | * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC |
AnnaBridge | 171:3a7713b1edbc | 810 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 811 | * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 812 | */ |
AnnaBridge | 171:3a7713b1edbc | 813 | __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 814 | { |
AnnaBridge | 171:3a7713b1edbc | 815 | return (uint32_t)(READ_REG(SPIx->RXCRCR)); |
AnnaBridge | 171:3a7713b1edbc | 816 | } |
AnnaBridge | 171:3a7713b1edbc | 817 | |
AnnaBridge | 171:3a7713b1edbc | 818 | /** |
AnnaBridge | 171:3a7713b1edbc | 819 | * @brief Get Tx CRC |
AnnaBridge | 171:3a7713b1edbc | 820 | * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC |
AnnaBridge | 171:3a7713b1edbc | 821 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 822 | * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 823 | */ |
AnnaBridge | 171:3a7713b1edbc | 824 | __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 825 | { |
AnnaBridge | 171:3a7713b1edbc | 826 | return (uint32_t)(READ_REG(SPIx->TXCRCR)); |
AnnaBridge | 171:3a7713b1edbc | 827 | } |
AnnaBridge | 171:3a7713b1edbc | 828 | |
AnnaBridge | 171:3a7713b1edbc | 829 | /** |
AnnaBridge | 171:3a7713b1edbc | 830 | * @} |
AnnaBridge | 171:3a7713b1edbc | 831 | */ |
AnnaBridge | 171:3a7713b1edbc | 832 | |
AnnaBridge | 171:3a7713b1edbc | 833 | /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management |
AnnaBridge | 171:3a7713b1edbc | 834 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 835 | */ |
AnnaBridge | 171:3a7713b1edbc | 836 | |
AnnaBridge | 171:3a7713b1edbc | 837 | /** |
AnnaBridge | 171:3a7713b1edbc | 838 | * @brief Set NSS mode |
AnnaBridge | 171:3a7713b1edbc | 839 | * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 840 | * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n |
AnnaBridge | 171:3a7713b1edbc | 841 | * @rmtoll CR2 SSOE LL_SPI_SetNSSMode |
AnnaBridge | 171:3a7713b1edbc | 842 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 843 | * @param NSS This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 844 | * @arg @ref LL_SPI_NSS_SOFT |
AnnaBridge | 171:3a7713b1edbc | 845 | * @arg @ref LL_SPI_NSS_HARD_INPUT |
AnnaBridge | 171:3a7713b1edbc | 846 | * @arg @ref LL_SPI_NSS_HARD_OUTPUT |
AnnaBridge | 171:3a7713b1edbc | 847 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 848 | */ |
AnnaBridge | 171:3a7713b1edbc | 849 | __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) |
AnnaBridge | 171:3a7713b1edbc | 850 | { |
AnnaBridge | 171:3a7713b1edbc | 851 | MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); |
AnnaBridge | 171:3a7713b1edbc | 852 | MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); |
AnnaBridge | 171:3a7713b1edbc | 853 | } |
AnnaBridge | 171:3a7713b1edbc | 854 | |
AnnaBridge | 171:3a7713b1edbc | 855 | /** |
AnnaBridge | 171:3a7713b1edbc | 856 | * @brief Get NSS mode |
AnnaBridge | 171:3a7713b1edbc | 857 | * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n |
AnnaBridge | 171:3a7713b1edbc | 858 | * @rmtoll CR2 SSOE LL_SPI_GetNSSMode |
AnnaBridge | 171:3a7713b1edbc | 859 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 860 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 861 | * @arg @ref LL_SPI_NSS_SOFT |
AnnaBridge | 171:3a7713b1edbc | 862 | * @arg @ref LL_SPI_NSS_HARD_INPUT |
AnnaBridge | 171:3a7713b1edbc | 863 | * @arg @ref LL_SPI_NSS_HARD_OUTPUT |
AnnaBridge | 171:3a7713b1edbc | 864 | */ |
AnnaBridge | 171:3a7713b1edbc | 865 | __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 866 | { |
AnnaBridge | 171:3a7713b1edbc | 867 | register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); |
AnnaBridge | 171:3a7713b1edbc | 868 | register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); |
AnnaBridge | 171:3a7713b1edbc | 869 | return (Ssm | Ssoe); |
AnnaBridge | 171:3a7713b1edbc | 870 | } |
AnnaBridge | 171:3a7713b1edbc | 871 | |
AnnaBridge | 171:3a7713b1edbc | 872 | /** |
AnnaBridge | 171:3a7713b1edbc | 873 | * @brief Enable NSS pulse management |
AnnaBridge | 171:3a7713b1edbc | 874 | * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 875 | * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt |
AnnaBridge | 171:3a7713b1edbc | 876 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 877 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 878 | */ |
AnnaBridge | 171:3a7713b1edbc | 879 | __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 880 | { |
AnnaBridge | 171:3a7713b1edbc | 881 | SET_BIT(SPIx->CR2, SPI_CR2_NSSP); |
AnnaBridge | 171:3a7713b1edbc | 882 | } |
AnnaBridge | 171:3a7713b1edbc | 883 | |
AnnaBridge | 171:3a7713b1edbc | 884 | /** |
AnnaBridge | 171:3a7713b1edbc | 885 | * @brief Disable NSS pulse management |
AnnaBridge | 171:3a7713b1edbc | 886 | * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 887 | * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt |
AnnaBridge | 171:3a7713b1edbc | 888 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 889 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 890 | */ |
AnnaBridge | 171:3a7713b1edbc | 891 | __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 892 | { |
AnnaBridge | 171:3a7713b1edbc | 893 | CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); |
AnnaBridge | 171:3a7713b1edbc | 894 | } |
AnnaBridge | 171:3a7713b1edbc | 895 | |
AnnaBridge | 171:3a7713b1edbc | 896 | /** |
AnnaBridge | 171:3a7713b1edbc | 897 | * @brief Check if NSS pulse is enabled |
AnnaBridge | 171:3a7713b1edbc | 898 | * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. |
AnnaBridge | 171:3a7713b1edbc | 899 | * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse |
AnnaBridge | 171:3a7713b1edbc | 900 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 901 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 902 | */ |
AnnaBridge | 171:3a7713b1edbc | 903 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 904 | { |
AnnaBridge | 171:3a7713b1edbc | 905 | return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); |
AnnaBridge | 171:3a7713b1edbc | 906 | } |
AnnaBridge | 171:3a7713b1edbc | 907 | |
AnnaBridge | 171:3a7713b1edbc | 908 | /** |
AnnaBridge | 171:3a7713b1edbc | 909 | * @} |
AnnaBridge | 171:3a7713b1edbc | 910 | */ |
AnnaBridge | 171:3a7713b1edbc | 911 | |
AnnaBridge | 171:3a7713b1edbc | 912 | /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 171:3a7713b1edbc | 913 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 914 | */ |
AnnaBridge | 171:3a7713b1edbc | 915 | |
AnnaBridge | 171:3a7713b1edbc | 916 | /** |
AnnaBridge | 171:3a7713b1edbc | 917 | * @brief Check if Rx buffer is not empty |
AnnaBridge | 171:3a7713b1edbc | 918 | * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE |
AnnaBridge | 171:3a7713b1edbc | 919 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 920 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 921 | */ |
AnnaBridge | 171:3a7713b1edbc | 922 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 923 | { |
AnnaBridge | 171:3a7713b1edbc | 924 | return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); |
AnnaBridge | 171:3a7713b1edbc | 925 | } |
AnnaBridge | 171:3a7713b1edbc | 926 | |
AnnaBridge | 171:3a7713b1edbc | 927 | /** |
AnnaBridge | 171:3a7713b1edbc | 928 | * @brief Check if Tx buffer is empty |
AnnaBridge | 171:3a7713b1edbc | 929 | * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE |
AnnaBridge | 171:3a7713b1edbc | 930 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 931 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 932 | */ |
AnnaBridge | 171:3a7713b1edbc | 933 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 934 | { |
AnnaBridge | 171:3a7713b1edbc | 935 | return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); |
AnnaBridge | 171:3a7713b1edbc | 936 | } |
AnnaBridge | 171:3a7713b1edbc | 937 | |
AnnaBridge | 171:3a7713b1edbc | 938 | /** |
AnnaBridge | 171:3a7713b1edbc | 939 | * @brief Get CRC error flag |
AnnaBridge | 171:3a7713b1edbc | 940 | * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR |
AnnaBridge | 171:3a7713b1edbc | 941 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 942 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 943 | */ |
AnnaBridge | 171:3a7713b1edbc | 944 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 945 | { |
AnnaBridge | 171:3a7713b1edbc | 946 | return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); |
AnnaBridge | 171:3a7713b1edbc | 947 | } |
AnnaBridge | 171:3a7713b1edbc | 948 | |
AnnaBridge | 171:3a7713b1edbc | 949 | /** |
AnnaBridge | 171:3a7713b1edbc | 950 | * @brief Get mode fault error flag |
AnnaBridge | 171:3a7713b1edbc | 951 | * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF |
AnnaBridge | 171:3a7713b1edbc | 952 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 953 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 954 | */ |
AnnaBridge | 171:3a7713b1edbc | 955 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 956 | { |
AnnaBridge | 171:3a7713b1edbc | 957 | return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); |
AnnaBridge | 171:3a7713b1edbc | 958 | } |
AnnaBridge | 171:3a7713b1edbc | 959 | |
AnnaBridge | 171:3a7713b1edbc | 960 | /** |
AnnaBridge | 171:3a7713b1edbc | 961 | * @brief Get overrun error flag |
AnnaBridge | 171:3a7713b1edbc | 962 | * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR |
AnnaBridge | 171:3a7713b1edbc | 963 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 964 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 965 | */ |
AnnaBridge | 171:3a7713b1edbc | 966 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 967 | { |
AnnaBridge | 171:3a7713b1edbc | 968 | return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); |
AnnaBridge | 171:3a7713b1edbc | 969 | } |
AnnaBridge | 171:3a7713b1edbc | 970 | |
AnnaBridge | 171:3a7713b1edbc | 971 | /** |
AnnaBridge | 171:3a7713b1edbc | 972 | * @brief Get busy flag |
AnnaBridge | 171:3a7713b1edbc | 973 | * @note The BSY flag is cleared under any one of the following conditions: |
AnnaBridge | 171:3a7713b1edbc | 974 | * -When the SPI is correctly disabled |
AnnaBridge | 171:3a7713b1edbc | 975 | * -When a fault is detected in Master mode (MODF bit set to 1) |
AnnaBridge | 171:3a7713b1edbc | 976 | * -In Master mode, when it finishes a data transmission and no new data is ready to be |
AnnaBridge | 171:3a7713b1edbc | 977 | * sent |
AnnaBridge | 171:3a7713b1edbc | 978 | * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between |
AnnaBridge | 171:3a7713b1edbc | 979 | * each data transfer. |
AnnaBridge | 171:3a7713b1edbc | 980 | * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY |
AnnaBridge | 171:3a7713b1edbc | 981 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 982 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 983 | */ |
AnnaBridge | 171:3a7713b1edbc | 984 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 985 | { |
AnnaBridge | 171:3a7713b1edbc | 986 | return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); |
AnnaBridge | 171:3a7713b1edbc | 987 | } |
AnnaBridge | 171:3a7713b1edbc | 988 | |
AnnaBridge | 171:3a7713b1edbc | 989 | /** |
AnnaBridge | 171:3a7713b1edbc | 990 | * @brief Get frame format error flag |
AnnaBridge | 171:3a7713b1edbc | 991 | * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE |
AnnaBridge | 171:3a7713b1edbc | 992 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 993 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 994 | */ |
AnnaBridge | 171:3a7713b1edbc | 995 | __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 996 | { |
AnnaBridge | 171:3a7713b1edbc | 997 | return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); |
AnnaBridge | 171:3a7713b1edbc | 998 | } |
AnnaBridge | 171:3a7713b1edbc | 999 | |
AnnaBridge | 171:3a7713b1edbc | 1000 | /** |
AnnaBridge | 171:3a7713b1edbc | 1001 | * @brief Get FIFO reception Level |
AnnaBridge | 171:3a7713b1edbc | 1002 | * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel |
AnnaBridge | 171:3a7713b1edbc | 1003 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1004 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1005 | * @arg @ref LL_SPI_RX_FIFO_EMPTY |
AnnaBridge | 171:3a7713b1edbc | 1006 | * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL |
AnnaBridge | 171:3a7713b1edbc | 1007 | * @arg @ref LL_SPI_RX_FIFO_HALF_FULL |
AnnaBridge | 171:3a7713b1edbc | 1008 | * @arg @ref LL_SPI_RX_FIFO_FULL |
AnnaBridge | 171:3a7713b1edbc | 1009 | */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1011 | { |
AnnaBridge | 171:3a7713b1edbc | 1012 | return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); |
AnnaBridge | 171:3a7713b1edbc | 1013 | } |
AnnaBridge | 171:3a7713b1edbc | 1014 | |
AnnaBridge | 171:3a7713b1edbc | 1015 | /** |
AnnaBridge | 171:3a7713b1edbc | 1016 | * @brief Get FIFO Transmission Level |
AnnaBridge | 171:3a7713b1edbc | 1017 | * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1019 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @arg @ref LL_SPI_TX_FIFO_EMPTY |
AnnaBridge | 171:3a7713b1edbc | 1021 | * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @arg @ref LL_SPI_TX_FIFO_HALF_FULL |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @arg @ref LL_SPI_TX_FIFO_FULL |
AnnaBridge | 171:3a7713b1edbc | 1024 | */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1026 | { |
AnnaBridge | 171:3a7713b1edbc | 1027 | return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); |
AnnaBridge | 171:3a7713b1edbc | 1028 | } |
AnnaBridge | 171:3a7713b1edbc | 1029 | |
AnnaBridge | 171:3a7713b1edbc | 1030 | /** |
AnnaBridge | 171:3a7713b1edbc | 1031 | * @brief Clear CRC error flag |
AnnaBridge | 171:3a7713b1edbc | 1032 | * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR |
AnnaBridge | 171:3a7713b1edbc | 1033 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1035 | */ |
AnnaBridge | 171:3a7713b1edbc | 1036 | __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1037 | { |
AnnaBridge | 171:3a7713b1edbc | 1038 | CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); |
AnnaBridge | 171:3a7713b1edbc | 1039 | } |
AnnaBridge | 171:3a7713b1edbc | 1040 | |
AnnaBridge | 171:3a7713b1edbc | 1041 | /** |
AnnaBridge | 171:3a7713b1edbc | 1042 | * @brief Clear mode fault error flag |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @note Clearing this flag is done by a read access to the SPIx_SR |
AnnaBridge | 171:3a7713b1edbc | 1044 | * register followed by a write access to the SPIx_CR1 register |
AnnaBridge | 171:3a7713b1edbc | 1045 | * @rmtoll SR MODF LL_SPI_ClearFlag_MODF |
AnnaBridge | 171:3a7713b1edbc | 1046 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1047 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1048 | */ |
AnnaBridge | 171:3a7713b1edbc | 1049 | __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1050 | { |
AnnaBridge | 171:3a7713b1edbc | 1051 | __IO uint32_t tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1052 | tmpreg = SPIx->SR; |
AnnaBridge | 171:3a7713b1edbc | 1053 | (void) tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1054 | tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); |
AnnaBridge | 171:3a7713b1edbc | 1055 | (void) tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1056 | } |
AnnaBridge | 171:3a7713b1edbc | 1057 | |
AnnaBridge | 171:3a7713b1edbc | 1058 | /** |
AnnaBridge | 171:3a7713b1edbc | 1059 | * @brief Clear overrun error flag |
AnnaBridge | 171:3a7713b1edbc | 1060 | * @note Clearing this flag is done by a read access to the SPIx_DR |
AnnaBridge | 171:3a7713b1edbc | 1061 | * register followed by a read access to the SPIx_SR register |
AnnaBridge | 171:3a7713b1edbc | 1062 | * @rmtoll SR OVR LL_SPI_ClearFlag_OVR |
AnnaBridge | 171:3a7713b1edbc | 1063 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1064 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1065 | */ |
AnnaBridge | 171:3a7713b1edbc | 1066 | __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1067 | { |
AnnaBridge | 171:3a7713b1edbc | 1068 | __IO uint32_t tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1069 | tmpreg = SPIx->DR; |
AnnaBridge | 171:3a7713b1edbc | 1070 | (void) tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1071 | tmpreg = SPIx->SR; |
AnnaBridge | 171:3a7713b1edbc | 1072 | (void) tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1073 | } |
AnnaBridge | 171:3a7713b1edbc | 1074 | |
AnnaBridge | 171:3a7713b1edbc | 1075 | /** |
AnnaBridge | 171:3a7713b1edbc | 1076 | * @brief Clear frame format error flag |
AnnaBridge | 171:3a7713b1edbc | 1077 | * @note Clearing this flag is done by reading SPIx_SR register |
AnnaBridge | 171:3a7713b1edbc | 1078 | * @rmtoll SR FRE LL_SPI_ClearFlag_FRE |
AnnaBridge | 171:3a7713b1edbc | 1079 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1080 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1081 | */ |
AnnaBridge | 171:3a7713b1edbc | 1082 | __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1083 | { |
AnnaBridge | 171:3a7713b1edbc | 1084 | __IO uint32_t tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1085 | tmpreg = SPIx->SR; |
AnnaBridge | 171:3a7713b1edbc | 1086 | (void) tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 1087 | } |
AnnaBridge | 171:3a7713b1edbc | 1088 | |
AnnaBridge | 171:3a7713b1edbc | 1089 | /** |
AnnaBridge | 171:3a7713b1edbc | 1090 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1091 | */ |
AnnaBridge | 171:3a7713b1edbc | 1092 | |
AnnaBridge | 171:3a7713b1edbc | 1093 | /** @defgroup SPI_LL_EF_IT_Management Interrupt Management |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1095 | */ |
AnnaBridge | 171:3a7713b1edbc | 1096 | |
AnnaBridge | 171:3a7713b1edbc | 1097 | /** |
AnnaBridge | 171:3a7713b1edbc | 1098 | * @brief Enable error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1099 | * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 1101 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1103 | */ |
AnnaBridge | 171:3a7713b1edbc | 1104 | __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1105 | { |
AnnaBridge | 171:3a7713b1edbc | 1106 | SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); |
AnnaBridge | 171:3a7713b1edbc | 1107 | } |
AnnaBridge | 171:3a7713b1edbc | 1108 | |
AnnaBridge | 171:3a7713b1edbc | 1109 | /** |
AnnaBridge | 171:3a7713b1edbc | 1110 | * @brief Enable Rx buffer not empty interrupt |
AnnaBridge | 171:3a7713b1edbc | 1111 | * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 1112 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1113 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1114 | */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1116 | { |
AnnaBridge | 171:3a7713b1edbc | 1117 | SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); |
AnnaBridge | 171:3a7713b1edbc | 1118 | } |
AnnaBridge | 171:3a7713b1edbc | 1119 | |
AnnaBridge | 171:3a7713b1edbc | 1120 | /** |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @brief Enable Tx buffer empty interrupt |
AnnaBridge | 171:3a7713b1edbc | 1122 | * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 1123 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1125 | */ |
AnnaBridge | 171:3a7713b1edbc | 1126 | __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1127 | { |
AnnaBridge | 171:3a7713b1edbc | 1128 | SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); |
AnnaBridge | 171:3a7713b1edbc | 1129 | } |
AnnaBridge | 171:3a7713b1edbc | 1130 | |
AnnaBridge | 171:3a7713b1edbc | 1131 | /** |
AnnaBridge | 171:3a7713b1edbc | 1132 | * @brief Disable error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1133 | * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). |
AnnaBridge | 171:3a7713b1edbc | 1134 | * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 1135 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1136 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1137 | */ |
AnnaBridge | 171:3a7713b1edbc | 1138 | __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1139 | { |
AnnaBridge | 171:3a7713b1edbc | 1140 | CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); |
AnnaBridge | 171:3a7713b1edbc | 1141 | } |
AnnaBridge | 171:3a7713b1edbc | 1142 | |
AnnaBridge | 171:3a7713b1edbc | 1143 | /** |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @brief Disable Rx buffer not empty interrupt |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1148 | */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1150 | { |
AnnaBridge | 171:3a7713b1edbc | 1151 | CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); |
AnnaBridge | 171:3a7713b1edbc | 1152 | } |
AnnaBridge | 171:3a7713b1edbc | 1153 | |
AnnaBridge | 171:3a7713b1edbc | 1154 | /** |
AnnaBridge | 171:3a7713b1edbc | 1155 | * @brief Disable Tx buffer empty interrupt |
AnnaBridge | 171:3a7713b1edbc | 1156 | * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 1157 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1159 | */ |
AnnaBridge | 171:3a7713b1edbc | 1160 | __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1161 | { |
AnnaBridge | 171:3a7713b1edbc | 1162 | CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); |
AnnaBridge | 171:3a7713b1edbc | 1163 | } |
AnnaBridge | 171:3a7713b1edbc | 1164 | |
AnnaBridge | 171:3a7713b1edbc | 1165 | /** |
AnnaBridge | 171:3a7713b1edbc | 1166 | * @brief Check if error interrupt is enabled |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1169 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1170 | */ |
AnnaBridge | 171:3a7713b1edbc | 1171 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1172 | { |
AnnaBridge | 171:3a7713b1edbc | 1173 | return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); |
AnnaBridge | 171:3a7713b1edbc | 1174 | } |
AnnaBridge | 171:3a7713b1edbc | 1175 | |
AnnaBridge | 171:3a7713b1edbc | 1176 | /** |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @brief Check if Rx buffer not empty interrupt is enabled |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1181 | */ |
AnnaBridge | 171:3a7713b1edbc | 1182 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1183 | { |
AnnaBridge | 171:3a7713b1edbc | 1184 | return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); |
AnnaBridge | 171:3a7713b1edbc | 1185 | } |
AnnaBridge | 171:3a7713b1edbc | 1186 | |
AnnaBridge | 171:3a7713b1edbc | 1187 | /** |
AnnaBridge | 171:3a7713b1edbc | 1188 | * @brief Check if Tx buffer empty interrupt |
AnnaBridge | 171:3a7713b1edbc | 1189 | * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 1190 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1191 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1192 | */ |
AnnaBridge | 171:3a7713b1edbc | 1193 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1194 | { |
AnnaBridge | 171:3a7713b1edbc | 1195 | return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); |
AnnaBridge | 171:3a7713b1edbc | 1196 | } |
AnnaBridge | 171:3a7713b1edbc | 1197 | |
AnnaBridge | 171:3a7713b1edbc | 1198 | /** |
AnnaBridge | 171:3a7713b1edbc | 1199 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1200 | */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | |
AnnaBridge | 171:3a7713b1edbc | 1202 | /** @defgroup SPI_LL_EF_DMA_Management DMA Management |
AnnaBridge | 171:3a7713b1edbc | 1203 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1204 | */ |
AnnaBridge | 171:3a7713b1edbc | 1205 | |
AnnaBridge | 171:3a7713b1edbc | 1206 | /** |
AnnaBridge | 171:3a7713b1edbc | 1207 | * @brief Enable DMA Rx |
AnnaBridge | 171:3a7713b1edbc | 1208 | * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 1209 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1210 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1211 | */ |
AnnaBridge | 171:3a7713b1edbc | 1212 | __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1213 | { |
AnnaBridge | 171:3a7713b1edbc | 1214 | SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); |
AnnaBridge | 171:3a7713b1edbc | 1215 | } |
AnnaBridge | 171:3a7713b1edbc | 1216 | |
AnnaBridge | 171:3a7713b1edbc | 1217 | /** |
AnnaBridge | 171:3a7713b1edbc | 1218 | * @brief Disable DMA Rx |
AnnaBridge | 171:3a7713b1edbc | 1219 | * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 1220 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1221 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1222 | */ |
AnnaBridge | 171:3a7713b1edbc | 1223 | __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1224 | { |
AnnaBridge | 171:3a7713b1edbc | 1225 | CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); |
AnnaBridge | 171:3a7713b1edbc | 1226 | } |
AnnaBridge | 171:3a7713b1edbc | 1227 | |
AnnaBridge | 171:3a7713b1edbc | 1228 | /** |
AnnaBridge | 171:3a7713b1edbc | 1229 | * @brief Check if DMA Rx is enabled |
AnnaBridge | 171:3a7713b1edbc | 1230 | * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 1231 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1232 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1233 | */ |
AnnaBridge | 171:3a7713b1edbc | 1234 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1235 | { |
AnnaBridge | 171:3a7713b1edbc | 1236 | return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); |
AnnaBridge | 171:3a7713b1edbc | 1237 | } |
AnnaBridge | 171:3a7713b1edbc | 1238 | |
AnnaBridge | 171:3a7713b1edbc | 1239 | /** |
AnnaBridge | 171:3a7713b1edbc | 1240 | * @brief Enable DMA Tx |
AnnaBridge | 171:3a7713b1edbc | 1241 | * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1244 | */ |
AnnaBridge | 171:3a7713b1edbc | 1245 | __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1246 | { |
AnnaBridge | 171:3a7713b1edbc | 1247 | SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); |
AnnaBridge | 171:3a7713b1edbc | 1248 | } |
AnnaBridge | 171:3a7713b1edbc | 1249 | |
AnnaBridge | 171:3a7713b1edbc | 1250 | /** |
AnnaBridge | 171:3a7713b1edbc | 1251 | * @brief Disable DMA Tx |
AnnaBridge | 171:3a7713b1edbc | 1252 | * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 1253 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1254 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1255 | */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1257 | { |
AnnaBridge | 171:3a7713b1edbc | 1258 | CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); |
AnnaBridge | 171:3a7713b1edbc | 1259 | } |
AnnaBridge | 171:3a7713b1edbc | 1260 | |
AnnaBridge | 171:3a7713b1edbc | 1261 | /** |
AnnaBridge | 171:3a7713b1edbc | 1262 | * @brief Check if DMA Tx is enabled |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 1264 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1265 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1266 | */ |
AnnaBridge | 171:3a7713b1edbc | 1267 | __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1268 | { |
AnnaBridge | 171:3a7713b1edbc | 1269 | return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); |
AnnaBridge | 171:3a7713b1edbc | 1270 | } |
AnnaBridge | 171:3a7713b1edbc | 1271 | |
AnnaBridge | 171:3a7713b1edbc | 1272 | /** |
AnnaBridge | 171:3a7713b1edbc | 1273 | * @brief Set parity of Last DMA reception |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @param Parity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @arg @ref LL_SPI_DMA_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1278 | * @arg @ref LL_SPI_DMA_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1279 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1280 | */ |
AnnaBridge | 171:3a7713b1edbc | 1281 | __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) |
AnnaBridge | 171:3a7713b1edbc | 1282 | { |
AnnaBridge | 171:3a7713b1edbc | 1283 | MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); |
AnnaBridge | 171:3a7713b1edbc | 1284 | } |
AnnaBridge | 171:3a7713b1edbc | 1285 | |
AnnaBridge | 171:3a7713b1edbc | 1286 | /** |
AnnaBridge | 171:3a7713b1edbc | 1287 | * @brief Get parity configuration for Last DMA reception |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX |
AnnaBridge | 171:3a7713b1edbc | 1289 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1290 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1291 | * @arg @ref LL_SPI_DMA_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1292 | * @arg @ref LL_SPI_DMA_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1293 | */ |
AnnaBridge | 171:3a7713b1edbc | 1294 | __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1295 | { |
AnnaBridge | 171:3a7713b1edbc | 1296 | return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); |
AnnaBridge | 171:3a7713b1edbc | 1297 | } |
AnnaBridge | 171:3a7713b1edbc | 1298 | |
AnnaBridge | 171:3a7713b1edbc | 1299 | /** |
AnnaBridge | 171:3a7713b1edbc | 1300 | * @brief Set parity of Last DMA transmission |
AnnaBridge | 171:3a7713b1edbc | 1301 | * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX |
AnnaBridge | 171:3a7713b1edbc | 1302 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1303 | * @param Parity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1304 | * @arg @ref LL_SPI_DMA_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1305 | * @arg @ref LL_SPI_DMA_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1306 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1307 | */ |
AnnaBridge | 171:3a7713b1edbc | 1308 | __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) |
AnnaBridge | 171:3a7713b1edbc | 1309 | { |
AnnaBridge | 171:3a7713b1edbc | 1310 | MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); |
AnnaBridge | 171:3a7713b1edbc | 1311 | } |
AnnaBridge | 171:3a7713b1edbc | 1312 | |
AnnaBridge | 171:3a7713b1edbc | 1313 | /** |
AnnaBridge | 171:3a7713b1edbc | 1314 | * @brief Get parity configuration for Last DMA transmission |
AnnaBridge | 171:3a7713b1edbc | 1315 | * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX |
AnnaBridge | 171:3a7713b1edbc | 1316 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1317 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1318 | * @arg @ref LL_SPI_DMA_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1319 | * @arg @ref LL_SPI_DMA_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1320 | */ |
AnnaBridge | 171:3a7713b1edbc | 1321 | __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1322 | { |
AnnaBridge | 171:3a7713b1edbc | 1323 | return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); |
AnnaBridge | 171:3a7713b1edbc | 1324 | } |
AnnaBridge | 171:3a7713b1edbc | 1325 | |
AnnaBridge | 171:3a7713b1edbc | 1326 | /** |
AnnaBridge | 171:3a7713b1edbc | 1327 | * @brief Get the data register address used for DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 1328 | * @rmtoll DR DR LL_SPI_DMA_GetRegAddr |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @retval Address of data register |
AnnaBridge | 171:3a7713b1edbc | 1331 | */ |
AnnaBridge | 171:3a7713b1edbc | 1332 | __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1333 | { |
AnnaBridge | 171:3a7713b1edbc | 1334 | return (uint32_t) & (SPIx->DR); |
AnnaBridge | 171:3a7713b1edbc | 1335 | } |
AnnaBridge | 171:3a7713b1edbc | 1336 | |
AnnaBridge | 171:3a7713b1edbc | 1337 | /** |
AnnaBridge | 171:3a7713b1edbc | 1338 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1339 | */ |
AnnaBridge | 171:3a7713b1edbc | 1340 | |
AnnaBridge | 171:3a7713b1edbc | 1341 | /** @defgroup SPI_LL_EF_DATA_Management DATA Management |
AnnaBridge | 171:3a7713b1edbc | 1342 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1343 | */ |
AnnaBridge | 171:3a7713b1edbc | 1344 | |
AnnaBridge | 171:3a7713b1edbc | 1345 | /** |
AnnaBridge | 171:3a7713b1edbc | 1346 | * @brief Read 8-Bits in the data register |
AnnaBridge | 171:3a7713b1edbc | 1347 | * @rmtoll DR DR LL_SPI_ReceiveData8 |
AnnaBridge | 171:3a7713b1edbc | 1348 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1349 | * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1350 | */ |
AnnaBridge | 171:3a7713b1edbc | 1351 | __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1352 | { |
AnnaBridge | 171:3a7713b1edbc | 1353 | return (uint8_t)(READ_REG(SPIx->DR)); |
AnnaBridge | 171:3a7713b1edbc | 1354 | } |
AnnaBridge | 171:3a7713b1edbc | 1355 | |
AnnaBridge | 171:3a7713b1edbc | 1356 | /** |
AnnaBridge | 171:3a7713b1edbc | 1357 | * @brief Read 16-Bits in the data register |
AnnaBridge | 171:3a7713b1edbc | 1358 | * @rmtoll DR DR LL_SPI_ReceiveData16 |
AnnaBridge | 171:3a7713b1edbc | 1359 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1360 | * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 1361 | */ |
AnnaBridge | 171:3a7713b1edbc | 1362 | __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1363 | { |
AnnaBridge | 171:3a7713b1edbc | 1364 | return (uint16_t)(READ_REG(SPIx->DR)); |
AnnaBridge | 171:3a7713b1edbc | 1365 | } |
AnnaBridge | 171:3a7713b1edbc | 1366 | |
AnnaBridge | 171:3a7713b1edbc | 1367 | /** |
AnnaBridge | 171:3a7713b1edbc | 1368 | * @brief Write 8-Bits in the data register |
AnnaBridge | 171:3a7713b1edbc | 1369 | * @rmtoll DR DR LL_SPI_TransmitData8 |
AnnaBridge | 171:3a7713b1edbc | 1370 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1371 | * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1372 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1373 | */ |
AnnaBridge | 171:3a7713b1edbc | 1374 | __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) |
AnnaBridge | 171:3a7713b1edbc | 1375 | { |
AnnaBridge | 171:3a7713b1edbc | 1376 | *((__IO uint8_t *)&SPIx->DR) = TxData; |
AnnaBridge | 171:3a7713b1edbc | 1377 | } |
AnnaBridge | 171:3a7713b1edbc | 1378 | |
AnnaBridge | 171:3a7713b1edbc | 1379 | #if __GNUC__ |
AnnaBridge | 171:3a7713b1edbc | 1380 | # define MAY_ALIAS __attribute__ ((__may_alias__)) |
AnnaBridge | 171:3a7713b1edbc | 1381 | #else |
AnnaBridge | 171:3a7713b1edbc | 1382 | # define MAY_ALIAS |
AnnaBridge | 171:3a7713b1edbc | 1383 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1384 | |
AnnaBridge | 171:3a7713b1edbc | 1385 | typedef __IO uint16_t MAY_ALIAS uint16_io_t; |
AnnaBridge | 171:3a7713b1edbc | 1386 | |
AnnaBridge | 171:3a7713b1edbc | 1387 | /** |
AnnaBridge | 171:3a7713b1edbc | 1388 | * @brief Write 16-Bits in the data register |
AnnaBridge | 171:3a7713b1edbc | 1389 | * @rmtoll DR DR LL_SPI_TransmitData16 |
AnnaBridge | 171:3a7713b1edbc | 1390 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1393 | */ |
AnnaBridge | 171:3a7713b1edbc | 1394 | __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) |
AnnaBridge | 171:3a7713b1edbc | 1395 | { |
AnnaBridge | 171:3a7713b1edbc | 1396 | *((uint16_io_t*)&SPIx->DR) = TxData; |
AnnaBridge | 171:3a7713b1edbc | 1397 | } |
AnnaBridge | 171:3a7713b1edbc | 1398 | |
AnnaBridge | 171:3a7713b1edbc | 1399 | /** |
AnnaBridge | 171:3a7713b1edbc | 1400 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1401 | */ |
AnnaBridge | 171:3a7713b1edbc | 1402 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 1403 | /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 1404 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1405 | */ |
AnnaBridge | 171:3a7713b1edbc | 1406 | |
AnnaBridge | 171:3a7713b1edbc | 1407 | ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1408 | ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 1409 | void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 1410 | |
AnnaBridge | 171:3a7713b1edbc | 1411 | /** |
AnnaBridge | 171:3a7713b1edbc | 1412 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1413 | */ |
AnnaBridge | 171:3a7713b1edbc | 1414 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 1415 | /** |
AnnaBridge | 171:3a7713b1edbc | 1416 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1417 | */ |
AnnaBridge | 171:3a7713b1edbc | 1418 | |
AnnaBridge | 171:3a7713b1edbc | 1419 | /** |
AnnaBridge | 171:3a7713b1edbc | 1420 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1421 | */ |
AnnaBridge | 171:3a7713b1edbc | 1422 | |
AnnaBridge | 171:3a7713b1edbc | 1423 | #if defined(SPI_I2S_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1424 | /** @defgroup I2S_LL I2S |
AnnaBridge | 171:3a7713b1edbc | 1425 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1426 | */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | |
AnnaBridge | 171:3a7713b1edbc | 1428 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1429 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1430 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1431 | |
AnnaBridge | 171:3a7713b1edbc | 1432 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1433 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 1434 | /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 1435 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1436 | */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | |
AnnaBridge | 171:3a7713b1edbc | 1438 | /** |
AnnaBridge | 171:3a7713b1edbc | 1439 | * @brief I2S Init structure definition |
AnnaBridge | 171:3a7713b1edbc | 1440 | */ |
AnnaBridge | 171:3a7713b1edbc | 1441 | |
AnnaBridge | 171:3a7713b1edbc | 1442 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 1443 | { |
AnnaBridge | 171:3a7713b1edbc | 1444 | uint32_t Mode; /*!< Specifies the I2S operating mode. |
AnnaBridge | 171:3a7713b1edbc | 1445 | This parameter can be a value of @ref I2S_LL_EC_MODE |
AnnaBridge | 171:3a7713b1edbc | 1446 | |
AnnaBridge | 171:3a7713b1edbc | 1447 | This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 1448 | |
AnnaBridge | 171:3a7713b1edbc | 1449 | uint32_t Standard; /*!< Specifies the standard used for the I2S communication. |
AnnaBridge | 171:3a7713b1edbc | 1450 | This parameter can be a value of @ref I2S_LL_EC_STANDARD |
AnnaBridge | 171:3a7713b1edbc | 1451 | |
AnnaBridge | 171:3a7713b1edbc | 1452 | This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ |
AnnaBridge | 171:3a7713b1edbc | 1453 | |
AnnaBridge | 171:3a7713b1edbc | 1454 | |
AnnaBridge | 171:3a7713b1edbc | 1455 | uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. |
AnnaBridge | 171:3a7713b1edbc | 1456 | This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT |
AnnaBridge | 171:3a7713b1edbc | 1457 | |
AnnaBridge | 171:3a7713b1edbc | 1458 | This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ |
AnnaBridge | 171:3a7713b1edbc | 1459 | |
AnnaBridge | 171:3a7713b1edbc | 1460 | |
AnnaBridge | 171:3a7713b1edbc | 1461 | uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 1462 | This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT |
AnnaBridge | 171:3a7713b1edbc | 1463 | |
AnnaBridge | 171:3a7713b1edbc | 1464 | This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ |
AnnaBridge | 171:3a7713b1edbc | 1465 | |
AnnaBridge | 171:3a7713b1edbc | 1466 | |
AnnaBridge | 171:3a7713b1edbc | 1467 | uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
AnnaBridge | 171:3a7713b1edbc | 1468 | This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ |
AnnaBridge | 171:3a7713b1edbc | 1469 | |
AnnaBridge | 171:3a7713b1edbc | 1470 | Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity |
AnnaBridge | 171:3a7713b1edbc | 1471 | and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ |
AnnaBridge | 171:3a7713b1edbc | 1472 | |
AnnaBridge | 171:3a7713b1edbc | 1473 | |
AnnaBridge | 171:3a7713b1edbc | 1474 | uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. |
AnnaBridge | 171:3a7713b1edbc | 1475 | This parameter can be a value of @ref I2S_LL_EC_POLARITY |
AnnaBridge | 171:3a7713b1edbc | 1476 | |
AnnaBridge | 171:3a7713b1edbc | 1477 | This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 1478 | |
AnnaBridge | 171:3a7713b1edbc | 1479 | } LL_I2S_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 1480 | |
AnnaBridge | 171:3a7713b1edbc | 1481 | /** |
AnnaBridge | 171:3a7713b1edbc | 1482 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1483 | */ |
AnnaBridge | 171:3a7713b1edbc | 1484 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 1485 | |
AnnaBridge | 171:3a7713b1edbc | 1486 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1487 | /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 1488 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1489 | */ |
AnnaBridge | 171:3a7713b1edbc | 1490 | |
AnnaBridge | 171:3a7713b1edbc | 1491 | /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 1492 | * @brief Flags defines which can be used with LL_I2S_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 1493 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1494 | */ |
AnnaBridge | 171:3a7713b1edbc | 1495 | #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ |
AnnaBridge | 171:3a7713b1edbc | 1496 | #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ |
AnnaBridge | 171:3a7713b1edbc | 1499 | #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ |
AnnaBridge | 171:3a7713b1edbc | 1501 | /** |
AnnaBridge | 171:3a7713b1edbc | 1502 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1503 | */ |
AnnaBridge | 171:3a7713b1edbc | 1504 | |
AnnaBridge | 171:3a7713b1edbc | 1505 | /** @defgroup SPI_LL_EC_IT IT Defines |
AnnaBridge | 171:3a7713b1edbc | 1506 | * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions |
AnnaBridge | 171:3a7713b1edbc | 1507 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1508 | */ |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1512 | /** |
AnnaBridge | 171:3a7713b1edbc | 1513 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1514 | */ |
AnnaBridge | 171:3a7713b1edbc | 1515 | |
AnnaBridge | 171:3a7713b1edbc | 1516 | /** @defgroup I2S_LL_EC_DATA_FORMAT Data format |
AnnaBridge | 171:3a7713b1edbc | 1517 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1518 | */ |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ |
AnnaBridge | 171:3a7713b1edbc | 1520 | #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ |
AnnaBridge | 171:3a7713b1edbc | 1521 | #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ |
AnnaBridge | 171:3a7713b1edbc | 1522 | #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ |
AnnaBridge | 171:3a7713b1edbc | 1523 | /** |
AnnaBridge | 171:3a7713b1edbc | 1524 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1525 | */ |
AnnaBridge | 171:3a7713b1edbc | 1526 | |
AnnaBridge | 171:3a7713b1edbc | 1527 | /** @defgroup I2S_LL_EC_POLARITY Clock Polarity |
AnnaBridge | 171:3a7713b1edbc | 1528 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1529 | */ |
AnnaBridge | 171:3a7713b1edbc | 1530 | #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ |
AnnaBridge | 171:3a7713b1edbc | 1532 | /** |
AnnaBridge | 171:3a7713b1edbc | 1533 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1534 | */ |
AnnaBridge | 171:3a7713b1edbc | 1535 | |
AnnaBridge | 171:3a7713b1edbc | 1536 | /** @defgroup I2S_LL_EC_STANDARD I2s Standard |
AnnaBridge | 171:3a7713b1edbc | 1537 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1538 | */ |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ |
AnnaBridge | 171:3a7713b1edbc | 1542 | #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 1543 | #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | /** |
AnnaBridge | 171:3a7713b1edbc | 1545 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1546 | */ |
AnnaBridge | 171:3a7713b1edbc | 1547 | |
AnnaBridge | 171:3a7713b1edbc | 1548 | /** @defgroup I2S_LL_EC_MODE Operation Mode |
AnnaBridge | 171:3a7713b1edbc | 1549 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1550 | */ |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1552 | #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1554 | #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1555 | /** |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1557 | */ |
AnnaBridge | 171:3a7713b1edbc | 1558 | |
AnnaBridge | 171:3a7713b1edbc | 1559 | /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor |
AnnaBridge | 171:3a7713b1edbc | 1560 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1561 | */ |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ |
AnnaBridge | 171:3a7713b1edbc | 1564 | /** |
AnnaBridge | 171:3a7713b1edbc | 1565 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1566 | */ |
AnnaBridge | 171:3a7713b1edbc | 1567 | |
AnnaBridge | 171:3a7713b1edbc | 1568 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 1569 | |
AnnaBridge | 171:3a7713b1edbc | 1570 | /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output |
AnnaBridge | 171:3a7713b1edbc | 1571 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1572 | */ |
AnnaBridge | 171:3a7713b1edbc | 1573 | #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ |
AnnaBridge | 171:3a7713b1edbc | 1574 | #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ |
AnnaBridge | 171:3a7713b1edbc | 1575 | /** |
AnnaBridge | 171:3a7713b1edbc | 1576 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1577 | */ |
AnnaBridge | 171:3a7713b1edbc | 1578 | |
AnnaBridge | 171:3a7713b1edbc | 1579 | /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency |
AnnaBridge | 171:3a7713b1edbc | 1580 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1581 | */ |
AnnaBridge | 171:3a7713b1edbc | 1582 | |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1584 | #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1586 | #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1588 | #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1590 | #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ |
AnnaBridge | 171:3a7713b1edbc | 1593 | /** |
AnnaBridge | 171:3a7713b1edbc | 1594 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1595 | */ |
AnnaBridge | 171:3a7713b1edbc | 1596 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 1597 | |
AnnaBridge | 171:3a7713b1edbc | 1598 | /** |
AnnaBridge | 171:3a7713b1edbc | 1599 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1600 | */ |
AnnaBridge | 171:3a7713b1edbc | 1601 | |
AnnaBridge | 171:3a7713b1edbc | 1602 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1603 | /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 1604 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1605 | */ |
AnnaBridge | 171:3a7713b1edbc | 1606 | |
AnnaBridge | 171:3a7713b1edbc | 1607 | /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 171:3a7713b1edbc | 1608 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1609 | */ |
AnnaBridge | 171:3a7713b1edbc | 1610 | |
AnnaBridge | 171:3a7713b1edbc | 1611 | /** |
AnnaBridge | 171:3a7713b1edbc | 1612 | * @brief Write a value in I2S register |
AnnaBridge | 171:3a7713b1edbc | 1613 | * @param __INSTANCE__ I2S Instance |
AnnaBridge | 171:3a7713b1edbc | 1614 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 1615 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 1616 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1617 | */ |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 1619 | |
AnnaBridge | 171:3a7713b1edbc | 1620 | /** |
AnnaBridge | 171:3a7713b1edbc | 1621 | * @brief Read a value in I2S register |
AnnaBridge | 171:3a7713b1edbc | 1622 | * @param __INSTANCE__ I2S Instance |
AnnaBridge | 171:3a7713b1edbc | 1623 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 1624 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 1625 | */ |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 1627 | /** |
AnnaBridge | 171:3a7713b1edbc | 1628 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1629 | */ |
AnnaBridge | 171:3a7713b1edbc | 1630 | |
AnnaBridge | 171:3a7713b1edbc | 1631 | /** |
AnnaBridge | 171:3a7713b1edbc | 1632 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1633 | */ |
AnnaBridge | 171:3a7713b1edbc | 1634 | |
AnnaBridge | 171:3a7713b1edbc | 1635 | |
AnnaBridge | 171:3a7713b1edbc | 1636 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1637 | |
AnnaBridge | 171:3a7713b1edbc | 1638 | /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 1639 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1640 | */ |
AnnaBridge | 171:3a7713b1edbc | 1641 | |
AnnaBridge | 171:3a7713b1edbc | 1642 | /** @defgroup I2S_LL_EF_Configuration Configuration |
AnnaBridge | 171:3a7713b1edbc | 1643 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1644 | */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | |
AnnaBridge | 171:3a7713b1edbc | 1646 | /** |
AnnaBridge | 171:3a7713b1edbc | 1647 | * @brief Select I2S mode and Enable I2S peripheral |
AnnaBridge | 171:3a7713b1edbc | 1648 | * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n |
AnnaBridge | 171:3a7713b1edbc | 1649 | * I2SCFGR I2SE LL_I2S_Enable |
AnnaBridge | 171:3a7713b1edbc | 1650 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1651 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1652 | */ |
AnnaBridge | 171:3a7713b1edbc | 1653 | __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1654 | { |
AnnaBridge | 171:3a7713b1edbc | 1655 | SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); |
AnnaBridge | 171:3a7713b1edbc | 1656 | } |
AnnaBridge | 171:3a7713b1edbc | 1657 | |
AnnaBridge | 171:3a7713b1edbc | 1658 | /** |
AnnaBridge | 171:3a7713b1edbc | 1659 | * @brief Disable I2S peripheral |
AnnaBridge | 171:3a7713b1edbc | 1660 | * @rmtoll I2SCFGR I2SE LL_I2S_Disable |
AnnaBridge | 171:3a7713b1edbc | 1661 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1662 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1663 | */ |
AnnaBridge | 171:3a7713b1edbc | 1664 | __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1665 | { |
AnnaBridge | 171:3a7713b1edbc | 1666 | CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); |
AnnaBridge | 171:3a7713b1edbc | 1667 | } |
AnnaBridge | 171:3a7713b1edbc | 1668 | |
AnnaBridge | 171:3a7713b1edbc | 1669 | /** |
AnnaBridge | 171:3a7713b1edbc | 1670 | * @brief Check if I2S peripheral is enabled |
AnnaBridge | 171:3a7713b1edbc | 1671 | * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled |
AnnaBridge | 171:3a7713b1edbc | 1672 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1673 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1674 | */ |
AnnaBridge | 171:3a7713b1edbc | 1675 | __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1676 | { |
AnnaBridge | 171:3a7713b1edbc | 1677 | return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)); |
AnnaBridge | 171:3a7713b1edbc | 1678 | } |
AnnaBridge | 171:3a7713b1edbc | 1679 | |
AnnaBridge | 171:3a7713b1edbc | 1680 | /** |
AnnaBridge | 171:3a7713b1edbc | 1681 | * @brief Set I2S data frame length |
AnnaBridge | 171:3a7713b1edbc | 1682 | * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n |
AnnaBridge | 171:3a7713b1edbc | 1683 | * I2SCFGR CHLEN LL_I2S_SetDataFormat |
AnnaBridge | 171:3a7713b1edbc | 1684 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1685 | * @param DataFormat This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1686 | * @arg @ref LL_I2S_DATAFORMAT_16B |
AnnaBridge | 171:3a7713b1edbc | 1687 | * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED |
AnnaBridge | 171:3a7713b1edbc | 1688 | * @arg @ref LL_I2S_DATAFORMAT_24B |
AnnaBridge | 171:3a7713b1edbc | 1689 | * @arg @ref LL_I2S_DATAFORMAT_32B |
AnnaBridge | 171:3a7713b1edbc | 1690 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1691 | */ |
AnnaBridge | 171:3a7713b1edbc | 1692 | __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) |
AnnaBridge | 171:3a7713b1edbc | 1693 | { |
AnnaBridge | 171:3a7713b1edbc | 1694 | MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); |
AnnaBridge | 171:3a7713b1edbc | 1695 | } |
AnnaBridge | 171:3a7713b1edbc | 1696 | |
AnnaBridge | 171:3a7713b1edbc | 1697 | /** |
AnnaBridge | 171:3a7713b1edbc | 1698 | * @brief Get I2S data frame length |
AnnaBridge | 171:3a7713b1edbc | 1699 | * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n |
AnnaBridge | 171:3a7713b1edbc | 1700 | * I2SCFGR CHLEN LL_I2S_GetDataFormat |
AnnaBridge | 171:3a7713b1edbc | 1701 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1702 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1703 | * @arg @ref LL_I2S_DATAFORMAT_16B |
AnnaBridge | 171:3a7713b1edbc | 1704 | * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED |
AnnaBridge | 171:3a7713b1edbc | 1705 | * @arg @ref LL_I2S_DATAFORMAT_24B |
AnnaBridge | 171:3a7713b1edbc | 1706 | * @arg @ref LL_I2S_DATAFORMAT_32B |
AnnaBridge | 171:3a7713b1edbc | 1707 | */ |
AnnaBridge | 171:3a7713b1edbc | 1708 | __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1709 | { |
AnnaBridge | 171:3a7713b1edbc | 1710 | return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); |
AnnaBridge | 171:3a7713b1edbc | 1711 | } |
AnnaBridge | 171:3a7713b1edbc | 1712 | |
AnnaBridge | 171:3a7713b1edbc | 1713 | /** |
AnnaBridge | 171:3a7713b1edbc | 1714 | * @brief Set I2S clock polarity |
AnnaBridge | 171:3a7713b1edbc | 1715 | * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity |
AnnaBridge | 171:3a7713b1edbc | 1716 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1717 | * @param ClockPolarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1718 | * @arg @ref LL_I2S_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 1719 | * @arg @ref LL_I2S_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1720 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1721 | */ |
AnnaBridge | 171:3a7713b1edbc | 1722 | __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) |
AnnaBridge | 171:3a7713b1edbc | 1723 | { |
AnnaBridge | 171:3a7713b1edbc | 1724 | SET_BIT(SPIx->I2SCFGR, ClockPolarity); |
AnnaBridge | 171:3a7713b1edbc | 1725 | } |
AnnaBridge | 171:3a7713b1edbc | 1726 | |
AnnaBridge | 171:3a7713b1edbc | 1727 | /** |
AnnaBridge | 171:3a7713b1edbc | 1728 | * @brief Get I2S clock polarity |
AnnaBridge | 171:3a7713b1edbc | 1729 | * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity |
AnnaBridge | 171:3a7713b1edbc | 1730 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1731 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1732 | * @arg @ref LL_I2S_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 1733 | * @arg @ref LL_I2S_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1734 | */ |
AnnaBridge | 171:3a7713b1edbc | 1735 | __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1736 | { |
AnnaBridge | 171:3a7713b1edbc | 1737 | return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); |
AnnaBridge | 171:3a7713b1edbc | 1738 | } |
AnnaBridge | 171:3a7713b1edbc | 1739 | |
AnnaBridge | 171:3a7713b1edbc | 1740 | /** |
AnnaBridge | 171:3a7713b1edbc | 1741 | * @brief Set I2S standard protocol |
AnnaBridge | 171:3a7713b1edbc | 1742 | * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n |
AnnaBridge | 171:3a7713b1edbc | 1743 | * I2SCFGR PCMSYNC LL_I2S_SetStandard |
AnnaBridge | 171:3a7713b1edbc | 1744 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1745 | * @param Standard This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1746 | * @arg @ref LL_I2S_STANDARD_PHILIPS |
AnnaBridge | 171:3a7713b1edbc | 1747 | * @arg @ref LL_I2S_STANDARD_MSB |
AnnaBridge | 171:3a7713b1edbc | 1748 | * @arg @ref LL_I2S_STANDARD_LSB |
AnnaBridge | 171:3a7713b1edbc | 1749 | * @arg @ref LL_I2S_STANDARD_PCM_SHORT |
AnnaBridge | 171:3a7713b1edbc | 1750 | * @arg @ref LL_I2S_STANDARD_PCM_LONG |
AnnaBridge | 171:3a7713b1edbc | 1751 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1752 | */ |
AnnaBridge | 171:3a7713b1edbc | 1753 | __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) |
AnnaBridge | 171:3a7713b1edbc | 1754 | { |
AnnaBridge | 171:3a7713b1edbc | 1755 | MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); |
AnnaBridge | 171:3a7713b1edbc | 1756 | } |
AnnaBridge | 171:3a7713b1edbc | 1757 | |
AnnaBridge | 171:3a7713b1edbc | 1758 | /** |
AnnaBridge | 171:3a7713b1edbc | 1759 | * @brief Get I2S standard protocol |
AnnaBridge | 171:3a7713b1edbc | 1760 | * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n |
AnnaBridge | 171:3a7713b1edbc | 1761 | * I2SCFGR PCMSYNC LL_I2S_GetStandard |
AnnaBridge | 171:3a7713b1edbc | 1762 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1763 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1764 | * @arg @ref LL_I2S_STANDARD_PHILIPS |
AnnaBridge | 171:3a7713b1edbc | 1765 | * @arg @ref LL_I2S_STANDARD_MSB |
AnnaBridge | 171:3a7713b1edbc | 1766 | * @arg @ref LL_I2S_STANDARD_LSB |
AnnaBridge | 171:3a7713b1edbc | 1767 | * @arg @ref LL_I2S_STANDARD_PCM_SHORT |
AnnaBridge | 171:3a7713b1edbc | 1768 | * @arg @ref LL_I2S_STANDARD_PCM_LONG |
AnnaBridge | 171:3a7713b1edbc | 1769 | */ |
AnnaBridge | 171:3a7713b1edbc | 1770 | __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1771 | { |
AnnaBridge | 171:3a7713b1edbc | 1772 | return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); |
AnnaBridge | 171:3a7713b1edbc | 1773 | } |
AnnaBridge | 171:3a7713b1edbc | 1774 | |
AnnaBridge | 171:3a7713b1edbc | 1775 | /** |
AnnaBridge | 171:3a7713b1edbc | 1776 | * @brief Set I2S transfer mode |
AnnaBridge | 171:3a7713b1edbc | 1777 | * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode |
AnnaBridge | 171:3a7713b1edbc | 1778 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1779 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1780 | * @arg @ref LL_I2S_MODE_SLAVE_TX |
AnnaBridge | 171:3a7713b1edbc | 1781 | * @arg @ref LL_I2S_MODE_SLAVE_RX |
AnnaBridge | 171:3a7713b1edbc | 1782 | * @arg @ref LL_I2S_MODE_MASTER_TX |
AnnaBridge | 171:3a7713b1edbc | 1783 | * @arg @ref LL_I2S_MODE_MASTER_RX |
AnnaBridge | 171:3a7713b1edbc | 1784 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1785 | */ |
AnnaBridge | 171:3a7713b1edbc | 1786 | __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) |
AnnaBridge | 171:3a7713b1edbc | 1787 | { |
AnnaBridge | 171:3a7713b1edbc | 1788 | MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); |
AnnaBridge | 171:3a7713b1edbc | 1789 | } |
AnnaBridge | 171:3a7713b1edbc | 1790 | |
AnnaBridge | 171:3a7713b1edbc | 1791 | /** |
AnnaBridge | 171:3a7713b1edbc | 1792 | * @brief Get I2S transfer mode |
AnnaBridge | 171:3a7713b1edbc | 1793 | * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode |
AnnaBridge | 171:3a7713b1edbc | 1794 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1795 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1796 | * @arg @ref LL_I2S_MODE_SLAVE_TX |
AnnaBridge | 171:3a7713b1edbc | 1797 | * @arg @ref LL_I2S_MODE_SLAVE_RX |
AnnaBridge | 171:3a7713b1edbc | 1798 | * @arg @ref LL_I2S_MODE_MASTER_TX |
AnnaBridge | 171:3a7713b1edbc | 1799 | * @arg @ref LL_I2S_MODE_MASTER_RX |
AnnaBridge | 171:3a7713b1edbc | 1800 | */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1802 | { |
AnnaBridge | 171:3a7713b1edbc | 1803 | return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); |
AnnaBridge | 171:3a7713b1edbc | 1804 | } |
AnnaBridge | 171:3a7713b1edbc | 1805 | |
AnnaBridge | 171:3a7713b1edbc | 1806 | /** |
AnnaBridge | 171:3a7713b1edbc | 1807 | * @brief Set I2S linear prescaler |
AnnaBridge | 171:3a7713b1edbc | 1808 | * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear |
AnnaBridge | 171:3a7713b1edbc | 1809 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1810 | * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1811 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1812 | */ |
AnnaBridge | 171:3a7713b1edbc | 1813 | __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) |
AnnaBridge | 171:3a7713b1edbc | 1814 | { |
AnnaBridge | 171:3a7713b1edbc | 1815 | MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); |
AnnaBridge | 171:3a7713b1edbc | 1816 | } |
AnnaBridge | 171:3a7713b1edbc | 1817 | |
AnnaBridge | 171:3a7713b1edbc | 1818 | /** |
AnnaBridge | 171:3a7713b1edbc | 1819 | * @brief Get I2S linear prescaler |
AnnaBridge | 171:3a7713b1edbc | 1820 | * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear |
AnnaBridge | 171:3a7713b1edbc | 1821 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1822 | * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1823 | */ |
AnnaBridge | 171:3a7713b1edbc | 1824 | __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1825 | { |
AnnaBridge | 171:3a7713b1edbc | 1826 | return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); |
AnnaBridge | 171:3a7713b1edbc | 1827 | } |
AnnaBridge | 171:3a7713b1edbc | 1828 | |
AnnaBridge | 171:3a7713b1edbc | 1829 | /** |
AnnaBridge | 171:3a7713b1edbc | 1830 | * @brief Set I2S parity prescaler |
AnnaBridge | 171:3a7713b1edbc | 1831 | * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity |
AnnaBridge | 171:3a7713b1edbc | 1832 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1833 | * @param PrescalerParity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1834 | * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1835 | * @arg @ref LL_I2S_PRESCALER_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1836 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1837 | */ |
AnnaBridge | 171:3a7713b1edbc | 1838 | __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) |
AnnaBridge | 171:3a7713b1edbc | 1839 | { |
AnnaBridge | 171:3a7713b1edbc | 1840 | MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); |
AnnaBridge | 171:3a7713b1edbc | 1841 | } |
AnnaBridge | 171:3a7713b1edbc | 1842 | |
AnnaBridge | 171:3a7713b1edbc | 1843 | /** |
AnnaBridge | 171:3a7713b1edbc | 1844 | * @brief Get I2S parity prescaler |
AnnaBridge | 171:3a7713b1edbc | 1845 | * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity |
AnnaBridge | 171:3a7713b1edbc | 1846 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1847 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1848 | * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN |
AnnaBridge | 171:3a7713b1edbc | 1849 | * @arg @ref LL_I2S_PRESCALER_PARITY_ODD |
AnnaBridge | 171:3a7713b1edbc | 1850 | */ |
AnnaBridge | 171:3a7713b1edbc | 1851 | __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1852 | { |
AnnaBridge | 171:3a7713b1edbc | 1853 | return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); |
AnnaBridge | 171:3a7713b1edbc | 1854 | } |
AnnaBridge | 171:3a7713b1edbc | 1855 | |
AnnaBridge | 171:3a7713b1edbc | 1856 | /** |
AnnaBridge | 171:3a7713b1edbc | 1857 | * @brief Enable the master clock ouput (Pin MCK) |
AnnaBridge | 171:3a7713b1edbc | 1858 | * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock |
AnnaBridge | 171:3a7713b1edbc | 1859 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1860 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1861 | */ |
AnnaBridge | 171:3a7713b1edbc | 1862 | __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1863 | { |
AnnaBridge | 171:3a7713b1edbc | 1864 | SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); |
AnnaBridge | 171:3a7713b1edbc | 1865 | } |
AnnaBridge | 171:3a7713b1edbc | 1866 | |
AnnaBridge | 171:3a7713b1edbc | 1867 | /** |
AnnaBridge | 171:3a7713b1edbc | 1868 | * @brief Disable the master clock ouput (Pin MCK) |
AnnaBridge | 171:3a7713b1edbc | 1869 | * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock |
AnnaBridge | 171:3a7713b1edbc | 1870 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1871 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1872 | */ |
AnnaBridge | 171:3a7713b1edbc | 1873 | __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1874 | { |
AnnaBridge | 171:3a7713b1edbc | 1875 | CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); |
AnnaBridge | 171:3a7713b1edbc | 1876 | } |
AnnaBridge | 171:3a7713b1edbc | 1877 | |
AnnaBridge | 171:3a7713b1edbc | 1878 | /** |
AnnaBridge | 171:3a7713b1edbc | 1879 | * @brief Check if the master clock ouput (Pin MCK) is enabled |
AnnaBridge | 171:3a7713b1edbc | 1880 | * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock |
AnnaBridge | 171:3a7713b1edbc | 1881 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1882 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1883 | */ |
AnnaBridge | 171:3a7713b1edbc | 1884 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1885 | { |
AnnaBridge | 171:3a7713b1edbc | 1886 | return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)); |
AnnaBridge | 171:3a7713b1edbc | 1887 | } |
AnnaBridge | 171:3a7713b1edbc | 1888 | |
AnnaBridge | 171:3a7713b1edbc | 1889 | #if defined(SPI_I2SCFGR_ASTRTEN) |
AnnaBridge | 171:3a7713b1edbc | 1890 | /** |
AnnaBridge | 171:3a7713b1edbc | 1891 | * @brief Enable asynchronous start |
AnnaBridge | 171:3a7713b1edbc | 1892 | * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart |
AnnaBridge | 171:3a7713b1edbc | 1893 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1894 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1895 | */ |
AnnaBridge | 171:3a7713b1edbc | 1896 | __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1897 | { |
AnnaBridge | 171:3a7713b1edbc | 1898 | SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); |
AnnaBridge | 171:3a7713b1edbc | 1899 | } |
AnnaBridge | 171:3a7713b1edbc | 1900 | |
AnnaBridge | 171:3a7713b1edbc | 1901 | /** |
AnnaBridge | 171:3a7713b1edbc | 1902 | * @brief Disable asynchronous start |
AnnaBridge | 171:3a7713b1edbc | 1903 | * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart |
AnnaBridge | 171:3a7713b1edbc | 1904 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1905 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1906 | */ |
AnnaBridge | 171:3a7713b1edbc | 1907 | __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1908 | { |
AnnaBridge | 171:3a7713b1edbc | 1909 | CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); |
AnnaBridge | 171:3a7713b1edbc | 1910 | } |
AnnaBridge | 171:3a7713b1edbc | 1911 | |
AnnaBridge | 171:3a7713b1edbc | 1912 | /** |
AnnaBridge | 171:3a7713b1edbc | 1913 | * @brief Check if asynchronous start is enabled |
AnnaBridge | 171:3a7713b1edbc | 1914 | * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1917 | */ |
AnnaBridge | 171:3a7713b1edbc | 1918 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1919 | { |
AnnaBridge | 171:3a7713b1edbc | 1920 | return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)); |
AnnaBridge | 171:3a7713b1edbc | 1921 | } |
AnnaBridge | 171:3a7713b1edbc | 1922 | #endif /* SPI_I2SCFGR_ASTRTEN */ |
AnnaBridge | 171:3a7713b1edbc | 1923 | |
AnnaBridge | 171:3a7713b1edbc | 1924 | /** |
AnnaBridge | 171:3a7713b1edbc | 1925 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1926 | */ |
AnnaBridge | 171:3a7713b1edbc | 1927 | |
AnnaBridge | 171:3a7713b1edbc | 1928 | /** @defgroup I2S_LL_EF_FLAG FLAG Management |
AnnaBridge | 171:3a7713b1edbc | 1929 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1930 | */ |
AnnaBridge | 171:3a7713b1edbc | 1931 | |
AnnaBridge | 171:3a7713b1edbc | 1932 | /** |
AnnaBridge | 171:3a7713b1edbc | 1933 | * @brief Check if Rx buffer is not empty |
AnnaBridge | 171:3a7713b1edbc | 1934 | * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE |
AnnaBridge | 171:3a7713b1edbc | 1935 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1936 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1937 | */ |
AnnaBridge | 171:3a7713b1edbc | 1938 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1939 | { |
AnnaBridge | 171:3a7713b1edbc | 1940 | return LL_SPI_IsActiveFlag_RXNE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1941 | } |
AnnaBridge | 171:3a7713b1edbc | 1942 | |
AnnaBridge | 171:3a7713b1edbc | 1943 | /** |
AnnaBridge | 171:3a7713b1edbc | 1944 | * @brief Check if Tx buffer is empty |
AnnaBridge | 171:3a7713b1edbc | 1945 | * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE |
AnnaBridge | 171:3a7713b1edbc | 1946 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1947 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1948 | */ |
AnnaBridge | 171:3a7713b1edbc | 1949 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1950 | { |
AnnaBridge | 171:3a7713b1edbc | 1951 | return LL_SPI_IsActiveFlag_TXE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1952 | } |
AnnaBridge | 171:3a7713b1edbc | 1953 | |
AnnaBridge | 171:3a7713b1edbc | 1954 | /** |
AnnaBridge | 171:3a7713b1edbc | 1955 | * @brief Get busy flag |
AnnaBridge | 171:3a7713b1edbc | 1956 | * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY |
AnnaBridge | 171:3a7713b1edbc | 1957 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1958 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1959 | */ |
AnnaBridge | 171:3a7713b1edbc | 1960 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1961 | { |
AnnaBridge | 171:3a7713b1edbc | 1962 | return LL_SPI_IsActiveFlag_BSY(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1963 | } |
AnnaBridge | 171:3a7713b1edbc | 1964 | |
AnnaBridge | 171:3a7713b1edbc | 1965 | /** |
AnnaBridge | 171:3a7713b1edbc | 1966 | * @brief Get overrun error flag |
AnnaBridge | 171:3a7713b1edbc | 1967 | * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR |
AnnaBridge | 171:3a7713b1edbc | 1968 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1969 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1970 | */ |
AnnaBridge | 171:3a7713b1edbc | 1971 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1972 | { |
AnnaBridge | 171:3a7713b1edbc | 1973 | return LL_SPI_IsActiveFlag_OVR(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1974 | } |
AnnaBridge | 171:3a7713b1edbc | 1975 | |
AnnaBridge | 171:3a7713b1edbc | 1976 | /** |
AnnaBridge | 171:3a7713b1edbc | 1977 | * @brief Get underrun error flag |
AnnaBridge | 171:3a7713b1edbc | 1978 | * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR |
AnnaBridge | 171:3a7713b1edbc | 1979 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1980 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1981 | */ |
AnnaBridge | 171:3a7713b1edbc | 1982 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1983 | { |
AnnaBridge | 171:3a7713b1edbc | 1984 | return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)); |
AnnaBridge | 171:3a7713b1edbc | 1985 | } |
AnnaBridge | 171:3a7713b1edbc | 1986 | |
AnnaBridge | 171:3a7713b1edbc | 1987 | /** |
AnnaBridge | 171:3a7713b1edbc | 1988 | * @brief Get frame format error flag |
AnnaBridge | 171:3a7713b1edbc | 1989 | * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE |
AnnaBridge | 171:3a7713b1edbc | 1990 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 1991 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1992 | */ |
AnnaBridge | 171:3a7713b1edbc | 1993 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 1994 | { |
AnnaBridge | 171:3a7713b1edbc | 1995 | return LL_SPI_IsActiveFlag_FRE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 1996 | } |
AnnaBridge | 171:3a7713b1edbc | 1997 | |
AnnaBridge | 171:3a7713b1edbc | 1998 | /** |
AnnaBridge | 171:3a7713b1edbc | 1999 | * @brief Get channel side flag. |
AnnaBridge | 171:3a7713b1edbc | 2000 | * @note 0: Channel Left has to be transmitted or has been received\n |
AnnaBridge | 171:3a7713b1edbc | 2001 | * 1: Channel Right has to be transmitted or has been received\n |
AnnaBridge | 171:3a7713b1edbc | 2002 | * It has no significance in PCM mode. |
AnnaBridge | 171:3a7713b1edbc | 2003 | * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE |
AnnaBridge | 171:3a7713b1edbc | 2004 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2005 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2006 | */ |
AnnaBridge | 171:3a7713b1edbc | 2007 | __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2008 | { |
AnnaBridge | 171:3a7713b1edbc | 2009 | return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)); |
AnnaBridge | 171:3a7713b1edbc | 2010 | } |
AnnaBridge | 171:3a7713b1edbc | 2011 | |
AnnaBridge | 171:3a7713b1edbc | 2012 | /** |
AnnaBridge | 171:3a7713b1edbc | 2013 | * @brief Clear overrun error flag |
AnnaBridge | 171:3a7713b1edbc | 2014 | * @rmtoll SR OVR LL_I2S_ClearFlag_OVR |
AnnaBridge | 171:3a7713b1edbc | 2015 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2017 | */ |
AnnaBridge | 171:3a7713b1edbc | 2018 | __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2019 | { |
AnnaBridge | 171:3a7713b1edbc | 2020 | LL_SPI_ClearFlag_OVR(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2021 | } |
AnnaBridge | 171:3a7713b1edbc | 2022 | |
AnnaBridge | 171:3a7713b1edbc | 2023 | /** |
AnnaBridge | 171:3a7713b1edbc | 2024 | * @brief Clear underrun error flag |
AnnaBridge | 171:3a7713b1edbc | 2025 | * @rmtoll SR UDR LL_I2S_ClearFlag_UDR |
AnnaBridge | 171:3a7713b1edbc | 2026 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2027 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2028 | */ |
AnnaBridge | 171:3a7713b1edbc | 2029 | __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2030 | { |
AnnaBridge | 171:3a7713b1edbc | 2031 | __IO uint32_t tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 2032 | tmpreg = SPIx->SR; |
AnnaBridge | 171:3a7713b1edbc | 2033 | (void)tmpreg; |
AnnaBridge | 171:3a7713b1edbc | 2034 | } |
AnnaBridge | 171:3a7713b1edbc | 2035 | |
AnnaBridge | 171:3a7713b1edbc | 2036 | /** |
AnnaBridge | 171:3a7713b1edbc | 2037 | * @brief Clear frame format error flag |
AnnaBridge | 171:3a7713b1edbc | 2038 | * @rmtoll SR FRE LL_I2S_ClearFlag_FRE |
AnnaBridge | 171:3a7713b1edbc | 2039 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2040 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2041 | */ |
AnnaBridge | 171:3a7713b1edbc | 2042 | __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2043 | { |
AnnaBridge | 171:3a7713b1edbc | 2044 | LL_SPI_ClearFlag_FRE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2045 | } |
AnnaBridge | 171:3a7713b1edbc | 2046 | |
AnnaBridge | 171:3a7713b1edbc | 2047 | /** |
AnnaBridge | 171:3a7713b1edbc | 2048 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2049 | */ |
AnnaBridge | 171:3a7713b1edbc | 2050 | |
AnnaBridge | 171:3a7713b1edbc | 2051 | /** @defgroup I2S_LL_EF_IT Interrupt Management |
AnnaBridge | 171:3a7713b1edbc | 2052 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2053 | */ |
AnnaBridge | 171:3a7713b1edbc | 2054 | |
AnnaBridge | 171:3a7713b1edbc | 2055 | /** |
AnnaBridge | 171:3a7713b1edbc | 2056 | * @brief Enable error IT |
AnnaBridge | 171:3a7713b1edbc | 2057 | * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). |
AnnaBridge | 171:3a7713b1edbc | 2058 | * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 2059 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2060 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2061 | */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2063 | { |
AnnaBridge | 171:3a7713b1edbc | 2064 | LL_SPI_EnableIT_ERR(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2065 | } |
AnnaBridge | 171:3a7713b1edbc | 2066 | |
AnnaBridge | 171:3a7713b1edbc | 2067 | /** |
AnnaBridge | 171:3a7713b1edbc | 2068 | * @brief Enable Rx buffer not empty IT |
AnnaBridge | 171:3a7713b1edbc | 2069 | * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 2070 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2071 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2072 | */ |
AnnaBridge | 171:3a7713b1edbc | 2073 | __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2074 | { |
AnnaBridge | 171:3a7713b1edbc | 2075 | LL_SPI_EnableIT_RXNE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2076 | } |
AnnaBridge | 171:3a7713b1edbc | 2077 | |
AnnaBridge | 171:3a7713b1edbc | 2078 | /** |
AnnaBridge | 171:3a7713b1edbc | 2079 | * @brief Enable Tx buffer empty IT |
AnnaBridge | 171:3a7713b1edbc | 2080 | * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 2081 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2082 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2083 | */ |
AnnaBridge | 171:3a7713b1edbc | 2084 | __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2085 | { |
AnnaBridge | 171:3a7713b1edbc | 2086 | LL_SPI_EnableIT_TXE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2087 | } |
AnnaBridge | 171:3a7713b1edbc | 2088 | |
AnnaBridge | 171:3a7713b1edbc | 2089 | /** |
AnnaBridge | 171:3a7713b1edbc | 2090 | * @brief Disable error IT |
AnnaBridge | 171:3a7713b1edbc | 2091 | * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). |
AnnaBridge | 171:3a7713b1edbc | 2092 | * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 2093 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2094 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2095 | */ |
AnnaBridge | 171:3a7713b1edbc | 2096 | __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2097 | { |
AnnaBridge | 171:3a7713b1edbc | 2098 | LL_SPI_DisableIT_ERR(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2099 | } |
AnnaBridge | 171:3a7713b1edbc | 2100 | |
AnnaBridge | 171:3a7713b1edbc | 2101 | /** |
AnnaBridge | 171:3a7713b1edbc | 2102 | * @brief Disable Rx buffer not empty IT |
AnnaBridge | 171:3a7713b1edbc | 2103 | * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 2104 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2105 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2106 | */ |
AnnaBridge | 171:3a7713b1edbc | 2107 | __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2108 | { |
AnnaBridge | 171:3a7713b1edbc | 2109 | LL_SPI_DisableIT_RXNE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2110 | } |
AnnaBridge | 171:3a7713b1edbc | 2111 | |
AnnaBridge | 171:3a7713b1edbc | 2112 | /** |
AnnaBridge | 171:3a7713b1edbc | 2113 | * @brief Disable Tx buffer empty IT |
AnnaBridge | 171:3a7713b1edbc | 2114 | * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 2115 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2116 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2117 | */ |
AnnaBridge | 171:3a7713b1edbc | 2118 | __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2119 | { |
AnnaBridge | 171:3a7713b1edbc | 2120 | LL_SPI_DisableIT_TXE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2121 | } |
AnnaBridge | 171:3a7713b1edbc | 2122 | |
AnnaBridge | 171:3a7713b1edbc | 2123 | /** |
AnnaBridge | 171:3a7713b1edbc | 2124 | * @brief Check if ERR IT is enabled |
AnnaBridge | 171:3a7713b1edbc | 2125 | * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR |
AnnaBridge | 171:3a7713b1edbc | 2126 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2127 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2128 | */ |
AnnaBridge | 171:3a7713b1edbc | 2129 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2130 | { |
AnnaBridge | 171:3a7713b1edbc | 2131 | return LL_SPI_IsEnabledIT_ERR(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2132 | } |
AnnaBridge | 171:3a7713b1edbc | 2133 | |
AnnaBridge | 171:3a7713b1edbc | 2134 | /** |
AnnaBridge | 171:3a7713b1edbc | 2135 | * @brief Check if RXNE IT is enabled |
AnnaBridge | 171:3a7713b1edbc | 2136 | * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE |
AnnaBridge | 171:3a7713b1edbc | 2137 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2138 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2139 | */ |
AnnaBridge | 171:3a7713b1edbc | 2140 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2141 | { |
AnnaBridge | 171:3a7713b1edbc | 2142 | return LL_SPI_IsEnabledIT_RXNE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2143 | } |
AnnaBridge | 171:3a7713b1edbc | 2144 | |
AnnaBridge | 171:3a7713b1edbc | 2145 | /** |
AnnaBridge | 171:3a7713b1edbc | 2146 | * @brief Check if TXE IT is enabled |
AnnaBridge | 171:3a7713b1edbc | 2147 | * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE |
AnnaBridge | 171:3a7713b1edbc | 2148 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2149 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2150 | */ |
AnnaBridge | 171:3a7713b1edbc | 2151 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2152 | { |
AnnaBridge | 171:3a7713b1edbc | 2153 | return LL_SPI_IsEnabledIT_TXE(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2154 | } |
AnnaBridge | 171:3a7713b1edbc | 2155 | |
AnnaBridge | 171:3a7713b1edbc | 2156 | /** |
AnnaBridge | 171:3a7713b1edbc | 2157 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2158 | */ |
AnnaBridge | 171:3a7713b1edbc | 2159 | |
AnnaBridge | 171:3a7713b1edbc | 2160 | /** @defgroup I2S_LL_EF_DMA DMA Management |
AnnaBridge | 171:3a7713b1edbc | 2161 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2162 | */ |
AnnaBridge | 171:3a7713b1edbc | 2163 | |
AnnaBridge | 171:3a7713b1edbc | 2164 | /** |
AnnaBridge | 171:3a7713b1edbc | 2165 | * @brief Enable DMA Rx |
AnnaBridge | 171:3a7713b1edbc | 2166 | * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 2167 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2169 | */ |
AnnaBridge | 171:3a7713b1edbc | 2170 | __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2171 | { |
AnnaBridge | 171:3a7713b1edbc | 2172 | LL_SPI_EnableDMAReq_RX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2173 | } |
AnnaBridge | 171:3a7713b1edbc | 2174 | |
AnnaBridge | 171:3a7713b1edbc | 2175 | /** |
AnnaBridge | 171:3a7713b1edbc | 2176 | * @brief Disable DMA Rx |
AnnaBridge | 171:3a7713b1edbc | 2177 | * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 2178 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2179 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2180 | */ |
AnnaBridge | 171:3a7713b1edbc | 2181 | __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2182 | { |
AnnaBridge | 171:3a7713b1edbc | 2183 | LL_SPI_DisableDMAReq_RX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2184 | } |
AnnaBridge | 171:3a7713b1edbc | 2185 | |
AnnaBridge | 171:3a7713b1edbc | 2186 | /** |
AnnaBridge | 171:3a7713b1edbc | 2187 | * @brief Check if DMA Rx is enabled |
AnnaBridge | 171:3a7713b1edbc | 2188 | * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX |
AnnaBridge | 171:3a7713b1edbc | 2189 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2190 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2191 | */ |
AnnaBridge | 171:3a7713b1edbc | 2192 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2193 | { |
AnnaBridge | 171:3a7713b1edbc | 2194 | return LL_SPI_IsEnabledDMAReq_RX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2195 | } |
AnnaBridge | 171:3a7713b1edbc | 2196 | |
AnnaBridge | 171:3a7713b1edbc | 2197 | /** |
AnnaBridge | 171:3a7713b1edbc | 2198 | * @brief Enable DMA Tx |
AnnaBridge | 171:3a7713b1edbc | 2199 | * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 2200 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2201 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2202 | */ |
AnnaBridge | 171:3a7713b1edbc | 2203 | __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2204 | { |
AnnaBridge | 171:3a7713b1edbc | 2205 | LL_SPI_EnableDMAReq_TX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2206 | } |
AnnaBridge | 171:3a7713b1edbc | 2207 | |
AnnaBridge | 171:3a7713b1edbc | 2208 | /** |
AnnaBridge | 171:3a7713b1edbc | 2209 | * @brief Disable DMA Tx |
AnnaBridge | 171:3a7713b1edbc | 2210 | * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 2211 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2212 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2213 | */ |
AnnaBridge | 171:3a7713b1edbc | 2214 | __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2215 | { |
AnnaBridge | 171:3a7713b1edbc | 2216 | LL_SPI_DisableDMAReq_TX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2217 | } |
AnnaBridge | 171:3a7713b1edbc | 2218 | |
AnnaBridge | 171:3a7713b1edbc | 2219 | /** |
AnnaBridge | 171:3a7713b1edbc | 2220 | * @brief Check if DMA Tx is enabled |
AnnaBridge | 171:3a7713b1edbc | 2221 | * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX |
AnnaBridge | 171:3a7713b1edbc | 2222 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2223 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2224 | */ |
AnnaBridge | 171:3a7713b1edbc | 2225 | __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2226 | { |
AnnaBridge | 171:3a7713b1edbc | 2227 | return LL_SPI_IsEnabledDMAReq_TX(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2228 | } |
AnnaBridge | 171:3a7713b1edbc | 2229 | |
AnnaBridge | 171:3a7713b1edbc | 2230 | /** |
AnnaBridge | 171:3a7713b1edbc | 2231 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2232 | */ |
AnnaBridge | 171:3a7713b1edbc | 2233 | |
AnnaBridge | 171:3a7713b1edbc | 2234 | /** @defgroup I2S_LL_EF_DATA DATA Management |
AnnaBridge | 171:3a7713b1edbc | 2235 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2236 | */ |
AnnaBridge | 171:3a7713b1edbc | 2237 | |
AnnaBridge | 171:3a7713b1edbc | 2238 | /** |
AnnaBridge | 171:3a7713b1edbc | 2239 | * @brief Read 16-Bits in data register |
AnnaBridge | 171:3a7713b1edbc | 2240 | * @rmtoll DR DR LL_I2S_ReceiveData16 |
AnnaBridge | 171:3a7713b1edbc | 2241 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2242 | * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 2243 | */ |
AnnaBridge | 171:3a7713b1edbc | 2244 | __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) |
AnnaBridge | 171:3a7713b1edbc | 2245 | { |
AnnaBridge | 171:3a7713b1edbc | 2246 | return LL_SPI_ReceiveData16(SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2247 | } |
AnnaBridge | 171:3a7713b1edbc | 2248 | |
AnnaBridge | 171:3a7713b1edbc | 2249 | /** |
AnnaBridge | 171:3a7713b1edbc | 2250 | * @brief Write 16-Bits in data register |
AnnaBridge | 171:3a7713b1edbc | 2251 | * @rmtoll DR DR LL_I2S_TransmitData16 |
AnnaBridge | 171:3a7713b1edbc | 2252 | * @param SPIx SPI Instance |
AnnaBridge | 171:3a7713b1edbc | 2253 | * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF |
AnnaBridge | 171:3a7713b1edbc | 2254 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2255 | */ |
AnnaBridge | 171:3a7713b1edbc | 2256 | __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) |
AnnaBridge | 171:3a7713b1edbc | 2257 | { |
AnnaBridge | 171:3a7713b1edbc | 2258 | LL_SPI_TransmitData16(SPIx, TxData); |
AnnaBridge | 171:3a7713b1edbc | 2259 | } |
AnnaBridge | 171:3a7713b1edbc | 2260 | |
AnnaBridge | 171:3a7713b1edbc | 2261 | /** |
AnnaBridge | 171:3a7713b1edbc | 2262 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2263 | */ |
AnnaBridge | 171:3a7713b1edbc | 2264 | |
AnnaBridge | 171:3a7713b1edbc | 2265 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 2266 | /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 2267 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2268 | */ |
AnnaBridge | 171:3a7713b1edbc | 2269 | |
AnnaBridge | 171:3a7713b1edbc | 2270 | ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); |
AnnaBridge | 171:3a7713b1edbc | 2271 | ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2272 | void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2273 | void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); |
AnnaBridge | 171:3a7713b1edbc | 2274 | |
AnnaBridge | 171:3a7713b1edbc | 2275 | /** |
AnnaBridge | 171:3a7713b1edbc | 2276 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2277 | */ |
AnnaBridge | 171:3a7713b1edbc | 2278 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 2279 | |
AnnaBridge | 171:3a7713b1edbc | 2280 | /** |
AnnaBridge | 171:3a7713b1edbc | 2281 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2282 | */ |
AnnaBridge | 171:3a7713b1edbc | 2283 | |
AnnaBridge | 171:3a7713b1edbc | 2284 | /** |
AnnaBridge | 171:3a7713b1edbc | 2285 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2286 | */ |
AnnaBridge | 171:3a7713b1edbc | 2287 | #endif /* SPI_I2S_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 2288 | |
AnnaBridge | 171:3a7713b1edbc | 2289 | #endif /* defined (SPI1) || defined (SPI2) */ |
AnnaBridge | 171:3a7713b1edbc | 2290 | |
AnnaBridge | 171:3a7713b1edbc | 2291 | /** |
AnnaBridge | 171:3a7713b1edbc | 2292 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2293 | */ |
AnnaBridge | 171:3a7713b1edbc | 2294 | |
AnnaBridge | 171:3a7713b1edbc | 2295 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2296 | } |
AnnaBridge | 171:3a7713b1edbc | 2297 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2298 | |
AnnaBridge | 171:3a7713b1edbc | 2299 | #endif /* __STM32F0xx_LL_SPI_H */ |
AnnaBridge | 171:3a7713b1edbc | 2300 | |
AnnaBridge | 171:3a7713b1edbc | 2301 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |