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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/spib_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/device/spib_regs.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21838 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_SPIB_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_SPIB_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */
AnnaBridge 167:84c0a372a020 76 } mxc_spib_regs_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78
AnnaBridge 167:84c0a372a020 79 /*
AnnaBridge 167:84c0a372a020 80 Register offsets for module SPIB.
AnnaBridge 167:84c0a372a020 81 */
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 #define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 84 #define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 85 #define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 86 #define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 87 #define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 88
AnnaBridge 167:84c0a372a020 89
AnnaBridge 167:84c0a372a020 90 /*
AnnaBridge 167:84c0a372a020 91 Field positions and masks for module SPIB.
AnnaBridge 167:84c0a372a020 92 */
AnnaBridge 167:84c0a372a020 93
AnnaBridge 167:84c0a372a020 94 #define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0
AnnaBridge 167:84c0a372a020 95 #define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 96 #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2
AnnaBridge 167:84c0a372a020 97 #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
AnnaBridge 167:84c0a372a020 98 #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8
AnnaBridge 167:84c0a372a020 99 #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS))
AnnaBridge 167:84c0a372a020 100 #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12
AnnaBridge 167:84c0a372a020 101 #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS))
AnnaBridge 167:84c0a372a020 102 #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16
AnnaBridge 167:84c0a372a020 103 #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 104 #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18
AnnaBridge 167:84c0a372a020 105 #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 106
AnnaBridge 167:84c0a372a020 107 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0
AnnaBridge 167:84c0a372a020 108 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
AnnaBridge 167:84c0a372a020 109 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1
AnnaBridge 167:84c0a372a020 110 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
AnnaBridge 167:84c0a372a020 111 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2
AnnaBridge 167:84c0a372a020 112 #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
AnnaBridge 167:84c0a372a020 113
AnnaBridge 167:84c0a372a020 114 #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0
AnnaBridge 167:84c0a372a020 115 #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 116 #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1
AnnaBridge 167:84c0a372a020 117 #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 118 #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2
AnnaBridge 167:84c0a372a020 119 #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
AnnaBridge 167:84c0a372a020 120
AnnaBridge 167:84c0a372a020 121 #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0
AnnaBridge 167:84c0a372a020 122 #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 123 #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1
AnnaBridge 167:84c0a372a020 124 #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 125 #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2
AnnaBridge 167:84c0a372a020 126 #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
AnnaBridge 167:84c0a372a020 127
AnnaBridge 167:84c0a372a020 128 #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0
AnnaBridge 167:84c0a372a020 129 #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS))
AnnaBridge 167:84c0a372a020 130 #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1
AnnaBridge 167:84c0a372a020 131 #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS))
AnnaBridge 167:84c0a372a020 132 #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2
AnnaBridge 167:84c0a372a020 133 #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
AnnaBridge 167:84c0a372a020 134 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8
AnnaBridge 167:84c0a372a020 135 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS))
AnnaBridge 167:84c0a372a020 136 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16
AnnaBridge 167:84c0a372a020 137 #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS))
AnnaBridge 167:84c0a372a020 138
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 /*
AnnaBridge 167:84c0a372a020 142 Field values and shifted values for module SPIB.
AnnaBridge 167:84c0a372a020 143 */
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145 #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 146 #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 147
AnnaBridge 167:84c0a372a020 148 #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 149 #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 152 #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 153
AnnaBridge 167:84c0a372a020 154 #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
AnnaBridge 167:84c0a372a020 155 #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
AnnaBridge 167:84c0a372a020 156
AnnaBridge 167:84c0a372a020 157 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 158 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 159 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 160 #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 161
AnnaBridge 167:84c0a372a020 162 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 163 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 164 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 165 #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 166
AnnaBridge 167:84c0a372a020 167 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 168 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 169 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 170 #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 171
AnnaBridge 167:84c0a372a020 172 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 173 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 174 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 175 #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 176
AnnaBridge 167:84c0a372a020 177 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 178 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 179
AnnaBridge 167:84c0a372a020 180 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
AnnaBridge 167:84c0a372a020 181 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
AnnaBridge 167:84c0a372a020 182
AnnaBridge 167:84c0a372a020 183 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 184 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 185
AnnaBridge 167:84c0a372a020 186 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
AnnaBridge 167:84c0a372a020 188
AnnaBridge 167:84c0a372a020 189 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 190 #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 191
AnnaBridge 167:84c0a372a020 192 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
AnnaBridge 167:84c0a372a020 193 #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
AnnaBridge 167:84c0a372a020 194
AnnaBridge 167:84c0a372a020 195 #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 196 #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 197
AnnaBridge 167:84c0a372a020 198 #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 199 #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 200
AnnaBridge 167:84c0a372a020 201 #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 202 #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 203
AnnaBridge 167:84c0a372a020 204 #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 205 #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 206
AnnaBridge 167:84c0a372a020 207 #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 208 #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 209
AnnaBridge 167:84c0a372a020 210 #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
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AnnaBridge 167:84c0a372a020 213 #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 214 #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 215
AnnaBridge 167:84c0a372a020 216 #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 217 #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
AnnaBridge 167:84c0a372a020 218
AnnaBridge 167:84c0a372a020 219 #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 220 #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 221
AnnaBridge 167:84c0a372a020 222 #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 223 #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225 #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 226 #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 227
AnnaBridge 167:84c0a372a020 228 #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
AnnaBridge 167:84c0a372a020 229 #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
AnnaBridge 167:84c0a372a020 230
AnnaBridge 167:84c0a372a020 231 #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 232 #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 233
AnnaBridge 167:84c0a372a020 234 #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
AnnaBridge 167:84c0a372a020 235 #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
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AnnaBridge 167:84c0a372a020 237
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AnnaBridge 167:84c0a372a020 239 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 240 }
AnnaBridge 167:84c0a372a020 241 #endif
AnnaBridge 167:84c0a372a020 242
AnnaBridge 167:84c0a372a020 243 #endif /* _MXC_SPIB_REGS_H_ */
AnnaBridge 167:84c0a372a020 244