mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32620FTHR/TOOLCHAIN_IAR/uart_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/device/uart_regs.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_UART_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_UART_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t ctrl; /* 0x0000 UART Control Register */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t baud; /* 0x0004 UART Baud Control Register */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t tx_fifo_ctrl; /* 0x0008 UART TX FIFO Control Register */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t rx_fifo_ctrl; /* 0x000C UART RX FIFO Control Register */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t md_ctrl; /* 0x0010 UART Multidrop Control Register */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t intfl; /* 0x0014 UART Interrupt Flags */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t inten; /* 0x0018 UART Interrupt Enable/Disable Controls */
AnnaBridge 167:84c0a372a020 78 #if (MXC_UART_REV > 0)
AnnaBridge 167:84c0a372a020 79 __RO uint32_t idle; /* 0x001C UART Idle Status */
AnnaBridge 167:84c0a372a020 80 #endif
AnnaBridge 167:84c0a372a020 81 } mxc_uart_regs_t;
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83
AnnaBridge 167:84c0a372a020 84 /* Offset Register Description
AnnaBridge 167:84c0a372a020 85 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 86 typedef struct {
AnnaBridge 167:84c0a372a020 87 union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */
AnnaBridge 167:84c0a372a020 88 __IO uint8_t tx;
AnnaBridge 167:84c0a372a020 89 __IO uint8_t tx_8[2048];
AnnaBridge 167:84c0a372a020 90 __IO uint16_t tx_16[1024];
AnnaBridge 167:84c0a372a020 91 __IO uint32_t tx_32[512];
AnnaBridge 167:84c0a372a020 92 };
AnnaBridge 167:84c0a372a020 93 union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */
AnnaBridge 167:84c0a372a020 94 __IO uint8_t rx;
AnnaBridge 167:84c0a372a020 95 __IO uint8_t rx_8[2048];
AnnaBridge 167:84c0a372a020 96 __IO uint16_t rx_16[1024];
AnnaBridge 167:84c0a372a020 97 __IO uint32_t rx_32[512];
AnnaBridge 167:84c0a372a020 98 };
AnnaBridge 167:84c0a372a020 99 } mxc_uart_fifo_regs_t;
AnnaBridge 167:84c0a372a020 100
AnnaBridge 167:84c0a372a020 101
AnnaBridge 167:84c0a372a020 102 /*
AnnaBridge 167:84c0a372a020 103 Register offsets for module UART.
AnnaBridge 167:84c0a372a020 104 */
AnnaBridge 167:84c0a372a020 105
AnnaBridge 167:84c0a372a020 106 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 107 #define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 108 #define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 109 #define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 110 #define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 111 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 112 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 113 #define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 114 #define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
AnnaBridge 167:84c0a372a020 115
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117 /*
AnnaBridge 167:84c0a372a020 118 Field positions and masks for module UART.
AnnaBridge 167:84c0a372a020 119 */
AnnaBridge 167:84c0a372a020 120
AnnaBridge 167:84c0a372a020 121 #define MXC_F_UART_CTRL_UART_EN_POS 0
AnnaBridge 167:84c0a372a020 122 #define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
AnnaBridge 167:84c0a372a020 123 #define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
AnnaBridge 167:84c0a372a020 124 #define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 125 #define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
AnnaBridge 167:84c0a372a020 126 #define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 127 #define MXC_F_UART_CTRL_DATA_SIZE_POS 4
AnnaBridge 167:84c0a372a020 128 #define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
AnnaBridge 167:84c0a372a020 129 #define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
AnnaBridge 167:84c0a372a020 130 #define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
AnnaBridge 167:84c0a372a020 131 #define MXC_F_UART_CTRL_PARITY_POS 12
AnnaBridge 167:84c0a372a020 132 #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
AnnaBridge 167:84c0a372a020 133 #define MXC_F_UART_CTRL_CTS_EN_POS 16
AnnaBridge 167:84c0a372a020 134 #define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
AnnaBridge 167:84c0a372a020 135 #define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
AnnaBridge 167:84c0a372a020 136 #define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
AnnaBridge 167:84c0a372a020 137 #define MXC_F_UART_CTRL_RTS_EN_POS 18
AnnaBridge 167:84c0a372a020 138 #define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
AnnaBridge 167:84c0a372a020 139 #define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
AnnaBridge 167:84c0a372a020 140 #define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
AnnaBridge 167:84c0a372a020 141 #define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
AnnaBridge 167:84c0a372a020 142 #define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
AnnaBridge 167:84c0a372a020 143
AnnaBridge 167:84c0a372a020 144 #define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
AnnaBridge 167:84c0a372a020 145 #define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
AnnaBridge 167:84c0a372a020 146 #define MXC_F_UART_BAUD_BAUD_MODE_POS 8
AnnaBridge 167:84c0a372a020 147 #define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
AnnaBridge 167:84c0a372a020 148
AnnaBridge 167:84c0a372a020 149 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
AnnaBridge 167:84c0a372a020 150 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
AnnaBridge 167:84c0a372a020 151 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
AnnaBridge 167:84c0a372a020 152 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
AnnaBridge 167:84c0a372a020 153
AnnaBridge 167:84c0a372a020 154 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
AnnaBridge 167:84c0a372a020 155 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
AnnaBridge 167:84c0a372a020 157 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
AnnaBridge 167:84c0a372a020 158
AnnaBridge 167:84c0a372a020 159 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
AnnaBridge 167:84c0a372a020 160 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
AnnaBridge 167:84c0a372a020 161 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
AnnaBridge 167:84c0a372a020 162 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
AnnaBridge 167:84c0a372a020 163 #define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
AnnaBridge 167:84c0a372a020 164 #define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
AnnaBridge 167:84c0a372a020 165 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
AnnaBridge 167:84c0a372a020 166 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
AnnaBridge 167:84c0a372a020 167
AnnaBridge 167:84c0a372a020 168 #define MXC_F_UART_INTFL_TX_DONE_POS 0
AnnaBridge 167:84c0a372a020 169 #define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
AnnaBridge 167:84c0a372a020 170 #define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
AnnaBridge 167:84c0a372a020 171 #define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
AnnaBridge 167:84c0a372a020 172 #define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
AnnaBridge 167:84c0a372a020 173 #define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 174 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
AnnaBridge 167:84c0a372a020 175 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
AnnaBridge 167:84c0a372a020 176 #define MXC_F_UART_INTFL_RX_STALLED_POS 4
AnnaBridge 167:84c0a372a020 177 #define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
AnnaBridge 167:84c0a372a020 178 #define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
AnnaBridge 167:84c0a372a020 179 #define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 180 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
AnnaBridge 167:84c0a372a020 181 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
AnnaBridge 167:84c0a372a020 182 #define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
AnnaBridge 167:84c0a372a020 183 #define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
AnnaBridge 167:84c0a372a020 184 #define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
AnnaBridge 167:84c0a372a020 185 #define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
AnnaBridge 167:84c0a372a020 186
AnnaBridge 167:84c0a372a020 187 #define MXC_F_UART_INTEN_TX_DONE_POS 0
AnnaBridge 167:84c0a372a020 188 #define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
AnnaBridge 167:84c0a372a020 190 #define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
AnnaBridge 167:84c0a372a020 191 #define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
AnnaBridge 167:84c0a372a020 192 #define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 193 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
AnnaBridge 167:84c0a372a020 194 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
AnnaBridge 167:84c0a372a020 195 #define MXC_F_UART_INTEN_RX_STALLED_POS 4
AnnaBridge 167:84c0a372a020 196 #define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
AnnaBridge 167:84c0a372a020 197 #define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
AnnaBridge 167:84c0a372a020 198 #define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 199 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
AnnaBridge 167:84c0a372a020 200 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
AnnaBridge 167:84c0a372a020 201 #define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
AnnaBridge 167:84c0a372a020 202 #define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
AnnaBridge 167:84c0a372a020 203 #define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
AnnaBridge 167:84c0a372a020 204 #define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
AnnaBridge 167:84c0a372a020 205
AnnaBridge 167:84c0a372a020 206 #if (MXC_UART_REV > 0)
AnnaBridge 167:84c0a372a020 207 #define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
AnnaBridge 167:84c0a372a020 208 #define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_UART_IDLE_TX_IDLE_POS 1
AnnaBridge 167:84c0a372a020 210 #define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_F_UART_IDLE_RX_IDLE_POS 2
AnnaBridge 167:84c0a372a020 212 #define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
AnnaBridge 167:84c0a372a020 213 #endif
AnnaBridge 167:84c0a372a020 214
AnnaBridge 167:84c0a372a020 215 /*
AnnaBridge 167:84c0a372a020 216 Field values and shifted values for module UART.
AnnaBridge 167:84c0a372a020 217 */
AnnaBridge 167:84c0a372a020 218
AnnaBridge 167:84c0a372a020 219 #define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 220 #define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 221 #define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 222 #define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 223
AnnaBridge 167:84c0a372a020 224 #define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
AnnaBridge 167:84c0a372a020 225 #define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
AnnaBridge 167:84c0a372a020 226 #define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
AnnaBridge 167:84c0a372a020 227 #define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
AnnaBridge 167:84c0a372a020 228
AnnaBridge 167:84c0a372a020 229 #define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 230 #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 231 #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 232 #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 233
AnnaBridge 167:84c0a372a020 234 #define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
AnnaBridge 167:84c0a372a020 235 #define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
AnnaBridge 167:84c0a372a020 236 #define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
AnnaBridge 167:84c0a372a020 237 #define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
AnnaBridge 167:84c0a372a020 238
AnnaBridge 167:84c0a372a020 239
AnnaBridge 167:84c0a372a020 240
AnnaBridge 167:84c0a372a020 241 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 242 }
AnnaBridge 167:84c0a372a020 243 #endif
AnnaBridge 167:84c0a372a020 244
AnnaBridge 167:84c0a372a020 245 #endif /* _MXC_UART_REGS_H_ */