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TARGET_MAX32620FTHR/TOOLCHAIN_IAR/spis.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_MAX32620FTHR/TARGET_Maxim/TARGET_MAX32620C/mxc/spis.h@167:84c0a372a020 
mbed library. Release version 164

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AnnaBridge 167:84c0a372a020 1 /**
AnnaBridge 167:84c0a372a020 2 * @file
AnnaBridge 167:84c0a372a020 3 * @brief SPI Slave High Level API.
AnnaBridge 167:84c0a372a020 4 */
AnnaBridge 167:84c0a372a020 5
AnnaBridge 167:84c0a372a020 6 /* ****************************************************************************
AnnaBridge 167:84c0a372a020 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 8 *
AnnaBridge 167:84c0a372a020 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 17 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 18 *
AnnaBridge 167:84c0a372a020 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 26 *
AnnaBridge 167:84c0a372a020 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 29 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 30 *
AnnaBridge 167:84c0a372a020 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 35 * ownership rights.
AnnaBridge 167:84c0a372a020 36 *
AnnaBridge 167:84c0a372a020 37 * $Date: 2016-10-03 14:23:55 -0500 (Mon, 03 Oct 2016) $
AnnaBridge 167:84c0a372a020 38 * $Revision: 24550 $
AnnaBridge 167:84c0a372a020 39 *
AnnaBridge 167:84c0a372a020 40 **************************************************************************** */
AnnaBridge 167:84c0a372a020 41
AnnaBridge 167:84c0a372a020 42 /* Define to prevent redundant inclusion */
AnnaBridge 167:84c0a372a020 43 #ifndef _SPIS_H_
AnnaBridge 167:84c0a372a020 44 #define _SPIS_H_
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /* **** Includes **** */
AnnaBridge 167:84c0a372a020 47 #include "mxc_config.h"
AnnaBridge 167:84c0a372a020 48 #include "mxc_sys.h"
AnnaBridge 167:84c0a372a020 49 #include "spis_regs.h"
AnnaBridge 167:84c0a372a020 50
AnnaBridge 167:84c0a372a020 51 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 52 extern "C" {
AnnaBridge 167:84c0a372a020 53 #endif
AnnaBridge 167:84c0a372a020 54
AnnaBridge 167:84c0a372a020 55 /**
AnnaBridge 167:84c0a372a020 56 * @defgroup spis SPI Slave
AnnaBridge 167:84c0a372a020 57 * @ingroup spi_comm
AnnaBridge 167:84c0a372a020 58 * @brief SPI Slave (SPIS) Communications Interface API.
AnnaBridge 167:84c0a372a020 59 * @{
AnnaBridge 167:84c0a372a020 60 */
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62 /* **** Definitions **** */
AnnaBridge 167:84c0a372a020 63
AnnaBridge 167:84c0a372a020 64 /**
AnnaBridge 167:84c0a372a020 65 * Enumeration type for setting the number data lines to use for communication.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67 typedef enum {
AnnaBridge 167:84c0a372a020 68 SPIS_WIDTH_1 = 0, /**< 1 Data Line */
AnnaBridge 167:84c0a372a020 69 SPIS_WIDTH_2 = 1, /**< 2 Data Lines (x2) */
AnnaBridge 167:84c0a372a020 70 SPIS_WIDTH_4 = 2 /**< 4 Data Lines (x4) */
AnnaBridge 167:84c0a372a020 71 } spis_width_t;
AnnaBridge 167:84c0a372a020 72
AnnaBridge 167:84c0a372a020 73 /**
AnnaBridge 167:84c0a372a020 74 * Structure type for an SPI Slave transaction request.
AnnaBridge 167:84c0a372a020 75 */
AnnaBridge 167:84c0a372a020 76 typedef struct spis_req spis_req_t;
AnnaBridge 167:84c0a372a020 77
AnnaBridge 167:84c0a372a020 78 /**
AnnaBridge 167:84c0a372a020 79 * Callback function type used in asynchromous SPIS communications requests.
AnnaBridge 167:84c0a372a020 80 * The function declaration for the SPI Slave callback is:
AnnaBridge 167:84c0a372a020 81 * \code
AnnaBridge 167:84c0a372a020 82 * void callback(spis_req_t * req, int error_code);
AnnaBridge 167:84c0a372a020 83 * \endcode
AnnaBridge 167:84c0a372a020 84 * | | |
AnnaBridge 167:84c0a372a020 85 * | -----: | :----------------------------------------- |
AnnaBridge 167:84c0a372a020 86 * | \p req | Pointer to an #spis_req object representing the active SPIS active transaction. |
AnnaBridge 167:84c0a372a020 87 * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
AnnaBridge 167:84c0a372a020 88 * @addtogroup spis_async
AnnaBridge 167:84c0a372a020 89 * @{
AnnaBridge 167:84c0a372a020 90 */
AnnaBridge 167:84c0a372a020 91 typedef void (*callback_fn)(spis_req_t*, int);
AnnaBridge 167:84c0a372a020 92 /**@} end of async group for this prototype */
AnnaBridge 167:84c0a372a020 93
AnnaBridge 167:84c0a372a020 94
AnnaBridge 167:84c0a372a020 95 /**
AnnaBridge 167:84c0a372a020 96 * Struture for the SPI Slave transaction request.
AnnaBridge 167:84c0a372a020 97 */
AnnaBridge 167:84c0a372a020 98 struct spis_req {
AnnaBridge 167:84c0a372a020 99 uint8_t deass; /**< End the transaction when SS is deasserted. */
AnnaBridge 167:84c0a372a020 100 const uint8_t *tx_data; /**< TX buffer. */
AnnaBridge 167:84c0a372a020 101 uint8_t *rx_data; /**< RX buffer. */
AnnaBridge 167:84c0a372a020 102 spis_width_t width; /**< Number of data lines to use. */
AnnaBridge 167:84c0a372a020 103 unsigned len; /**< Number of bytes to send. */
AnnaBridge 167:84c0a372a020 104 unsigned read_num; /**< Number of bytes transacted. */
AnnaBridge 167:84c0a372a020 105 unsigned write_num; /**< Number of bytes transacted. */
AnnaBridge 167:84c0a372a020 106 callback_fn callback; /**< Function pointer to a callback function if desired, NULL otherwise */
AnnaBridge 167:84c0a372a020 107 };
AnnaBridge 167:84c0a372a020 108
AnnaBridge 167:84c0a372a020 109 /* **** Globals **** */
AnnaBridge 167:84c0a372a020 110
AnnaBridge 167:84c0a372a020 111 /* **** Function Prototypes **** */
AnnaBridge 167:84c0a372a020 112
AnnaBridge 167:84c0a372a020 113 /**
AnnaBridge 167:84c0a372a020 114 * @brief Initialize SPIS module.
AnnaBridge 167:84c0a372a020 115 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 116 * @param mode SPI Mode to configure the slave, 0 to 3.
AnnaBridge 167:84c0a372a020 117 * @param sys_cfg Pointer to system configuration object, see #sys_cfg_spis_t.
AnnaBridge 167:84c0a372a020 118 * @return #E_NO_ERROR if everything is successful.
AnnaBridge 167:84c0a372a020 119 */
AnnaBridge 167:84c0a372a020 120 int SPIS_Init(mxc_spis_regs_t *spis, uint8_t mode, const sys_cfg_spis_t *sys_cfg);
AnnaBridge 167:84c0a372a020 121
AnnaBridge 167:84c0a372a020 122
AnnaBridge 167:84c0a372a020 123 /**
AnnaBridge 167:84c0a372a020 124 * @brief Shutdown SPIS module.
AnnaBridge 167:84c0a372a020 125 * @param spis Pointer to SPIS regs.
AnnaBridge 167:84c0a372a020 126 * @return #E_NO_ERROR if everything is successful
AnnaBridge 167:84c0a372a020 127 */
AnnaBridge 167:84c0a372a020 128 int SPIS_Shutdown(mxc_spis_regs_t *spis);
AnnaBridge 167:84c0a372a020 129
AnnaBridge 167:84c0a372a020 130 /**
AnnaBridge 167:84c0a372a020 131 * @brief Read/write SPIS data. Will block until transaction is complete.
AnnaBridge 167:84c0a372a020 132 * @note Callback is ignored.
AnnaBridge 167:84c0a372a020 133 *
AnnaBridge 167:84c0a372a020 134 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 135 * @param req Pointer to a request structure for a SPI Slave transaction.
AnnaBridge 167:84c0a372a020 136 * @return Bytes transacted if everything is successful, @ref
AnnaBridge 167:84c0a372a020 137 * MXC_Error_Codes "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 138 */
AnnaBridge 167:84c0a372a020 139 int SPIS_Trans(mxc_spis_regs_t *spis, spis_req_t *req);
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 /**
AnnaBridge 167:84c0a372a020 142 * @defgroup spis_async SPI Slave Asynchrous Functions
AnnaBridge 167:84c0a372a020 143 * @{
AnnaBridge 167:84c0a372a020 144 */
AnnaBridge 167:84c0a372a020 145
AnnaBridge 167:84c0a372a020 146 /**
AnnaBridge 167:84c0a372a020 147 * @brief Asynchronously read/write SPIS data.
AnnaBridge 167:84c0a372a020 148 * @note Request struct, @p req must remain allocated until callback.
AnnaBridge 167:84c0a372a020 149 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 150 * @param req Pointer to a request structure for a SPI Slave transaction.
AnnaBridge 167:84c0a372a020 151 * @return #E_NO_ERROR if everything is successful, @ref
AnnaBridge 167:84c0a372a020 152 * MXC_Error_Codes "error" if unsuccessful.
AnnaBridge 167:84c0a372a020 153 */
AnnaBridge 167:84c0a372a020 154 int SPIS_TransAsync(mxc_spis_regs_t *spis, spis_req_t *req);
AnnaBridge 167:84c0a372a020 155
AnnaBridge 167:84c0a372a020 156 /**
AnnaBridge 167:84c0a372a020 157 * @brief Abort asynchronous request.
AnnaBridge 167:84c0a372a020 158 * @param req Pointer to request for a SPIS transaction.
AnnaBridge 167:84c0a372a020 159 * @returns #E_NO_ERROR if request aborted, error if unsuccessful.
AnnaBridge 167:84c0a372a020 160 */
AnnaBridge 167:84c0a372a020 161 int SPIS_AbortAsync(spis_req_t *req);
AnnaBridge 167:84c0a372a020 162
AnnaBridge 167:84c0a372a020 163 /**
AnnaBridge 167:84c0a372a020 164 * @brief SPI Slave interrupt handler.
AnnaBridge 167:84c0a372a020 165 * @details This function should be called by the application from the interrupt
AnnaBridge 167:84c0a372a020 166 * handler if SPIS interrupts are enabled. Alternately, this function
AnnaBridge 167:84c0a372a020 167 * can be periodically called by the application if SPIS interrupts are
AnnaBridge 167:84c0a372a020 168 * disabled.
AnnaBridge 167:84c0a372a020 169 * @param spis Pointer to the base address of the SPIS[n] module.
AnnaBridge 167:84c0a372a020 170 */
AnnaBridge 167:84c0a372a020 171 void SPIS_Handler(mxc_spis_regs_t *spis);
AnnaBridge 167:84c0a372a020 172
AnnaBridge 167:84c0a372a020 173 /**
AnnaBridge 167:84c0a372a020 174 * @brief Check the SPIS to see if it's busy.
AnnaBridge 167:84c0a372a020 175 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 176 * @return #E_NO_ERROR if idle.
AnnaBridge 167:84c0a372a020 177 * @return #E_BUSY if in use.
AnnaBridge 167:84c0a372a020 178 */
AnnaBridge 167:84c0a372a020 179 int SPIS_Busy(mxc_spis_regs_t *spis);
AnnaBridge 167:84c0a372a020 180 /**@} end of group spis_async*/
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 /**
AnnaBridge 167:84c0a372a020 183 * @brief Attempt to prepare the SPI Slave for sleep.
AnnaBridge 167:84c0a372a020 184 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 185 * @details Checks for any ongoing transactions. Disables interrupts if the
AnnaBridge 167:84c0a372a020 186 * SPI Slave is idle.
AnnaBridge 167:84c0a372a020 187 * @return #E_NO_ERROR if ready to sleep.
AnnaBridge 167:84c0a372a020 188 * @return #E_BUSY if not ready for sleep.
AnnaBridge 167:84c0a372a020 189 */
AnnaBridge 167:84c0a372a020 190 int SPIS_PrepForSleep(mxc_spis_regs_t *spis);
AnnaBridge 167:84c0a372a020 191
AnnaBridge 167:84c0a372a020 192 /**
AnnaBridge 167:84c0a372a020 193 * @brief Inline function that enables the SPI Slave without overwriting the existing configuration.
AnnaBridge 167:84c0a372a020 194 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 195 */
AnnaBridge 167:84c0a372a020 196 __STATIC_INLINE void SPIS_Enable(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 197 {
AnnaBridge 167:84c0a372a020 198 spis->gen_ctrl |= (MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN |
AnnaBridge 167:84c0a372a020 199 MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN);
AnnaBridge 167:84c0a372a020 200 }
AnnaBridge 167:84c0a372a020 201
AnnaBridge 167:84c0a372a020 202 /**
AnnaBridge 167:84c0a372a020 203 * @brief Inline function that drains all of the data in the Receive FIFO.
AnnaBridge 167:84c0a372a020 204 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 205 */
AnnaBridge 167:84c0a372a020 206 __STATIC_INLINE void SPIS_DrainRX(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 207 {
AnnaBridge 167:84c0a372a020 208 uint32_t ctrl_save = spis->gen_ctrl;
AnnaBridge 167:84c0a372a020 209 spis->gen_ctrl = (ctrl_save & ~MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN);
AnnaBridge 167:84c0a372a020 210 spis->gen_ctrl = ctrl_save;
AnnaBridge 167:84c0a372a020 211 }
AnnaBridge 167:84c0a372a020 212
AnnaBridge 167:84c0a372a020 213 /**
AnnaBridge 167:84c0a372a020 214 * @brief Inline function that drains all of the data in the Transmit FIFO.
AnnaBridge 167:84c0a372a020 215 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 216 */
AnnaBridge 167:84c0a372a020 217 __STATIC_INLINE void SPIS_DrainTX(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 218 {
AnnaBridge 167:84c0a372a020 219 uint32_t ctrl_save = spis->gen_ctrl;
AnnaBridge 167:84c0a372a020 220 spis->gen_ctrl = (ctrl_save & ~MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN);
AnnaBridge 167:84c0a372a020 221 spis->gen_ctrl = ctrl_save;
AnnaBridge 167:84c0a372a020 222 }
AnnaBridge 167:84c0a372a020 223
AnnaBridge 167:84c0a372a020 224 /**
AnnaBridge 167:84c0a372a020 225 * @brief Inline function that returns the Transmit FIFO availability.
AnnaBridge 167:84c0a372a020 226 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 227 * @return Number of empty bytes available in write FIFO.
AnnaBridge 167:84c0a372a020 228 */
AnnaBridge 167:84c0a372a020 229 __STATIC_INLINE unsigned SPIS_NumWriteAvail(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 230 {
AnnaBridge 167:84c0a372a020 231 return (MXC_CFG_SPIS_FIFO_DEPTH - ((spis->fifo_stat &
AnnaBridge 167:84c0a372a020 232 MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED) >> MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS));
AnnaBridge 167:84c0a372a020 233 }
AnnaBridge 167:84c0a372a020 234
AnnaBridge 167:84c0a372a020 235 /**
AnnaBridge 167:84c0a372a020 236 * @brief Inline function that returns the Receive FIFO availability.
AnnaBridge 167:84c0a372a020 237 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 238 * @return Number of bytes in read FIFO.
AnnaBridge 167:84c0a372a020 239 */
AnnaBridge 167:84c0a372a020 240 __STATIC_INLINE unsigned SPIS_NumReadAvail(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 241 {
AnnaBridge 167:84c0a372a020 242 return ((spis->fifo_stat & MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED) >>
AnnaBridge 167:84c0a372a020 243 MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS);
AnnaBridge 167:84c0a372a020 244 }
AnnaBridge 167:84c0a372a020 245
AnnaBridge 167:84c0a372a020 246 /**
AnnaBridge 167:84c0a372a020 247 * @brief Inline function that clears the specified interrupt flags.
AnnaBridge 167:84c0a372a020 248 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 249 * @param mask Mask of interrupts to clear, see the @ref SPIS_INTFL_Register Register for details.
AnnaBridge 167:84c0a372a020 250 */
AnnaBridge 167:84c0a372a020 251 __STATIC_INLINE void SPIS_ClearFlags(mxc_spis_regs_t *spis, uint32_t mask)
AnnaBridge 167:84c0a372a020 252 {
AnnaBridge 167:84c0a372a020 253 spis->intfl = mask;
AnnaBridge 167:84c0a372a020 254 }
AnnaBridge 167:84c0a372a020 255
AnnaBridge 167:84c0a372a020 256 /**
AnnaBridge 167:84c0a372a020 257 * @brief Inline function to get the currently interrupt flags.
AnnaBridge 167:84c0a372a020 258 * @param spis Pointer to the SPIS register structure.
AnnaBridge 167:84c0a372a020 259 * @returns Mask of active flags, see the @ref SPIS_INTFL_Register Register for details.
AnnaBridge 167:84c0a372a020 260 */
AnnaBridge 167:84c0a372a020 261 __STATIC_INLINE unsigned SPIS_GetFlags(mxc_spis_regs_t *spis)
AnnaBridge 167:84c0a372a020 262 {
AnnaBridge 167:84c0a372a020 263 return (spis->intfl);
AnnaBridge 167:84c0a372a020 264 }
AnnaBridge 167:84c0a372a020 265 /**@} end of group spis */
AnnaBridge 167:84c0a372a020 266 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 267 }
AnnaBridge 167:84c0a372a020 268 #endif
AnnaBridge 167:84c0a372a020 269
AnnaBridge 167:84c0a372a020 270 #endif /* _SPIS_H_ */