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TARGET_EFM32GG11_STK3701/TOOLCHAIN_ARM_MICRO/efm32gg11b520f2048iq64.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_EFM32GG11_STK3701/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b520f2048iq64.h@170:e95d10626187
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 170:e95d10626187 | 1 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 2 | * @file efm32gg11b520f2048iq64.h |
AnnaBridge | 170:e95d10626187 | 3 | * @brief CMSIS Cortex-M Peripheral Access Layer Header File |
AnnaBridge | 170:e95d10626187 | 4 | * for EFM32GG11B520F2048IQ64 |
AnnaBridge | 170:e95d10626187 | 5 | * @version 5.3.2 |
AnnaBridge | 170:e95d10626187 | 6 | ****************************************************************************** |
AnnaBridge | 170:e95d10626187 | 7 | * # License |
AnnaBridge | 170:e95d10626187 | 8 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
AnnaBridge | 170:e95d10626187 | 9 | ****************************************************************************** |
AnnaBridge | 170:e95d10626187 | 10 | * |
AnnaBridge | 170:e95d10626187 | 11 | * Permission is granted to anyone to use this software for any purpose, |
AnnaBridge | 170:e95d10626187 | 12 | * including commercial applications, and to alter it and redistribute it |
AnnaBridge | 170:e95d10626187 | 13 | * freely, subject to the following restrictions: |
AnnaBridge | 170:e95d10626187 | 14 | * |
AnnaBridge | 170:e95d10626187 | 15 | * 1. The origin of this software must not be misrepresented; you must not |
AnnaBridge | 170:e95d10626187 | 16 | * claim that you wrote the original software.@n |
AnnaBridge | 170:e95d10626187 | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
AnnaBridge | 170:e95d10626187 | 18 | * misrepresented as being the original software.@n |
AnnaBridge | 170:e95d10626187 | 19 | * 3. This notice may not be removed or altered from any source distribution. |
AnnaBridge | 170:e95d10626187 | 20 | * |
AnnaBridge | 170:e95d10626187 | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
AnnaBridge | 170:e95d10626187 | 22 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
AnnaBridge | 170:e95d10626187 | 23 | * providing the Software "AS IS", with no express or implied warranties of any |
AnnaBridge | 170:e95d10626187 | 24 | * kind, including, but not limited to, any implied warranties of |
AnnaBridge | 170:e95d10626187 | 25 | * merchantability or fitness for any particular purpose or warranties against |
AnnaBridge | 170:e95d10626187 | 26 | * infringement of any proprietary rights of a third party. |
AnnaBridge | 170:e95d10626187 | 27 | * |
AnnaBridge | 170:e95d10626187 | 28 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
AnnaBridge | 170:e95d10626187 | 29 | * incidental, or special damages, or any other relief, or for any claim by |
AnnaBridge | 170:e95d10626187 | 30 | * any third party, arising from your use of this Software. |
AnnaBridge | 170:e95d10626187 | 31 | * |
AnnaBridge | 170:e95d10626187 | 32 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 33 | |
AnnaBridge | 170:e95d10626187 | 34 | #if defined(__ICCARM__) |
AnnaBridge | 170:e95d10626187 | 35 | #pragma system_include /* Treat file as system include file. */ |
AnnaBridge | 170:e95d10626187 | 36 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
AnnaBridge | 170:e95d10626187 | 37 | #pragma clang system_header /* Treat file as system include file. */ |
AnnaBridge | 170:e95d10626187 | 38 | #endif |
AnnaBridge | 170:e95d10626187 | 39 | |
AnnaBridge | 170:e95d10626187 | 40 | #ifndef EFM32GG11B520F2048IQ64_H |
AnnaBridge | 170:e95d10626187 | 41 | #define EFM32GG11B520F2048IQ64_H |
AnnaBridge | 170:e95d10626187 | 42 | |
AnnaBridge | 170:e95d10626187 | 43 | #ifdef __cplusplus |
AnnaBridge | 170:e95d10626187 | 44 | extern "C" { |
AnnaBridge | 170:e95d10626187 | 45 | #endif |
AnnaBridge | 170:e95d10626187 | 46 | |
AnnaBridge | 170:e95d10626187 | 47 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 48 | * @addtogroup Parts |
AnnaBridge | 170:e95d10626187 | 49 | * @{ |
AnnaBridge | 170:e95d10626187 | 50 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 51 | |
AnnaBridge | 170:e95d10626187 | 52 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 53 | * @defgroup EFM32GG11B520F2048IQ64 EFM32GG11B520F2048IQ64 |
AnnaBridge | 170:e95d10626187 | 54 | * @{ |
AnnaBridge | 170:e95d10626187 | 55 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 56 | |
AnnaBridge | 170:e95d10626187 | 57 | /** Interrupt Number Definition */ |
AnnaBridge | 170:e95d10626187 | 58 | typedef enum IRQn{ |
AnnaBridge | 170:e95d10626187 | 59 | /****** Cortex-M4 Processor Exceptions Numbers *******************************************/ |
AnnaBridge | 170:e95d10626187 | 60 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
AnnaBridge | 170:e95d10626187 | 61 | HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ |
AnnaBridge | 170:e95d10626187 | 62 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
AnnaBridge | 170:e95d10626187 | 63 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
AnnaBridge | 170:e95d10626187 | 64 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
AnnaBridge | 170:e95d10626187 | 65 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
AnnaBridge | 170:e95d10626187 | 66 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
AnnaBridge | 170:e95d10626187 | 67 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
AnnaBridge | 170:e95d10626187 | 68 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
AnnaBridge | 170:e95d10626187 | 69 | |
AnnaBridge | 170:e95d10626187 | 70 | /****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ |
AnnaBridge | 170:e95d10626187 | 71 | |
AnnaBridge | 170:e95d10626187 | 72 | EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ |
AnnaBridge | 170:e95d10626187 | 73 | WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 74 | LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ |
AnnaBridge | 170:e95d10626187 | 75 | GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ |
AnnaBridge | 170:e95d10626187 | 76 | SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ |
AnnaBridge | 170:e95d10626187 | 77 | TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 78 | USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 79 | USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 80 | ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 81 | ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 82 | IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 83 | I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 84 | I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 85 | GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ |
AnnaBridge | 170:e95d10626187 | 86 | TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 87 | TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 88 | TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 89 | USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 90 | USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 91 | USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 92 | USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 93 | UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 94 | UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 95 | UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 96 | UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 97 | LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 98 | LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 99 | LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 100 | PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 101 | PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 102 | PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 103 | RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ |
AnnaBridge | 170:e95d10626187 | 104 | CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ |
AnnaBridge | 170:e95d10626187 | 105 | MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ |
AnnaBridge | 170:e95d10626187 | 106 | CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 107 | CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ |
AnnaBridge | 170:e95d10626187 | 108 | FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ |
AnnaBridge | 170:e95d10626187 | 109 | USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 110 | USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 111 | USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 112 | USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 113 | WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 114 | WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 115 | WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 116 | WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 117 | I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 118 | VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 119 | TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 120 | TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 121 | TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 122 | USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 123 | USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ |
AnnaBridge | 170:e95d10626187 | 124 | CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ |
AnnaBridge | 170:e95d10626187 | 125 | LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ |
AnnaBridge | 170:e95d10626187 | 126 | EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ |
AnnaBridge | 170:e95d10626187 | 127 | ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 128 | ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 129 | LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ |
AnnaBridge | 170:e95d10626187 | 130 | CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 131 | CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 132 | RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ |
AnnaBridge | 170:e95d10626187 | 133 | WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 134 | LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 135 | TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ |
AnnaBridge | 170:e95d10626187 | 136 | } IRQn_Type; |
AnnaBridge | 170:e95d10626187 | 137 | |
AnnaBridge | 170:e95d10626187 | 138 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 139 | * @defgroup EFM32GG11B520F2048IQ64_Core Core |
AnnaBridge | 170:e95d10626187 | 140 | * @{ |
AnnaBridge | 170:e95d10626187 | 141 | * @brief Processor and Core Peripheral Section |
AnnaBridge | 170:e95d10626187 | 142 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 143 | #define __MPU_PRESENT 1 /**< Presence of MPU */ |
AnnaBridge | 170:e95d10626187 | 144 | #define __FPU_PRESENT 1 /**< Presence of FPU */ |
AnnaBridge | 170:e95d10626187 | 145 | #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ |
AnnaBridge | 170:e95d10626187 | 146 | #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ |
AnnaBridge | 170:e95d10626187 | 147 | #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ |
AnnaBridge | 170:e95d10626187 | 148 | |
AnnaBridge | 170:e95d10626187 | 149 | /** @} End of group EFM32GG11B520F2048IQ64_Core */ |
AnnaBridge | 170:e95d10626187 | 150 | |
AnnaBridge | 170:e95d10626187 | 151 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 152 | * @defgroup EFM32GG11B520F2048IQ64_Part Part |
AnnaBridge | 170:e95d10626187 | 153 | * @{ |
AnnaBridge | 170:e95d10626187 | 154 | ******************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 155 | |
AnnaBridge | 170:e95d10626187 | 156 | /** Part family */ |
AnnaBridge | 170:e95d10626187 | 157 | |
AnnaBridge | 170:e95d10626187 | 158 | #define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ |
AnnaBridge | 170:e95d10626187 | 159 | #define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ |
AnnaBridge | 170:e95d10626187 | 160 | #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ |
AnnaBridge | 170:e95d10626187 | 161 | #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ |
AnnaBridge | 170:e95d10626187 | 162 | #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ |
AnnaBridge | 170:e95d10626187 | 163 | #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ |
AnnaBridge | 170:e95d10626187 | 164 | #define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ |
AnnaBridge | 170:e95d10626187 | 165 | #define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ |
AnnaBridge | 170:e95d10626187 | 166 | #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ |
AnnaBridge | 170:e95d10626187 | 167 | #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ |
AnnaBridge | 170:e95d10626187 | 168 | #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ |
AnnaBridge | 170:e95d10626187 | 169 | #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ |
AnnaBridge | 170:e95d10626187 | 170 | |
AnnaBridge | 170:e95d10626187 | 171 | /* If part number is not defined as compiler option, define it */ |
AnnaBridge | 170:e95d10626187 | 172 | #if !defined(EFM32GG11B520F2048IQ64) |
AnnaBridge | 170:e95d10626187 | 173 | #define EFM32GG11B520F2048IQ64 1 /**< GIANT Gecko Part */ |
AnnaBridge | 170:e95d10626187 | 174 | #endif |
AnnaBridge | 170:e95d10626187 | 175 | |
AnnaBridge | 170:e95d10626187 | 176 | /** Configure part number */ |
AnnaBridge | 170:e95d10626187 | 177 | #define PART_NUMBER "EFM32GG11B520F2048IQ64" /**< Part Number */ |
AnnaBridge | 170:e95d10626187 | 178 | |
AnnaBridge | 170:e95d10626187 | 179 | /** Memory Base addresses and limits */ |
AnnaBridge | 170:e95d10626187 | 180 | #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ |
AnnaBridge | 170:e95d10626187 | 181 | #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ |
AnnaBridge | 170:e95d10626187 | 182 | #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ |
AnnaBridge | 170:e95d10626187 | 183 | #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ |
AnnaBridge | 170:e95d10626187 | 184 | #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ |
AnnaBridge | 170:e95d10626187 | 185 | #define RAM2_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2 available address space */ |
AnnaBridge | 170:e95d10626187 | 186 | #define RAM2_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM2 end address */ |
AnnaBridge | 170:e95d10626187 | 187 | #define RAM2_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2 used bits */ |
AnnaBridge | 170:e95d10626187 | 188 | #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ |
AnnaBridge | 170:e95d10626187 | 189 | #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ |
AnnaBridge | 170:e95d10626187 | 190 | #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ |
AnnaBridge | 170:e95d10626187 | 191 | #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ |
AnnaBridge | 170:e95d10626187 | 192 | #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ |
AnnaBridge | 170:e95d10626187 | 193 | #define PER_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER available address space */ |
AnnaBridge | 170:e95d10626187 | 194 | #define PER_MEM_END ((uint32_t) 0x4004FFFFUL) /**< PER end address */ |
AnnaBridge | 170:e95d10626187 | 195 | #define PER_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER used bits */ |
AnnaBridge | 170:e95d10626187 | 196 | #define SDIO_MEM_BASE ((uint32_t) 0x400F1000UL) /**< SDIO base address */ |
AnnaBridge | 170:e95d10626187 | 197 | #define SDIO_MEM_SIZE ((uint32_t) 0x1000UL) /**< SDIO available address space */ |
AnnaBridge | 170:e95d10626187 | 198 | #define SDIO_MEM_END ((uint32_t) 0x400F1FFFUL) /**< SDIO end address */ |
AnnaBridge | 170:e95d10626187 | 199 | #define SDIO_MEM_BITS ((uint32_t) 0x0000000CUL) /**< SDIO used bits */ |
AnnaBridge | 170:e95d10626187 | 200 | #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ |
AnnaBridge | 170:e95d10626187 | 201 | #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ |
AnnaBridge | 170:e95d10626187 | 202 | #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ |
AnnaBridge | 170:e95d10626187 | 203 | #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ |
AnnaBridge | 170:e95d10626187 | 204 | #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ |
AnnaBridge | 170:e95d10626187 | 205 | #define FLASH_MEM_SIZE ((uint32_t) 0x4000000UL) /**< FLASH available address space */ |
AnnaBridge | 170:e95d10626187 | 206 | #define FLASH_MEM_END ((uint32_t) 0x03FFFFFFUL) /**< FLASH end address */ |
AnnaBridge | 170:e95d10626187 | 207 | #define FLASH_MEM_BITS ((uint32_t) 0x0000001AUL) /**< FLASH used bits */ |
AnnaBridge | 170:e95d10626187 | 208 | #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ |
AnnaBridge | 170:e95d10626187 | 209 | #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ |
AnnaBridge | 170:e95d10626187 | 210 | #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ |
AnnaBridge | 170:e95d10626187 | 211 | #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ |
AnnaBridge | 170:e95d10626187 | 212 | #define QSPI0_MEM_BASE ((uint32_t) 0xC0000000UL) /**< QSPI0 base address */ |
AnnaBridge | 170:e95d10626187 | 213 | #define QSPI0_MEM_SIZE ((uint32_t) 0x10000000UL) /**< QSPI0 available address space */ |
AnnaBridge | 170:e95d10626187 | 214 | #define QSPI0_MEM_END ((uint32_t) 0xCFFFFFFFUL) /**< QSPI0 end address */ |
AnnaBridge | 170:e95d10626187 | 215 | #define QSPI0_MEM_BITS ((uint32_t) 0x0000001CUL) /**< QSPI0 used bits */ |
AnnaBridge | 170:e95d10626187 | 216 | #define PER1_BITCLR_MEM_BASE ((uint32_t) 0x44050000UL) /**< PER1_BITCLR base address */ |
AnnaBridge | 170:e95d10626187 | 217 | #define PER1_BITCLR_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITCLR available address space */ |
AnnaBridge | 170:e95d10626187 | 218 | #define PER1_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER1_BITCLR end address */ |
AnnaBridge | 170:e95d10626187 | 219 | #define PER1_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITCLR used bits */ |
AnnaBridge | 170:e95d10626187 | 220 | #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ |
AnnaBridge | 170:e95d10626187 | 221 | #define PER_BITCLR_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITCLR available address space */ |
AnnaBridge | 170:e95d10626187 | 222 | #define PER_BITCLR_MEM_END ((uint32_t) 0x4404FFFFUL) /**< PER_BITCLR end address */ |
AnnaBridge | 170:e95d10626187 | 223 | #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITCLR used bits */ |
AnnaBridge | 170:e95d10626187 | 224 | #define PER1_BITSET_MEM_BASE ((uint32_t) 0x46050000UL) /**< PER1_BITSET base address */ |
AnnaBridge | 170:e95d10626187 | 225 | #define PER1_BITSET_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITSET available address space */ |
AnnaBridge | 170:e95d10626187 | 226 | #define PER1_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER1_BITSET end address */ |
AnnaBridge | 170:e95d10626187 | 227 | #define PER1_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITSET used bits */ |
AnnaBridge | 170:e95d10626187 | 228 | #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ |
AnnaBridge | 170:e95d10626187 | 229 | #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ |
AnnaBridge | 170:e95d10626187 | 230 | #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ |
AnnaBridge | 170:e95d10626187 | 231 | #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ |
AnnaBridge | 170:e95d10626187 | 232 | #define USB_MEM_BASE ((uint32_t) 0x40100000UL) /**< USB base address */ |
AnnaBridge | 170:e95d10626187 | 233 | #define USB_MEM_SIZE ((uint32_t) 0x40000UL) /**< USB available address space */ |
AnnaBridge | 170:e95d10626187 | 234 | #define USB_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USB end address */ |
AnnaBridge | 170:e95d10626187 | 235 | #define USB_MEM_BITS ((uint32_t) 0x00000012UL) /**< USB used bits */ |
AnnaBridge | 170:e95d10626187 | 236 | #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */ |
AnnaBridge | 170:e95d10626187 | 237 | #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */ |
AnnaBridge | 170:e95d10626187 | 238 | #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */ |
AnnaBridge | 170:e95d10626187 | 239 | #define EBI_CODE_MEM_BITS ((uint32_t) 0x0000001CUL) /**< EBI_CODE used bits */ |
AnnaBridge | 170:e95d10626187 | 240 | #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ |
AnnaBridge | 170:e95d10626187 | 241 | #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ |
AnnaBridge | 170:e95d10626187 | 242 | #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ |
AnnaBridge | 170:e95d10626187 | 243 | #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ |
AnnaBridge | 170:e95d10626187 | 244 | #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ |
AnnaBridge | 170:e95d10626187 | 245 | #define PER_BITSET_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITSET available address space */ |
AnnaBridge | 170:e95d10626187 | 246 | #define PER_BITSET_MEM_END ((uint32_t) 0x4604FFFFUL) /**< PER_BITSET end address */ |
AnnaBridge | 170:e95d10626187 | 247 | #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITSET used bits */ |
AnnaBridge | 170:e95d10626187 | 248 | #define PER1_MEM_BASE ((uint32_t) 0x40050000UL) /**< PER1 base address */ |
AnnaBridge | 170:e95d10626187 | 249 | #define PER1_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1 available address space */ |
AnnaBridge | 170:e95d10626187 | 250 | #define PER1_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER1 end address */ |
AnnaBridge | 170:e95d10626187 | 251 | #define PER1_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1 used bits */ |
AnnaBridge | 170:e95d10626187 | 252 | #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ |
AnnaBridge | 170:e95d10626187 | 253 | #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2_CODE available address space */ |
AnnaBridge | 170:e95d10626187 | 254 | #define RAM2_CODE_MEM_END ((uint32_t) 0x1007FFFFUL) /**< RAM2_CODE end address */ |
AnnaBridge | 170:e95d10626187 | 255 | #define RAM2_CODE_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2_CODE used bits */ |
AnnaBridge | 170:e95d10626187 | 256 | #define QSPI0_CODE_MEM_BASE ((uint32_t) 0x04000000UL) /**< QSPI0_CODE base address */ |
AnnaBridge | 170:e95d10626187 | 257 | #define QSPI0_CODE_MEM_SIZE ((uint32_t) 0x8000000UL) /**< QSPI0_CODE available address space */ |
AnnaBridge | 170:e95d10626187 | 258 | #define QSPI0_CODE_MEM_END ((uint32_t) 0x0BFFFFFFUL) /**< QSPI0_CODE end address */ |
AnnaBridge | 170:e95d10626187 | 259 | #define QSPI0_CODE_MEM_BITS ((uint32_t) 0x0000001BUL) /**< QSPI0_CODE used bits */ |
AnnaBridge | 170:e95d10626187 | 260 | #define FLASH_INFO_MEM_BASE ((uint32_t) 0x0F000000UL) /**< FLASH_INFO base address */ |
AnnaBridge | 170:e95d10626187 | 261 | #define FLASH_INFO_MEM_SIZE ((uint32_t) 0x1000000UL) /**< FLASH_INFO available address space */ |
AnnaBridge | 170:e95d10626187 | 262 | #define FLASH_INFO_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH_INFO end address */ |
AnnaBridge | 170:e95d10626187 | 263 | #define FLASH_INFO_MEM_BITS ((uint32_t) 0x00000018UL) /**< FLASH_INFO used bits */ |
AnnaBridge | 170:e95d10626187 | 264 | #define RAM0_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM0 base address */ |
AnnaBridge | 170:e95d10626187 | 265 | #define RAM0_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0 available address space */ |
AnnaBridge | 170:e95d10626187 | 266 | #define RAM0_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM0 end address */ |
AnnaBridge | 170:e95d10626187 | 267 | #define RAM0_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0 used bits */ |
AnnaBridge | 170:e95d10626187 | 268 | #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ |
AnnaBridge | 170:e95d10626187 | 269 | #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */ |
AnnaBridge | 170:e95d10626187 | 270 | #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */ |
AnnaBridge | 170:e95d10626187 | 271 | #define EBI_MEM_BITS ((uint32_t) 0x0000001EUL) /**< EBI used bits */ |
AnnaBridge | 170:e95d10626187 | 272 | |
AnnaBridge | 170:e95d10626187 | 273 | /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ |
AnnaBridge | 170:e95d10626187 | 274 | #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ |
AnnaBridge | 170:e95d10626187 | 275 | #define RAM_MEM_SIZE ((uint32_t) 0x80000UL) /**< RAM available address space */ |
AnnaBridge | 170:e95d10626187 | 276 | #define RAM_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM end address */ |
AnnaBridge | 170:e95d10626187 | 277 | #define RAM_MEM_BITS ((uint32_t) 0x00000013UL) /**< RAM used bits */ |
AnnaBridge | 170:e95d10626187 | 278 | |
AnnaBridge | 170:e95d10626187 | 279 | /** Bit banding area */ |
AnnaBridge | 170:e95d10626187 | 280 | #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ |
AnnaBridge | 170:e95d10626187 | 281 | #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ |
AnnaBridge | 170:e95d10626187 | 282 | |
AnnaBridge | 170:e95d10626187 | 283 | /** Flash and SRAM limits for EFM32GG11B520F2048IQ64 */ |
AnnaBridge | 170:e95d10626187 | 284 | #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ |
AnnaBridge | 170:e95d10626187 | 285 | #define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ |
AnnaBridge | 170:e95d10626187 | 286 | #define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ |
AnnaBridge | 170:e95d10626187 | 287 | #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ |
AnnaBridge | 170:e95d10626187 | 288 | #define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ |
AnnaBridge | 170:e95d10626187 | 289 | #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ |
AnnaBridge | 170:e95d10626187 | 290 | #define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ |
AnnaBridge | 170:e95d10626187 | 291 | #define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ |
AnnaBridge | 170:e95d10626187 | 292 | #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ |
AnnaBridge | 170:e95d10626187 | 293 | |
AnnaBridge | 170:e95d10626187 | 294 | /** AF channels connect the different on-chip peripherals with the af-mux */ |
AnnaBridge | 170:e95d10626187 | 295 | #define AFCHAN_MAX 355 |
AnnaBridge | 170:e95d10626187 | 296 | /** AF channel maximum location number */ |
AnnaBridge | 170:e95d10626187 | 297 | #define AFCHANLOC_MAX 8 |
AnnaBridge | 170:e95d10626187 | 298 | /** Analog AF channels */ |
AnnaBridge | 170:e95d10626187 | 299 | #define AFACHAN_MAX 184 |
AnnaBridge | 170:e95d10626187 | 300 | |
AnnaBridge | 170:e95d10626187 | 301 | /* Part number capabilities */ |
AnnaBridge | 170:e95d10626187 | 302 | |
AnnaBridge | 170:e95d10626187 | 303 | #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ |
AnnaBridge | 170:e95d10626187 | 304 | #define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ |
AnnaBridge | 170:e95d10626187 | 305 | #define CAN_PRESENT /**< CAN is available in this part */ |
AnnaBridge | 170:e95d10626187 | 306 | #define CAN_COUNT 2 /**< 2 CANs available */ |
AnnaBridge | 170:e95d10626187 | 307 | #define TIMER_PRESENT /**< TIMER is available in this part */ |
AnnaBridge | 170:e95d10626187 | 308 | #define TIMER_COUNT 7 /**< 7 TIMERs available */ |
AnnaBridge | 170:e95d10626187 | 309 | #define WTIMER_PRESENT /**< WTIMER is available in this part */ |
AnnaBridge | 170:e95d10626187 | 310 | #define WTIMER_COUNT 4 /**< 4 WTIMERs available */ |
AnnaBridge | 170:e95d10626187 | 311 | #define USART_PRESENT /**< USART is available in this part */ |
AnnaBridge | 170:e95d10626187 | 312 | #define USART_COUNT 6 /**< 6 USARTs available */ |
AnnaBridge | 170:e95d10626187 | 313 | #define UART_PRESENT /**< UART is available in this part */ |
AnnaBridge | 170:e95d10626187 | 314 | #define UART_COUNT 2 /**< 2 UARTs available */ |
AnnaBridge | 170:e95d10626187 | 315 | #define LEUART_PRESENT /**< LEUART is available in this part */ |
AnnaBridge | 170:e95d10626187 | 316 | #define LEUART_COUNT 2 /**< 2 LEUARTs available */ |
AnnaBridge | 170:e95d10626187 | 317 | #define LETIMER_PRESENT /**< LETIMER is available in this part */ |
AnnaBridge | 170:e95d10626187 | 318 | #define LETIMER_COUNT 2 /**< 2 LETIMERs available */ |
AnnaBridge | 170:e95d10626187 | 319 | #define PCNT_PRESENT /**< PCNT is available in this part */ |
AnnaBridge | 170:e95d10626187 | 320 | #define PCNT_COUNT 3 /**< 3 PCNTs available */ |
AnnaBridge | 170:e95d10626187 | 321 | #define I2C_PRESENT /**< I2C is available in this part */ |
AnnaBridge | 170:e95d10626187 | 322 | #define I2C_COUNT 3 /**< 3 I2Cs available */ |
AnnaBridge | 170:e95d10626187 | 323 | #define ADC_PRESENT /**< ADC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 324 | #define ADC_COUNT 2 /**< 2 ADCs available */ |
AnnaBridge | 170:e95d10626187 | 325 | #define ACMP_PRESENT /**< ACMP is available in this part */ |
AnnaBridge | 170:e95d10626187 | 326 | #define ACMP_COUNT 4 /**< 4 ACMPs available */ |
AnnaBridge | 170:e95d10626187 | 327 | #define VDAC_PRESENT /**< VDAC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 328 | #define VDAC_COUNT 1 /**< 1 VDACs available */ |
AnnaBridge | 170:e95d10626187 | 329 | #define IDAC_PRESENT /**< IDAC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 330 | #define IDAC_COUNT 1 /**< 1 IDACs available */ |
AnnaBridge | 170:e95d10626187 | 331 | #define WDOG_PRESENT /**< WDOG is available in this part */ |
AnnaBridge | 170:e95d10626187 | 332 | #define WDOG_COUNT 2 /**< 2 WDOGs available */ |
AnnaBridge | 170:e95d10626187 | 333 | #define TRNG_PRESENT /**< TRNG is available in this part */ |
AnnaBridge | 170:e95d10626187 | 334 | #define TRNG_COUNT 1 /**< 1 TRNGs available */ |
AnnaBridge | 170:e95d10626187 | 335 | #define MSC_PRESENT /**< MSC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 336 | #define MSC_COUNT 1 /**< 1 MSC available */ |
AnnaBridge | 170:e95d10626187 | 337 | #define EMU_PRESENT /**< EMU is available in this part */ |
AnnaBridge | 170:e95d10626187 | 338 | #define EMU_COUNT 1 /**< 1 EMU available */ |
AnnaBridge | 170:e95d10626187 | 339 | #define RMU_PRESENT /**< RMU is available in this part */ |
AnnaBridge | 170:e95d10626187 | 340 | #define RMU_COUNT 1 /**< 1 RMU available */ |
AnnaBridge | 170:e95d10626187 | 341 | #define CMU_PRESENT /**< CMU is available in this part */ |
AnnaBridge | 170:e95d10626187 | 342 | #define CMU_COUNT 1 /**< 1 CMU available */ |
AnnaBridge | 170:e95d10626187 | 343 | #define LESENSE_PRESENT /**< LESENSE is available in this part */ |
AnnaBridge | 170:e95d10626187 | 344 | #define LESENSE_COUNT 1 /**< 1 LESENSE available */ |
AnnaBridge | 170:e95d10626187 | 345 | #define EBI_PRESENT /**< EBI is available in this part */ |
AnnaBridge | 170:e95d10626187 | 346 | #define EBI_COUNT 1 /**< 1 EBI available */ |
AnnaBridge | 170:e95d10626187 | 347 | #define GPIO_PRESENT /**< GPIO is available in this part */ |
AnnaBridge | 170:e95d10626187 | 348 | #define GPIO_COUNT 1 /**< 1 GPIO available */ |
AnnaBridge | 170:e95d10626187 | 349 | #define PRS_PRESENT /**< PRS is available in this part */ |
AnnaBridge | 170:e95d10626187 | 350 | #define PRS_COUNT 1 /**< 1 PRS available */ |
AnnaBridge | 170:e95d10626187 | 351 | #define LDMA_PRESENT /**< LDMA is available in this part */ |
AnnaBridge | 170:e95d10626187 | 352 | #define LDMA_COUNT 1 /**< 1 LDMA available */ |
AnnaBridge | 170:e95d10626187 | 353 | #define FPUEH_PRESENT /**< FPUEH is available in this part */ |
AnnaBridge | 170:e95d10626187 | 354 | #define FPUEH_COUNT 1 /**< 1 FPUEH available */ |
AnnaBridge | 170:e95d10626187 | 355 | #define GPCRC_PRESENT /**< GPCRC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 356 | #define GPCRC_COUNT 1 /**< 1 GPCRC available */ |
AnnaBridge | 170:e95d10626187 | 357 | #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ |
AnnaBridge | 170:e95d10626187 | 358 | #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ |
AnnaBridge | 170:e95d10626187 | 359 | #define CSEN_PRESENT /**< CSEN is available in this part */ |
AnnaBridge | 170:e95d10626187 | 360 | #define CSEN_COUNT 1 /**< 1 CSEN available */ |
AnnaBridge | 170:e95d10626187 | 361 | #define LCD_PRESENT /**< LCD is available in this part */ |
AnnaBridge | 170:e95d10626187 | 362 | #define LCD_COUNT 1 /**< 1 LCD available */ |
AnnaBridge | 170:e95d10626187 | 363 | #define RTC_PRESENT /**< RTC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 364 | #define RTC_COUNT 1 /**< 1 RTC available */ |
AnnaBridge | 170:e95d10626187 | 365 | #define RTCC_PRESENT /**< RTCC is available in this part */ |
AnnaBridge | 170:e95d10626187 | 366 | #define RTCC_COUNT 1 /**< 1 RTCC available */ |
AnnaBridge | 170:e95d10626187 | 367 | #define ETM_PRESENT /**< ETM is available in this part */ |
AnnaBridge | 170:e95d10626187 | 368 | #define ETM_COUNT 1 /**< 1 ETM available */ |
AnnaBridge | 170:e95d10626187 | 369 | #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ |
AnnaBridge | 170:e95d10626187 | 370 | #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ |
AnnaBridge | 170:e95d10626187 | 371 | #define SMU_PRESENT /**< SMU is available in this part */ |
AnnaBridge | 170:e95d10626187 | 372 | #define SMU_COUNT 1 /**< 1 SMU available */ |
AnnaBridge | 170:e95d10626187 | 373 | |
AnnaBridge | 170:e95d10626187 | 374 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
AnnaBridge | 170:e95d10626187 | 375 | #include "system_efm32gg11b.h" /* System Header File */ |
AnnaBridge | 170:e95d10626187 | 376 | |
AnnaBridge | 170:e95d10626187 | 377 | /** @} End of group EFM32GG11B520F2048IQ64_Part */ |
AnnaBridge | 170:e95d10626187 | 378 | |
AnnaBridge | 170:e95d10626187 | 379 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 380 | * @defgroup EFM32GG11B520F2048IQ64_Peripheral_TypeDefs Peripheral TypeDefs |
AnnaBridge | 170:e95d10626187 | 381 | * @{ |
AnnaBridge | 170:e95d10626187 | 382 | * @brief Device Specific Peripheral Register Structures |
AnnaBridge | 170:e95d10626187 | 383 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 384 | |
AnnaBridge | 170:e95d10626187 | 385 | #include "efm32gg11b_msc.h" |
AnnaBridge | 170:e95d10626187 | 386 | #include "efm32gg11b_emu.h" |
AnnaBridge | 170:e95d10626187 | 387 | #include "efm32gg11b_rmu.h" |
AnnaBridge | 170:e95d10626187 | 388 | |
AnnaBridge | 170:e95d10626187 | 389 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 390 | * @defgroup EFM32GG11B520F2048IQ64_CMU CMU |
AnnaBridge | 170:e95d10626187 | 391 | * @{ |
AnnaBridge | 170:e95d10626187 | 392 | * @brief EFM32GG11B520F2048IQ64_CMU Register Declaration |
AnnaBridge | 170:e95d10626187 | 393 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 394 | /** CMU Register Declaration */ |
AnnaBridge | 170:e95d10626187 | 395 | typedef struct { |
AnnaBridge | 170:e95d10626187 | 396 | __IOM uint32_t CTRL; /**< CMU Control Register */ |
AnnaBridge | 170:e95d10626187 | 397 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 398 | __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ |
AnnaBridge | 170:e95d10626187 | 399 | |
AnnaBridge | 170:e95d10626187 | 400 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 401 | __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ |
AnnaBridge | 170:e95d10626187 | 402 | |
AnnaBridge | 170:e95d10626187 | 403 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 404 | __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ |
AnnaBridge | 170:e95d10626187 | 405 | |
AnnaBridge | 170:e95d10626187 | 406 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 407 | __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ |
AnnaBridge | 170:e95d10626187 | 408 | __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ |
AnnaBridge | 170:e95d10626187 | 409 | |
AnnaBridge | 170:e95d10626187 | 410 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 411 | __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ |
AnnaBridge | 170:e95d10626187 | 412 | __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ |
AnnaBridge | 170:e95d10626187 | 413 | __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ |
AnnaBridge | 170:e95d10626187 | 414 | __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ |
AnnaBridge | 170:e95d10626187 | 415 | |
AnnaBridge | 170:e95d10626187 | 416 | uint32_t RESERVED5[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 417 | __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ |
AnnaBridge | 170:e95d10626187 | 418 | __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ |
AnnaBridge | 170:e95d10626187 | 419 | uint32_t RESERVED6[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 420 | __IOM uint32_t CALCTRL; /**< Calibration Control Register */ |
AnnaBridge | 170:e95d10626187 | 421 | __IOM uint32_t CALCNT; /**< Calibration Counter Register */ |
AnnaBridge | 170:e95d10626187 | 422 | uint32_t RESERVED7[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 423 | __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ |
AnnaBridge | 170:e95d10626187 | 424 | __IOM uint32_t CMD; /**< Command Register */ |
AnnaBridge | 170:e95d10626187 | 425 | uint32_t RESERVED8[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 426 | __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ |
AnnaBridge | 170:e95d10626187 | 427 | __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ |
AnnaBridge | 170:e95d10626187 | 428 | uint32_t RESERVED9[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 429 | __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ |
AnnaBridge | 170:e95d10626187 | 430 | __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ |
AnnaBridge | 170:e95d10626187 | 431 | __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ |
AnnaBridge | 170:e95d10626187 | 432 | __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ |
AnnaBridge | 170:e95d10626187 | 433 | __IM uint32_t STATUS; /**< Status Register */ |
AnnaBridge | 170:e95d10626187 | 434 | __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ |
AnnaBridge | 170:e95d10626187 | 435 | uint32_t RESERVED10[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 436 | __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ |
AnnaBridge | 170:e95d10626187 | 437 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
AnnaBridge | 170:e95d10626187 | 438 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
AnnaBridge | 170:e95d10626187 | 439 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
AnnaBridge | 170:e95d10626187 | 440 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
AnnaBridge | 170:e95d10626187 | 441 | __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ |
AnnaBridge | 170:e95d10626187 | 442 | |
AnnaBridge | 170:e95d10626187 | 443 | uint32_t RESERVED11[3]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 444 | __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ |
AnnaBridge | 170:e95d10626187 | 445 | __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ |
AnnaBridge | 170:e95d10626187 | 446 | |
AnnaBridge | 170:e95d10626187 | 447 | uint32_t RESERVED12[6]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 448 | __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 449 | uint32_t RESERVED13[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 450 | __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 451 | __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 452 | __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 453 | uint32_t RESERVED14[3]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 454 | __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ |
AnnaBridge | 170:e95d10626187 | 455 | __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ |
AnnaBridge | 170:e95d10626187 | 456 | __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ |
AnnaBridge | 170:e95d10626187 | 457 | __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ |
AnnaBridge | 170:e95d10626187 | 458 | |
AnnaBridge | 170:e95d10626187 | 459 | uint32_t RESERVED15[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 460 | __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ |
AnnaBridge | 170:e95d10626187 | 461 | __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ |
AnnaBridge | 170:e95d10626187 | 462 | __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ |
AnnaBridge | 170:e95d10626187 | 463 | __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 464 | uint32_t RESERVED16[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 465 | __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ |
AnnaBridge | 170:e95d10626187 | 466 | uint32_t RESERVED17[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 467 | __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ |
AnnaBridge | 170:e95d10626187 | 468 | |
AnnaBridge | 170:e95d10626187 | 469 | uint32_t RESERVED18[3]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 470 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
AnnaBridge | 170:e95d10626187 | 471 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
AnnaBridge | 170:e95d10626187 | 472 | uint32_t RESERVED19[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 473 | __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ |
AnnaBridge | 170:e95d10626187 | 474 | |
AnnaBridge | 170:e95d10626187 | 475 | uint32_t RESERVED20[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 476 | __IOM uint32_t ADCCTRL; /**< ADC Control Register */ |
AnnaBridge | 170:e95d10626187 | 477 | |
AnnaBridge | 170:e95d10626187 | 478 | uint32_t RESERVED21[4]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 479 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
AnnaBridge | 170:e95d10626187 | 480 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 481 | __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 482 | uint32_t RESERVED22[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 483 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
AnnaBridge | 170:e95d10626187 | 484 | __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ |
AnnaBridge | 170:e95d10626187 | 485 | |
AnnaBridge | 170:e95d10626187 | 486 | uint32_t RESERVED23[26]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 487 | __IOM uint32_t USBCTRL; /**< USB Control Register */ |
AnnaBridge | 170:e95d10626187 | 488 | __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ |
AnnaBridge | 170:e95d10626187 | 489 | } CMU_TypeDef; /** @} */ |
AnnaBridge | 170:e95d10626187 | 490 | |
AnnaBridge | 170:e95d10626187 | 491 | #include "efm32gg11b_crypto.h" |
AnnaBridge | 170:e95d10626187 | 492 | #include "efm32gg11b_lesense_st.h" |
AnnaBridge | 170:e95d10626187 | 493 | #include "efm32gg11b_lesense_buf.h" |
AnnaBridge | 170:e95d10626187 | 494 | #include "efm32gg11b_lesense_ch.h" |
AnnaBridge | 170:e95d10626187 | 495 | #include "efm32gg11b_lesense.h" |
AnnaBridge | 170:e95d10626187 | 496 | #include "efm32gg11b_ebi.h" |
AnnaBridge | 170:e95d10626187 | 497 | #include "efm32gg11b_gpio_p.h" |
AnnaBridge | 170:e95d10626187 | 498 | #include "efm32gg11b_gpio.h" |
AnnaBridge | 170:e95d10626187 | 499 | #include "efm32gg11b_prs_ch.h" |
AnnaBridge | 170:e95d10626187 | 500 | |
AnnaBridge | 170:e95d10626187 | 501 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 502 | * @defgroup EFM32GG11B520F2048IQ64_PRS PRS |
AnnaBridge | 170:e95d10626187 | 503 | * @{ |
AnnaBridge | 170:e95d10626187 | 504 | * @brief EFM32GG11B520F2048IQ64_PRS Register Declaration |
AnnaBridge | 170:e95d10626187 | 505 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 506 | /** PRS Register Declaration */ |
AnnaBridge | 170:e95d10626187 | 507 | typedef struct { |
AnnaBridge | 170:e95d10626187 | 508 | __IOM uint32_t SWPULSE; /**< Software Pulse Register */ |
AnnaBridge | 170:e95d10626187 | 509 | __IOM uint32_t SWLEVEL; /**< Software Level Register */ |
AnnaBridge | 170:e95d10626187 | 510 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
AnnaBridge | 170:e95d10626187 | 511 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 512 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 513 | __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 514 | __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 515 | __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 516 | __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 517 | __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ |
AnnaBridge | 170:e95d10626187 | 518 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 519 | __IOM uint32_t CTRL; /**< Control Register */ |
AnnaBridge | 170:e95d10626187 | 520 | __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ |
AnnaBridge | 170:e95d10626187 | 521 | __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ |
AnnaBridge | 170:e95d10626187 | 522 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 523 | __IM uint32_t PEEK; /**< PRS Channel Values */ |
AnnaBridge | 170:e95d10626187 | 524 | |
AnnaBridge | 170:e95d10626187 | 525 | uint32_t RESERVED3[3]; /**< Reserved registers */ |
AnnaBridge | 170:e95d10626187 | 526 | PRS_CH_TypeDef CH[24]; /**< Channel registers */ |
AnnaBridge | 170:e95d10626187 | 527 | } PRS_TypeDef; /** @} */ |
AnnaBridge | 170:e95d10626187 | 528 | |
AnnaBridge | 170:e95d10626187 | 529 | #include "efm32gg11b_ldma_ch.h" |
AnnaBridge | 170:e95d10626187 | 530 | #include "efm32gg11b_ldma.h" |
AnnaBridge | 170:e95d10626187 | 531 | #include "efm32gg11b_fpueh.h" |
AnnaBridge | 170:e95d10626187 | 532 | #include "efm32gg11b_gpcrc.h" |
AnnaBridge | 170:e95d10626187 | 533 | #include "efm32gg11b_can_mir.h" |
AnnaBridge | 170:e95d10626187 | 534 | #include "efm32gg11b_can.h" |
AnnaBridge | 170:e95d10626187 | 535 | #include "efm32gg11b_timer_cc.h" |
AnnaBridge | 170:e95d10626187 | 536 | #include "efm32gg11b_timer.h" |
AnnaBridge | 170:e95d10626187 | 537 | #include "efm32gg11b_usart.h" |
AnnaBridge | 170:e95d10626187 | 538 | #include "efm32gg11b_leuart.h" |
AnnaBridge | 170:e95d10626187 | 539 | #include "efm32gg11b_letimer.h" |
AnnaBridge | 170:e95d10626187 | 540 | #include "efm32gg11b_cryotimer.h" |
AnnaBridge | 170:e95d10626187 | 541 | #include "efm32gg11b_pcnt.h" |
AnnaBridge | 170:e95d10626187 | 542 | #include "efm32gg11b_i2c.h" |
AnnaBridge | 170:e95d10626187 | 543 | #include "efm32gg11b_adc.h" |
AnnaBridge | 170:e95d10626187 | 544 | #include "efm32gg11b_acmp.h" |
AnnaBridge | 170:e95d10626187 | 545 | #include "efm32gg11b_vdac_opa.h" |
AnnaBridge | 170:e95d10626187 | 546 | #include "efm32gg11b_vdac.h" |
AnnaBridge | 170:e95d10626187 | 547 | #include "efm32gg11b_idac.h" |
AnnaBridge | 170:e95d10626187 | 548 | #include "efm32gg11b_csen.h" |
AnnaBridge | 170:e95d10626187 | 549 | #include "efm32gg11b_lcd.h" |
AnnaBridge | 170:e95d10626187 | 550 | #include "efm32gg11b_rtc_comp.h" |
AnnaBridge | 170:e95d10626187 | 551 | #include "efm32gg11b_rtc.h" |
AnnaBridge | 170:e95d10626187 | 552 | #include "efm32gg11b_rtcc_cc.h" |
AnnaBridge | 170:e95d10626187 | 553 | #include "efm32gg11b_rtcc_ret.h" |
AnnaBridge | 170:e95d10626187 | 554 | #include "efm32gg11b_rtcc.h" |
AnnaBridge | 170:e95d10626187 | 555 | #include "efm32gg11b_wdog_pch.h" |
AnnaBridge | 170:e95d10626187 | 556 | #include "efm32gg11b_wdog.h" |
AnnaBridge | 170:e95d10626187 | 557 | #include "efm32gg11b_etm.h" |
AnnaBridge | 170:e95d10626187 | 558 | |
AnnaBridge | 170:e95d10626187 | 559 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 560 | * @defgroup EFM32GG11B520F2048IQ64_SMU SMU |
AnnaBridge | 170:e95d10626187 | 561 | * @{ |
AnnaBridge | 170:e95d10626187 | 562 | * @brief EFM32GG11B520F2048IQ64_SMU Register Declaration |
AnnaBridge | 170:e95d10626187 | 563 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 564 | /** SMU Register Declaration */ |
AnnaBridge | 170:e95d10626187 | 565 | typedef struct { |
AnnaBridge | 170:e95d10626187 | 566 | uint32_t RESERVED0[3]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 567 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
AnnaBridge | 170:e95d10626187 | 568 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
AnnaBridge | 170:e95d10626187 | 569 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
AnnaBridge | 170:e95d10626187 | 570 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
AnnaBridge | 170:e95d10626187 | 571 | |
AnnaBridge | 170:e95d10626187 | 572 | uint32_t RESERVED1[9]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 573 | __IOM uint32_t PPUCTRL; /**< PPU Control Register */ |
AnnaBridge | 170:e95d10626187 | 574 | uint32_t RESERVED2[3]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 575 | __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ |
AnnaBridge | 170:e95d10626187 | 576 | __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ |
AnnaBridge | 170:e95d10626187 | 577 | __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ |
AnnaBridge | 170:e95d10626187 | 578 | |
AnnaBridge | 170:e95d10626187 | 579 | uint32_t RESERVED3[13]; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 580 | __IM uint32_t PPUFS; /**< PPU Fault Status */ |
AnnaBridge | 170:e95d10626187 | 581 | } SMU_TypeDef; /** @} */ |
AnnaBridge | 170:e95d10626187 | 582 | |
AnnaBridge | 170:e95d10626187 | 583 | #include "efm32gg11b_trng.h" |
AnnaBridge | 170:e95d10626187 | 584 | #include "efm32gg11b_dma_descriptor.h" |
AnnaBridge | 170:e95d10626187 | 585 | |
AnnaBridge | 170:e95d10626187 | 586 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 587 | * @defgroup EFM32GG11B520F2048IQ64_PERPRIV_REGISTER Peripheral Privilege Register |
AnnaBridge | 170:e95d10626187 | 588 | * @{ |
AnnaBridge | 170:e95d10626187 | 589 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 590 | /** PERPRIV_REGISTER Register Declaration */ |
AnnaBridge | 170:e95d10626187 | 591 | typedef struct { |
AnnaBridge | 170:e95d10626187 | 592 | /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ |
AnnaBridge | 170:e95d10626187 | 593 | /* pointer and referenced memory are declared volatile. */ |
AnnaBridge | 170:e95d10626187 | 594 | __IOM int TIMER0 : 1; |
AnnaBridge | 170:e95d10626187 | 595 | __IOM int TIMER1 : 1; |
AnnaBridge | 170:e95d10626187 | 596 | __IOM int TIMER2 : 1; |
AnnaBridge | 170:e95d10626187 | 597 | __IOM int TIMER3 : 1; |
AnnaBridge | 170:e95d10626187 | 598 | __IOM int TIMER4 : 1; |
AnnaBridge | 170:e95d10626187 | 599 | __IOM int TIMER5 : 1; |
AnnaBridge | 170:e95d10626187 | 600 | __IOM int TIMER6 : 1; |
AnnaBridge | 170:e95d10626187 | 601 | __IOM int WTIMER0 : 1; |
AnnaBridge | 170:e95d10626187 | 602 | __IOM int WTIMER1 : 1; |
AnnaBridge | 170:e95d10626187 | 603 | __IOM int WTIMER2 : 1; |
AnnaBridge | 170:e95d10626187 | 604 | __IOM int WTIMER3 : 1; |
AnnaBridge | 170:e95d10626187 | 605 | __IOM int USART0 : 1; |
AnnaBridge | 170:e95d10626187 | 606 | __IOM int USART1 : 1; |
AnnaBridge | 170:e95d10626187 | 607 | __IOM int USART2 : 1; |
AnnaBridge | 170:e95d10626187 | 608 | __IOM int USART3 : 1; |
AnnaBridge | 170:e95d10626187 | 609 | __IOM int USART4 : 1; |
AnnaBridge | 170:e95d10626187 | 610 | __IOM int USART5 : 1; |
AnnaBridge | 170:e95d10626187 | 611 | __IOM int UART0 : 1; |
AnnaBridge | 170:e95d10626187 | 612 | __IOM int UART1 : 1; |
AnnaBridge | 170:e95d10626187 | 613 | __IOM int CAN0 : 1; |
AnnaBridge | 170:e95d10626187 | 614 | __IOM int CAN1 : 1; |
AnnaBridge | 170:e95d10626187 | 615 | __IOM int RESERVED0 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 616 | __IOM int RESERVED1 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 617 | __IOM int TRNG0 : 1; |
AnnaBridge | 170:e95d10626187 | 618 | __IOM int MSC : 1; |
AnnaBridge | 170:e95d10626187 | 619 | __IOM int EBI : 1; |
AnnaBridge | 170:e95d10626187 | 620 | __IOM int RESERVED2 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 621 | __IOM int LDMA : 1; |
AnnaBridge | 170:e95d10626187 | 622 | __IOM int FPUEH : 1; |
AnnaBridge | 170:e95d10626187 | 623 | __IOM int GPCRC : 1; |
AnnaBridge | 170:e95d10626187 | 624 | __IOM int RESERVED3 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 625 | __IOM int RESERVED4 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 626 | __IOM int SMU : 1; |
AnnaBridge | 170:e95d10626187 | 627 | |
AnnaBridge | 170:e95d10626187 | 628 | __IOM int ACMP0 : 1; |
AnnaBridge | 170:e95d10626187 | 629 | __IOM int ACMP1 : 1; |
AnnaBridge | 170:e95d10626187 | 630 | __IOM int ACMP2 : 1; |
AnnaBridge | 170:e95d10626187 | 631 | __IOM int ACMP3 : 1; |
AnnaBridge | 170:e95d10626187 | 632 | __IOM int I2C0 : 1; |
AnnaBridge | 170:e95d10626187 | 633 | __IOM int I2C1 : 1; |
AnnaBridge | 170:e95d10626187 | 634 | __IOM int I2C2 : 1; |
AnnaBridge | 170:e95d10626187 | 635 | __IOM int ADC0 : 1; |
AnnaBridge | 170:e95d10626187 | 636 | __IOM int ADC1 : 1; |
AnnaBridge | 170:e95d10626187 | 637 | __IOM int CRYOTIMER : 1; |
AnnaBridge | 170:e95d10626187 | 638 | __IOM int VDAC0 : 1; |
AnnaBridge | 170:e95d10626187 | 639 | __IOM int IDAC0 : 1; |
AnnaBridge | 170:e95d10626187 | 640 | __IOM int CSEN : 1; |
AnnaBridge | 170:e95d10626187 | 641 | __IOM int RESERVED5 : 1; /**< Reserved for future use **/ |
AnnaBridge | 170:e95d10626187 | 642 | __IOM int APB_RSYNC_COMB : 1; |
AnnaBridge | 170:e95d10626187 | 643 | __IOM int GPIO : 1; |
AnnaBridge | 170:e95d10626187 | 644 | __IOM int PRS : 1; |
AnnaBridge | 170:e95d10626187 | 645 | __IOM int EMU : 1; |
AnnaBridge | 170:e95d10626187 | 646 | __IOM int RMU : 1; |
AnnaBridge | 170:e95d10626187 | 647 | __IOM int CMU : 1; |
AnnaBridge | 170:e95d10626187 | 648 | |
AnnaBridge | 170:e95d10626187 | 649 | __IOM int PCNT0 : 1; |
AnnaBridge | 170:e95d10626187 | 650 | __IOM int PCNT1 : 1; |
AnnaBridge | 170:e95d10626187 | 651 | __IOM int PCNT2 : 1; |
AnnaBridge | 170:e95d10626187 | 652 | __IOM int LEUART0 : 1; |
AnnaBridge | 170:e95d10626187 | 653 | __IOM int LEUART1 : 1; |
AnnaBridge | 170:e95d10626187 | 654 | __IOM int LETIMER0 : 1; |
AnnaBridge | 170:e95d10626187 | 655 | __IOM int LETIMER1 : 1; |
AnnaBridge | 170:e95d10626187 | 656 | __IOM int WDOG0 : 1; |
AnnaBridge | 170:e95d10626187 | 657 | __IOM int WDOG1 : 1; |
AnnaBridge | 170:e95d10626187 | 658 | __IOM int LESENSE : 1; |
AnnaBridge | 170:e95d10626187 | 659 | __IOM int LCD : 1; |
AnnaBridge | 170:e95d10626187 | 660 | __IOM int RTC : 1; |
AnnaBridge | 170:e95d10626187 | 661 | __IOM int RTCC : 1; |
AnnaBridge | 170:e95d10626187 | 662 | } PERPRIV_REGISTER_TypeDef; /**< @} */ |
AnnaBridge | 170:e95d10626187 | 663 | |
AnnaBridge | 170:e95d10626187 | 664 | #include "efm32gg11b_devinfo.h" |
AnnaBridge | 170:e95d10626187 | 665 | #include "efm32gg11b_romtable.h" |
AnnaBridge | 170:e95d10626187 | 666 | |
AnnaBridge | 170:e95d10626187 | 667 | /** @} End of group EFM32GG11B520F2048IQ64_Peripheral_TypeDefs */ |
AnnaBridge | 170:e95d10626187 | 668 | |
AnnaBridge | 170:e95d10626187 | 669 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 670 | * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Base Peripheral Memory Map |
AnnaBridge | 170:e95d10626187 | 671 | * @{ |
AnnaBridge | 170:e95d10626187 | 672 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 673 | |
AnnaBridge | 170:e95d10626187 | 674 | #define MSC_BASE (0x40000000UL) /**< MSC base address */ |
AnnaBridge | 170:e95d10626187 | 675 | #define EMU_BASE (0x400E3000UL) /**< EMU base address */ |
AnnaBridge | 170:e95d10626187 | 676 | #define RMU_BASE (0x400E5000UL) /**< RMU base address */ |
AnnaBridge | 170:e95d10626187 | 677 | #define CMU_BASE (0x400E4000UL) /**< CMU base address */ |
AnnaBridge | 170:e95d10626187 | 678 | #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ |
AnnaBridge | 170:e95d10626187 | 679 | #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ |
AnnaBridge | 170:e95d10626187 | 680 | #define EBI_BASE (0x4000B000UL) /**< EBI base address */ |
AnnaBridge | 170:e95d10626187 | 681 | #define GPIO_BASE (0x40088000UL) /**< GPIO base address */ |
AnnaBridge | 170:e95d10626187 | 682 | #define PRS_BASE (0x400E6000UL) /**< PRS base address */ |
AnnaBridge | 170:e95d10626187 | 683 | #define LDMA_BASE (0x40002000UL) /**< LDMA base address */ |
AnnaBridge | 170:e95d10626187 | 684 | #define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ |
AnnaBridge | 170:e95d10626187 | 685 | #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ |
AnnaBridge | 170:e95d10626187 | 686 | #define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ |
AnnaBridge | 170:e95d10626187 | 687 | #define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ |
AnnaBridge | 170:e95d10626187 | 688 | #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ |
AnnaBridge | 170:e95d10626187 | 689 | #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ |
AnnaBridge | 170:e95d10626187 | 690 | #define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ |
AnnaBridge | 170:e95d10626187 | 691 | #define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ |
AnnaBridge | 170:e95d10626187 | 692 | #define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ |
AnnaBridge | 170:e95d10626187 | 693 | #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ |
AnnaBridge | 170:e95d10626187 | 694 | #define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ |
AnnaBridge | 170:e95d10626187 | 695 | #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ |
AnnaBridge | 170:e95d10626187 | 696 | #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ |
AnnaBridge | 170:e95d10626187 | 697 | #define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ |
AnnaBridge | 170:e95d10626187 | 698 | #define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ |
AnnaBridge | 170:e95d10626187 | 699 | #define USART0_BASE (0x40010000UL) /**< USART0 base address */ |
AnnaBridge | 170:e95d10626187 | 700 | #define USART1_BASE (0x40010400UL) /**< USART1 base address */ |
AnnaBridge | 170:e95d10626187 | 701 | #define USART2_BASE (0x40010800UL) /**< USART2 base address */ |
AnnaBridge | 170:e95d10626187 | 702 | #define USART3_BASE (0x40010C00UL) /**< USART3 base address */ |
AnnaBridge | 170:e95d10626187 | 703 | #define USART4_BASE (0x40011000UL) /**< USART4 base address */ |
AnnaBridge | 170:e95d10626187 | 704 | #define USART5_BASE (0x40011400UL) /**< USART5 base address */ |
AnnaBridge | 170:e95d10626187 | 705 | #define UART0_BASE (0x40014000UL) /**< UART0 base address */ |
AnnaBridge | 170:e95d10626187 | 706 | #define UART1_BASE (0x40014400UL) /**< UART1 base address */ |
AnnaBridge | 170:e95d10626187 | 707 | #define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ |
AnnaBridge | 170:e95d10626187 | 708 | #define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ |
AnnaBridge | 170:e95d10626187 | 709 | #define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ |
AnnaBridge | 170:e95d10626187 | 710 | #define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ |
AnnaBridge | 170:e95d10626187 | 711 | #define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ |
AnnaBridge | 170:e95d10626187 | 712 | #define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ |
AnnaBridge | 170:e95d10626187 | 713 | #define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ |
AnnaBridge | 170:e95d10626187 | 714 | #define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ |
AnnaBridge | 170:e95d10626187 | 715 | #define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ |
AnnaBridge | 170:e95d10626187 | 716 | #define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ |
AnnaBridge | 170:e95d10626187 | 717 | #define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ |
AnnaBridge | 170:e95d10626187 | 718 | #define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ |
AnnaBridge | 170:e95d10626187 | 719 | #define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ |
AnnaBridge | 170:e95d10626187 | 720 | #define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ |
AnnaBridge | 170:e95d10626187 | 721 | #define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ |
AnnaBridge | 170:e95d10626187 | 722 | #define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ |
AnnaBridge | 170:e95d10626187 | 723 | #define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ |
AnnaBridge | 170:e95d10626187 | 724 | #define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ |
AnnaBridge | 170:e95d10626187 | 725 | #define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ |
AnnaBridge | 170:e95d10626187 | 726 | #define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ |
AnnaBridge | 170:e95d10626187 | 727 | #define LCD_BASE (0x40054000UL) /**< LCD base address */ |
AnnaBridge | 170:e95d10626187 | 728 | #define RTC_BASE (0x40060000UL) /**< RTC base address */ |
AnnaBridge | 170:e95d10626187 | 729 | #define RTCC_BASE (0x40062000UL) /**< RTCC base address */ |
AnnaBridge | 170:e95d10626187 | 730 | #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ |
AnnaBridge | 170:e95d10626187 | 731 | #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ |
AnnaBridge | 170:e95d10626187 | 732 | #define ETM_BASE (0xE0041000UL) /**< ETM base address */ |
AnnaBridge | 170:e95d10626187 | 733 | #define SMU_BASE (0x40020000UL) /**< SMU base address */ |
AnnaBridge | 170:e95d10626187 | 734 | #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ |
AnnaBridge | 170:e95d10626187 | 735 | #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ |
AnnaBridge | 170:e95d10626187 | 736 | #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ |
AnnaBridge | 170:e95d10626187 | 737 | #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ |
AnnaBridge | 170:e95d10626187 | 738 | #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ |
AnnaBridge | 170:e95d10626187 | 739 | |
AnnaBridge | 170:e95d10626187 | 740 | /** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Base */ |
AnnaBridge | 170:e95d10626187 | 741 | |
AnnaBridge | 170:e95d10626187 | 742 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 743 | * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Declaration Peripheral Declarations |
AnnaBridge | 170:e95d10626187 | 744 | * @{ |
AnnaBridge | 170:e95d10626187 | 745 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 746 | |
AnnaBridge | 170:e95d10626187 | 747 | #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ |
AnnaBridge | 170:e95d10626187 | 748 | #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ |
AnnaBridge | 170:e95d10626187 | 749 | #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ |
AnnaBridge | 170:e95d10626187 | 750 | #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ |
AnnaBridge | 170:e95d10626187 | 751 | #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 752 | #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ |
AnnaBridge | 170:e95d10626187 | 753 | #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ |
AnnaBridge | 170:e95d10626187 | 754 | #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ |
AnnaBridge | 170:e95d10626187 | 755 | #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ |
AnnaBridge | 170:e95d10626187 | 756 | #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ |
AnnaBridge | 170:e95d10626187 | 757 | #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ |
AnnaBridge | 170:e95d10626187 | 758 | #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ |
AnnaBridge | 170:e95d10626187 | 759 | #define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 760 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 761 | #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 762 | #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 763 | #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 764 | #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ |
AnnaBridge | 170:e95d10626187 | 765 | #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ |
AnnaBridge | 170:e95d10626187 | 766 | #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ |
AnnaBridge | 170:e95d10626187 | 767 | #define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ |
AnnaBridge | 170:e95d10626187 | 768 | #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 769 | #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 770 | #define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 771 | #define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ |
AnnaBridge | 170:e95d10626187 | 772 | #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 773 | #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 774 | #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 775 | #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ |
AnnaBridge | 170:e95d10626187 | 776 | #define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ |
AnnaBridge | 170:e95d10626187 | 777 | #define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ |
AnnaBridge | 170:e95d10626187 | 778 | #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 779 | #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 780 | #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 781 | #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 782 | #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 783 | #define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 784 | #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ |
AnnaBridge | 170:e95d10626187 | 785 | #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 786 | #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 787 | #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 788 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 789 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 790 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 791 | #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 792 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 793 | #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 794 | #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 795 | #define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ |
AnnaBridge | 170:e95d10626187 | 796 | #define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ |
AnnaBridge | 170:e95d10626187 | 797 | #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 798 | #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 799 | #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ |
AnnaBridge | 170:e95d10626187 | 800 | #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ |
AnnaBridge | 170:e95d10626187 | 801 | #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ |
AnnaBridge | 170:e95d10626187 | 802 | #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ |
AnnaBridge | 170:e95d10626187 | 803 | #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 804 | #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ |
AnnaBridge | 170:e95d10626187 | 805 | #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ |
AnnaBridge | 170:e95d10626187 | 806 | #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ |
AnnaBridge | 170:e95d10626187 | 807 | #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ |
AnnaBridge | 170:e95d10626187 | 808 | #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ |
AnnaBridge | 170:e95d10626187 | 809 | #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ |
AnnaBridge | 170:e95d10626187 | 810 | |
AnnaBridge | 170:e95d10626187 | 811 | /** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Declaration */ |
AnnaBridge | 170:e95d10626187 | 812 | |
AnnaBridge | 170:e95d10626187 | 813 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 814 | * @defgroup EFM32GG11B520F2048IQ64_Peripheral_Offsets Peripheral Offsets |
AnnaBridge | 170:e95d10626187 | 815 | * @{ |
AnnaBridge | 170:e95d10626187 | 816 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 817 | |
AnnaBridge | 170:e95d10626187 | 818 | #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ |
AnnaBridge | 170:e95d10626187 | 819 | #define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ |
AnnaBridge | 170:e95d10626187 | 820 | #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ |
AnnaBridge | 170:e95d10626187 | 821 | #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ |
AnnaBridge | 170:e95d10626187 | 822 | #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ |
AnnaBridge | 170:e95d10626187 | 823 | #define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ |
AnnaBridge | 170:e95d10626187 | 824 | #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ |
AnnaBridge | 170:e95d10626187 | 825 | #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ |
AnnaBridge | 170:e95d10626187 | 826 | #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ |
AnnaBridge | 170:e95d10626187 | 827 | #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ |
AnnaBridge | 170:e95d10626187 | 828 | #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ |
AnnaBridge | 170:e95d10626187 | 829 | #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ |
AnnaBridge | 170:e95d10626187 | 830 | #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ |
AnnaBridge | 170:e95d10626187 | 831 | #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ |
AnnaBridge | 170:e95d10626187 | 832 | #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ |
AnnaBridge | 170:e95d10626187 | 833 | #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ |
AnnaBridge | 170:e95d10626187 | 834 | |
AnnaBridge | 170:e95d10626187 | 835 | /** @} End of group EFM32GG11B520F2048IQ64_Peripheral_Offsets */ |
AnnaBridge | 170:e95d10626187 | 836 | |
AnnaBridge | 170:e95d10626187 | 837 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 838 | * @defgroup EFM32GG11B520F2048IQ64_BitFields Bit Fields |
AnnaBridge | 170:e95d10626187 | 839 | * @{ |
AnnaBridge | 170:e95d10626187 | 840 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 841 | |
AnnaBridge | 170:e95d10626187 | 842 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 843 | * @addtogroup EFM32GG11B520F2048IQ64_PRS |
AnnaBridge | 170:e95d10626187 | 844 | * @{ |
AnnaBridge | 170:e95d10626187 | 845 | * @addtogroup EFM32GG11B520F2048IQ64_PRS_Signals PRS Signals |
AnnaBridge | 170:e95d10626187 | 846 | * @{ |
AnnaBridge | 170:e95d10626187 | 847 | * @brief PRS Signal names |
AnnaBridge | 170:e95d10626187 | 848 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 849 | #define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ |
AnnaBridge | 170:e95d10626187 | 850 | #define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ |
AnnaBridge | 170:e95d10626187 | 851 | #define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ |
AnnaBridge | 170:e95d10626187 | 852 | #define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ |
AnnaBridge | 170:e95d10626187 | 853 | #define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ |
AnnaBridge | 170:e95d10626187 | 854 | #define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ |
AnnaBridge | 170:e95d10626187 | 855 | #define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ |
AnnaBridge | 170:e95d10626187 | 856 | #define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ |
AnnaBridge | 170:e95d10626187 | 857 | #define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ |
AnnaBridge | 170:e95d10626187 | 858 | #define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ |
AnnaBridge | 170:e95d10626187 | 859 | #define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ |
AnnaBridge | 170:e95d10626187 | 860 | #define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ |
AnnaBridge | 170:e95d10626187 | 861 | #define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ |
AnnaBridge | 170:e95d10626187 | 862 | #define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ |
AnnaBridge | 170:e95d10626187 | 863 | #define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ |
AnnaBridge | 170:e95d10626187 | 864 | #define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ |
AnnaBridge | 170:e95d10626187 | 865 | #define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ |
AnnaBridge | 170:e95d10626187 | 866 | #define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ |
AnnaBridge | 170:e95d10626187 | 867 | #define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ |
AnnaBridge | 170:e95d10626187 | 868 | #define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ |
AnnaBridge | 170:e95d10626187 | 869 | #define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ |
AnnaBridge | 170:e95d10626187 | 870 | #define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ |
AnnaBridge | 170:e95d10626187 | 871 | #define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ |
AnnaBridge | 170:e95d10626187 | 872 | #define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ |
AnnaBridge | 170:e95d10626187 | 873 | #define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 170:e95d10626187 | 874 | #define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 170:e95d10626187 | 875 | #define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ |
AnnaBridge | 170:e95d10626187 | 876 | #define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ |
AnnaBridge | 170:e95d10626187 | 877 | #define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ |
AnnaBridge | 170:e95d10626187 | 878 | #define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ |
AnnaBridge | 170:e95d10626187 | 879 | #define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ |
AnnaBridge | 170:e95d10626187 | 880 | #define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ |
AnnaBridge | 170:e95d10626187 | 881 | #define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ |
AnnaBridge | 170:e95d10626187 | 882 | #define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ |
AnnaBridge | 170:e95d10626187 | 883 | #define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ |
AnnaBridge | 170:e95d10626187 | 884 | #define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ |
AnnaBridge | 170:e95d10626187 | 885 | #define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ |
AnnaBridge | 170:e95d10626187 | 886 | #define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ |
AnnaBridge | 170:e95d10626187 | 887 | #define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ |
AnnaBridge | 170:e95d10626187 | 888 | #define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ |
AnnaBridge | 170:e95d10626187 | 889 | #define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ |
AnnaBridge | 170:e95d10626187 | 890 | #define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ |
AnnaBridge | 170:e95d10626187 | 891 | #define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ |
AnnaBridge | 170:e95d10626187 | 892 | #define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ |
AnnaBridge | 170:e95d10626187 | 893 | #define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ |
AnnaBridge | 170:e95d10626187 | 894 | #define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ |
AnnaBridge | 170:e95d10626187 | 895 | #define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ |
AnnaBridge | 170:e95d10626187 | 896 | #define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ |
AnnaBridge | 170:e95d10626187 | 897 | #define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ |
AnnaBridge | 170:e95d10626187 | 898 | #define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ |
AnnaBridge | 170:e95d10626187 | 899 | #define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ |
AnnaBridge | 170:e95d10626187 | 900 | #define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ |
AnnaBridge | 170:e95d10626187 | 901 | #define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ |
AnnaBridge | 170:e95d10626187 | 902 | #define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ |
AnnaBridge | 170:e95d10626187 | 903 | #define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ |
AnnaBridge | 170:e95d10626187 | 904 | #define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ |
AnnaBridge | 170:e95d10626187 | 905 | #define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ |
AnnaBridge | 170:e95d10626187 | 906 | #define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ |
AnnaBridge | 170:e95d10626187 | 907 | #define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ |
AnnaBridge | 170:e95d10626187 | 908 | #define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ |
AnnaBridge | 170:e95d10626187 | 909 | #define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ |
AnnaBridge | 170:e95d10626187 | 910 | #define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ |
AnnaBridge | 170:e95d10626187 | 911 | #define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ |
AnnaBridge | 170:e95d10626187 | 912 | #define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ |
AnnaBridge | 170:e95d10626187 | 913 | #define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ |
AnnaBridge | 170:e95d10626187 | 914 | #define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ |
AnnaBridge | 170:e95d10626187 | 915 | #define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ |
AnnaBridge | 170:e95d10626187 | 916 | #define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ |
AnnaBridge | 170:e95d10626187 | 917 | #define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ |
AnnaBridge | 170:e95d10626187 | 918 | #define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ |
AnnaBridge | 170:e95d10626187 | 919 | #define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ |
AnnaBridge | 170:e95d10626187 | 920 | #define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ |
AnnaBridge | 170:e95d10626187 | 921 | #define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ |
AnnaBridge | 170:e95d10626187 | 922 | #define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ |
AnnaBridge | 170:e95d10626187 | 923 | #define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ |
AnnaBridge | 170:e95d10626187 | 924 | #define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ |
AnnaBridge | 170:e95d10626187 | 925 | #define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ |
AnnaBridge | 170:e95d10626187 | 926 | #define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ |
AnnaBridge | 170:e95d10626187 | 927 | #define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ |
AnnaBridge | 170:e95d10626187 | 928 | #define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ |
AnnaBridge | 170:e95d10626187 | 929 | #define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ |
AnnaBridge | 170:e95d10626187 | 930 | #define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ |
AnnaBridge | 170:e95d10626187 | 931 | #define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ |
AnnaBridge | 170:e95d10626187 | 932 | #define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ |
AnnaBridge | 170:e95d10626187 | 933 | #define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ |
AnnaBridge | 170:e95d10626187 | 934 | #define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ |
AnnaBridge | 170:e95d10626187 | 935 | #define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ |
AnnaBridge | 170:e95d10626187 | 936 | #define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ |
AnnaBridge | 170:e95d10626187 | 937 | #define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ |
AnnaBridge | 170:e95d10626187 | 938 | #define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ |
AnnaBridge | 170:e95d10626187 | 939 | #define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ |
AnnaBridge | 170:e95d10626187 | 940 | #define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ |
AnnaBridge | 170:e95d10626187 | 941 | #define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ |
AnnaBridge | 170:e95d10626187 | 942 | #define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ |
AnnaBridge | 170:e95d10626187 | 943 | #define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ |
AnnaBridge | 170:e95d10626187 | 944 | #define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ |
AnnaBridge | 170:e95d10626187 | 945 | #define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ |
AnnaBridge | 170:e95d10626187 | 946 | #define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ |
AnnaBridge | 170:e95d10626187 | 947 | #define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 170:e95d10626187 | 948 | #define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ |
AnnaBridge | 170:e95d10626187 | 949 | #define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ |
AnnaBridge | 170:e95d10626187 | 950 | #define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ |
AnnaBridge | 170:e95d10626187 | 951 | #define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 952 | #define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 953 | #define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 954 | #define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 955 | #define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 956 | #define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 957 | #define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 958 | #define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 959 | #define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 960 | #define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 961 | #define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 962 | #define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ |
AnnaBridge | 170:e95d10626187 | 963 | #define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 964 | #define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 965 | #define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 966 | #define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 967 | #define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 968 | #define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 969 | #define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 970 | #define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 971 | #define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 972 | #define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 973 | #define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 974 | #define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 975 | #define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 976 | #define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 977 | #define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 978 | #define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 979 | #define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 980 | #define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 981 | #define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 982 | #define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 983 | #define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 984 | #define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 985 | #define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 986 | #define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 987 | #define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 988 | #define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 989 | #define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 990 | #define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 991 | #define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 992 | #define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 993 | #define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 994 | #define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 995 | #define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 996 | #define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 997 | #define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 998 | #define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 999 | #define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1000 | #define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1001 | #define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1002 | #define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1003 | #define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1004 | #define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1005 | #define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1006 | #define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1007 | #define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1008 | #define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1009 | #define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1010 | #define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1011 | #define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1012 | #define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1013 | #define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1014 | #define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1015 | #define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1016 | #define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1017 | #define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1018 | #define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1019 | #define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1020 | #define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1021 | #define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1022 | #define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1023 | #define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1024 | #define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1025 | #define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1026 | #define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1027 | #define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1028 | #define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1029 | #define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1030 | #define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1031 | #define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1032 | #define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1033 | #define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1034 | #define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1035 | #define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1036 | #define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1037 | #define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1038 | #define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1039 | #define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1040 | #define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1041 | #define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1042 | #define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1043 | #define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1044 | #define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1045 | #define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1046 | #define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1047 | #define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1048 | #define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1049 | #define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1050 | #define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1051 | #define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1052 | #define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ |
AnnaBridge | 170:e95d10626187 | 1053 | |
AnnaBridge | 170:e95d10626187 | 1054 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 1055 | /** @} End of group EFM32GG11B520F2048IQ64_PRS */ |
AnnaBridge | 170:e95d10626187 | 1056 | |
AnnaBridge | 170:e95d10626187 | 1057 | #include "efm32gg11b_dmareq.h" |
AnnaBridge | 170:e95d10626187 | 1058 | |
AnnaBridge | 170:e95d10626187 | 1059 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 1060 | * @addtogroup EFM32GG11B520F2048IQ64_WTIMER |
AnnaBridge | 170:e95d10626187 | 1061 | * @{ |
AnnaBridge | 170:e95d10626187 | 1062 | * @defgroup EFM32GG11B520F2048IQ64_WTIMER_BitFields WTIMER Bit Fields |
AnnaBridge | 170:e95d10626187 | 1063 | * @{ |
AnnaBridge | 170:e95d10626187 | 1064 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 1065 | |
AnnaBridge | 170:e95d10626187 | 1066 | /* Bit fields for WTIMER CTRL */ |
AnnaBridge | 170:e95d10626187 | 1067 | #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1068 | #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1069 | #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
AnnaBridge | 170:e95d10626187 | 1070 | #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
AnnaBridge | 170:e95d10626187 | 1071 | #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1072 | #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1073 | #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1074 | #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1075 | #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1076 | #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1077 | #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1078 | #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1079 | #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1080 | #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1081 | #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ |
AnnaBridge | 170:e95d10626187 | 1082 | #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ |
AnnaBridge | 170:e95d10626187 | 1083 | #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ |
AnnaBridge | 170:e95d10626187 | 1084 | #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1085 | #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1086 | #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ |
AnnaBridge | 170:e95d10626187 | 1087 | #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ |
AnnaBridge | 170:e95d10626187 | 1088 | #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ |
AnnaBridge | 170:e95d10626187 | 1089 | #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1090 | #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1091 | #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ |
AnnaBridge | 170:e95d10626187 | 1092 | #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ |
AnnaBridge | 170:e95d10626187 | 1093 | #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ |
AnnaBridge | 170:e95d10626187 | 1094 | #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1095 | #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1096 | #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1097 | #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1098 | #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1099 | #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1100 | #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ |
AnnaBridge | 170:e95d10626187 | 1101 | #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ |
AnnaBridge | 170:e95d10626187 | 1102 | #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ |
AnnaBridge | 170:e95d10626187 | 1103 | #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1104 | #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1105 | #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ |
AnnaBridge | 170:e95d10626187 | 1106 | #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ |
AnnaBridge | 170:e95d10626187 | 1107 | #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ |
AnnaBridge | 170:e95d10626187 | 1108 | #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1109 | #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1110 | #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ |
AnnaBridge | 170:e95d10626187 | 1111 | #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ |
AnnaBridge | 170:e95d10626187 | 1112 | #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1113 | #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1114 | #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1115 | #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1116 | #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1117 | #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1118 | #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1119 | #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1120 | #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1121 | #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1122 | #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ |
AnnaBridge | 170:e95d10626187 | 1123 | #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ |
AnnaBridge | 170:e95d10626187 | 1124 | #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1125 | #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1126 | #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1127 | #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1128 | #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1129 | #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1130 | #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1131 | #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1132 | #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1133 | #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1134 | #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ |
AnnaBridge | 170:e95d10626187 | 1135 | #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ |
AnnaBridge | 170:e95d10626187 | 1136 | #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ |
AnnaBridge | 170:e95d10626187 | 1137 | #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1138 | #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1139 | #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer from Start/Stop/Reload other Synchronized Timers */ |
AnnaBridge | 170:e95d10626187 | 1140 | #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ |
AnnaBridge | 170:e95d10626187 | 1141 | #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ |
AnnaBridge | 170:e95d10626187 | 1142 | #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1143 | #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1144 | #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 1145 | #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 1146 | #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1147 | #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1148 | #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1149 | #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1150 | #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1151 | #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1152 | #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1153 | #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1154 | #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ |
AnnaBridge | 170:e95d10626187 | 1155 | #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ |
AnnaBridge | 170:e95d10626187 | 1156 | #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1157 | #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1158 | #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1159 | #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1160 | #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1161 | #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1162 | #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1163 | #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1164 | #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1165 | #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1166 | #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1167 | #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1168 | #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1169 | #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1170 | #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1171 | #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1172 | #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1173 | #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1174 | #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1175 | #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1176 | #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1177 | #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1178 | #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1179 | #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1180 | #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ |
AnnaBridge | 170:e95d10626187 | 1181 | #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ |
AnnaBridge | 170:e95d10626187 | 1182 | #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ |
AnnaBridge | 170:e95d10626187 | 1183 | #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1184 | #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1185 | #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ |
AnnaBridge | 170:e95d10626187 | 1186 | #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ |
AnnaBridge | 170:e95d10626187 | 1187 | #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ |
AnnaBridge | 170:e95d10626187 | 1188 | #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1189 | #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1190 | |
AnnaBridge | 170:e95d10626187 | 1191 | /* Bit fields for WTIMER CMD */ |
AnnaBridge | 170:e95d10626187 | 1192 | #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1193 | #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1194 | #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ |
AnnaBridge | 170:e95d10626187 | 1195 | #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ |
AnnaBridge | 170:e95d10626187 | 1196 | #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ |
AnnaBridge | 170:e95d10626187 | 1197 | #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1198 | #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1199 | #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ |
AnnaBridge | 170:e95d10626187 | 1200 | #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ |
AnnaBridge | 170:e95d10626187 | 1201 | #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ |
AnnaBridge | 170:e95d10626187 | 1202 | #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1203 | #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ |
AnnaBridge | 170:e95d10626187 | 1204 | |
AnnaBridge | 170:e95d10626187 | 1205 | /* Bit fields for WTIMER STATUS */ |
AnnaBridge | 170:e95d10626187 | 1206 | #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1207 | #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1208 | #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ |
AnnaBridge | 170:e95d10626187 | 1209 | #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ |
AnnaBridge | 170:e95d10626187 | 1210 | #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ |
AnnaBridge | 170:e95d10626187 | 1211 | #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1212 | #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1213 | #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ |
AnnaBridge | 170:e95d10626187 | 1214 | #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ |
AnnaBridge | 170:e95d10626187 | 1215 | #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ |
AnnaBridge | 170:e95d10626187 | 1216 | #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1217 | #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1218 | #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1219 | #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1220 | #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1221 | #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1222 | #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ |
AnnaBridge | 170:e95d10626187 | 1223 | #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ |
AnnaBridge | 170:e95d10626187 | 1224 | #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ |
AnnaBridge | 170:e95d10626187 | 1225 | #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1226 | #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1227 | #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ |
AnnaBridge | 170:e95d10626187 | 1228 | #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ |
AnnaBridge | 170:e95d10626187 | 1229 | #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ |
AnnaBridge | 170:e95d10626187 | 1230 | #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1231 | #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1232 | #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ |
AnnaBridge | 170:e95d10626187 | 1233 | #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ |
AnnaBridge | 170:e95d10626187 | 1234 | #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ |
AnnaBridge | 170:e95d10626187 | 1235 | #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1236 | #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1237 | #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ |
AnnaBridge | 170:e95d10626187 | 1238 | #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ |
AnnaBridge | 170:e95d10626187 | 1239 | #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ |
AnnaBridge | 170:e95d10626187 | 1240 | #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1241 | #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1242 | #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ |
AnnaBridge | 170:e95d10626187 | 1243 | #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ |
AnnaBridge | 170:e95d10626187 | 1244 | #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ |
AnnaBridge | 170:e95d10626187 | 1245 | #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1246 | #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1247 | #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ |
AnnaBridge | 170:e95d10626187 | 1248 | #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ |
AnnaBridge | 170:e95d10626187 | 1249 | #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ |
AnnaBridge | 170:e95d10626187 | 1250 | #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1251 | #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1252 | #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ |
AnnaBridge | 170:e95d10626187 | 1253 | #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ |
AnnaBridge | 170:e95d10626187 | 1254 | #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ |
AnnaBridge | 170:e95d10626187 | 1255 | #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1256 | #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1257 | #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ |
AnnaBridge | 170:e95d10626187 | 1258 | #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ |
AnnaBridge | 170:e95d10626187 | 1259 | #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ |
AnnaBridge | 170:e95d10626187 | 1260 | #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1261 | #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1262 | #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ |
AnnaBridge | 170:e95d10626187 | 1263 | #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ |
AnnaBridge | 170:e95d10626187 | 1264 | #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ |
AnnaBridge | 170:e95d10626187 | 1265 | #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1266 | #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1267 | #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ |
AnnaBridge | 170:e95d10626187 | 1268 | #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ |
AnnaBridge | 170:e95d10626187 | 1269 | #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ |
AnnaBridge | 170:e95d10626187 | 1270 | #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1271 | #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1272 | #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1273 | #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1274 | #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1275 | #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1276 | #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ |
AnnaBridge | 170:e95d10626187 | 1277 | #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ |
AnnaBridge | 170:e95d10626187 | 1278 | #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ |
AnnaBridge | 170:e95d10626187 | 1279 | #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1280 | #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1281 | #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1282 | #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1283 | #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1284 | #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1285 | #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ |
AnnaBridge | 170:e95d10626187 | 1286 | #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ |
AnnaBridge | 170:e95d10626187 | 1287 | #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ |
AnnaBridge | 170:e95d10626187 | 1288 | #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1289 | #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1290 | #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1291 | #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1292 | #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1293 | #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1294 | #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ |
AnnaBridge | 170:e95d10626187 | 1295 | #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ |
AnnaBridge | 170:e95d10626187 | 1296 | #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ |
AnnaBridge | 170:e95d10626187 | 1297 | #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1298 | #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1299 | #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1300 | #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1301 | #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1302 | #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
AnnaBridge | 170:e95d10626187 | 1303 | |
AnnaBridge | 170:e95d10626187 | 1304 | /* Bit fields for WTIMER IF */ |
AnnaBridge | 170:e95d10626187 | 1305 | #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1306 | #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1307 | #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1308 | #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1309 | #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1310 | #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1311 | #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1312 | #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1313 | #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1314 | #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1315 | #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1316 | #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1317 | #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1318 | #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1319 | #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1320 | #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1321 | #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1322 | #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1323 | #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1324 | #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1325 | #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1326 | #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1327 | #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1328 | #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1329 | #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1330 | #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1331 | #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1332 | #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1333 | #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1334 | #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1335 | #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1336 | #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1337 | #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1338 | #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1339 | #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1340 | #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1341 | #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1342 | #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1343 | #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1344 | #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1345 | #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1346 | #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1347 | #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1348 | #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1349 | #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1350 | #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1351 | #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1352 | #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1353 | #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1354 | #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1355 | #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1356 | #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1357 | #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1358 | #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1359 | #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1360 | #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1361 | #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ |
AnnaBridge | 170:e95d10626187 | 1362 | |
AnnaBridge | 170:e95d10626187 | 1363 | /* Bit fields for WTIMER IFS */ |
AnnaBridge | 170:e95d10626187 | 1364 | #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1365 | #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1366 | #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1367 | #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1368 | #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1369 | #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1370 | #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1371 | #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1372 | #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1373 | #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1374 | #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1375 | #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1376 | #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1377 | #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1378 | #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1379 | #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1380 | #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1381 | #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1382 | #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1383 | #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1384 | #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1385 | #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1386 | #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1387 | #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1388 | #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1389 | #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1390 | #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1391 | #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1392 | #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1393 | #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1394 | #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1395 | #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1396 | #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1397 | #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1398 | #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1399 | #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1400 | #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1401 | #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1402 | #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1403 | #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1404 | #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1405 | #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1406 | #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1407 | #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1408 | #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1409 | #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1410 | #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1411 | #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1412 | #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1413 | #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1414 | #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1415 | #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1416 | #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1417 | #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1418 | #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1419 | #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1420 | #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
AnnaBridge | 170:e95d10626187 | 1421 | |
AnnaBridge | 170:e95d10626187 | 1422 | /* Bit fields for WTIMER IFC */ |
AnnaBridge | 170:e95d10626187 | 1423 | #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1424 | #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1425 | #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1426 | #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1427 | #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1428 | #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1429 | #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1430 | #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1431 | #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1432 | #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1433 | #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1434 | #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1435 | #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1436 | #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1437 | #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1438 | #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1439 | #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1440 | #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1441 | #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1442 | #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1443 | #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1444 | #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1445 | #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1446 | #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1447 | #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1448 | #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1449 | #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1450 | #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1451 | #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1452 | #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1453 | #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1454 | #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1455 | #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1456 | #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1457 | #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1458 | #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1459 | #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1460 | #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1461 | #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1462 | #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1463 | #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1464 | #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1465 | #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1466 | #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1467 | #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1468 | #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1469 | #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1470 | #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1471 | #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1472 | #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1473 | #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1474 | #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1475 | #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 1476 | #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1477 | #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1478 | #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1479 | #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
AnnaBridge | 170:e95d10626187 | 1480 | |
AnnaBridge | 170:e95d10626187 | 1481 | /* Bit fields for WTIMER IEN */ |
AnnaBridge | 170:e95d10626187 | 1482 | #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1483 | #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1484 | #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1485 | #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1486 | #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
AnnaBridge | 170:e95d10626187 | 1487 | #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1488 | #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1489 | #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1490 | #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1491 | #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
AnnaBridge | 170:e95d10626187 | 1492 | #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1493 | #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1494 | #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1495 | #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1496 | #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
AnnaBridge | 170:e95d10626187 | 1497 | #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1498 | #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1499 | #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1500 | #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1501 | #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
AnnaBridge | 170:e95d10626187 | 1502 | #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1503 | #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1504 | #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1505 | #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1506 | #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
AnnaBridge | 170:e95d10626187 | 1507 | #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1508 | #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1509 | #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1510 | #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1511 | #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
AnnaBridge | 170:e95d10626187 | 1512 | #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1513 | #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1514 | #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1515 | #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1516 | #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
AnnaBridge | 170:e95d10626187 | 1517 | #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1518 | #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1519 | #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1520 | #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1521 | #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
AnnaBridge | 170:e95d10626187 | 1522 | #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1523 | #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1524 | #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1525 | #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1526 | #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
AnnaBridge | 170:e95d10626187 | 1527 | #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1528 | #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1529 | #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1530 | #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1531 | #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
AnnaBridge | 170:e95d10626187 | 1532 | #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1533 | #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1534 | #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 1535 | #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1536 | #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
AnnaBridge | 170:e95d10626187 | 1537 | #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1538 | #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
AnnaBridge | 170:e95d10626187 | 1539 | |
AnnaBridge | 170:e95d10626187 | 1540 | /* Bit fields for WTIMER TOP */ |
AnnaBridge | 170:e95d10626187 | 1541 | #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1542 | #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1543 | #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1544 | #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1545 | #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1546 | #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ |
AnnaBridge | 170:e95d10626187 | 1547 | |
AnnaBridge | 170:e95d10626187 | 1548 | /* Bit fields for WTIMER TOPB */ |
AnnaBridge | 170:e95d10626187 | 1549 | #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1550 | #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1551 | #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1552 | #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1553 | #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1554 | #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ |
AnnaBridge | 170:e95d10626187 | 1555 | |
AnnaBridge | 170:e95d10626187 | 1556 | /* Bit fields for WTIMER CNT */ |
AnnaBridge | 170:e95d10626187 | 1557 | #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1558 | #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1559 | #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1560 | #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1561 | #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1562 | #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ |
AnnaBridge | 170:e95d10626187 | 1563 | |
AnnaBridge | 170:e95d10626187 | 1564 | /* Bit fields for WTIMER LOCK */ |
AnnaBridge | 170:e95d10626187 | 1565 | #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1566 | #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1567 | #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 1568 | #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 1569 | #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1570 | #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1571 | #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1572 | #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1573 | #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1574 | #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1575 | #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1576 | #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1577 | #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1578 | #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ |
AnnaBridge | 170:e95d10626187 | 1579 | |
AnnaBridge | 170:e95d10626187 | 1580 | /* Bit fields for WTIMER ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1581 | #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1582 | #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1583 | #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1584 | #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ |
AnnaBridge | 170:e95d10626187 | 1585 | #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ |
AnnaBridge | 170:e95d10626187 | 1586 | #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1587 | #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1588 | #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1589 | #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ |
AnnaBridge | 170:e95d10626187 | 1590 | #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ |
AnnaBridge | 170:e95d10626187 | 1591 | #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1592 | #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1593 | #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1594 | #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ |
AnnaBridge | 170:e95d10626187 | 1595 | #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ |
AnnaBridge | 170:e95d10626187 | 1596 | #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1597 | #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1598 | #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1599 | #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ |
AnnaBridge | 170:e95d10626187 | 1600 | #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ |
AnnaBridge | 170:e95d10626187 | 1601 | #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1602 | #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1603 | #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1604 | #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ |
AnnaBridge | 170:e95d10626187 | 1605 | #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ |
AnnaBridge | 170:e95d10626187 | 1606 | #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1607 | #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1608 | #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1609 | #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ |
AnnaBridge | 170:e95d10626187 | 1610 | #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ |
AnnaBridge | 170:e95d10626187 | 1611 | #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1612 | #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1613 | #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 1614 | #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ |
AnnaBridge | 170:e95d10626187 | 1615 | #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ |
AnnaBridge | 170:e95d10626187 | 1616 | #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1617 | #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 1618 | |
AnnaBridge | 170:e95d10626187 | 1619 | /* Bit fields for WTIMER ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1620 | #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1621 | #define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1622 | #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ |
AnnaBridge | 170:e95d10626187 | 1623 | #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ |
AnnaBridge | 170:e95d10626187 | 1624 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1625 | #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1626 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1627 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1628 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1629 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1630 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1631 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1632 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1633 | #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1634 | #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1635 | #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1636 | #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1637 | #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1638 | #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1639 | #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1640 | #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1641 | #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1642 | #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ |
AnnaBridge | 170:e95d10626187 | 1643 | #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ |
AnnaBridge | 170:e95d10626187 | 1644 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1645 | #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1646 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1647 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1648 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1649 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1650 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1651 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1652 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1653 | #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1654 | #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1655 | #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1656 | #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1657 | #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1658 | #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1659 | #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1660 | #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1661 | #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1662 | #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ |
AnnaBridge | 170:e95d10626187 | 1663 | #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ |
AnnaBridge | 170:e95d10626187 | 1664 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1665 | #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1666 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1667 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1668 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1669 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1670 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1671 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1672 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1673 | #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1674 | #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1675 | #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1676 | #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1677 | #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1678 | #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1679 | #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1680 | #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1681 | #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1682 | #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ |
AnnaBridge | 170:e95d10626187 | 1683 | #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ |
AnnaBridge | 170:e95d10626187 | 1684 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1685 | #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1686 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1687 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1688 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1689 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1690 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1691 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1692 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1693 | #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1694 | #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1695 | #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1696 | #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1697 | #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1698 | #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1699 | #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1700 | #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1701 | #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 1702 | |
AnnaBridge | 170:e95d10626187 | 1703 | /* Bit fields for WTIMER ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1704 | #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1705 | #define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1706 | #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ |
AnnaBridge | 170:e95d10626187 | 1707 | #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ |
AnnaBridge | 170:e95d10626187 | 1708 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1709 | #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1710 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1711 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1712 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1713 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1714 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1715 | #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1716 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1717 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1718 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1719 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1720 | #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ |
AnnaBridge | 170:e95d10626187 | 1721 | #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ |
AnnaBridge | 170:e95d10626187 | 1722 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1723 | #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1724 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1725 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1726 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1727 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1728 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1729 | #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1730 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1731 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1732 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1733 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1734 | #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ |
AnnaBridge | 170:e95d10626187 | 1735 | #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ |
AnnaBridge | 170:e95d10626187 | 1736 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1737 | #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1738 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1739 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1740 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1741 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1742 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1743 | #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1744 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1745 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1746 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1747 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 1748 | |
AnnaBridge | 170:e95d10626187 | 1749 | /* Bit fields for WTIMER CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1750 | #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1751 | #define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1752 | #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
AnnaBridge | 170:e95d10626187 | 1753 | #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
AnnaBridge | 170:e95d10626187 | 1754 | #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1755 | #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1756 | #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1757 | #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1758 | #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1759 | #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1760 | #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1761 | #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1762 | #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1763 | #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1764 | #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ |
AnnaBridge | 170:e95d10626187 | 1765 | #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ |
AnnaBridge | 170:e95d10626187 | 1766 | #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ |
AnnaBridge | 170:e95d10626187 | 1767 | #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1768 | #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1769 | #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ |
AnnaBridge | 170:e95d10626187 | 1770 | #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ |
AnnaBridge | 170:e95d10626187 | 1771 | #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ |
AnnaBridge | 170:e95d10626187 | 1772 | #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1773 | #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1774 | #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ |
AnnaBridge | 170:e95d10626187 | 1775 | #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ |
AnnaBridge | 170:e95d10626187 | 1776 | #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1777 | #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1778 | #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1779 | #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1780 | #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1781 | #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1782 | #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1783 | #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1784 | #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1785 | #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1786 | #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ |
AnnaBridge | 170:e95d10626187 | 1787 | #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ |
AnnaBridge | 170:e95d10626187 | 1788 | #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1789 | #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1790 | #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1791 | #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1792 | #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1793 | #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1794 | #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1795 | #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1796 | #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1797 | #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1798 | #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ |
AnnaBridge | 170:e95d10626187 | 1799 | #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ |
AnnaBridge | 170:e95d10626187 | 1800 | #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1801 | #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1802 | #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1803 | #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1804 | #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1805 | #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1806 | #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1807 | #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1808 | #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1809 | #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1810 | #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 1811 | #define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 1812 | #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1813 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1814 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1815 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1816 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1817 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1818 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1819 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1820 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1821 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1822 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1823 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1824 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1825 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1826 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1827 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1828 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1829 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1830 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1831 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1832 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1833 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1834 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1835 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1836 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1837 | #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1838 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1839 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1840 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1841 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1842 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1843 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1844 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1845 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1846 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1847 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1848 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1849 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1850 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1851 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1852 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1853 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1854 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1855 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1856 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1857 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1858 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1859 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1860 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1861 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1862 | #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ |
AnnaBridge | 170:e95d10626187 | 1863 | #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ |
AnnaBridge | 170:e95d10626187 | 1864 | #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1865 | #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1866 | #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1867 | #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1868 | #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1869 | #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1870 | #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1871 | #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1872 | #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1873 | #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1874 | #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ |
AnnaBridge | 170:e95d10626187 | 1875 | #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ |
AnnaBridge | 170:e95d10626187 | 1876 | #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1877 | #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1878 | #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1879 | #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1880 | #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1881 | #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1882 | #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1883 | #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1884 | #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1885 | #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1886 | #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ |
AnnaBridge | 170:e95d10626187 | 1887 | #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ |
AnnaBridge | 170:e95d10626187 | 1888 | #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ |
AnnaBridge | 170:e95d10626187 | 1889 | #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1890 | #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1891 | #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1892 | #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1893 | #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1894 | #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1895 | #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ |
AnnaBridge | 170:e95d10626187 | 1896 | #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ |
AnnaBridge | 170:e95d10626187 | 1897 | #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ |
AnnaBridge | 170:e95d10626187 | 1898 | #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1899 | #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1900 | #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1901 | #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1902 | #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1903 | #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1904 | #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ |
AnnaBridge | 170:e95d10626187 | 1905 | #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ |
AnnaBridge | 170:e95d10626187 | 1906 | #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ |
AnnaBridge | 170:e95d10626187 | 1907 | #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1908 | #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1909 | #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1910 | #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1911 | #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1912 | #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ |
AnnaBridge | 170:e95d10626187 | 1913 | |
AnnaBridge | 170:e95d10626187 | 1914 | /* Bit fields for WTIMER CC_CCV */ |
AnnaBridge | 170:e95d10626187 | 1915 | #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ |
AnnaBridge | 170:e95d10626187 | 1916 | #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ |
AnnaBridge | 170:e95d10626187 | 1917 | #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ |
AnnaBridge | 170:e95d10626187 | 1918 | #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ |
AnnaBridge | 170:e95d10626187 | 1919 | #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ |
AnnaBridge | 170:e95d10626187 | 1920 | #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ |
AnnaBridge | 170:e95d10626187 | 1921 | |
AnnaBridge | 170:e95d10626187 | 1922 | /* Bit fields for WTIMER CC_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1923 | #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1924 | #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1925 | #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1926 | #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1927 | #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1928 | #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ |
AnnaBridge | 170:e95d10626187 | 1929 | |
AnnaBridge | 170:e95d10626187 | 1930 | /* Bit fields for WTIMER CC_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1931 | #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1932 | #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1933 | #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1934 | #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1935 | #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1936 | #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ |
AnnaBridge | 170:e95d10626187 | 1937 | |
AnnaBridge | 170:e95d10626187 | 1938 | /* Bit fields for WTIMER DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1939 | #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1940 | #define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1941 | #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ |
AnnaBridge | 170:e95d10626187 | 1942 | #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ |
AnnaBridge | 170:e95d10626187 | 1943 | #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ |
AnnaBridge | 170:e95d10626187 | 1944 | #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1945 | #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1946 | #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ |
AnnaBridge | 170:e95d10626187 | 1947 | #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ |
AnnaBridge | 170:e95d10626187 | 1948 | #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ |
AnnaBridge | 170:e95d10626187 | 1949 | #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1950 | #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1951 | #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1952 | #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1953 | #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1954 | #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1955 | #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ |
AnnaBridge | 170:e95d10626187 | 1956 | #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ |
AnnaBridge | 170:e95d10626187 | 1957 | #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ |
AnnaBridge | 170:e95d10626187 | 1958 | #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1959 | #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1960 | #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ |
AnnaBridge | 170:e95d10626187 | 1961 | #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ |
AnnaBridge | 170:e95d10626187 | 1962 | #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ |
AnnaBridge | 170:e95d10626187 | 1963 | #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1964 | #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1965 | #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ |
AnnaBridge | 170:e95d10626187 | 1966 | #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ |
AnnaBridge | 170:e95d10626187 | 1967 | #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1968 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1969 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1970 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1971 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1972 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1973 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1974 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1975 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1976 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1977 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1978 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1979 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1980 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1981 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1982 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1983 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1984 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1985 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1986 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1987 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1988 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1989 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1990 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1991 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1992 | #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1993 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1994 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1995 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1996 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1997 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1998 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 1999 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2000 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2001 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2002 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2003 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2004 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2005 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2006 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2007 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2008 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2009 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2010 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2011 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2012 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2013 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2014 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2015 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2016 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2017 | #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ |
AnnaBridge | 170:e95d10626187 | 2018 | #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ |
AnnaBridge | 170:e95d10626187 | 2019 | #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ |
AnnaBridge | 170:e95d10626187 | 2020 | #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2021 | #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2022 | #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ |
AnnaBridge | 170:e95d10626187 | 2023 | #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ |
AnnaBridge | 170:e95d10626187 | 2024 | #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ |
AnnaBridge | 170:e95d10626187 | 2025 | #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2026 | #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2027 | #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ |
AnnaBridge | 170:e95d10626187 | 2028 | #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ |
AnnaBridge | 170:e95d10626187 | 2029 | #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ |
AnnaBridge | 170:e95d10626187 | 2030 | #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2031 | #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2032 | |
AnnaBridge | 170:e95d10626187 | 2033 | /* Bit fields for WTIMER DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2034 | #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2035 | #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2036 | #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ |
AnnaBridge | 170:e95d10626187 | 2037 | #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ |
AnnaBridge | 170:e95d10626187 | 2038 | #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2039 | #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2040 | #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2041 | #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2042 | #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2043 | #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2044 | #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2045 | #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2046 | #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2047 | #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2048 | #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2049 | #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2050 | #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2051 | #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2052 | #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2053 | #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2054 | #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2055 | #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2056 | #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2057 | #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2058 | #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2059 | #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2060 | #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2061 | #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2062 | #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ |
AnnaBridge | 170:e95d10626187 | 2063 | #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ |
AnnaBridge | 170:e95d10626187 | 2064 | #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2065 | #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2066 | #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ |
AnnaBridge | 170:e95d10626187 | 2067 | #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ |
AnnaBridge | 170:e95d10626187 | 2068 | #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2069 | #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
AnnaBridge | 170:e95d10626187 | 2070 | |
AnnaBridge | 170:e95d10626187 | 2071 | /* Bit fields for WTIMER DTFC */ |
AnnaBridge | 170:e95d10626187 | 2072 | #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2073 | #define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2074 | #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ |
AnnaBridge | 170:e95d10626187 | 2075 | #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ |
AnnaBridge | 170:e95d10626187 | 2076 | #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2077 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2078 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2079 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2080 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2081 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2082 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2083 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2084 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2085 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2086 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2087 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2088 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2089 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2090 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2091 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2092 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2093 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2094 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2095 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2096 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2097 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2098 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2099 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2100 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2101 | #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2102 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2103 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2104 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2105 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2106 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2107 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2108 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2109 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2110 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2111 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2112 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2113 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2114 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2115 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2116 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2117 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2118 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2119 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2120 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2121 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2122 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2123 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2124 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2125 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2126 | #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ |
AnnaBridge | 170:e95d10626187 | 2127 | #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ |
AnnaBridge | 170:e95d10626187 | 2128 | #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2129 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2130 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2131 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2132 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2133 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2134 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2135 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2136 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2137 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2138 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2139 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2140 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2141 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2142 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2143 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2144 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2145 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2146 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2147 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2148 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2149 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2150 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2151 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2152 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2153 | #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2154 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2155 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2156 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2157 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2158 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2159 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2160 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2161 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2162 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2163 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2164 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2165 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2166 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2167 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2168 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2169 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2170 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2171 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2172 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2173 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2174 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2175 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2176 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2177 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2178 | #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ |
AnnaBridge | 170:e95d10626187 | 2179 | #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ |
AnnaBridge | 170:e95d10626187 | 2180 | #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2181 | #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2182 | #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2183 | #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2184 | #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2185 | #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2186 | #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2187 | #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2188 | #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2189 | #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2190 | #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ |
AnnaBridge | 170:e95d10626187 | 2191 | #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ |
AnnaBridge | 170:e95d10626187 | 2192 | #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ |
AnnaBridge | 170:e95d10626187 | 2193 | #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2194 | #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2195 | #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ |
AnnaBridge | 170:e95d10626187 | 2196 | #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ |
AnnaBridge | 170:e95d10626187 | 2197 | #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ |
AnnaBridge | 170:e95d10626187 | 2198 | #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2199 | #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2200 | #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ |
AnnaBridge | 170:e95d10626187 | 2201 | #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ |
AnnaBridge | 170:e95d10626187 | 2202 | #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ |
AnnaBridge | 170:e95d10626187 | 2203 | #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2204 | #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2205 | #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ |
AnnaBridge | 170:e95d10626187 | 2206 | #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ |
AnnaBridge | 170:e95d10626187 | 2207 | #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ |
AnnaBridge | 170:e95d10626187 | 2208 | #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2209 | #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
AnnaBridge | 170:e95d10626187 | 2210 | |
AnnaBridge | 170:e95d10626187 | 2211 | /* Bit fields for WTIMER DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2212 | #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2213 | #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2214 | #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2215 | #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ |
AnnaBridge | 170:e95d10626187 | 2216 | #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ |
AnnaBridge | 170:e95d10626187 | 2217 | #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2218 | #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2219 | #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2220 | #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ |
AnnaBridge | 170:e95d10626187 | 2221 | #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ |
AnnaBridge | 170:e95d10626187 | 2222 | #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2223 | #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2224 | #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2225 | #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ |
AnnaBridge | 170:e95d10626187 | 2226 | #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ |
AnnaBridge | 170:e95d10626187 | 2227 | #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2228 | #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2229 | #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2230 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ |
AnnaBridge | 170:e95d10626187 | 2231 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ |
AnnaBridge | 170:e95d10626187 | 2232 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2233 | #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2234 | #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2235 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ |
AnnaBridge | 170:e95d10626187 | 2236 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ |
AnnaBridge | 170:e95d10626187 | 2237 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2238 | #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2239 | #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ |
AnnaBridge | 170:e95d10626187 | 2240 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ |
AnnaBridge | 170:e95d10626187 | 2241 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ |
AnnaBridge | 170:e95d10626187 | 2242 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2243 | #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
AnnaBridge | 170:e95d10626187 | 2244 | |
AnnaBridge | 170:e95d10626187 | 2245 | /* Bit fields for WTIMER DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2246 | #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2247 | #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2248 | #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ |
AnnaBridge | 170:e95d10626187 | 2249 | #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ |
AnnaBridge | 170:e95d10626187 | 2250 | #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ |
AnnaBridge | 170:e95d10626187 | 2251 | #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2252 | #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2253 | #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ |
AnnaBridge | 170:e95d10626187 | 2254 | #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ |
AnnaBridge | 170:e95d10626187 | 2255 | #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ |
AnnaBridge | 170:e95d10626187 | 2256 | #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2257 | #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2258 | #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ |
AnnaBridge | 170:e95d10626187 | 2259 | #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ |
AnnaBridge | 170:e95d10626187 | 2260 | #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ |
AnnaBridge | 170:e95d10626187 | 2261 | #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2262 | #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2263 | #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ |
AnnaBridge | 170:e95d10626187 | 2264 | #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ |
AnnaBridge | 170:e95d10626187 | 2265 | #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ |
AnnaBridge | 170:e95d10626187 | 2266 | #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2267 | #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
AnnaBridge | 170:e95d10626187 | 2268 | |
AnnaBridge | 170:e95d10626187 | 2269 | /* Bit fields for WTIMER DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2270 | #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2271 | #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2272 | #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ |
AnnaBridge | 170:e95d10626187 | 2273 | #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ |
AnnaBridge | 170:e95d10626187 | 2274 | #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ |
AnnaBridge | 170:e95d10626187 | 2275 | #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2276 | #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2277 | #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ |
AnnaBridge | 170:e95d10626187 | 2278 | #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ |
AnnaBridge | 170:e95d10626187 | 2279 | #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ |
AnnaBridge | 170:e95d10626187 | 2280 | #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2281 | #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2282 | #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ |
AnnaBridge | 170:e95d10626187 | 2283 | #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ |
AnnaBridge | 170:e95d10626187 | 2284 | #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ |
AnnaBridge | 170:e95d10626187 | 2285 | #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2286 | #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2287 | #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ |
AnnaBridge | 170:e95d10626187 | 2288 | #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ |
AnnaBridge | 170:e95d10626187 | 2289 | #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ |
AnnaBridge | 170:e95d10626187 | 2290 | #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2291 | #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
AnnaBridge | 170:e95d10626187 | 2292 | |
AnnaBridge | 170:e95d10626187 | 2293 | /* Bit fields for WTIMER DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2294 | #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2295 | #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2296 | #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 2297 | #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 2298 | #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2299 | #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2300 | #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2301 | #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2302 | #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2303 | #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2304 | #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2305 | #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2306 | #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2307 | #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ |
AnnaBridge | 170:e95d10626187 | 2308 | |
AnnaBridge | 170:e95d10626187 | 2309 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 2310 | /** @} End of group EFM32GG11B520F2048IQ64_WTIMER */ |
AnnaBridge | 170:e95d10626187 | 2311 | |
AnnaBridge | 170:e95d10626187 | 2312 | #include "efm32gg11b_uart.h" |
AnnaBridge | 170:e95d10626187 | 2313 | |
AnnaBridge | 170:e95d10626187 | 2314 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 2315 | * @addtogroup EFM32GG11B520F2048IQ64_CMU |
AnnaBridge | 170:e95d10626187 | 2316 | * @{ |
AnnaBridge | 170:e95d10626187 | 2317 | * @defgroup EFM32GG11B520F2048IQ64_CMU_BitFields CMU Bit Fields |
AnnaBridge | 170:e95d10626187 | 2318 | * @{ |
AnnaBridge | 170:e95d10626187 | 2319 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 2320 | |
AnnaBridge | 170:e95d10626187 | 2321 | /* Bit fields for CMU CTRL */ |
AnnaBridge | 170:e95d10626187 | 2322 | #define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2323 | #define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2324 | #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ |
AnnaBridge | 170:e95d10626187 | 2325 | #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ |
AnnaBridge | 170:e95d10626187 | 2326 | #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2327 | #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2328 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2329 | #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2330 | #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2331 | #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2332 | #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2333 | #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2334 | #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2335 | #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2336 | #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2337 | #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2338 | #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2339 | #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2340 | #define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2341 | #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2342 | #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2343 | #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2344 | #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2345 | #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2346 | #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2347 | #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2348 | #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2349 | #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2350 | #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2351 | #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2352 | #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2353 | #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2354 | #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2355 | #define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2356 | #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ |
AnnaBridge | 170:e95d10626187 | 2357 | #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ |
AnnaBridge | 170:e95d10626187 | 2358 | #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2359 | #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2360 | #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2361 | #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2362 | #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2363 | #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2364 | #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2365 | #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2366 | #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2367 | #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2368 | #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2369 | #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2370 | #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2371 | #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2372 | #define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2373 | #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2374 | #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2375 | #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2376 | #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2377 | #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2378 | #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2379 | #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2380 | #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2381 | #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2382 | #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2383 | #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2384 | #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2385 | #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2386 | #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2387 | #define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2388 | #define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ |
AnnaBridge | 170:e95d10626187 | 2389 | #define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ |
AnnaBridge | 170:e95d10626187 | 2390 | #define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2391 | #define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2392 | #define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2393 | #define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2394 | #define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2395 | #define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2396 | #define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2397 | #define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2398 | #define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2399 | #define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2400 | #define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2401 | #define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2402 | #define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2403 | #define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2404 | #define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2405 | #define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2406 | #define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2407 | #define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2408 | #define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2409 | #define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2410 | #define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2411 | #define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2412 | #define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2413 | #define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2414 | #define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2415 | #define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2416 | #define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2417 | #define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2418 | #define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2419 | #define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2420 | #define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2421 | #define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2422 | #define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2423 | #define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2424 | #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ |
AnnaBridge | 170:e95d10626187 | 2425 | #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ |
AnnaBridge | 170:e95d10626187 | 2426 | #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ |
AnnaBridge | 170:e95d10626187 | 2427 | #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2428 | #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2429 | #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ |
AnnaBridge | 170:e95d10626187 | 2430 | #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ |
AnnaBridge | 170:e95d10626187 | 2431 | #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ |
AnnaBridge | 170:e95d10626187 | 2432 | #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2433 | #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ |
AnnaBridge | 170:e95d10626187 | 2434 | |
AnnaBridge | 170:e95d10626187 | 2435 | /* Bit fields for CMU USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2436 | #define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2437 | #define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2438 | #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2439 | #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2440 | #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2441 | #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2442 | #define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2443 | #define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2444 | #define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2445 | #define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2446 | #define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2447 | #define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2448 | #define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2449 | #define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2450 | #define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2451 | #define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2452 | #define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2453 | #define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2454 | #define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ |
AnnaBridge | 170:e95d10626187 | 2455 | #define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2456 | #define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2457 | #define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2458 | #define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2459 | #define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2460 | #define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2461 | #define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2462 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2463 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2464 | #define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2465 | #define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2466 | #define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2467 | #define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2468 | #define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2469 | #define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
AnnaBridge | 170:e95d10626187 | 2470 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2471 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2472 | #define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2473 | #define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2474 | #define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2475 | #define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2476 | #define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2477 | #define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2478 | |
AnnaBridge | 170:e95d10626187 | 2479 | /* Bit fields for CMU HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2480 | #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2481 | #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2482 | #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2483 | #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2484 | #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2485 | #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2486 | #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2487 | #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2488 | #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2489 | #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2490 | #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2491 | #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2492 | #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2493 | #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2494 | #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2495 | #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2496 | #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2497 | #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2498 | #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ |
AnnaBridge | 170:e95d10626187 | 2499 | #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2500 | #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2501 | #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2502 | #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2503 | #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2504 | #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2505 | #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2506 | #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2507 | #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2508 | #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2509 | #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2510 | #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2511 | #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2512 | #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2513 | #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
AnnaBridge | 170:e95d10626187 | 2514 | #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2515 | #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2516 | #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2517 | #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2518 | #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2519 | #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2520 | #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2521 | #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2522 | |
AnnaBridge | 170:e95d10626187 | 2523 | /* Bit fields for CMU AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2524 | #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2525 | #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2526 | #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2527 | #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2528 | #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2529 | #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2530 | #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2531 | #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ |
AnnaBridge | 170:e95d10626187 | 2532 | #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2533 | #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2534 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2535 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ |
AnnaBridge | 170:e95d10626187 | 2536 | #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2537 | #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2538 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2539 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ |
AnnaBridge | 170:e95d10626187 | 2540 | #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2541 | #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2542 | #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ |
AnnaBridge | 170:e95d10626187 | 2543 | #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2544 | #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ |
AnnaBridge | 170:e95d10626187 | 2545 | #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2546 | #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2547 | #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2548 | #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 2549 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2550 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2551 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2552 | #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2553 | #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2554 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2555 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2556 | #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2557 | #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ |
AnnaBridge | 170:e95d10626187 | 2558 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2559 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ |
AnnaBridge | 170:e95d10626187 | 2560 | #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2561 | #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2562 | #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2563 | #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ |
AnnaBridge | 170:e95d10626187 | 2564 | #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2565 | #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2566 | |
AnnaBridge | 170:e95d10626187 | 2567 | /* Bit fields for CMU LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2568 | #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2569 | #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2570 | #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2571 | #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2572 | #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2573 | #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2574 | #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ |
AnnaBridge | 170:e95d10626187 | 2575 | #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ |
AnnaBridge | 170:e95d10626187 | 2576 | #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ |
AnnaBridge | 170:e95d10626187 | 2577 | #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2578 | #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2579 | #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ |
AnnaBridge | 170:e95d10626187 | 2580 | #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ |
AnnaBridge | 170:e95d10626187 | 2581 | #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ |
AnnaBridge | 170:e95d10626187 | 2582 | #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2583 | #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2584 | #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ |
AnnaBridge | 170:e95d10626187 | 2585 | #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ |
AnnaBridge | 170:e95d10626187 | 2586 | #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ |
AnnaBridge | 170:e95d10626187 | 2587 | #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2588 | #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2589 | #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ |
AnnaBridge | 170:e95d10626187 | 2590 | #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ |
AnnaBridge | 170:e95d10626187 | 2591 | #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2592 | #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2593 | #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2594 | #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2595 | #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2596 | #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2597 | #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2598 | #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2599 | #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2600 | #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2601 | #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2602 | #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2603 | #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2604 | #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2605 | #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2606 | #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2607 | #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2608 | #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2609 | #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2610 | #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2611 | #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ |
AnnaBridge | 170:e95d10626187 | 2612 | #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ |
AnnaBridge | 170:e95d10626187 | 2613 | #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2614 | #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2615 | |
AnnaBridge | 170:e95d10626187 | 2616 | /* Bit fields for CMU HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2617 | #define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2618 | #define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2619 | #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2620 | #define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2621 | #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2622 | #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2623 | #define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2624 | #define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2625 | #define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2626 | #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2627 | #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2628 | #define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2629 | #define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2630 | #define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2631 | #define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable double frequency on HFXOX2 clock (compared to HFXO clock). */ |
AnnaBridge | 170:e95d10626187 | 2632 | #define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ |
AnnaBridge | 170:e95d10626187 | 2633 | #define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ |
AnnaBridge | 170:e95d10626187 | 2634 | #define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2635 | #define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2636 | #define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ |
AnnaBridge | 170:e95d10626187 | 2637 | #define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ |
AnnaBridge | 170:e95d10626187 | 2638 | #define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2639 | #define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2640 | #define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2641 | #define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2642 | #define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2643 | #define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2644 | #define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2645 | #define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2646 | #define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2647 | #define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2648 | #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2649 | #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2650 | #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2651 | #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2652 | #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2653 | #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2654 | #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2655 | #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2656 | #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2657 | #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2658 | #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2659 | #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2660 | #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2661 | #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2662 | #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2663 | #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2664 | #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2665 | #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2666 | #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2667 | #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2668 | #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ |
AnnaBridge | 170:e95d10626187 | 2669 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ |
AnnaBridge | 170:e95d10626187 | 2670 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ |
AnnaBridge | 170:e95d10626187 | 2671 | #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2672 | #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2673 | #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ |
AnnaBridge | 170:e95d10626187 | 2674 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ |
AnnaBridge | 170:e95d10626187 | 2675 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ |
AnnaBridge | 170:e95d10626187 | 2676 | #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2677 | #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2678 | |
AnnaBridge | 170:e95d10626187 | 2679 | /* Bit fields for CMU HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2680 | #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2681 | #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2682 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 2683 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 2684 | #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2685 | #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2686 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ |
AnnaBridge | 170:e95d10626187 | 2687 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ |
AnnaBridge | 170:e95d10626187 | 2688 | #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2689 | #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ |
AnnaBridge | 170:e95d10626187 | 2690 | |
AnnaBridge | 170:e95d10626187 | 2691 | /* Bit fields for CMU HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2692 | #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2693 | #define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2694 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 2695 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 2696 | #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2697 | #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2698 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ |
AnnaBridge | 170:e95d10626187 | 2699 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ |
AnnaBridge | 170:e95d10626187 | 2700 | #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2701 | #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2702 | #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ |
AnnaBridge | 170:e95d10626187 | 2703 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ |
AnnaBridge | 170:e95d10626187 | 2704 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ |
AnnaBridge | 170:e95d10626187 | 2705 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2706 | #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2707 | #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically perform Peak Monitoring Algorithm on every rising edge of ULFRCO */ |
AnnaBridge | 170:e95d10626187 | 2708 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ |
AnnaBridge | 170:e95d10626187 | 2709 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ |
AnnaBridge | 170:e95d10626187 | 2710 | #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2711 | #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ |
AnnaBridge | 170:e95d10626187 | 2712 | |
AnnaBridge | 170:e95d10626187 | 2713 | /* Bit fields for CMU HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2714 | #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D04EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2715 | #define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2716 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2717 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2718 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2719 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2720 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2721 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2722 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2723 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2724 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2725 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2726 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2727 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2728 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2729 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2730 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2731 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2732 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2733 | #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2734 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2735 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2736 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2737 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2738 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2739 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2740 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2741 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2742 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2743 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2744 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2745 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2746 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2747 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2748 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2749 | #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2750 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2751 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2752 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2753 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2754 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2755 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2756 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000004UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2757 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2758 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2759 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2760 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2761 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2762 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2763 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2764 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2765 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2766 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2767 | #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2768 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2769 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2770 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2771 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2772 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2773 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2774 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2775 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2776 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2777 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2778 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2779 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2780 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2781 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2782 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2783 | #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2784 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2785 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2786 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2787 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2788 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2789 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2790 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2791 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2792 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2793 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2794 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2795 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2796 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2797 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2798 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2799 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2800 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2801 | #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2802 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2803 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2804 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2805 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2806 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2807 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2808 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2809 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2810 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2811 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2812 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2813 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2814 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2815 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2816 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2817 | #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ |
AnnaBridge | 170:e95d10626187 | 2818 | |
AnnaBridge | 170:e95d10626187 | 2819 | /* Bit fields for CMU LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2820 | #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2821 | #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2822 | #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2823 | #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ |
AnnaBridge | 170:e95d10626187 | 2824 | #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2825 | #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2826 | #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2827 | #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2828 | #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2829 | #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2830 | #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2831 | #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2832 | #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2833 | #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2834 | #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2835 | #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2836 | #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ |
AnnaBridge | 170:e95d10626187 | 2837 | #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ |
AnnaBridge | 170:e95d10626187 | 2838 | #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2839 | #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2840 | #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ |
AnnaBridge | 170:e95d10626187 | 2841 | #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ |
AnnaBridge | 170:e95d10626187 | 2842 | #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ |
AnnaBridge | 170:e95d10626187 | 2843 | #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2844 | #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2845 | #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ |
AnnaBridge | 170:e95d10626187 | 2846 | #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ |
AnnaBridge | 170:e95d10626187 | 2847 | #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ |
AnnaBridge | 170:e95d10626187 | 2848 | #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2849 | #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2850 | #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ |
AnnaBridge | 170:e95d10626187 | 2851 | #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ |
AnnaBridge | 170:e95d10626187 | 2852 | #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2853 | #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2854 | #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ |
AnnaBridge | 170:e95d10626187 | 2855 | #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ |
AnnaBridge | 170:e95d10626187 | 2856 | #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ |
AnnaBridge | 170:e95d10626187 | 2857 | #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2858 | #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2859 | #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2860 | #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ |
AnnaBridge | 170:e95d10626187 | 2861 | #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2862 | #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2863 | #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2864 | #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2865 | #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2866 | #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2867 | #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2868 | #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2869 | #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2870 | #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2871 | #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2872 | #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2873 | #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2874 | #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2875 | #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2876 | #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2877 | #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2878 | #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ |
AnnaBridge | 170:e95d10626187 | 2879 | |
AnnaBridge | 170:e95d10626187 | 2880 | /* Bit fields for CMU DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2881 | #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2882 | #define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2883 | #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ |
AnnaBridge | 170:e95d10626187 | 2884 | #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2885 | #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ |
AnnaBridge | 170:e95d10626187 | 2886 | #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2887 | #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2888 | #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2889 | #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2890 | #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2891 | #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2892 | #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ |
AnnaBridge | 170:e95d10626187 | 2893 | #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ |
AnnaBridge | 170:e95d10626187 | 2894 | #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ |
AnnaBridge | 170:e95d10626187 | 2895 | #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2896 | #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2897 | #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2898 | #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2899 | #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2900 | #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2901 | #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ |
AnnaBridge | 170:e95d10626187 | 2902 | #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ |
AnnaBridge | 170:e95d10626187 | 2903 | #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ |
AnnaBridge | 170:e95d10626187 | 2904 | #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2905 | #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2906 | #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ |
AnnaBridge | 170:e95d10626187 | 2907 | #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ |
AnnaBridge | 170:e95d10626187 | 2908 | #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2909 | #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2910 | #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2911 | #define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2912 | #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2913 | #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2914 | #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2915 | #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2916 | #define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2917 | #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2918 | #define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ |
AnnaBridge | 170:e95d10626187 | 2919 | #define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ |
AnnaBridge | 170:e95d10626187 | 2920 | #define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ |
AnnaBridge | 170:e95d10626187 | 2921 | #define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2922 | #define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ |
AnnaBridge | 170:e95d10626187 | 2923 | |
AnnaBridge | 170:e95d10626187 | 2924 | /* Bit fields for CMU DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2925 | #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2926 | #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2927 | #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ |
AnnaBridge | 170:e95d10626187 | 2928 | #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ |
AnnaBridge | 170:e95d10626187 | 2929 | #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2930 | #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2931 | #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ |
AnnaBridge | 170:e95d10626187 | 2932 | #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ |
AnnaBridge | 170:e95d10626187 | 2933 | #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2934 | #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ |
AnnaBridge | 170:e95d10626187 | 2935 | |
AnnaBridge | 170:e95d10626187 | 2936 | /* Bit fields for CMU CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2937 | #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2938 | #define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2939 | #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ |
AnnaBridge | 170:e95d10626187 | 2940 | #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ |
AnnaBridge | 170:e95d10626187 | 2941 | #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2942 | #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2943 | #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2944 | #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2945 | #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2946 | #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2947 | #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2948 | #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2949 | #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2950 | #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2951 | #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2952 | #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2953 | #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2954 | #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2955 | #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2956 | #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2957 | #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ |
AnnaBridge | 170:e95d10626187 | 2958 | #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ |
AnnaBridge | 170:e95d10626187 | 2959 | #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2960 | #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2961 | #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2962 | #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2963 | #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2964 | #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2965 | #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2966 | #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2967 | #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2968 | #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2969 | #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2970 | #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2971 | #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2972 | #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2973 | #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2974 | #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2975 | #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2976 | #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2977 | #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ |
AnnaBridge | 170:e95d10626187 | 2978 | #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ |
AnnaBridge | 170:e95d10626187 | 2979 | #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ |
AnnaBridge | 170:e95d10626187 | 2980 | #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2981 | #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2982 | #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ |
AnnaBridge | 170:e95d10626187 | 2983 | #define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ |
AnnaBridge | 170:e95d10626187 | 2984 | #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2985 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2986 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2987 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2988 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2989 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2990 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2991 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2992 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2993 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2994 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2995 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2996 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2997 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2998 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 2999 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3000 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3001 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3002 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3003 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3004 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3005 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3006 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3007 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3008 | #define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3009 | #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3010 | #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3011 | #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3012 | #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3013 | #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3014 | #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3015 | #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3016 | #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3017 | #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3018 | #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3019 | #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3020 | #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3021 | #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3022 | #define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3023 | #define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3024 | #define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3025 | #define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3026 | #define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3027 | #define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3028 | #define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3029 | #define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3030 | #define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3031 | #define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3032 | #define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3033 | #define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3034 | #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ |
AnnaBridge | 170:e95d10626187 | 3035 | #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ |
AnnaBridge | 170:e95d10626187 | 3036 | #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3037 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3038 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3039 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3040 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3041 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3042 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3043 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3044 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3045 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3046 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3047 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3048 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3049 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3050 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3051 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3052 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3053 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3054 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3055 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3056 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3057 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3058 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3059 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3060 | #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3061 | #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3062 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3063 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3064 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3065 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3066 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3067 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3068 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3069 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3070 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3071 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3072 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3073 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3074 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3075 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3076 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3077 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3078 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3079 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3080 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3081 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3082 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3083 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3084 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3085 | #define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ |
AnnaBridge | 170:e95d10626187 | 3086 | |
AnnaBridge | 170:e95d10626187 | 3087 | /* Bit fields for CMU CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3088 | #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3089 | #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3090 | #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3091 | #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3092 | #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3093 | #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ |
AnnaBridge | 170:e95d10626187 | 3094 | |
AnnaBridge | 170:e95d10626187 | 3095 | /* Bit fields for CMU OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3096 | #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3097 | #define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3098 | #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ |
AnnaBridge | 170:e95d10626187 | 3099 | #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3100 | #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3101 | #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3102 | #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3103 | #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ |
AnnaBridge | 170:e95d10626187 | 3104 | #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3105 | #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3106 | #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3107 | #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3108 | #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ |
AnnaBridge | 170:e95d10626187 | 3109 | #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ |
AnnaBridge | 170:e95d10626187 | 3110 | #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ |
AnnaBridge | 170:e95d10626187 | 3111 | #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3112 | #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3113 | #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ |
AnnaBridge | 170:e95d10626187 | 3114 | #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ |
AnnaBridge | 170:e95d10626187 | 3115 | #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ |
AnnaBridge | 170:e95d10626187 | 3116 | #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3117 | #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3118 | #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ |
AnnaBridge | 170:e95d10626187 | 3119 | #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3120 | #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3121 | #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3122 | #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3123 | #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ |
AnnaBridge | 170:e95d10626187 | 3124 | #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3125 | #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3126 | #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3127 | #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3128 | #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ |
AnnaBridge | 170:e95d10626187 | 3129 | #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3130 | #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3131 | #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3132 | #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3133 | #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ |
AnnaBridge | 170:e95d10626187 | 3134 | #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3135 | #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3136 | #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3137 | #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3138 | #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ |
AnnaBridge | 170:e95d10626187 | 3139 | #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ |
AnnaBridge | 170:e95d10626187 | 3140 | #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ |
AnnaBridge | 170:e95d10626187 | 3141 | #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3142 | #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3143 | #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ |
AnnaBridge | 170:e95d10626187 | 3144 | #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ |
AnnaBridge | 170:e95d10626187 | 3145 | #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ |
AnnaBridge | 170:e95d10626187 | 3146 | #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3147 | #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3148 | #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ |
AnnaBridge | 170:e95d10626187 | 3149 | #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3150 | #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ |
AnnaBridge | 170:e95d10626187 | 3151 | #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3152 | #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3153 | #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ |
AnnaBridge | 170:e95d10626187 | 3154 | #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3155 | #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3156 | #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3157 | #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3158 | #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ |
AnnaBridge | 170:e95d10626187 | 3159 | #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ |
AnnaBridge | 170:e95d10626187 | 3160 | #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ |
AnnaBridge | 170:e95d10626187 | 3161 | #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3162 | #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3163 | #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ |
AnnaBridge | 170:e95d10626187 | 3164 | #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ |
AnnaBridge | 170:e95d10626187 | 3165 | #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ |
AnnaBridge | 170:e95d10626187 | 3166 | #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3167 | #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ |
AnnaBridge | 170:e95d10626187 | 3168 | |
AnnaBridge | 170:e95d10626187 | 3169 | /* Bit fields for CMU CMD */ |
AnnaBridge | 170:e95d10626187 | 3170 | #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3171 | #define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3172 | #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ |
AnnaBridge | 170:e95d10626187 | 3173 | #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ |
AnnaBridge | 170:e95d10626187 | 3174 | #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ |
AnnaBridge | 170:e95d10626187 | 3175 | #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3176 | #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3177 | #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ |
AnnaBridge | 170:e95d10626187 | 3178 | #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ |
AnnaBridge | 170:e95d10626187 | 3179 | #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ |
AnnaBridge | 170:e95d10626187 | 3180 | #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3181 | #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3182 | #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ |
AnnaBridge | 170:e95d10626187 | 3183 | #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ |
AnnaBridge | 170:e95d10626187 | 3184 | #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ |
AnnaBridge | 170:e95d10626187 | 3185 | #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3186 | #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ |
AnnaBridge | 170:e95d10626187 | 3187 | |
AnnaBridge | 170:e95d10626187 | 3188 | /* Bit fields for CMU DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3189 | #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3190 | #define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3191 | #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ |
AnnaBridge | 170:e95d10626187 | 3192 | #define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ |
AnnaBridge | 170:e95d10626187 | 3193 | #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3194 | #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3195 | #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3196 | #define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3197 | #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3198 | #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3199 | #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3200 | #define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3201 | |
AnnaBridge | 170:e95d10626187 | 3202 | /* Bit fields for CMU HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3203 | #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3204 | #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3205 | #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ |
AnnaBridge | 170:e95d10626187 | 3206 | #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ |
AnnaBridge | 170:e95d10626187 | 3207 | #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3208 | #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3209 | #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3210 | #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3211 | #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3212 | #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3213 | #define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3214 | #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3215 | #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3216 | #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3217 | #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3218 | #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3219 | #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3220 | #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3221 | #define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3222 | #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3223 | |
AnnaBridge | 170:e95d10626187 | 3224 | /* Bit fields for CMU LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3225 | #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3226 | #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3227 | #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ |
AnnaBridge | 170:e95d10626187 | 3228 | #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ |
AnnaBridge | 170:e95d10626187 | 3229 | #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3230 | #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3231 | #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3232 | #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3233 | #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3234 | #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3235 | #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3236 | #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3237 | #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3238 | #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3239 | |
AnnaBridge | 170:e95d10626187 | 3240 | /* Bit fields for CMU LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3241 | #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3242 | #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3243 | #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ |
AnnaBridge | 170:e95d10626187 | 3244 | #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ |
AnnaBridge | 170:e95d10626187 | 3245 | #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3246 | #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3247 | #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3248 | #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3249 | #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3250 | #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3251 | #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3252 | #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3253 | #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3254 | #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3255 | #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3256 | #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3257 | |
AnnaBridge | 170:e95d10626187 | 3258 | /* Bit fields for CMU LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3259 | #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3260 | #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3261 | #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ |
AnnaBridge | 170:e95d10626187 | 3262 | #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ |
AnnaBridge | 170:e95d10626187 | 3263 | #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3264 | #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3265 | #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3266 | #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3267 | #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3268 | #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3269 | #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3270 | #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3271 | #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3272 | #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3273 | |
AnnaBridge | 170:e95d10626187 | 3274 | /* Bit fields for CMU LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3275 | #define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3276 | #define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3277 | #define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ |
AnnaBridge | 170:e95d10626187 | 3278 | #define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ |
AnnaBridge | 170:e95d10626187 | 3279 | #define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3280 | #define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3281 | #define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3282 | #define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3283 | #define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3284 | #define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3285 | #define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3286 | #define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3287 | #define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3288 | #define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ |
AnnaBridge | 170:e95d10626187 | 3289 | |
AnnaBridge | 170:e95d10626187 | 3290 | /* Bit fields for CMU STATUS */ |
AnnaBridge | 170:e95d10626187 | 3291 | #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3292 | #define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3293 | #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3294 | #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3295 | #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3296 | #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3297 | #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3298 | #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ |
AnnaBridge | 170:e95d10626187 | 3299 | #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3300 | #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3301 | #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3302 | #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3303 | #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3304 | #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ |
AnnaBridge | 170:e95d10626187 | 3305 | #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ |
AnnaBridge | 170:e95d10626187 | 3306 | #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3307 | #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3308 | #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ |
AnnaBridge | 170:e95d10626187 | 3309 | #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3310 | #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3311 | #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3312 | #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3313 | #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3314 | #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3315 | #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3316 | #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3317 | #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3318 | #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ |
AnnaBridge | 170:e95d10626187 | 3319 | #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3320 | #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3321 | #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3322 | #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3323 | #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3324 | #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3325 | #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3326 | #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3327 | #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3328 | #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ |
AnnaBridge | 170:e95d10626187 | 3329 | #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3330 | #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3331 | #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3332 | #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3333 | #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3334 | #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ |
AnnaBridge | 170:e95d10626187 | 3335 | #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ |
AnnaBridge | 170:e95d10626187 | 3336 | #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3337 | #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3338 | #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ |
AnnaBridge | 170:e95d10626187 | 3339 | #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3340 | #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3341 | #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3342 | #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3343 | #define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3344 | #define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3345 | #define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ |
AnnaBridge | 170:e95d10626187 | 3346 | #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3347 | #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3348 | #define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ |
AnnaBridge | 170:e95d10626187 | 3349 | #define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3350 | #define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3351 | #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3352 | #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3353 | #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ |
AnnaBridge | 170:e95d10626187 | 3354 | #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ |
AnnaBridge | 170:e95d10626187 | 3355 | #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ |
AnnaBridge | 170:e95d10626187 | 3356 | #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3357 | #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3358 | #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ |
AnnaBridge | 170:e95d10626187 | 3359 | #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3360 | #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3361 | #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3362 | #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3363 | #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ |
AnnaBridge | 170:e95d10626187 | 3364 | #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3365 | #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3366 | #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3367 | #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3368 | #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ |
AnnaBridge | 170:e95d10626187 | 3369 | #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3370 | #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3371 | #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3372 | #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3373 | #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ |
AnnaBridge | 170:e95d10626187 | 3374 | #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ |
AnnaBridge | 170:e95d10626187 | 3375 | #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ |
AnnaBridge | 170:e95d10626187 | 3376 | #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3377 | #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3378 | #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO clock phase */ |
AnnaBridge | 170:e95d10626187 | 3379 | #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3380 | #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3381 | #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3382 | #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3383 | #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO clock phase */ |
AnnaBridge | 170:e95d10626187 | 3384 | #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3385 | #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3386 | #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3387 | #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3388 | #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO clock phase */ |
AnnaBridge | 170:e95d10626187 | 3389 | #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3390 | #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ |
AnnaBridge | 170:e95d10626187 | 3391 | #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3392 | #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ |
AnnaBridge | 170:e95d10626187 | 3393 | |
AnnaBridge | 170:e95d10626187 | 3394 | /* Bit fields for CMU HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3395 | #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3396 | #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3397 | #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ |
AnnaBridge | 170:e95d10626187 | 3398 | #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ |
AnnaBridge | 170:e95d10626187 | 3399 | #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3400 | #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3401 | #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3402 | #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3403 | #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3404 | #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3405 | #define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3406 | #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3407 | #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3408 | #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3409 | #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3410 | #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3411 | #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3412 | #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3413 | #define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3414 | #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3415 | |
AnnaBridge | 170:e95d10626187 | 3416 | /* Bit fields for CMU HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3417 | #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3418 | #define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3419 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 3420 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ |
AnnaBridge | 170:e95d10626187 | 3421 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3422 | #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3423 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ |
AnnaBridge | 170:e95d10626187 | 3424 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ |
AnnaBridge | 170:e95d10626187 | 3425 | #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3426 | #define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3427 | #define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm found a value for IBTRIMXOCORE. If HFXO is started again with PEAKDETTMODE=ONCECMD the IBTRIMXOCORE value from CMU_HFXOTRIMSTATUS will be used and Peak Detection algorithm will be skipped. */ |
AnnaBridge | 170:e95d10626187 | 3428 | #define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ |
AnnaBridge | 170:e95d10626187 | 3429 | #define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ |
AnnaBridge | 170:e95d10626187 | 3430 | #define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3431 | #define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3432 | #define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm found a value for IBTRIMXOCOREMON. */ |
AnnaBridge | 170:e95d10626187 | 3433 | #define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ |
AnnaBridge | 170:e95d10626187 | 3434 | #define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ |
AnnaBridge | 170:e95d10626187 | 3435 | #define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3436 | #define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ |
AnnaBridge | 170:e95d10626187 | 3437 | |
AnnaBridge | 170:e95d10626187 | 3438 | /* Bit fields for CMU IF */ |
AnnaBridge | 170:e95d10626187 | 3439 | #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3440 | #define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3441 | #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3442 | #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3443 | #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3444 | #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3445 | #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3446 | #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3447 | #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3448 | #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3449 | #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3450 | #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3451 | #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3452 | #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3453 | #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3454 | #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3455 | #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3456 | #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3457 | #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3458 | #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3459 | #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3460 | #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3461 | #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3462 | #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3463 | #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3464 | #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3465 | #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3466 | #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3467 | #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3468 | #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3469 | #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3470 | #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3471 | #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3472 | #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3473 | #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3474 | #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3475 | #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3476 | #define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3477 | #define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3478 | #define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3479 | #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3480 | #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3481 | #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3482 | #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3483 | #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3484 | #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3485 | #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3486 | #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3487 | #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3488 | #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3489 | #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3490 | #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3491 | #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3492 | #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3493 | #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3494 | #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3495 | #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3496 | #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3497 | #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3498 | #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3499 | #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3500 | #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3501 | #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3502 | #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3503 | #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3504 | #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3505 | #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3506 | #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3507 | #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3508 | #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3509 | #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3510 | #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3511 | #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3512 | #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3513 | #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3514 | #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3515 | #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3516 | #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3517 | #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3518 | #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3519 | #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3520 | #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3521 | #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3522 | #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3523 | #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3524 | #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3525 | #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3526 | #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3527 | #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3528 | #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3529 | #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3530 | #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3531 | #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3532 | #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3533 | #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3534 | #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3535 | #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3536 | #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3537 | #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3538 | #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3539 | #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3540 | #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ |
AnnaBridge | 170:e95d10626187 | 3541 | |
AnnaBridge | 170:e95d10626187 | 3542 | /* Bit fields for CMU IFS */ |
AnnaBridge | 170:e95d10626187 | 3543 | #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3544 | #define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3545 | #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3546 | #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3547 | #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3548 | #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3549 | #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3550 | #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3551 | #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3552 | #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3553 | #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3554 | #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3555 | #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3556 | #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3557 | #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3558 | #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3559 | #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3560 | #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3561 | #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3562 | #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3563 | #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3564 | #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3565 | #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3566 | #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3567 | #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3568 | #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3569 | #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3570 | #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3571 | #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3572 | #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3573 | #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3574 | #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3575 | #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3576 | #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3577 | #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3578 | #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3579 | #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3580 | #define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3581 | #define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3582 | #define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3583 | #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3584 | #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3585 | #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3586 | #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3587 | #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3588 | #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3589 | #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3590 | #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3591 | #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3592 | #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3593 | #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3594 | #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3595 | #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3596 | #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3597 | #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3598 | #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3599 | #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3600 | #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3601 | #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3602 | #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3603 | #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3604 | #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3605 | #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3606 | #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3607 | #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3608 | #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3609 | #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3610 | #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3611 | #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3612 | #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3613 | #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3614 | #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3615 | #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3616 | #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3617 | #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3618 | #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3619 | #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3620 | #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3621 | #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3622 | #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3623 | #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3624 | #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3625 | #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3626 | #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3627 | #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3628 | #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3629 | #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3630 | #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3631 | #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3632 | #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3633 | #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3634 | #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3635 | #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3636 | #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3637 | #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3638 | #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3639 | #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3640 | #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3641 | #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3642 | #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3643 | #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3644 | #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 3645 | |
AnnaBridge | 170:e95d10626187 | 3646 | /* Bit fields for CMU IFC */ |
AnnaBridge | 170:e95d10626187 | 3647 | #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3648 | #define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3649 | #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3650 | #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3651 | #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3652 | #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3653 | #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3654 | #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3655 | #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3656 | #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3657 | #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3658 | #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3659 | #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3660 | #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3661 | #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3662 | #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3663 | #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3664 | #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3665 | #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3666 | #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3667 | #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3668 | #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3669 | #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3670 | #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3671 | #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3672 | #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3673 | #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3674 | #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3675 | #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3676 | #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3677 | #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3678 | #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3679 | #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3680 | #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3681 | #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3682 | #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3683 | #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3684 | #define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3685 | #define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3686 | #define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3687 | #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3688 | #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3689 | #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3690 | #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3691 | #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3692 | #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3693 | #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3694 | #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3695 | #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3696 | #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3697 | #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3698 | #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3699 | #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3700 | #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3701 | #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3702 | #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3703 | #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3704 | #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3705 | #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3706 | #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3707 | #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3708 | #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3709 | #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3710 | #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3711 | #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3712 | #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3713 | #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3714 | #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3715 | #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3716 | #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3717 | #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3718 | #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3719 | #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3720 | #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3721 | #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3722 | #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3723 | #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3724 | #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3725 | #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3726 | #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3727 | #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3728 | #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3729 | #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3730 | #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3731 | #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3732 | #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3733 | #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3734 | #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3735 | #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3736 | #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3737 | #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3738 | #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3739 | #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3740 | #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3741 | #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3742 | #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3743 | #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3744 | #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 3745 | #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3746 | #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3747 | #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3748 | #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 3749 | |
AnnaBridge | 170:e95d10626187 | 3750 | /* Bit fields for CMU IEN */ |
AnnaBridge | 170:e95d10626187 | 3751 | #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3752 | #define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3753 | #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3754 | #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3755 | #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3756 | #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3757 | #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3758 | #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3759 | #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3760 | #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3761 | #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3762 | #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3763 | #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3764 | #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3765 | #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3766 | #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3767 | #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3768 | #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3769 | #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3770 | #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ |
AnnaBridge | 170:e95d10626187 | 3771 | #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3772 | #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3773 | #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3774 | #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3775 | #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3776 | #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3777 | #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3778 | #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3779 | #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3780 | #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ |
AnnaBridge | 170:e95d10626187 | 3781 | #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3782 | #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3783 | #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3784 | #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3785 | #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ |
AnnaBridge | 170:e95d10626187 | 3786 | #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3787 | #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3788 | #define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3789 | #define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3790 | #define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ |
AnnaBridge | 170:e95d10626187 | 3791 | #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3792 | #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3793 | #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3794 | #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3795 | #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ |
AnnaBridge | 170:e95d10626187 | 3796 | #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3797 | #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3798 | #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3799 | #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3800 | #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ |
AnnaBridge | 170:e95d10626187 | 3801 | #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3802 | #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3803 | #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3804 | #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3805 | #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ |
AnnaBridge | 170:e95d10626187 | 3806 | #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3807 | #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3808 | #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3809 | #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3810 | #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ |
AnnaBridge | 170:e95d10626187 | 3811 | #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3812 | #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3813 | #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3814 | #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3815 | #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ |
AnnaBridge | 170:e95d10626187 | 3816 | #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3817 | #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3818 | #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3819 | #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3820 | #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ |
AnnaBridge | 170:e95d10626187 | 3821 | #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3822 | #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3823 | #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3824 | #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3825 | #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ |
AnnaBridge | 170:e95d10626187 | 3826 | #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3827 | #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3828 | #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3829 | #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3830 | #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ |
AnnaBridge | 170:e95d10626187 | 3831 | #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3832 | #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3833 | #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3834 | #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3835 | #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3836 | #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3837 | #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3838 | #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3839 | #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3840 | #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3841 | #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3842 | #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3843 | #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3844 | #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3845 | #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ |
AnnaBridge | 170:e95d10626187 | 3846 | #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3847 | #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3848 | #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 3849 | #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3850 | #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ |
AnnaBridge | 170:e95d10626187 | 3851 | #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3852 | #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 3853 | |
AnnaBridge | 170:e95d10626187 | 3854 | /* Bit fields for CMU HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3855 | #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3856 | #define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3857 | #define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3858 | #define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ |
AnnaBridge | 170:e95d10626187 | 3859 | #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ |
AnnaBridge | 170:e95d10626187 | 3860 | #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3861 | #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3862 | #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3863 | #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ |
AnnaBridge | 170:e95d10626187 | 3864 | #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ |
AnnaBridge | 170:e95d10626187 | 3865 | #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3866 | #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3867 | #define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3868 | #define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ |
AnnaBridge | 170:e95d10626187 | 3869 | #define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ |
AnnaBridge | 170:e95d10626187 | 3870 | #define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3871 | #define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3872 | #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3873 | #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ |
AnnaBridge | 170:e95d10626187 | 3874 | #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ |
AnnaBridge | 170:e95d10626187 | 3875 | #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3876 | #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3877 | #define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3878 | #define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ |
AnnaBridge | 170:e95d10626187 | 3879 | #define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ |
AnnaBridge | 170:e95d10626187 | 3880 | #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3881 | #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3882 | #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3883 | #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ |
AnnaBridge | 170:e95d10626187 | 3884 | #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ |
AnnaBridge | 170:e95d10626187 | 3885 | #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3886 | #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3887 | #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3888 | #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ |
AnnaBridge | 170:e95d10626187 | 3889 | #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ |
AnnaBridge | 170:e95d10626187 | 3890 | #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3891 | #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3892 | |
AnnaBridge | 170:e95d10626187 | 3893 | /* Bit fields for CMU HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3894 | #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3895 | #define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3896 | #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3897 | #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ |
AnnaBridge | 170:e95d10626187 | 3898 | #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ |
AnnaBridge | 170:e95d10626187 | 3899 | #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3900 | #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3901 | #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3902 | #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ |
AnnaBridge | 170:e95d10626187 | 3903 | #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ |
AnnaBridge | 170:e95d10626187 | 3904 | #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3905 | #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3906 | #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3907 | #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ |
AnnaBridge | 170:e95d10626187 | 3908 | #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ |
AnnaBridge | 170:e95d10626187 | 3909 | #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3910 | #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3911 | #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3912 | #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ |
AnnaBridge | 170:e95d10626187 | 3913 | #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ |
AnnaBridge | 170:e95d10626187 | 3914 | #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3915 | #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3916 | #define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3917 | #define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ |
AnnaBridge | 170:e95d10626187 | 3918 | #define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ |
AnnaBridge | 170:e95d10626187 | 3919 | #define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3920 | #define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3921 | #define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3922 | #define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ |
AnnaBridge | 170:e95d10626187 | 3923 | #define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ |
AnnaBridge | 170:e95d10626187 | 3924 | #define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3925 | #define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3926 | #define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3927 | #define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ |
AnnaBridge | 170:e95d10626187 | 3928 | #define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ |
AnnaBridge | 170:e95d10626187 | 3929 | #define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3930 | #define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3931 | #define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3932 | #define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ |
AnnaBridge | 170:e95d10626187 | 3933 | #define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ |
AnnaBridge | 170:e95d10626187 | 3934 | #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3935 | #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3936 | #define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3937 | #define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ |
AnnaBridge | 170:e95d10626187 | 3938 | #define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ |
AnnaBridge | 170:e95d10626187 | 3939 | #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3940 | #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3941 | #define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3942 | #define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ |
AnnaBridge | 170:e95d10626187 | 3943 | #define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ |
AnnaBridge | 170:e95d10626187 | 3944 | #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3945 | #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3946 | #define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3947 | #define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ |
AnnaBridge | 170:e95d10626187 | 3948 | #define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ |
AnnaBridge | 170:e95d10626187 | 3949 | #define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3950 | #define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3951 | #define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3952 | #define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ |
AnnaBridge | 170:e95d10626187 | 3953 | #define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ |
AnnaBridge | 170:e95d10626187 | 3954 | #define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3955 | #define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3956 | #define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3957 | #define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ |
AnnaBridge | 170:e95d10626187 | 3958 | #define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ |
AnnaBridge | 170:e95d10626187 | 3959 | #define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3960 | #define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3961 | #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3962 | #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ |
AnnaBridge | 170:e95d10626187 | 3963 | #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ |
AnnaBridge | 170:e95d10626187 | 3964 | #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3965 | #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3966 | #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3967 | #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ |
AnnaBridge | 170:e95d10626187 | 3968 | #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ |
AnnaBridge | 170:e95d10626187 | 3969 | #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3970 | #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3971 | #define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3972 | #define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ |
AnnaBridge | 170:e95d10626187 | 3973 | #define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ |
AnnaBridge | 170:e95d10626187 | 3974 | #define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3975 | #define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3976 | #define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3977 | #define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ |
AnnaBridge | 170:e95d10626187 | 3978 | #define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ |
AnnaBridge | 170:e95d10626187 | 3979 | #define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3980 | #define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3981 | #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3982 | #define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ |
AnnaBridge | 170:e95d10626187 | 3983 | #define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ |
AnnaBridge | 170:e95d10626187 | 3984 | #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3985 | #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3986 | #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3987 | #define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ |
AnnaBridge | 170:e95d10626187 | 3988 | #define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ |
AnnaBridge | 170:e95d10626187 | 3989 | #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3990 | #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3991 | #define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3992 | #define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ |
AnnaBridge | 170:e95d10626187 | 3993 | #define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ |
AnnaBridge | 170:e95d10626187 | 3994 | #define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3995 | #define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 3996 | #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 3997 | #define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ |
AnnaBridge | 170:e95d10626187 | 3998 | #define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ |
AnnaBridge | 170:e95d10626187 | 3999 | #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4000 | #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4001 | #define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4002 | #define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ |
AnnaBridge | 170:e95d10626187 | 4003 | #define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ |
AnnaBridge | 170:e95d10626187 | 4004 | #define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4005 | #define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4006 | #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CryoTimer Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4007 | #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ |
AnnaBridge | 170:e95d10626187 | 4008 | #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ |
AnnaBridge | 170:e95d10626187 | 4009 | #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4010 | #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4011 | #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4012 | #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ |
AnnaBridge | 170:e95d10626187 | 4013 | #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ |
AnnaBridge | 170:e95d10626187 | 4014 | #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4015 | #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4016 | #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4017 | #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ |
AnnaBridge | 170:e95d10626187 | 4018 | #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ |
AnnaBridge | 170:e95d10626187 | 4019 | #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4020 | #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4021 | |
AnnaBridge | 170:e95d10626187 | 4022 | /* Bit fields for CMU HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4023 | #define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4024 | #define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4025 | #define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4026 | #define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4027 | #define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4028 | #define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4029 | #define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4030 | #define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4031 | #define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4032 | #define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4033 | #define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4034 | #define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4035 | #define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4036 | #define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ |
AnnaBridge | 170:e95d10626187 | 4037 | #define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ |
AnnaBridge | 170:e95d10626187 | 4038 | #define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4039 | #define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4040 | #define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4041 | #define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ |
AnnaBridge | 170:e95d10626187 | 4042 | #define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ |
AnnaBridge | 170:e95d10626187 | 4043 | #define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4044 | #define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4045 | #define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4046 | #define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ |
AnnaBridge | 170:e95d10626187 | 4047 | #define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ |
AnnaBridge | 170:e95d10626187 | 4048 | #define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4049 | #define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4050 | #define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4051 | #define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ |
AnnaBridge | 170:e95d10626187 | 4052 | #define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ |
AnnaBridge | 170:e95d10626187 | 4053 | #define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4054 | #define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4055 | #define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4056 | #define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ |
AnnaBridge | 170:e95d10626187 | 4057 | #define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ |
AnnaBridge | 170:e95d10626187 | 4058 | #define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4059 | #define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4060 | #define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4061 | #define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ |
AnnaBridge | 170:e95d10626187 | 4062 | #define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ |
AnnaBridge | 170:e95d10626187 | 4063 | #define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4064 | #define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4065 | #define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4066 | #define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ |
AnnaBridge | 170:e95d10626187 | 4067 | #define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ |
AnnaBridge | 170:e95d10626187 | 4068 | #define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4069 | #define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4070 | #define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4071 | #define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4072 | #define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4073 | #define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4074 | #define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ |
AnnaBridge | 170:e95d10626187 | 4075 | |
AnnaBridge | 170:e95d10626187 | 4076 | /* Bit fields for CMU LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4077 | #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4078 | #define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4079 | #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4080 | #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4081 | #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4082 | #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4083 | #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4084 | #define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4085 | #define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4086 | #define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4087 | #define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4088 | #define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4089 | #define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4090 | #define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 4091 | #define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 4092 | #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4093 | #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4094 | #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4095 | #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 4096 | #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 4097 | #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4098 | #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4099 | #define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4100 | #define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 4101 | #define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 4102 | #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4103 | #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4104 | |
AnnaBridge | 170:e95d10626187 | 4105 | /* Bit fields for CMU LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4106 | #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4107 | #define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4108 | #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4109 | #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 4110 | #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 4111 | #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4112 | #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4113 | #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4114 | #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 4115 | #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 4116 | #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4117 | #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4118 | #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4119 | #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ |
AnnaBridge | 170:e95d10626187 | 4120 | #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ |
AnnaBridge | 170:e95d10626187 | 4121 | #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4122 | #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4123 | #define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4124 | #define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4125 | #define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4126 | #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4127 | #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4128 | |
AnnaBridge | 170:e95d10626187 | 4129 | /* Bit fields for CMU LFCCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4130 | #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4131 | #define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4132 | |
AnnaBridge | 170:e95d10626187 | 4133 | /* Bit fields for CMU LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4134 | #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4135 | #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4136 | #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4137 | #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 4138 | #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 4139 | #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4140 | #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4141 | |
AnnaBridge | 170:e95d10626187 | 4142 | /* Bit fields for CMU HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4143 | #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4144 | #define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4145 | #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4146 | #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4147 | #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4148 | #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4149 | #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4150 | #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4151 | #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ |
AnnaBridge | 170:e95d10626187 | 4152 | #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ |
AnnaBridge | 170:e95d10626187 | 4153 | #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4154 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4155 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4156 | #define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4157 | #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4158 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4159 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4160 | #define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ |
AnnaBridge | 170:e95d10626187 | 4161 | |
AnnaBridge | 170:e95d10626187 | 4162 | /* Bit fields for CMU HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4163 | #define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4164 | #define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4165 | #define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4166 | #define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4167 | #define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4168 | #define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4169 | #define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4170 | #define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ |
AnnaBridge | 170:e95d10626187 | 4171 | |
AnnaBridge | 170:e95d10626187 | 4172 | /* Bit fields for CMU HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4173 | #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4174 | #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4175 | #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4176 | #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4177 | #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4178 | #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4179 | #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4180 | #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ |
AnnaBridge | 170:e95d10626187 | 4181 | |
AnnaBridge | 170:e95d10626187 | 4182 | /* Bit fields for CMU HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4183 | #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4184 | #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4185 | #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4186 | #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4187 | #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4188 | #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4189 | #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4190 | #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ |
AnnaBridge | 170:e95d10626187 | 4191 | |
AnnaBridge | 170:e95d10626187 | 4192 | /* Bit fields for CMU HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4193 | #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4194 | #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4195 | #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4196 | #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4197 | #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4198 | #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4199 | #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4200 | #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ |
AnnaBridge | 170:e95d10626187 | 4201 | |
AnnaBridge | 170:e95d10626187 | 4202 | /* Bit fields for CMU HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4203 | #define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4204 | #define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4205 | #define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4206 | #define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4207 | #define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4208 | #define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4209 | #define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4210 | #define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ |
AnnaBridge | 170:e95d10626187 | 4211 | |
AnnaBridge | 170:e95d10626187 | 4212 | /* Bit fields for CMU HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4213 | #define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4214 | #define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4215 | #define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4216 | #define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ |
AnnaBridge | 170:e95d10626187 | 4217 | #define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4218 | #define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4219 | #define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4220 | #define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ |
AnnaBridge | 170:e95d10626187 | 4221 | |
AnnaBridge | 170:e95d10626187 | 4222 | /* Bit fields for CMU LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4223 | #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4224 | #define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4225 | #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4226 | #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 4227 | #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4228 | #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4229 | #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4230 | #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4231 | #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4232 | #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4233 | #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4234 | #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4235 | #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4236 | #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4237 | #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4238 | #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4239 | #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4240 | #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4241 | #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4242 | #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4243 | #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4244 | #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4245 | #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4246 | #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4247 | #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4248 | #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4249 | #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4250 | #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4251 | #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4252 | #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4253 | #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4254 | #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4255 | #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4256 | #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4257 | #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4258 | #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4259 | #define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4260 | #define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 4261 | #define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4262 | #define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4263 | #define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4264 | #define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4265 | #define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4266 | #define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4267 | #define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4268 | #define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4269 | #define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4270 | #define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4271 | #define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4272 | #define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4273 | #define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4274 | #define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4275 | #define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4276 | #define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4277 | #define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4278 | #define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4279 | #define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4280 | #define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4281 | #define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4282 | #define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4283 | #define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4284 | #define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4285 | #define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4286 | #define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4287 | #define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4288 | #define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4289 | #define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4290 | #define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4291 | #define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4292 | #define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4293 | #define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 4294 | #define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 4295 | #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4296 | #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4297 | #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4298 | #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4299 | #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4300 | #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4301 | #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4302 | #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4303 | #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 4304 | #define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 4305 | #define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4306 | #define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4307 | #define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4308 | #define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4309 | #define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4310 | #define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4311 | #define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4312 | #define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4313 | #define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4314 | #define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4315 | #define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4316 | #define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4317 | #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4318 | #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4319 | #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4320 | #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4321 | #define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 4322 | #define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 4323 | #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4324 | #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4325 | #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4326 | #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4327 | #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4328 | #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4329 | #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4330 | #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4331 | #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4332 | #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4333 | #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4334 | #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4335 | #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4336 | #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4337 | #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4338 | #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4339 | #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4340 | #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4341 | #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4342 | #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4343 | #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4344 | #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4345 | #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4346 | #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4347 | #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4348 | #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4349 | #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4350 | #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4351 | #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4352 | #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4353 | #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4354 | #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4355 | |
AnnaBridge | 170:e95d10626187 | 4356 | /* Bit fields for CMU LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4357 | #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4358 | #define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4359 | #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 4360 | #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 4361 | #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4362 | #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4363 | #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4364 | #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4365 | #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4366 | #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4367 | #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4368 | #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4369 | #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 4370 | #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 4371 | #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4372 | #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4373 | #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4374 | #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4375 | #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4376 | #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4377 | #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4378 | #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4379 | #define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ |
AnnaBridge | 170:e95d10626187 | 4380 | #define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ |
AnnaBridge | 170:e95d10626187 | 4381 | #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4382 | #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4383 | #define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4384 | #define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 4385 | #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4386 | #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4387 | #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4388 | #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4389 | #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4390 | #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4391 | #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4392 | #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4393 | |
AnnaBridge | 170:e95d10626187 | 4394 | /* Bit fields for CMU LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4395 | #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4396 | #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4397 | #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 4398 | #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 4399 | #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4400 | #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4401 | #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4402 | #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4403 | #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4404 | #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4405 | |
AnnaBridge | 170:e95d10626187 | 4406 | /* Bit fields for CMU SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4407 | #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4408 | #define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4409 | #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4410 | #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4411 | #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4412 | #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4413 | #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4414 | #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4415 | #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4416 | #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4417 | #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4418 | #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4419 | #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4420 | #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4421 | #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4422 | #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4423 | #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4424 | #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4425 | #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4426 | #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4427 | #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4428 | #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4429 | #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4430 | #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4431 | #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4432 | #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4433 | #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4434 | #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4435 | #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4436 | #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ |
AnnaBridge | 170:e95d10626187 | 4437 | #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4438 | #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4439 | #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ |
AnnaBridge | 170:e95d10626187 | 4440 | #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4441 | #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ |
AnnaBridge | 170:e95d10626187 | 4442 | #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4443 | #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4444 | #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ |
AnnaBridge | 170:e95d10626187 | 4445 | #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4446 | #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4447 | #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4448 | #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4449 | #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ |
AnnaBridge | 170:e95d10626187 | 4450 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4451 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4452 | #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4453 | #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4454 | #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ |
AnnaBridge | 170:e95d10626187 | 4455 | #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4456 | #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4457 | #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4458 | #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4459 | #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ |
AnnaBridge | 170:e95d10626187 | 4460 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ |
AnnaBridge | 170:e95d10626187 | 4461 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ |
AnnaBridge | 170:e95d10626187 | 4462 | #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4463 | #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4464 | #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ |
AnnaBridge | 170:e95d10626187 | 4465 | #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ |
AnnaBridge | 170:e95d10626187 | 4466 | #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ |
AnnaBridge | 170:e95d10626187 | 4467 | #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4468 | #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4469 | #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ |
AnnaBridge | 170:e95d10626187 | 4470 | #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ |
AnnaBridge | 170:e95d10626187 | 4471 | #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ |
AnnaBridge | 170:e95d10626187 | 4472 | #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4473 | #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4474 | #define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ |
AnnaBridge | 170:e95d10626187 | 4475 | #define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4476 | #define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ |
AnnaBridge | 170:e95d10626187 | 4477 | #define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4478 | #define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ |
AnnaBridge | 170:e95d10626187 | 4479 | |
AnnaBridge | 170:e95d10626187 | 4480 | /* Bit fields for CMU FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4481 | #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4482 | #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4483 | #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
AnnaBridge | 170:e95d10626187 | 4484 | #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ |
AnnaBridge | 170:e95d10626187 | 4485 | #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ |
AnnaBridge | 170:e95d10626187 | 4486 | #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4487 | #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4488 | #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4489 | #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4490 | #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4491 | #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ |
AnnaBridge | 170:e95d10626187 | 4492 | |
AnnaBridge | 170:e95d10626187 | 4493 | /* Bit fields for CMU PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4494 | #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4495 | #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4496 | #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4497 | #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4498 | #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4499 | #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4500 | #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4501 | #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ |
AnnaBridge | 170:e95d10626187 | 4502 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4503 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4504 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4505 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4506 | #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4507 | #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4508 | #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4509 | #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4510 | #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4511 | #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4512 | #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4513 | #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4514 | #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4515 | #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ |
AnnaBridge | 170:e95d10626187 | 4516 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4517 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4518 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4519 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4520 | #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4521 | #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4522 | #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4523 | #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4524 | #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ |
AnnaBridge | 170:e95d10626187 | 4525 | #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4526 | #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ |
AnnaBridge | 170:e95d10626187 | 4527 | #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4528 | #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4529 | #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ |
AnnaBridge | 170:e95d10626187 | 4530 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4531 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4532 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4533 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4534 | #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4535 | #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4536 | #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4537 | #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ |
AnnaBridge | 170:e95d10626187 | 4538 | |
AnnaBridge | 170:e95d10626187 | 4539 | /* Bit fields for CMU ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4540 | #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4541 | #define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4542 | #define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 4543 | #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 4544 | #define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4545 | #define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4546 | #define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4547 | #define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4548 | #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4549 | #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4550 | #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4551 | #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4552 | #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4553 | #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4554 | #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4555 | #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4556 | #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4557 | #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4558 | #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4559 | #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4560 | #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4561 | #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ |
AnnaBridge | 170:e95d10626187 | 4562 | #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ |
AnnaBridge | 170:e95d10626187 | 4563 | #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4564 | #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4565 | #define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 4566 | #define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ |
AnnaBridge | 170:e95d10626187 | 4567 | #define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4568 | #define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4569 | #define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4570 | #define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4571 | #define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4572 | #define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4573 | #define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4574 | #define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4575 | #define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4576 | #define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4577 | #define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4578 | #define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4579 | #define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4580 | #define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4581 | #define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4582 | #define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4583 | #define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert clock selected by ADC1CLKSEL */ |
AnnaBridge | 170:e95d10626187 | 4584 | #define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ |
AnnaBridge | 170:e95d10626187 | 4585 | #define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ |
AnnaBridge | 170:e95d10626187 | 4586 | #define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4587 | #define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ |
AnnaBridge | 170:e95d10626187 | 4588 | |
AnnaBridge | 170:e95d10626187 | 4589 | /* Bit fields for CMU ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4590 | #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4591 | #define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4592 | #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4593 | #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ |
AnnaBridge | 170:e95d10626187 | 4594 | #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ |
AnnaBridge | 170:e95d10626187 | 4595 | #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4596 | #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4597 | #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4598 | #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ |
AnnaBridge | 170:e95d10626187 | 4599 | #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ |
AnnaBridge | 170:e95d10626187 | 4600 | #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4601 | #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4602 | #define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4603 | #define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ |
AnnaBridge | 170:e95d10626187 | 4604 | #define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ |
AnnaBridge | 170:e95d10626187 | 4605 | #define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4606 | #define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4607 | #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4608 | #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ |
AnnaBridge | 170:e95d10626187 | 4609 | #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ |
AnnaBridge | 170:e95d10626187 | 4610 | #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4611 | #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4612 | |
AnnaBridge | 170:e95d10626187 | 4613 | /* Bit fields for CMU ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4614 | #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4615 | #define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4616 | #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ |
AnnaBridge | 170:e95d10626187 | 4617 | #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ |
AnnaBridge | 170:e95d10626187 | 4618 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4619 | #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4620 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4621 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4622 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4623 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4624 | #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4625 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4626 | #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4627 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4628 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4629 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4630 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4631 | #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4632 | #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ |
AnnaBridge | 170:e95d10626187 | 4633 | #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ |
AnnaBridge | 170:e95d10626187 | 4634 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4635 | #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4636 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4637 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4638 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4639 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4640 | #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4641 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4642 | #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4643 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4644 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4645 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4646 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4647 | #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4648 | #define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ |
AnnaBridge | 170:e95d10626187 | 4649 | #define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ |
AnnaBridge | 170:e95d10626187 | 4650 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4651 | #define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4652 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4653 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4654 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4655 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4656 | #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4657 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4658 | #define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4659 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4660 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4661 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4662 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4663 | #define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 4664 | |
AnnaBridge | 170:e95d10626187 | 4665 | /* Bit fields for CMU ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4666 | #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4667 | #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4668 | #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ |
AnnaBridge | 170:e95d10626187 | 4669 | #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ |
AnnaBridge | 170:e95d10626187 | 4670 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4671 | #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4672 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4673 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4674 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4675 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4676 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4677 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4678 | #define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4679 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4680 | #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4681 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4682 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4683 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4684 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4685 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4686 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4687 | #define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 4688 | |
AnnaBridge | 170:e95d10626187 | 4689 | /* Bit fields for CMU LOCK */ |
AnnaBridge | 170:e95d10626187 | 4690 | #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4691 | #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4692 | #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 4693 | #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ |
AnnaBridge | 170:e95d10626187 | 4694 | #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4695 | #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4696 | #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4697 | #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4698 | #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4699 | #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4700 | #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4701 | #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4702 | #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4703 | #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ |
AnnaBridge | 170:e95d10626187 | 4704 | |
AnnaBridge | 170:e95d10626187 | 4705 | /* Bit fields for CMU HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4706 | #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4707 | #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4708 | #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ |
AnnaBridge | 170:e95d10626187 | 4709 | #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ |
AnnaBridge | 170:e95d10626187 | 4710 | #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4711 | #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4712 | #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ |
AnnaBridge | 170:e95d10626187 | 4713 | #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ |
AnnaBridge | 170:e95d10626187 | 4714 | #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4715 | #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ |
AnnaBridge | 170:e95d10626187 | 4716 | |
AnnaBridge | 170:e95d10626187 | 4717 | /* Bit fields for CMU USBCTRL */ |
AnnaBridge | 170:e95d10626187 | 4718 | #define _CMU_USBCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCTRL */ |
AnnaBridge | 170:e95d10626187 | 4719 | #define _CMU_USBCTRL_MASK 0x00000000UL /**< Mask for CMU_USBCTRL */ |
AnnaBridge | 170:e95d10626187 | 4720 | |
AnnaBridge | 170:e95d10626187 | 4721 | /* Bit fields for CMU USBCRCTRL */ |
AnnaBridge | 170:e95d10626187 | 4722 | #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ |
AnnaBridge | 170:e95d10626187 | 4723 | #define _CMU_USBCRCTRL_MASK 0x00000000UL /**< Mask for CMU_USBCRCTRL */ |
AnnaBridge | 170:e95d10626187 | 4724 | |
AnnaBridge | 170:e95d10626187 | 4725 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 4726 | /** @} End of group EFM32GG11B520F2048IQ64_CMU */ |
AnnaBridge | 170:e95d10626187 | 4727 | |
AnnaBridge | 170:e95d10626187 | 4728 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 4729 | * @addtogroup EFM32GG11B520F2048IQ64_PRS |
AnnaBridge | 170:e95d10626187 | 4730 | * @{ |
AnnaBridge | 170:e95d10626187 | 4731 | * @defgroup EFM32GG11B520F2048IQ64_PRS_BitFields PRS Bit Fields |
AnnaBridge | 170:e95d10626187 | 4732 | * @{ |
AnnaBridge | 170:e95d10626187 | 4733 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 4734 | |
AnnaBridge | 170:e95d10626187 | 4735 | /* Bit fields for PRS SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4736 | #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4737 | #define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4738 | #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4739 | #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ |
AnnaBridge | 170:e95d10626187 | 4740 | #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ |
AnnaBridge | 170:e95d10626187 | 4741 | #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4742 | #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4743 | #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4744 | #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ |
AnnaBridge | 170:e95d10626187 | 4745 | #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ |
AnnaBridge | 170:e95d10626187 | 4746 | #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4747 | #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4748 | #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4749 | #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ |
AnnaBridge | 170:e95d10626187 | 4750 | #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ |
AnnaBridge | 170:e95d10626187 | 4751 | #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4752 | #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4753 | #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4754 | #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ |
AnnaBridge | 170:e95d10626187 | 4755 | #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ |
AnnaBridge | 170:e95d10626187 | 4756 | #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4757 | #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4758 | #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4759 | #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ |
AnnaBridge | 170:e95d10626187 | 4760 | #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ |
AnnaBridge | 170:e95d10626187 | 4761 | #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4762 | #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4763 | #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4764 | #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ |
AnnaBridge | 170:e95d10626187 | 4765 | #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ |
AnnaBridge | 170:e95d10626187 | 4766 | #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4767 | #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4768 | #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4769 | #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ |
AnnaBridge | 170:e95d10626187 | 4770 | #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ |
AnnaBridge | 170:e95d10626187 | 4771 | #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4772 | #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4773 | #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4774 | #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ |
AnnaBridge | 170:e95d10626187 | 4775 | #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ |
AnnaBridge | 170:e95d10626187 | 4776 | #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4777 | #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4778 | #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4779 | #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ |
AnnaBridge | 170:e95d10626187 | 4780 | #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ |
AnnaBridge | 170:e95d10626187 | 4781 | #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4782 | #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4783 | #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4784 | #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ |
AnnaBridge | 170:e95d10626187 | 4785 | #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ |
AnnaBridge | 170:e95d10626187 | 4786 | #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4787 | #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4788 | #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4789 | #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ |
AnnaBridge | 170:e95d10626187 | 4790 | #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ |
AnnaBridge | 170:e95d10626187 | 4791 | #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4792 | #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4793 | #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4794 | #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ |
AnnaBridge | 170:e95d10626187 | 4795 | #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ |
AnnaBridge | 170:e95d10626187 | 4796 | #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4797 | #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4798 | #define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4799 | #define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ |
AnnaBridge | 170:e95d10626187 | 4800 | #define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ |
AnnaBridge | 170:e95d10626187 | 4801 | #define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4802 | #define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4803 | #define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4804 | #define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ |
AnnaBridge | 170:e95d10626187 | 4805 | #define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ |
AnnaBridge | 170:e95d10626187 | 4806 | #define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4807 | #define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4808 | #define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4809 | #define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ |
AnnaBridge | 170:e95d10626187 | 4810 | #define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ |
AnnaBridge | 170:e95d10626187 | 4811 | #define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4812 | #define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4813 | #define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4814 | #define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ |
AnnaBridge | 170:e95d10626187 | 4815 | #define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ |
AnnaBridge | 170:e95d10626187 | 4816 | #define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4817 | #define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4818 | #define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4819 | #define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ |
AnnaBridge | 170:e95d10626187 | 4820 | #define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ |
AnnaBridge | 170:e95d10626187 | 4821 | #define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4822 | #define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4823 | #define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4824 | #define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ |
AnnaBridge | 170:e95d10626187 | 4825 | #define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ |
AnnaBridge | 170:e95d10626187 | 4826 | #define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4827 | #define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4828 | #define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4829 | #define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ |
AnnaBridge | 170:e95d10626187 | 4830 | #define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ |
AnnaBridge | 170:e95d10626187 | 4831 | #define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4832 | #define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4833 | #define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4834 | #define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ |
AnnaBridge | 170:e95d10626187 | 4835 | #define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ |
AnnaBridge | 170:e95d10626187 | 4836 | #define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4837 | #define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4838 | #define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4839 | #define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ |
AnnaBridge | 170:e95d10626187 | 4840 | #define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ |
AnnaBridge | 170:e95d10626187 | 4841 | #define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4842 | #define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4843 | #define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4844 | #define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ |
AnnaBridge | 170:e95d10626187 | 4845 | #define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ |
AnnaBridge | 170:e95d10626187 | 4846 | #define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4847 | #define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4848 | #define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4849 | #define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ |
AnnaBridge | 170:e95d10626187 | 4850 | #define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ |
AnnaBridge | 170:e95d10626187 | 4851 | #define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4852 | #define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4853 | #define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ |
AnnaBridge | 170:e95d10626187 | 4854 | #define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ |
AnnaBridge | 170:e95d10626187 | 4855 | #define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ |
AnnaBridge | 170:e95d10626187 | 4856 | #define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4857 | #define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
AnnaBridge | 170:e95d10626187 | 4858 | |
AnnaBridge | 170:e95d10626187 | 4859 | /* Bit fields for PRS SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4860 | #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4861 | #define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4862 | #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4863 | #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4864 | #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4865 | #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4866 | #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4867 | #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4868 | #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4869 | #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4870 | #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4871 | #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4872 | #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4873 | #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4874 | #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4875 | #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4876 | #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4877 | #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4878 | #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4879 | #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4880 | #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4881 | #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4882 | #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4883 | #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4884 | #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4885 | #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4886 | #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4887 | #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4888 | #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4889 | #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4890 | #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4891 | #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4892 | #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4893 | #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4894 | #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4895 | #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4896 | #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4897 | #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4898 | #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4899 | #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4900 | #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4901 | #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4902 | #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4903 | #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4904 | #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4905 | #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4906 | #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4907 | #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4908 | #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4909 | #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4910 | #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4911 | #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4912 | #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4913 | #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4914 | #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4915 | #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4916 | #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4917 | #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4918 | #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4919 | #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4920 | #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4921 | #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4922 | #define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4923 | #define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4924 | #define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4925 | #define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4926 | #define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4927 | #define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4928 | #define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4929 | #define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4930 | #define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4931 | #define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4932 | #define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4933 | #define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4934 | #define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4935 | #define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4936 | #define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4937 | #define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4938 | #define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4939 | #define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4940 | #define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4941 | #define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4942 | #define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4943 | #define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4944 | #define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4945 | #define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4946 | #define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4947 | #define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4948 | #define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4949 | #define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4950 | #define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4951 | #define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4952 | #define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4953 | #define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4954 | #define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4955 | #define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4956 | #define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4957 | #define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4958 | #define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4959 | #define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4960 | #define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4961 | #define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4962 | #define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4963 | #define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4964 | #define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4965 | #define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4966 | #define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4967 | #define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4968 | #define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4969 | #define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4970 | #define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4971 | #define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4972 | #define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4973 | #define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4974 | #define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4975 | #define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4976 | #define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4977 | #define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ |
AnnaBridge | 170:e95d10626187 | 4978 | #define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4979 | #define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ |
AnnaBridge | 170:e95d10626187 | 4980 | #define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4981 | #define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
AnnaBridge | 170:e95d10626187 | 4982 | |
AnnaBridge | 170:e95d10626187 | 4983 | /* Bit fields for PRS ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4984 | #define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4985 | #define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4986 | #define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4987 | #define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ |
AnnaBridge | 170:e95d10626187 | 4988 | #define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ |
AnnaBridge | 170:e95d10626187 | 4989 | #define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4990 | #define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4991 | #define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4992 | #define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ |
AnnaBridge | 170:e95d10626187 | 4993 | #define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ |
AnnaBridge | 170:e95d10626187 | 4994 | #define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4995 | #define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 4996 | #define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 4997 | #define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ |
AnnaBridge | 170:e95d10626187 | 4998 | #define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ |
AnnaBridge | 170:e95d10626187 | 4999 | #define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5000 | #define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5001 | #define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5002 | #define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ |
AnnaBridge | 170:e95d10626187 | 5003 | #define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ |
AnnaBridge | 170:e95d10626187 | 5004 | #define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5005 | #define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5006 | #define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5007 | #define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ |
AnnaBridge | 170:e95d10626187 | 5008 | #define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ |
AnnaBridge | 170:e95d10626187 | 5009 | #define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5010 | #define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5011 | #define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5012 | #define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ |
AnnaBridge | 170:e95d10626187 | 5013 | #define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ |
AnnaBridge | 170:e95d10626187 | 5014 | #define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5015 | #define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5016 | #define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5017 | #define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ |
AnnaBridge | 170:e95d10626187 | 5018 | #define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ |
AnnaBridge | 170:e95d10626187 | 5019 | #define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5020 | #define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5021 | #define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5022 | #define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ |
AnnaBridge | 170:e95d10626187 | 5023 | #define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ |
AnnaBridge | 170:e95d10626187 | 5024 | #define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5025 | #define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5026 | #define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5027 | #define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ |
AnnaBridge | 170:e95d10626187 | 5028 | #define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ |
AnnaBridge | 170:e95d10626187 | 5029 | #define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5030 | #define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5031 | #define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5032 | #define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ |
AnnaBridge | 170:e95d10626187 | 5033 | #define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ |
AnnaBridge | 170:e95d10626187 | 5034 | #define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5035 | #define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5036 | #define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5037 | #define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ |
AnnaBridge | 170:e95d10626187 | 5038 | #define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ |
AnnaBridge | 170:e95d10626187 | 5039 | #define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5040 | #define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5041 | #define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5042 | #define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ |
AnnaBridge | 170:e95d10626187 | 5043 | #define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ |
AnnaBridge | 170:e95d10626187 | 5044 | #define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5045 | #define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5046 | #define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5047 | #define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ |
AnnaBridge | 170:e95d10626187 | 5048 | #define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ |
AnnaBridge | 170:e95d10626187 | 5049 | #define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5050 | #define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5051 | #define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5052 | #define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ |
AnnaBridge | 170:e95d10626187 | 5053 | #define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ |
AnnaBridge | 170:e95d10626187 | 5054 | #define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5055 | #define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5056 | #define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5057 | #define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ |
AnnaBridge | 170:e95d10626187 | 5058 | #define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ |
AnnaBridge | 170:e95d10626187 | 5059 | #define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5060 | #define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5061 | #define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5062 | #define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ |
AnnaBridge | 170:e95d10626187 | 5063 | #define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ |
AnnaBridge | 170:e95d10626187 | 5064 | #define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5065 | #define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5066 | #define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5067 | #define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ |
AnnaBridge | 170:e95d10626187 | 5068 | #define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ |
AnnaBridge | 170:e95d10626187 | 5069 | #define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5070 | #define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5071 | #define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5072 | #define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ |
AnnaBridge | 170:e95d10626187 | 5073 | #define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ |
AnnaBridge | 170:e95d10626187 | 5074 | #define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5075 | #define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5076 | #define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5077 | #define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ |
AnnaBridge | 170:e95d10626187 | 5078 | #define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ |
AnnaBridge | 170:e95d10626187 | 5079 | #define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5080 | #define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5081 | #define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5082 | #define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ |
AnnaBridge | 170:e95d10626187 | 5083 | #define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ |
AnnaBridge | 170:e95d10626187 | 5084 | #define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5085 | #define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5086 | #define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5087 | #define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ |
AnnaBridge | 170:e95d10626187 | 5088 | #define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ |
AnnaBridge | 170:e95d10626187 | 5089 | #define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5090 | #define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5091 | #define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5092 | #define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ |
AnnaBridge | 170:e95d10626187 | 5093 | #define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ |
AnnaBridge | 170:e95d10626187 | 5094 | #define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5095 | #define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5096 | #define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5097 | #define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ |
AnnaBridge | 170:e95d10626187 | 5098 | #define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ |
AnnaBridge | 170:e95d10626187 | 5099 | #define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5100 | #define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5101 | #define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ |
AnnaBridge | 170:e95d10626187 | 5102 | #define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ |
AnnaBridge | 170:e95d10626187 | 5103 | #define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ |
AnnaBridge | 170:e95d10626187 | 5104 | #define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5105 | #define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ |
AnnaBridge | 170:e95d10626187 | 5106 | |
AnnaBridge | 170:e95d10626187 | 5107 | /* Bit fields for PRS ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5108 | #define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5109 | #define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5110 | #define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ |
AnnaBridge | 170:e95d10626187 | 5111 | #define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ |
AnnaBridge | 170:e95d10626187 | 5112 | #define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5113 | #define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5114 | #define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5115 | #define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5116 | #define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5117 | #define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5118 | #define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5119 | #define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5120 | #define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5121 | #define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5122 | #define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ |
AnnaBridge | 170:e95d10626187 | 5123 | #define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ |
AnnaBridge | 170:e95d10626187 | 5124 | #define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5125 | #define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5126 | #define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5127 | #define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5128 | #define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5129 | #define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5130 | #define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5131 | #define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5132 | #define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5133 | #define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5134 | #define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ |
AnnaBridge | 170:e95d10626187 | 5135 | #define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ |
AnnaBridge | 170:e95d10626187 | 5136 | #define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5137 | #define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5138 | #define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5139 | #define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5140 | #define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5141 | #define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5142 | #define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5143 | #define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5144 | #define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5145 | #define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5146 | #define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ |
AnnaBridge | 170:e95d10626187 | 5147 | #define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ |
AnnaBridge | 170:e95d10626187 | 5148 | #define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5149 | #define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5150 | #define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5151 | #define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5152 | #define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5153 | #define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5154 | #define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5155 | #define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5156 | #define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5157 | #define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ |
AnnaBridge | 170:e95d10626187 | 5158 | |
AnnaBridge | 170:e95d10626187 | 5159 | /* Bit fields for PRS ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5160 | #define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5161 | #define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5162 | #define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ |
AnnaBridge | 170:e95d10626187 | 5163 | #define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ |
AnnaBridge | 170:e95d10626187 | 5164 | #define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5165 | #define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5166 | #define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5167 | #define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5168 | #define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5169 | #define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5170 | #define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5171 | #define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5172 | #define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ |
AnnaBridge | 170:e95d10626187 | 5173 | #define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ |
AnnaBridge | 170:e95d10626187 | 5174 | #define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5175 | #define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5176 | #define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5177 | #define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5178 | #define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5179 | #define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5180 | #define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5181 | #define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5182 | #define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ |
AnnaBridge | 170:e95d10626187 | 5183 | #define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ |
AnnaBridge | 170:e95d10626187 | 5184 | #define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5185 | #define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5186 | #define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5187 | #define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5188 | #define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5189 | #define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5190 | #define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5191 | #define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5192 | #define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ |
AnnaBridge | 170:e95d10626187 | 5193 | #define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ |
AnnaBridge | 170:e95d10626187 | 5194 | #define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5195 | #define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5196 | #define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5197 | #define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5198 | #define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5199 | #define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5200 | #define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5201 | #define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ |
AnnaBridge | 170:e95d10626187 | 5202 | |
AnnaBridge | 170:e95d10626187 | 5203 | /* Bit fields for PRS ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5204 | #define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5205 | #define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5206 | #define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ |
AnnaBridge | 170:e95d10626187 | 5207 | #define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ |
AnnaBridge | 170:e95d10626187 | 5208 | #define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5209 | #define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5210 | #define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5211 | #define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5212 | #define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5213 | #define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5214 | #define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5215 | #define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5216 | #define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ |
AnnaBridge | 170:e95d10626187 | 5217 | #define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ |
AnnaBridge | 170:e95d10626187 | 5218 | #define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5219 | #define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5220 | #define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5221 | #define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5222 | #define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5223 | #define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5224 | #define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5225 | #define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5226 | #define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ |
AnnaBridge | 170:e95d10626187 | 5227 | #define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ |
AnnaBridge | 170:e95d10626187 | 5228 | #define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5229 | #define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5230 | #define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5231 | #define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5232 | #define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5233 | #define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5234 | #define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5235 | #define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5236 | #define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ |
AnnaBridge | 170:e95d10626187 | 5237 | #define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ |
AnnaBridge | 170:e95d10626187 | 5238 | #define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5239 | #define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5240 | #define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5241 | #define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5242 | #define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5243 | #define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5244 | #define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5245 | #define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ |
AnnaBridge | 170:e95d10626187 | 5246 | |
AnnaBridge | 170:e95d10626187 | 5247 | /* Bit fields for PRS ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5248 | #define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5249 | #define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5250 | #define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ |
AnnaBridge | 170:e95d10626187 | 5251 | #define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ |
AnnaBridge | 170:e95d10626187 | 5252 | #define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5253 | #define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5254 | #define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5255 | #define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5256 | #define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5257 | #define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5258 | #define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5259 | #define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5260 | #define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ |
AnnaBridge | 170:e95d10626187 | 5261 | #define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ |
AnnaBridge | 170:e95d10626187 | 5262 | #define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5263 | #define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5264 | #define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5265 | #define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5266 | #define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5267 | #define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5268 | #define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5269 | #define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5270 | #define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ |
AnnaBridge | 170:e95d10626187 | 5271 | #define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ |
AnnaBridge | 170:e95d10626187 | 5272 | #define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5273 | #define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5274 | #define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5275 | #define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5276 | #define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5277 | #define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5278 | #define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5279 | #define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5280 | #define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ |
AnnaBridge | 170:e95d10626187 | 5281 | #define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ |
AnnaBridge | 170:e95d10626187 | 5282 | #define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5283 | #define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5284 | #define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5285 | #define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5286 | #define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5287 | #define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5288 | #define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5289 | #define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ |
AnnaBridge | 170:e95d10626187 | 5290 | |
AnnaBridge | 170:e95d10626187 | 5291 | /* Bit fields for PRS ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5292 | #define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5293 | #define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5294 | #define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ |
AnnaBridge | 170:e95d10626187 | 5295 | #define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ |
AnnaBridge | 170:e95d10626187 | 5296 | #define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5297 | #define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5298 | #define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5299 | #define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5300 | #define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5301 | #define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5302 | #define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5303 | #define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5304 | #define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ |
AnnaBridge | 170:e95d10626187 | 5305 | #define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ |
AnnaBridge | 170:e95d10626187 | 5306 | #define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5307 | #define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5308 | #define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5309 | #define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5310 | #define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5311 | #define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5312 | #define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5313 | #define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5314 | #define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ |
AnnaBridge | 170:e95d10626187 | 5315 | #define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ |
AnnaBridge | 170:e95d10626187 | 5316 | #define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5317 | #define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5318 | #define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5319 | #define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5320 | #define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5321 | #define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5322 | #define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5323 | #define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5324 | #define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ |
AnnaBridge | 170:e95d10626187 | 5325 | #define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ |
AnnaBridge | 170:e95d10626187 | 5326 | #define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5327 | #define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5328 | #define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5329 | #define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5330 | #define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5331 | #define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5332 | #define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5333 | #define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ |
AnnaBridge | 170:e95d10626187 | 5334 | |
AnnaBridge | 170:e95d10626187 | 5335 | /* Bit fields for PRS ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5336 | #define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5337 | #define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5338 | #define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ |
AnnaBridge | 170:e95d10626187 | 5339 | #define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ |
AnnaBridge | 170:e95d10626187 | 5340 | #define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5341 | #define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5342 | #define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5343 | #define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5344 | #define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5345 | #define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5346 | #define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5347 | #define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5348 | #define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ |
AnnaBridge | 170:e95d10626187 | 5349 | #define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ |
AnnaBridge | 170:e95d10626187 | 5350 | #define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5351 | #define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5352 | #define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5353 | #define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5354 | #define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5355 | #define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5356 | #define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5357 | #define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5358 | #define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ |
AnnaBridge | 170:e95d10626187 | 5359 | #define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ |
AnnaBridge | 170:e95d10626187 | 5360 | #define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5361 | #define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5362 | #define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5363 | #define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5364 | #define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5365 | #define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5366 | #define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5367 | #define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5368 | #define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ |
AnnaBridge | 170:e95d10626187 | 5369 | #define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ |
AnnaBridge | 170:e95d10626187 | 5370 | #define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5371 | #define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5372 | #define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5373 | #define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5374 | #define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5375 | #define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5376 | #define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5377 | #define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ |
AnnaBridge | 170:e95d10626187 | 5378 | |
AnnaBridge | 170:e95d10626187 | 5379 | /* Bit fields for PRS CTRL */ |
AnnaBridge | 170:e95d10626187 | 5380 | #define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5381 | #define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5382 | #define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ |
AnnaBridge | 170:e95d10626187 | 5383 | #define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ |
AnnaBridge | 170:e95d10626187 | 5384 | #define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ |
AnnaBridge | 170:e95d10626187 | 5385 | #define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5386 | #define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5387 | #define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5388 | #define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5389 | #define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5390 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5391 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5392 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5393 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5394 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5395 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5396 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5397 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5398 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5399 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5400 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5401 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5402 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5403 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5404 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5405 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5406 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5407 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5408 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5409 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5410 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5411 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5412 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5413 | #define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5414 | #define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5415 | #define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5416 | #define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5417 | #define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5418 | #define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5419 | #define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5420 | #define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5421 | #define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5422 | #define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5423 | #define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5424 | #define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5425 | #define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5426 | #define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5427 | #define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5428 | #define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5429 | #define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5430 | #define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5431 | #define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5432 | #define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5433 | #define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5434 | #define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5435 | #define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5436 | #define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5437 | #define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5438 | #define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5439 | |
AnnaBridge | 170:e95d10626187 | 5440 | /* Bit fields for PRS DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5441 | #define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5442 | #define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5443 | #define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5444 | #define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5445 | #define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5446 | #define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5447 | #define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5448 | #define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5449 | #define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5450 | #define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5451 | #define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5452 | #define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5453 | #define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5454 | #define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5455 | #define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5456 | #define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5457 | #define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5458 | #define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5459 | #define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5460 | #define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5461 | #define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5462 | #define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5463 | #define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5464 | #define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5465 | #define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5466 | #define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5467 | #define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5468 | #define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5469 | #define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5470 | #define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5471 | #define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5472 | #define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5473 | #define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5474 | #define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5475 | #define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5476 | #define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5477 | #define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5478 | #define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5479 | #define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5480 | #define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5481 | #define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5482 | #define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5483 | #define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5484 | #define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5485 | #define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5486 | #define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5487 | #define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5488 | #define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5489 | #define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5490 | #define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5491 | #define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5492 | #define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5493 | #define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5494 | #define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ |
AnnaBridge | 170:e95d10626187 | 5495 | |
AnnaBridge | 170:e95d10626187 | 5496 | /* Bit fields for PRS DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5497 | #define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5498 | #define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5499 | #define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5500 | #define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ |
AnnaBridge | 170:e95d10626187 | 5501 | #define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5502 | #define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5503 | #define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5504 | #define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5505 | #define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5506 | #define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5507 | #define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5508 | #define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5509 | #define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5510 | #define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5511 | #define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5512 | #define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5513 | #define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5514 | #define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5515 | #define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5516 | #define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5517 | #define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5518 | #define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5519 | #define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5520 | #define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5521 | #define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5522 | #define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5523 | #define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5524 | #define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5525 | #define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5526 | #define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5527 | #define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5528 | #define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5529 | #define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5530 | #define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5531 | #define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5532 | #define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5533 | #define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5534 | #define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5535 | #define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5536 | #define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5537 | #define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5538 | #define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5539 | #define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5540 | #define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5541 | #define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5542 | #define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5543 | #define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5544 | #define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5545 | #define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5546 | #define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5547 | #define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5548 | #define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5549 | #define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5550 | #define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ |
AnnaBridge | 170:e95d10626187 | 5551 | |
AnnaBridge | 170:e95d10626187 | 5552 | /* Bit fields for PRS PEEK */ |
AnnaBridge | 170:e95d10626187 | 5553 | #define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5554 | #define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5555 | #define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5556 | #define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ |
AnnaBridge | 170:e95d10626187 | 5557 | #define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ |
AnnaBridge | 170:e95d10626187 | 5558 | #define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5559 | #define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5560 | #define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5561 | #define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ |
AnnaBridge | 170:e95d10626187 | 5562 | #define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ |
AnnaBridge | 170:e95d10626187 | 5563 | #define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5564 | #define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5565 | #define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5566 | #define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ |
AnnaBridge | 170:e95d10626187 | 5567 | #define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ |
AnnaBridge | 170:e95d10626187 | 5568 | #define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5569 | #define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5570 | #define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5571 | #define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ |
AnnaBridge | 170:e95d10626187 | 5572 | #define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ |
AnnaBridge | 170:e95d10626187 | 5573 | #define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5574 | #define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5575 | #define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5576 | #define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ |
AnnaBridge | 170:e95d10626187 | 5577 | #define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ |
AnnaBridge | 170:e95d10626187 | 5578 | #define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5579 | #define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5580 | #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5581 | #define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ |
AnnaBridge | 170:e95d10626187 | 5582 | #define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ |
AnnaBridge | 170:e95d10626187 | 5583 | #define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5584 | #define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5585 | #define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5586 | #define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ |
AnnaBridge | 170:e95d10626187 | 5587 | #define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ |
AnnaBridge | 170:e95d10626187 | 5588 | #define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5589 | #define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5590 | #define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5591 | #define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ |
AnnaBridge | 170:e95d10626187 | 5592 | #define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ |
AnnaBridge | 170:e95d10626187 | 5593 | #define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5594 | #define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5595 | #define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5596 | #define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ |
AnnaBridge | 170:e95d10626187 | 5597 | #define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ |
AnnaBridge | 170:e95d10626187 | 5598 | #define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5599 | #define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5600 | #define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5601 | #define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ |
AnnaBridge | 170:e95d10626187 | 5602 | #define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ |
AnnaBridge | 170:e95d10626187 | 5603 | #define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5604 | #define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5605 | #define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5606 | #define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ |
AnnaBridge | 170:e95d10626187 | 5607 | #define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ |
AnnaBridge | 170:e95d10626187 | 5608 | #define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5609 | #define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5610 | #define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5611 | #define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ |
AnnaBridge | 170:e95d10626187 | 5612 | #define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ |
AnnaBridge | 170:e95d10626187 | 5613 | #define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5614 | #define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5615 | #define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5616 | #define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ |
AnnaBridge | 170:e95d10626187 | 5617 | #define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ |
AnnaBridge | 170:e95d10626187 | 5618 | #define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5619 | #define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5620 | #define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5621 | #define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ |
AnnaBridge | 170:e95d10626187 | 5622 | #define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ |
AnnaBridge | 170:e95d10626187 | 5623 | #define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5624 | #define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5625 | #define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5626 | #define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ |
AnnaBridge | 170:e95d10626187 | 5627 | #define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ |
AnnaBridge | 170:e95d10626187 | 5628 | #define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5629 | #define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5630 | #define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5631 | #define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ |
AnnaBridge | 170:e95d10626187 | 5632 | #define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ |
AnnaBridge | 170:e95d10626187 | 5633 | #define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5634 | #define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5635 | #define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5636 | #define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ |
AnnaBridge | 170:e95d10626187 | 5637 | #define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ |
AnnaBridge | 170:e95d10626187 | 5638 | #define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5639 | #define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5640 | #define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5641 | #define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ |
AnnaBridge | 170:e95d10626187 | 5642 | #define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ |
AnnaBridge | 170:e95d10626187 | 5643 | #define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5644 | #define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5645 | #define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5646 | #define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ |
AnnaBridge | 170:e95d10626187 | 5647 | #define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ |
AnnaBridge | 170:e95d10626187 | 5648 | #define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5649 | #define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5650 | #define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5651 | #define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ |
AnnaBridge | 170:e95d10626187 | 5652 | #define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ |
AnnaBridge | 170:e95d10626187 | 5653 | #define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5654 | #define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5655 | #define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5656 | #define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ |
AnnaBridge | 170:e95d10626187 | 5657 | #define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ |
AnnaBridge | 170:e95d10626187 | 5658 | #define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5659 | #define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5660 | #define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5661 | #define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ |
AnnaBridge | 170:e95d10626187 | 5662 | #define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ |
AnnaBridge | 170:e95d10626187 | 5663 | #define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5664 | #define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5665 | #define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5666 | #define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ |
AnnaBridge | 170:e95d10626187 | 5667 | #define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ |
AnnaBridge | 170:e95d10626187 | 5668 | #define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5669 | #define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5670 | #define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ |
AnnaBridge | 170:e95d10626187 | 5671 | #define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ |
AnnaBridge | 170:e95d10626187 | 5672 | #define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ |
AnnaBridge | 170:e95d10626187 | 5673 | #define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5674 | #define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ |
AnnaBridge | 170:e95d10626187 | 5675 | |
AnnaBridge | 170:e95d10626187 | 5676 | /* Bit fields for PRS CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5677 | #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5678 | #define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5679 | #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ |
AnnaBridge | 170:e95d10626187 | 5680 | #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ |
AnnaBridge | 170:e95d10626187 | 5681 | #define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5682 | #define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5683 | #define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5684 | #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5685 | #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5686 | #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5687 | #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5688 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5689 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5690 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5691 | #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5692 | #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5693 | #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5694 | #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5695 | #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5696 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5697 | #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5698 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5699 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5700 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5701 | #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5702 | #define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5703 | #define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5704 | #define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5705 | #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5706 | #define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5707 | #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5708 | #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5709 | #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5710 | #define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5711 | #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5712 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5713 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5714 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5715 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5716 | #define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5717 | #define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5718 | #define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5719 | #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5720 | #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5721 | #define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5722 | #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5723 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5724 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5725 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5726 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5727 | #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5728 | #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5729 | #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5730 | #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5731 | #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5732 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5733 | #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5734 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5735 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5736 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5737 | #define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5738 | #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5739 | #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5740 | #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5741 | #define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5742 | #define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5743 | #define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5744 | #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5745 | #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5746 | #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5747 | #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5748 | #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5749 | #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5750 | #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5751 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5752 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5753 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5754 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5755 | #define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5756 | #define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5757 | #define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5758 | #define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5759 | #define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5760 | #define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5761 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5762 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5763 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5764 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5765 | #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5766 | #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5767 | #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5768 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5769 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5770 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5771 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5772 | #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5773 | #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5774 | #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5775 | #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5776 | #define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5777 | #define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5778 | #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5779 | #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5780 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5781 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5782 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5783 | #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5784 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5785 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5786 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5787 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5788 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5789 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5790 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5791 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5792 | #define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5793 | #define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5794 | #define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5795 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5796 | #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5797 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5798 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5799 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5800 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5801 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5802 | #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5803 | #define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5804 | #define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5805 | #define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5806 | #define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5807 | #define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5808 | #define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5809 | #define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5810 | #define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5811 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5812 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5813 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5814 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5815 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5816 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5817 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5818 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5819 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5820 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5821 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5822 | #define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5823 | #define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5824 | #define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5825 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5826 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5827 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5828 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5829 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5830 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5831 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5832 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5833 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5834 | #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5835 | #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5836 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5837 | #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5838 | #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5839 | #define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5840 | #define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5841 | #define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5842 | #define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5843 | #define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5844 | #define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5845 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5846 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5847 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5848 | #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5849 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5850 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5851 | #define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5852 | #define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5853 | #define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5854 | #define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5855 | #define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5856 | #define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5857 | #define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5858 | #define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5859 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5860 | #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5861 | #define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5862 | #define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5863 | #define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5864 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5865 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5866 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5867 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5868 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5869 | #define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5870 | #define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5871 | #define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5872 | #define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5873 | #define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5874 | #define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5875 | #define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5876 | #define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5877 | #define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5878 | #define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5879 | #define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5880 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5881 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5882 | #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5883 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5884 | #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5885 | #define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5886 | #define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5887 | #define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5888 | #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5889 | #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5890 | #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5891 | #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5892 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5893 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5894 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5895 | #define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5896 | #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5897 | #define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5898 | #define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5899 | #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5900 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5901 | #define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5902 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5903 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5904 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5905 | #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5906 | #define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5907 | #define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5908 | #define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5909 | #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5910 | #define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5911 | #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5912 | #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5913 | #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5914 | #define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5915 | #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5916 | #define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5917 | #define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5918 | #define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5919 | #define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5920 | #define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5921 | #define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5922 | #define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5923 | #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5924 | #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5925 | #define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5926 | #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5927 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5928 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5929 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5930 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5931 | #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5932 | #define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5933 | #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5934 | #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5935 | #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5936 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5937 | #define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5938 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5939 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5940 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5941 | #define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5942 | #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5943 | #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5944 | #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5945 | #define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5946 | #define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5947 | #define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5948 | #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5949 | #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5950 | #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5951 | #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5952 | #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5953 | #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5954 | #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5955 | #define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5956 | #define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5957 | #define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5958 | #define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5959 | #define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5960 | #define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5961 | #define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5962 | #define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5963 | #define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5964 | #define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5965 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5966 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5967 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5968 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5969 | #define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5970 | #define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5971 | #define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5972 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5973 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5974 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5975 | #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5976 | #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5977 | #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5978 | #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5979 | #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5980 | #define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5981 | #define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5982 | #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5983 | #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5984 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5985 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5986 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5987 | #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5988 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5989 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5990 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5991 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5992 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5993 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5994 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5995 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5996 | #define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5997 | #define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5998 | #define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 5999 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6000 | #define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6001 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6002 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6003 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6004 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6005 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6006 | #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6007 | #define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6008 | #define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6009 | #define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6010 | #define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6011 | #define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6012 | #define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6013 | #define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6014 | #define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6015 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6016 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6017 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6018 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6019 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6020 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6021 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6022 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6023 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6024 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6025 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6026 | #define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6027 | #define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6028 | #define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6029 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6030 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6031 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6032 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6033 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6034 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6035 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6036 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6037 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6038 | #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6039 | #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6040 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6041 | #define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6042 | #define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6043 | #define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6044 | #define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6045 | #define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6046 | #define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6047 | #define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6048 | #define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6049 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6050 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6051 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6052 | #define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6053 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6054 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6055 | #define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6056 | #define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6057 | #define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6058 | #define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6059 | #define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6060 | #define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6061 | #define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6062 | #define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6063 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6064 | #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6065 | #define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6066 | #define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6067 | #define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6068 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6069 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6070 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6071 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6072 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6073 | #define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6074 | #define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6075 | #define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6076 | #define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6077 | #define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6078 | #define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6079 | #define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6080 | #define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6081 | #define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6082 | #define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6083 | #define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6084 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6085 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6086 | #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6087 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6088 | #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6089 | #define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ |
AnnaBridge | 170:e95d10626187 | 6090 | #define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ |
AnnaBridge | 170:e95d10626187 | 6091 | #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6092 | #define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6093 | #define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6094 | #define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6095 | #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6096 | #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6097 | #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6098 | #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6099 | #define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6100 | #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6101 | #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6102 | #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6103 | #define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6104 | #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6105 | #define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6106 | #define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6107 | #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6108 | #define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6109 | #define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6110 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6111 | #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6112 | #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6113 | #define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6114 | #define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6115 | #define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6116 | #define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6117 | #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6118 | #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6119 | #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6120 | #define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6121 | #define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6122 | #define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6123 | #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6124 | #define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6125 | #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6126 | #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6127 | #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6128 | #define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6129 | #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6130 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6131 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6132 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6133 | #define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6134 | #define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6135 | #define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6136 | #define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6137 | #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6138 | #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6139 | #define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6140 | #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6141 | #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6142 | #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6143 | #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6144 | #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6145 | #define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6146 | #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6147 | #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6148 | #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6149 | #define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6150 | #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6151 | #define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6152 | #define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6153 | #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6154 | #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6155 | #define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6156 | #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6157 | #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6158 | #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6159 | #define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6160 | #define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6161 | #define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6162 | #define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6163 | #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6164 | #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6165 | #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6166 | #define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6167 | #define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6168 | #define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6169 | #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6170 | #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6171 | #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6172 | #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6173 | #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6174 | #define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6175 | #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6176 | #define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6177 | #define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6178 | #define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6179 | #define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6180 | #define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6181 | #define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6182 | #define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6183 | #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ |
AnnaBridge | 170:e95d10626187 | 6184 | #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ |
AnnaBridge | 170:e95d10626187 | 6185 | #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6186 | #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6187 | #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6188 | #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6189 | #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6190 | #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6191 | #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6192 | #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6193 | #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6194 | #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6195 | #define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ |
AnnaBridge | 170:e95d10626187 | 6196 | #define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ |
AnnaBridge | 170:e95d10626187 | 6197 | #define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ |
AnnaBridge | 170:e95d10626187 | 6198 | #define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6199 | #define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6200 | #define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ |
AnnaBridge | 170:e95d10626187 | 6201 | #define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ |
AnnaBridge | 170:e95d10626187 | 6202 | #define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ |
AnnaBridge | 170:e95d10626187 | 6203 | #define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6204 | #define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6205 | #define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ |
AnnaBridge | 170:e95d10626187 | 6206 | #define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ |
AnnaBridge | 170:e95d10626187 | 6207 | #define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ |
AnnaBridge | 170:e95d10626187 | 6208 | #define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6209 | #define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6210 | #define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ |
AnnaBridge | 170:e95d10626187 | 6211 | #define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ |
AnnaBridge | 170:e95d10626187 | 6212 | #define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ |
AnnaBridge | 170:e95d10626187 | 6213 | #define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6214 | #define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6215 | #define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ |
AnnaBridge | 170:e95d10626187 | 6216 | #define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ |
AnnaBridge | 170:e95d10626187 | 6217 | #define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ |
AnnaBridge | 170:e95d10626187 | 6218 | #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6219 | #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
AnnaBridge | 170:e95d10626187 | 6220 | |
AnnaBridge | 170:e95d10626187 | 6221 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 6222 | /** @} End of group EFM32GG11B520F2048IQ64_PRS */ |
AnnaBridge | 170:e95d10626187 | 6223 | |
AnnaBridge | 170:e95d10626187 | 6224 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 6225 | * @addtogroup EFM32GG11B520F2048IQ64_SMU |
AnnaBridge | 170:e95d10626187 | 6226 | * @{ |
AnnaBridge | 170:e95d10626187 | 6227 | * @defgroup EFM32GG11B520F2048IQ64_SMU_BitFields SMU Bit Fields |
AnnaBridge | 170:e95d10626187 | 6228 | * @{ |
AnnaBridge | 170:e95d10626187 | 6229 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 6230 | |
AnnaBridge | 170:e95d10626187 | 6231 | /* Bit fields for SMU IF */ |
AnnaBridge | 170:e95d10626187 | 6232 | #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ |
AnnaBridge | 170:e95d10626187 | 6233 | #define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ |
AnnaBridge | 170:e95d10626187 | 6234 | #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 6235 | #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6236 | #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6237 | #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ |
AnnaBridge | 170:e95d10626187 | 6238 | #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ |
AnnaBridge | 170:e95d10626187 | 6239 | |
AnnaBridge | 170:e95d10626187 | 6240 | /* Bit fields for SMU IFS */ |
AnnaBridge | 170:e95d10626187 | 6241 | #define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 6242 | #define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 6243 | #define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 6244 | #define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6245 | #define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6246 | #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 6247 | #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ |
AnnaBridge | 170:e95d10626187 | 6248 | |
AnnaBridge | 170:e95d10626187 | 6249 | /* Bit fields for SMU IFC */ |
AnnaBridge | 170:e95d10626187 | 6250 | #define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 6251 | #define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 6252 | #define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ |
AnnaBridge | 170:e95d10626187 | 6253 | #define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6254 | #define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6255 | #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 6256 | #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ |
AnnaBridge | 170:e95d10626187 | 6257 | |
AnnaBridge | 170:e95d10626187 | 6258 | /* Bit fields for SMU IEN */ |
AnnaBridge | 170:e95d10626187 | 6259 | #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 6260 | #define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 6261 | #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ |
AnnaBridge | 170:e95d10626187 | 6262 | #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6263 | #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ |
AnnaBridge | 170:e95d10626187 | 6264 | #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 6265 | #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ |
AnnaBridge | 170:e95d10626187 | 6266 | |
AnnaBridge | 170:e95d10626187 | 6267 | /* Bit fields for SMU PPUCTRL */ |
AnnaBridge | 170:e95d10626187 | 6268 | #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ |
AnnaBridge | 170:e95d10626187 | 6269 | #define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ |
AnnaBridge | 170:e95d10626187 | 6270 | #define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ |
AnnaBridge | 170:e95d10626187 | 6271 | #define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ |
AnnaBridge | 170:e95d10626187 | 6272 | #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ |
AnnaBridge | 170:e95d10626187 | 6273 | #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ |
AnnaBridge | 170:e95d10626187 | 6274 | #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ |
AnnaBridge | 170:e95d10626187 | 6275 | |
AnnaBridge | 170:e95d10626187 | 6276 | /* Bit fields for SMU PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6277 | #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6278 | #define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6279 | #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6280 | #define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ |
AnnaBridge | 170:e95d10626187 | 6281 | #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ |
AnnaBridge | 170:e95d10626187 | 6282 | #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6283 | #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6284 | #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6285 | #define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ |
AnnaBridge | 170:e95d10626187 | 6286 | #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ |
AnnaBridge | 170:e95d10626187 | 6287 | #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6288 | #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6289 | #define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6290 | #define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ |
AnnaBridge | 170:e95d10626187 | 6291 | #define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ |
AnnaBridge | 170:e95d10626187 | 6292 | #define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6293 | #define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6294 | #define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6295 | #define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ |
AnnaBridge | 170:e95d10626187 | 6296 | #define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ |
AnnaBridge | 170:e95d10626187 | 6297 | #define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6298 | #define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6299 | #define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6300 | #define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ |
AnnaBridge | 170:e95d10626187 | 6301 | #define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ |
AnnaBridge | 170:e95d10626187 | 6302 | #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6303 | #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6304 | #define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6305 | #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ |
AnnaBridge | 170:e95d10626187 | 6306 | #define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ |
AnnaBridge | 170:e95d10626187 | 6307 | #define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6308 | #define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6309 | #define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6310 | #define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ |
AnnaBridge | 170:e95d10626187 | 6311 | #define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ |
AnnaBridge | 170:e95d10626187 | 6312 | #define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6313 | #define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6314 | #define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6315 | #define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ |
AnnaBridge | 170:e95d10626187 | 6316 | #define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ |
AnnaBridge | 170:e95d10626187 | 6317 | #define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6318 | #define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6319 | #define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ |
AnnaBridge | 170:e95d10626187 | 6320 | #define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ |
AnnaBridge | 170:e95d10626187 | 6321 | #define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ |
AnnaBridge | 170:e95d10626187 | 6322 | #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6323 | #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6324 | #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CryoTimer access control bit */ |
AnnaBridge | 170:e95d10626187 | 6325 | #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ |
AnnaBridge | 170:e95d10626187 | 6326 | #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ |
AnnaBridge | 170:e95d10626187 | 6327 | #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6328 | #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6329 | #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ |
AnnaBridge | 170:e95d10626187 | 6330 | #define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ |
AnnaBridge | 170:e95d10626187 | 6331 | #define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ |
AnnaBridge | 170:e95d10626187 | 6332 | #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6333 | #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6334 | #define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ |
AnnaBridge | 170:e95d10626187 | 6335 | #define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 6336 | #define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ |
AnnaBridge | 170:e95d10626187 | 6337 | #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6338 | #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6339 | #define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6340 | #define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ |
AnnaBridge | 170:e95d10626187 | 6341 | #define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ |
AnnaBridge | 170:e95d10626187 | 6342 | #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6343 | #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6344 | #define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ |
AnnaBridge | 170:e95d10626187 | 6345 | #define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ |
AnnaBridge | 170:e95d10626187 | 6346 | #define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ |
AnnaBridge | 170:e95d10626187 | 6347 | #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6348 | #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6349 | #define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ |
AnnaBridge | 170:e95d10626187 | 6350 | #define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ |
AnnaBridge | 170:e95d10626187 | 6351 | #define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ |
AnnaBridge | 170:e95d10626187 | 6352 | #define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6353 | #define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6354 | #define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ |
AnnaBridge | 170:e95d10626187 | 6355 | #define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ |
AnnaBridge | 170:e95d10626187 | 6356 | #define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ |
AnnaBridge | 170:e95d10626187 | 6357 | #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6358 | #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6359 | #define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ |
AnnaBridge | 170:e95d10626187 | 6360 | #define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ |
AnnaBridge | 170:e95d10626187 | 6361 | #define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ |
AnnaBridge | 170:e95d10626187 | 6362 | #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6363 | #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6364 | #define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ |
AnnaBridge | 170:e95d10626187 | 6365 | #define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ |
AnnaBridge | 170:e95d10626187 | 6366 | #define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ |
AnnaBridge | 170:e95d10626187 | 6367 | #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6368 | #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6369 | #define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ |
AnnaBridge | 170:e95d10626187 | 6370 | #define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ |
AnnaBridge | 170:e95d10626187 | 6371 | #define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ |
AnnaBridge | 170:e95d10626187 | 6372 | #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6373 | #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6374 | #define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6375 | #define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ |
AnnaBridge | 170:e95d10626187 | 6376 | #define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ |
AnnaBridge | 170:e95d10626187 | 6377 | #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6378 | #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6379 | #define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6380 | #define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ |
AnnaBridge | 170:e95d10626187 | 6381 | #define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ |
AnnaBridge | 170:e95d10626187 | 6382 | #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6383 | #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6384 | #define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6385 | #define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ |
AnnaBridge | 170:e95d10626187 | 6386 | #define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ |
AnnaBridge | 170:e95d10626187 | 6387 | #define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6388 | #define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6389 | #define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6390 | #define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ |
AnnaBridge | 170:e95d10626187 | 6391 | #define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ |
AnnaBridge | 170:e95d10626187 | 6392 | #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6393 | #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6394 | #define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ |
AnnaBridge | 170:e95d10626187 | 6395 | #define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ |
AnnaBridge | 170:e95d10626187 | 6396 | #define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ |
AnnaBridge | 170:e95d10626187 | 6397 | #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6398 | #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6399 | #define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ |
AnnaBridge | 170:e95d10626187 | 6400 | #define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 6401 | #define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ |
AnnaBridge | 170:e95d10626187 | 6402 | #define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6403 | #define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6404 | #define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ |
AnnaBridge | 170:e95d10626187 | 6405 | #define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ |
AnnaBridge | 170:e95d10626187 | 6406 | #define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ |
AnnaBridge | 170:e95d10626187 | 6407 | #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6408 | #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6409 | #define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ |
AnnaBridge | 170:e95d10626187 | 6410 | #define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 6411 | #define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ |
AnnaBridge | 170:e95d10626187 | 6412 | #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6413 | #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6414 | #define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6415 | #define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6416 | #define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6417 | #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6418 | #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6419 | #define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6420 | #define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6421 | #define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6422 | #define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6423 | #define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6424 | #define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6425 | #define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 6426 | #define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ |
AnnaBridge | 170:e95d10626187 | 6427 | #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6428 | #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6429 | #define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6430 | #define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 6431 | #define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ |
AnnaBridge | 170:e95d10626187 | 6432 | #define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6433 | #define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ |
AnnaBridge | 170:e95d10626187 | 6434 | |
AnnaBridge | 170:e95d10626187 | 6435 | /* Bit fields for SMU PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6436 | #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6437 | #define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6438 | #define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6439 | #define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ |
AnnaBridge | 170:e95d10626187 | 6440 | #define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ |
AnnaBridge | 170:e95d10626187 | 6441 | #define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6442 | #define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6443 | #define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6444 | #define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ |
AnnaBridge | 170:e95d10626187 | 6445 | #define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ |
AnnaBridge | 170:e95d10626187 | 6446 | #define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6447 | #define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6448 | #define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6449 | #define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ |
AnnaBridge | 170:e95d10626187 | 6450 | #define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ |
AnnaBridge | 170:e95d10626187 | 6451 | #define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6452 | #define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6453 | #define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ |
AnnaBridge | 170:e95d10626187 | 6454 | #define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ |
AnnaBridge | 170:e95d10626187 | 6455 | #define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ |
AnnaBridge | 170:e95d10626187 | 6456 | #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6457 | #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6458 | #define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ |
AnnaBridge | 170:e95d10626187 | 6459 | #define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 6460 | #define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ |
AnnaBridge | 170:e95d10626187 | 6461 | #define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6462 | #define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6463 | #define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ |
AnnaBridge | 170:e95d10626187 | 6464 | #define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 6465 | #define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ |
AnnaBridge | 170:e95d10626187 | 6466 | #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6467 | #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6468 | #define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ |
AnnaBridge | 170:e95d10626187 | 6469 | #define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ |
AnnaBridge | 170:e95d10626187 | 6470 | #define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ |
AnnaBridge | 170:e95d10626187 | 6471 | #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6472 | #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6473 | #define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6474 | #define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6475 | #define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6476 | #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6477 | #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6478 | #define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6479 | #define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6480 | #define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6481 | #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6482 | #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6483 | #define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6484 | #define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ |
AnnaBridge | 170:e95d10626187 | 6485 | #define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ |
AnnaBridge | 170:e95d10626187 | 6486 | #define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6487 | #define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6488 | #define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6489 | #define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ |
AnnaBridge | 170:e95d10626187 | 6490 | #define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ |
AnnaBridge | 170:e95d10626187 | 6491 | #define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6492 | #define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6493 | #define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6494 | #define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ |
AnnaBridge | 170:e95d10626187 | 6495 | #define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ |
AnnaBridge | 170:e95d10626187 | 6496 | #define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6497 | #define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6498 | #define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6499 | #define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ |
AnnaBridge | 170:e95d10626187 | 6500 | #define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ |
AnnaBridge | 170:e95d10626187 | 6501 | #define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6502 | #define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6503 | #define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6504 | #define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ |
AnnaBridge | 170:e95d10626187 | 6505 | #define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ |
AnnaBridge | 170:e95d10626187 | 6506 | #define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6507 | #define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6508 | #define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6509 | #define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ |
AnnaBridge | 170:e95d10626187 | 6510 | #define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ |
AnnaBridge | 170:e95d10626187 | 6511 | #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6512 | #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6513 | #define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6514 | #define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ |
AnnaBridge | 170:e95d10626187 | 6515 | #define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ |
AnnaBridge | 170:e95d10626187 | 6516 | #define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6517 | #define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6518 | #define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6519 | #define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ |
AnnaBridge | 170:e95d10626187 | 6520 | #define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ |
AnnaBridge | 170:e95d10626187 | 6521 | #define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6522 | #define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6523 | #define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6524 | #define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ |
AnnaBridge | 170:e95d10626187 | 6525 | #define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ |
AnnaBridge | 170:e95d10626187 | 6526 | #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6527 | #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6528 | #define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6529 | #define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ |
AnnaBridge | 170:e95d10626187 | 6530 | #define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ |
AnnaBridge | 170:e95d10626187 | 6531 | #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6532 | #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6533 | #define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6534 | #define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ |
AnnaBridge | 170:e95d10626187 | 6535 | #define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ |
AnnaBridge | 170:e95d10626187 | 6536 | #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6537 | #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6538 | #define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6539 | #define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ |
AnnaBridge | 170:e95d10626187 | 6540 | #define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ |
AnnaBridge | 170:e95d10626187 | 6541 | #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6542 | #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6543 | #define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6544 | #define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ |
AnnaBridge | 170:e95d10626187 | 6545 | #define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ |
AnnaBridge | 170:e95d10626187 | 6546 | #define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6547 | #define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6548 | #define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6549 | #define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ |
AnnaBridge | 170:e95d10626187 | 6550 | #define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ |
AnnaBridge | 170:e95d10626187 | 6551 | #define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6552 | #define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6553 | #define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ |
AnnaBridge | 170:e95d10626187 | 6554 | #define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ |
AnnaBridge | 170:e95d10626187 | 6555 | #define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ |
AnnaBridge | 170:e95d10626187 | 6556 | #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6557 | #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6558 | #define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ |
AnnaBridge | 170:e95d10626187 | 6559 | #define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ |
AnnaBridge | 170:e95d10626187 | 6560 | #define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ |
AnnaBridge | 170:e95d10626187 | 6561 | #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6562 | #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6563 | #define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6564 | #define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6565 | #define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ |
AnnaBridge | 170:e95d10626187 | 6566 | #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6567 | #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6568 | #define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6569 | #define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6570 | #define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ |
AnnaBridge | 170:e95d10626187 | 6571 | #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6572 | #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6573 | #define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6574 | #define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ |
AnnaBridge | 170:e95d10626187 | 6575 | #define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ |
AnnaBridge | 170:e95d10626187 | 6576 | #define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6577 | #define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6578 | #define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ |
AnnaBridge | 170:e95d10626187 | 6579 | #define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ |
AnnaBridge | 170:e95d10626187 | 6580 | #define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ |
AnnaBridge | 170:e95d10626187 | 6581 | #define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6582 | #define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ |
AnnaBridge | 170:e95d10626187 | 6583 | |
AnnaBridge | 170:e95d10626187 | 6584 | /* Bit fields for SMU PPUPATD2 */ |
AnnaBridge | 170:e95d10626187 | 6585 | #define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ |
AnnaBridge | 170:e95d10626187 | 6586 | #define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ |
AnnaBridge | 170:e95d10626187 | 6587 | |
AnnaBridge | 170:e95d10626187 | 6588 | /* Bit fields for SMU PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6589 | #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6590 | #define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6591 | #define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ |
AnnaBridge | 170:e95d10626187 | 6592 | #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ |
AnnaBridge | 170:e95d10626187 | 6593 | #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6594 | #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6595 | #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6596 | #define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6597 | #define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6598 | #define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6599 | #define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6600 | #define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6601 | #define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6602 | #define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6603 | #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6604 | #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6605 | #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6606 | #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6607 | #define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6608 | #define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6609 | #define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6610 | #define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6611 | #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6612 | #define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6613 | #define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6614 | #define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6615 | #define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6616 | #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6617 | #define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6618 | #define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6619 | #define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6620 | #define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6621 | #define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6622 | #define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6623 | #define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6624 | #define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6625 | #define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6626 | #define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6627 | #define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6628 | #define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6629 | #define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6630 | #define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6631 | #define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6632 | #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6633 | #define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6634 | #define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6635 | #define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6636 | #define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6637 | #define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6638 | #define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6639 | #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6640 | #define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6641 | #define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6642 | #define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6643 | #define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6644 | #define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6645 | #define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6646 | #define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6647 | #define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6648 | #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6649 | #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6650 | #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6651 | #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6652 | #define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6653 | #define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6654 | #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6655 | #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6656 | #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6657 | #define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6658 | #define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6659 | #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6660 | #define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6661 | #define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6662 | #define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6663 | #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6664 | #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6665 | #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6666 | #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6667 | #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6668 | #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6669 | #define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6670 | #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6671 | #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6672 | #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6673 | #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6674 | #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6675 | #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6676 | #define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6677 | #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6678 | #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6679 | #define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6680 | #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6681 | #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6682 | #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6683 | #define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6684 | #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6685 | #define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6686 | #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6687 | #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6688 | #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6689 | #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6690 | #define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6691 | #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6692 | #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6693 | #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6694 | #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6695 | #define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6696 | #define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6697 | #define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6698 | #define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6699 | #define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6700 | #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6701 | #define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6702 | #define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6703 | #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6704 | #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6705 | #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6706 | #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6707 | #define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6708 | #define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6709 | #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6710 | #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6711 | #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6712 | #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6713 | #define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6714 | #define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ |
AnnaBridge | 170:e95d10626187 | 6715 | |
AnnaBridge | 170:e95d10626187 | 6716 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 6717 | /** @} End of group EFM32GG11B520F2048IQ64_SMU */ |
AnnaBridge | 170:e95d10626187 | 6718 | |
AnnaBridge | 170:e95d10626187 | 6719 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 6720 | * @defgroup EFM32GG11B520F2048IQ64_UNLOCK Unlock Codes |
AnnaBridge | 170:e95d10626187 | 6721 | * @{ |
AnnaBridge | 170:e95d10626187 | 6722 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 6723 | #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ |
AnnaBridge | 170:e95d10626187 | 6724 | #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ |
AnnaBridge | 170:e95d10626187 | 6725 | #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ |
AnnaBridge | 170:e95d10626187 | 6726 | #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ |
AnnaBridge | 170:e95d10626187 | 6727 | #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ |
AnnaBridge | 170:e95d10626187 | 6728 | #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ |
AnnaBridge | 170:e95d10626187 | 6729 | #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ |
AnnaBridge | 170:e95d10626187 | 6730 | |
AnnaBridge | 170:e95d10626187 | 6731 | /** @} End of group EFM32GG11B520F2048IQ64_UNLOCK */ |
AnnaBridge | 170:e95d10626187 | 6732 | |
AnnaBridge | 170:e95d10626187 | 6733 | /** @} End of group EFM32GG11B520F2048IQ64_BitFields */ |
AnnaBridge | 170:e95d10626187 | 6734 | |
AnnaBridge | 170:e95d10626187 | 6735 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 6736 | * @addtogroup EFM32GG11B520F2048IQ64_Alternate_Function Alternate Function |
AnnaBridge | 170:e95d10626187 | 6737 | * @{ |
AnnaBridge | 170:e95d10626187 | 6738 | * @defgroup EFM32GG11B520F2048IQ64_AF_Ports Alternate Function Ports |
AnnaBridge | 170:e95d10626187 | 6739 | * @{ |
AnnaBridge | 170:e95d10626187 | 6740 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 6741 | |
AnnaBridge | 170:e95d10626187 | 6742 | #define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6743 | #define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6744 | #define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6745 | #define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6746 | #define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6747 | #define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ |
AnnaBridge | 170:e95d10626187 | 6748 | #define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ |
AnnaBridge | 170:e95d10626187 | 6749 | #define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6750 | #define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6751 | #define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6752 | #define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6753 | #define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ |
AnnaBridge | 170:e95d10626187 | 6754 | #define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ |
AnnaBridge | 170:e95d10626187 | 6755 | #define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ |
AnnaBridge | 170:e95d10626187 | 6756 | #define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ |
AnnaBridge | 170:e95d10626187 | 6757 | #define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ |
AnnaBridge | 170:e95d10626187 | 6758 | #define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ |
AnnaBridge | 170:e95d10626187 | 6759 | #define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ |
AnnaBridge | 170:e95d10626187 | 6760 | #define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ |
AnnaBridge | 170:e95d10626187 | 6761 | #define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ |
AnnaBridge | 170:e95d10626187 | 6762 | #define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ |
AnnaBridge | 170:e95d10626187 | 6763 | #define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ |
AnnaBridge | 170:e95d10626187 | 6764 | #define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ |
AnnaBridge | 170:e95d10626187 | 6765 | #define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6766 | #define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6767 | #define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6768 | #define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6769 | #define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ |
AnnaBridge | 170:e95d10626187 | 6770 | #define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ |
AnnaBridge | 170:e95d10626187 | 6771 | #define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ |
AnnaBridge | 170:e95d10626187 | 6772 | #define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ |
AnnaBridge | 170:e95d10626187 | 6773 | #define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ |
AnnaBridge | 170:e95d10626187 | 6774 | #define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ |
AnnaBridge | 170:e95d10626187 | 6775 | #define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ |
AnnaBridge | 170:e95d10626187 | 6776 | #define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ |
AnnaBridge | 170:e95d10626187 | 6777 | #define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ |
AnnaBridge | 170:e95d10626187 | 6778 | #define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ |
AnnaBridge | 170:e95d10626187 | 6779 | #define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ |
AnnaBridge | 170:e95d10626187 | 6780 | #define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ |
AnnaBridge | 170:e95d10626187 | 6781 | #define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ |
AnnaBridge | 170:e95d10626187 | 6782 | #define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ |
AnnaBridge | 170:e95d10626187 | 6783 | #define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ |
AnnaBridge | 170:e95d10626187 | 6784 | #define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ |
AnnaBridge | 170:e95d10626187 | 6785 | #define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ |
AnnaBridge | 170:e95d10626187 | 6786 | #define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ |
AnnaBridge | 170:e95d10626187 | 6787 | #define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ |
AnnaBridge | 170:e95d10626187 | 6788 | #define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ |
AnnaBridge | 170:e95d10626187 | 6789 | #define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6790 | #define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6791 | #define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6792 | #define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6793 | #define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ |
AnnaBridge | 170:e95d10626187 | 6794 | #define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ |
AnnaBridge | 170:e95d10626187 | 6795 | #define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ |
AnnaBridge | 170:e95d10626187 | 6796 | #define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ |
AnnaBridge | 170:e95d10626187 | 6797 | #define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6798 | #define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6799 | #define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ |
AnnaBridge | 170:e95d10626187 | 6800 | #define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ |
AnnaBridge | 170:e95d10626187 | 6801 | #define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ |
AnnaBridge | 170:e95d10626187 | 6802 | #define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ |
AnnaBridge | 170:e95d10626187 | 6803 | #define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ |
AnnaBridge | 170:e95d10626187 | 6804 | #define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ |
AnnaBridge | 170:e95d10626187 | 6805 | #define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ |
AnnaBridge | 170:e95d10626187 | 6806 | #define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ |
AnnaBridge | 170:e95d10626187 | 6807 | #define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ |
AnnaBridge | 170:e95d10626187 | 6808 | #define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ |
AnnaBridge | 170:e95d10626187 | 6809 | #define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ |
AnnaBridge | 170:e95d10626187 | 6810 | #define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ |
AnnaBridge | 170:e95d10626187 | 6811 | #define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ |
AnnaBridge | 170:e95d10626187 | 6812 | #define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ |
AnnaBridge | 170:e95d10626187 | 6813 | #define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ |
AnnaBridge | 170:e95d10626187 | 6814 | #define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ |
AnnaBridge | 170:e95d10626187 | 6815 | #define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ |
AnnaBridge | 170:e95d10626187 | 6816 | #define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ |
AnnaBridge | 170:e95d10626187 | 6817 | #define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ |
AnnaBridge | 170:e95d10626187 | 6818 | #define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ |
AnnaBridge | 170:e95d10626187 | 6819 | #define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ |
AnnaBridge | 170:e95d10626187 | 6820 | #define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ |
AnnaBridge | 170:e95d10626187 | 6821 | #define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ |
AnnaBridge | 170:e95d10626187 | 6822 | #define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ |
AnnaBridge | 170:e95d10626187 | 6823 | #define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ |
AnnaBridge | 170:e95d10626187 | 6824 | #define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ |
AnnaBridge | 170:e95d10626187 | 6825 | #define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ |
AnnaBridge | 170:e95d10626187 | 6826 | #define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ |
AnnaBridge | 170:e95d10626187 | 6827 | #define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ |
AnnaBridge | 170:e95d10626187 | 6828 | #define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ |
AnnaBridge | 170:e95d10626187 | 6829 | #define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ |
AnnaBridge | 170:e95d10626187 | 6830 | #define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6831 | #define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ |
AnnaBridge | 170:e95d10626187 | 6832 | #define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ |
AnnaBridge | 170:e95d10626187 | 6833 | #define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ |
AnnaBridge | 170:e95d10626187 | 6834 | #define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6835 | #define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6836 | #define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6837 | #define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6838 | #define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ |
AnnaBridge | 170:e95d10626187 | 6839 | #define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ |
AnnaBridge | 170:e95d10626187 | 6840 | #define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ |
AnnaBridge | 170:e95d10626187 | 6841 | #define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ |
AnnaBridge | 170:e95d10626187 | 6842 | #define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ |
AnnaBridge | 170:e95d10626187 | 6843 | #define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ |
AnnaBridge | 170:e95d10626187 | 6844 | #define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ |
AnnaBridge | 170:e95d10626187 | 6845 | #define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ |
AnnaBridge | 170:e95d10626187 | 6846 | #define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ |
AnnaBridge | 170:e95d10626187 | 6847 | #define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ |
AnnaBridge | 170:e95d10626187 | 6848 | #define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ |
AnnaBridge | 170:e95d10626187 | 6849 | #define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ |
AnnaBridge | 170:e95d10626187 | 6850 | #define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ |
AnnaBridge | 170:e95d10626187 | 6851 | #define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ |
AnnaBridge | 170:e95d10626187 | 6852 | #define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ |
AnnaBridge | 170:e95d10626187 | 6853 | #define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ |
AnnaBridge | 170:e95d10626187 | 6854 | #define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ |
AnnaBridge | 170:e95d10626187 | 6855 | #define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ |
AnnaBridge | 170:e95d10626187 | 6856 | #define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ |
AnnaBridge | 170:e95d10626187 | 6857 | #define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ |
AnnaBridge | 170:e95d10626187 | 6858 | #define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6859 | #define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6860 | #define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6861 | #define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6862 | #define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6863 | #define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6864 | #define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6865 | #define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6866 | #define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6867 | #define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6868 | #define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6869 | #define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6870 | #define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6871 | #define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6872 | #define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6873 | #define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6874 | #define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6875 | #define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6876 | #define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6877 | #define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6878 | #define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6879 | #define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6880 | #define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6881 | #define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6882 | #define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6883 | #define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6884 | #define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6885 | #define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6886 | #define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6887 | #define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6888 | #define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6889 | #define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6890 | #define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6891 | #define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6892 | #define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6893 | #define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6894 | #define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6895 | #define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6896 | #define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6897 | #define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6898 | #define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6899 | #define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6900 | #define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6901 | #define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6902 | #define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6903 | #define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6904 | #define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6905 | #define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6906 | #define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6907 | #define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6908 | #define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6909 | #define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6910 | #define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6911 | #define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6912 | #define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6913 | #define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6914 | #define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6915 | #define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6916 | #define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6917 | #define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6918 | #define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6919 | #define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6920 | #define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6921 | #define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6922 | #define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6923 | #define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6924 | #define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6925 | #define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6926 | #define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6927 | #define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6928 | #define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6929 | #define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6930 | #define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6931 | #define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6932 | #define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6933 | #define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6934 | #define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6935 | #define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6936 | #define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6937 | #define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6938 | #define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6939 | #define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6940 | #define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6941 | #define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6942 | #define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6943 | #define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6944 | #define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6945 | #define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6946 | #define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 6947 | #define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 6948 | #define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 6949 | #define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 6950 | #define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6951 | #define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6952 | #define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6953 | #define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6954 | #define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6955 | #define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6956 | #define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6957 | #define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6958 | #define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6959 | #define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6960 | #define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6961 | #define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6962 | #define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6963 | #define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6964 | #define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6965 | #define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6966 | #define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6967 | #define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6968 | #define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6969 | #define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6970 | #define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6971 | #define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6972 | #define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6973 | #define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6974 | #define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6975 | #define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6976 | #define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6977 | #define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6978 | #define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6979 | #define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6980 | #define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6981 | #define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6982 | #define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6983 | #define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6984 | #define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6985 | #define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6986 | #define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6987 | #define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6988 | #define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6989 | #define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6990 | #define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6991 | #define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6992 | #define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6993 | #define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 6994 | #define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 6995 | #define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 6996 | #define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6997 | #define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 6998 | #define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 6999 | #define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7000 | #define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7001 | #define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7002 | #define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7003 | #define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7004 | #define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7005 | #define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7006 | #define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7007 | #define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7008 | #define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7009 | #define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7010 | #define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7011 | #define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7012 | #define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7013 | #define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7014 | #define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7015 | #define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7016 | #define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7017 | #define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7018 | #define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7019 | #define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7020 | #define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7021 | #define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7022 | #define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ |
AnnaBridge | 170:e95d10626187 | 7023 | #define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ |
AnnaBridge | 170:e95d10626187 | 7024 | #define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ |
AnnaBridge | 170:e95d10626187 | 7025 | #define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ |
AnnaBridge | 170:e95d10626187 | 7026 | #define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ |
AnnaBridge | 170:e95d10626187 | 7027 | #define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7028 | #define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7029 | #define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7030 | #define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7031 | #define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7032 | |
AnnaBridge | 170:e95d10626187 | 7033 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 7034 | /** @} End of group EFM32GG11B520F2048IQ64_AF_Ports */ |
AnnaBridge | 170:e95d10626187 | 7035 | |
AnnaBridge | 170:e95d10626187 | 7036 | /**************************************************************************//** |
AnnaBridge | 170:e95d10626187 | 7037 | * @addtogroup EFM32GG11B520F2048IQ64_Alternate_Function Alternate Function |
AnnaBridge | 170:e95d10626187 | 7038 | * @{ |
AnnaBridge | 170:e95d10626187 | 7039 | * @defgroup EFM32GG11B520F2048IQ64_AF_Pins Alternate Function Pins |
AnnaBridge | 170:e95d10626187 | 7040 | * @{ |
AnnaBridge | 170:e95d10626187 | 7041 | *****************************************************************************/ |
AnnaBridge | 170:e95d10626187 | 7042 | |
AnnaBridge | 170:e95d10626187 | 7043 | #define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7044 | #define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7045 | #define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7046 | #define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7047 | #define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7048 | #define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ |
AnnaBridge | 170:e95d10626187 | 7049 | #define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ |
AnnaBridge | 170:e95d10626187 | 7050 | #define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7051 | #define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7052 | #define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7053 | #define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7054 | #define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ |
AnnaBridge | 170:e95d10626187 | 7055 | #define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ |
AnnaBridge | 170:e95d10626187 | 7056 | #define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ |
AnnaBridge | 170:e95d10626187 | 7057 | #define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ |
AnnaBridge | 170:e95d10626187 | 7058 | #define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ |
AnnaBridge | 170:e95d10626187 | 7059 | #define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ |
AnnaBridge | 170:e95d10626187 | 7060 | #define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ |
AnnaBridge | 170:e95d10626187 | 7061 | #define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ |
AnnaBridge | 170:e95d10626187 | 7062 | #define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ |
AnnaBridge | 170:e95d10626187 | 7063 | #define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ |
AnnaBridge | 170:e95d10626187 | 7064 | #define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ |
AnnaBridge | 170:e95d10626187 | 7065 | #define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ |
AnnaBridge | 170:e95d10626187 | 7066 | #define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7067 | #define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7068 | #define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7069 | #define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7070 | #define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ |
AnnaBridge | 170:e95d10626187 | 7071 | #define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ |
AnnaBridge | 170:e95d10626187 | 7072 | #define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ |
AnnaBridge | 170:e95d10626187 | 7073 | #define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ |
AnnaBridge | 170:e95d10626187 | 7074 | #define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ |
AnnaBridge | 170:e95d10626187 | 7075 | #define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ |
AnnaBridge | 170:e95d10626187 | 7076 | #define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ |
AnnaBridge | 170:e95d10626187 | 7077 | #define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ |
AnnaBridge | 170:e95d10626187 | 7078 | #define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ |
AnnaBridge | 170:e95d10626187 | 7079 | #define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ |
AnnaBridge | 170:e95d10626187 | 7080 | #define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ |
AnnaBridge | 170:e95d10626187 | 7081 | #define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ |
AnnaBridge | 170:e95d10626187 | 7082 | #define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ |
AnnaBridge | 170:e95d10626187 | 7083 | #define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ |
AnnaBridge | 170:e95d10626187 | 7084 | #define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ |
AnnaBridge | 170:e95d10626187 | 7085 | #define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ |
AnnaBridge | 170:e95d10626187 | 7086 | #define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ |
AnnaBridge | 170:e95d10626187 | 7087 | #define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ |
AnnaBridge | 170:e95d10626187 | 7088 | #define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ |
AnnaBridge | 170:e95d10626187 | 7089 | #define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ |
AnnaBridge | 170:e95d10626187 | 7090 | #define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7091 | #define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7092 | #define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7093 | #define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7094 | #define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ |
AnnaBridge | 170:e95d10626187 | 7095 | #define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ |
AnnaBridge | 170:e95d10626187 | 7096 | #define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ |
AnnaBridge | 170:e95d10626187 | 7097 | #define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ |
AnnaBridge | 170:e95d10626187 | 7098 | #define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7099 | #define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7100 | #define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ |
AnnaBridge | 170:e95d10626187 | 7101 | #define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ |
AnnaBridge | 170:e95d10626187 | 7102 | #define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ |
AnnaBridge | 170:e95d10626187 | 7103 | #define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ |
AnnaBridge | 170:e95d10626187 | 7104 | #define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ |
AnnaBridge | 170:e95d10626187 | 7105 | #define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ |
AnnaBridge | 170:e95d10626187 | 7106 | #define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ |
AnnaBridge | 170:e95d10626187 | 7107 | #define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ |
AnnaBridge | 170:e95d10626187 | 7108 | #define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ |
AnnaBridge | 170:e95d10626187 | 7109 | #define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ |
AnnaBridge | 170:e95d10626187 | 7110 | #define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ |
AnnaBridge | 170:e95d10626187 | 7111 | #define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ |
AnnaBridge | 170:e95d10626187 | 7112 | #define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ |
AnnaBridge | 170:e95d10626187 | 7113 | #define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ |
AnnaBridge | 170:e95d10626187 | 7114 | #define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ |
AnnaBridge | 170:e95d10626187 | 7115 | #define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ |
AnnaBridge | 170:e95d10626187 | 7116 | #define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ |
AnnaBridge | 170:e95d10626187 | 7117 | #define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ |
AnnaBridge | 170:e95d10626187 | 7118 | #define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ |
AnnaBridge | 170:e95d10626187 | 7119 | #define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ |
AnnaBridge | 170:e95d10626187 | 7120 | #define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ |
AnnaBridge | 170:e95d10626187 | 7121 | #define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ |
AnnaBridge | 170:e95d10626187 | 7122 | #define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ |
AnnaBridge | 170:e95d10626187 | 7123 | #define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ |
AnnaBridge | 170:e95d10626187 | 7124 | #define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ |
AnnaBridge | 170:e95d10626187 | 7125 | #define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ |
AnnaBridge | 170:e95d10626187 | 7126 | #define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ |
AnnaBridge | 170:e95d10626187 | 7127 | #define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ |
AnnaBridge | 170:e95d10626187 | 7128 | #define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ |
AnnaBridge | 170:e95d10626187 | 7129 | #define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ |
AnnaBridge | 170:e95d10626187 | 7130 | #define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ |
AnnaBridge | 170:e95d10626187 | 7131 | #define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7132 | #define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ |
AnnaBridge | 170:e95d10626187 | 7133 | #define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ |
AnnaBridge | 170:e95d10626187 | 7134 | #define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ |
AnnaBridge | 170:e95d10626187 | 7135 | #define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7136 | #define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7137 | #define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7138 | #define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7139 | #define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ |
AnnaBridge | 170:e95d10626187 | 7140 | #define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ |
AnnaBridge | 170:e95d10626187 | 7141 | #define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ |
AnnaBridge | 170:e95d10626187 | 7142 | #define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ |
AnnaBridge | 170:e95d10626187 | 7143 | #define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ |
AnnaBridge | 170:e95d10626187 | 7144 | #define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ |
AnnaBridge | 170:e95d10626187 | 7145 | #define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ |
AnnaBridge | 170:e95d10626187 | 7146 | #define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ |
AnnaBridge | 170:e95d10626187 | 7147 | #define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ |
AnnaBridge | 170:e95d10626187 | 7148 | #define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ |
AnnaBridge | 170:e95d10626187 | 7149 | #define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ |
AnnaBridge | 170:e95d10626187 | 7150 | #define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ |
AnnaBridge | 170:e95d10626187 | 7151 | #define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ |
AnnaBridge | 170:e95d10626187 | 7152 | #define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ |
AnnaBridge | 170:e95d10626187 | 7153 | #define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ |
AnnaBridge | 170:e95d10626187 | 7154 | #define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ |
AnnaBridge | 170:e95d10626187 | 7155 | #define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ |
AnnaBridge | 170:e95d10626187 | 7156 | #define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ |
AnnaBridge | 170:e95d10626187 | 7157 | #define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ |
AnnaBridge | 170:e95d10626187 | 7158 | #define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ |
AnnaBridge | 170:e95d10626187 | 7159 | #define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7160 | #define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7161 | #define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7162 | #define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7163 | #define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7164 | #define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7165 | #define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7166 | #define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7167 | #define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7168 | #define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7169 | #define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7170 | #define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7171 | #define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7172 | #define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7173 | #define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7174 | #define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7175 | #define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7176 | #define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7177 | #define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7178 | #define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7179 | #define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7180 | #define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7181 | #define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7182 | #define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7183 | #define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7184 | #define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7185 | #define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7186 | #define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7187 | #define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7188 | #define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7189 | #define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7190 | #define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7191 | #define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7192 | #define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7193 | #define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7194 | #define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7195 | #define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7196 | #define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7197 | #define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7198 | #define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7199 | #define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7200 | #define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7201 | #define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7202 | #define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7203 | #define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7204 | #define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7205 | #define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7206 | #define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7207 | #define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7208 | #define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7209 | #define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7210 | #define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7211 | #define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7212 | #define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7213 | #define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7214 | #define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7215 | #define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7216 | #define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7217 | #define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7218 | #define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7219 | #define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7220 | #define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7221 | #define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7222 | #define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7223 | #define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7224 | #define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7225 | #define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7226 | #define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7227 | #define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7228 | #define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7229 | #define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7230 | #define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7231 | #define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7232 | #define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7233 | #define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7234 | #define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7235 | #define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7236 | #define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7237 | #define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7238 | #define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7239 | #define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7240 | #define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7241 | #define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7242 | #define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7243 | #define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7244 | #define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7245 | #define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7246 | #define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7247 | #define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7248 | #define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7249 | #define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7250 | #define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7251 | #define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7252 | #define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7253 | #define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7254 | #define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7255 | #define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7256 | #define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7257 | #define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7258 | #define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7259 | #define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7260 | #define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7261 | #define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7262 | #define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7263 | #define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7264 | #define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7265 | #define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7266 | #define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7267 | #define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7268 | #define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7269 | #define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7270 | #define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7271 | #define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7272 | #define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7273 | #define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7274 | #define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7275 | #define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7276 | #define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7277 | #define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7278 | #define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7279 | #define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7280 | #define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7281 | #define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7282 | #define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7283 | #define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7284 | #define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7285 | #define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7286 | #define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7287 | #define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7288 | #define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7289 | #define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7290 | #define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7291 | #define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7292 | #define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7293 | #define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7294 | #define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7295 | #define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7296 | #define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ |
AnnaBridge | 170:e95d10626187 | 7297 | #define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7298 | #define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ |
AnnaBridge | 170:e95d10626187 | 7299 | #define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7300 | #define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7301 | #define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ |
AnnaBridge | 170:e95d10626187 | 7302 | #define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ |
AnnaBridge | 170:e95d10626187 | 7303 | #define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7304 | #define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7305 | #define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7306 | #define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7307 | #define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7308 | #define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7309 | #define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7310 | #define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7311 | #define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7312 | #define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ |
AnnaBridge | 170:e95d10626187 | 7313 | #define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7314 | #define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7315 | #define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7316 | #define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7317 | #define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ |
AnnaBridge | 170:e95d10626187 | 7318 | #define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ |
AnnaBridge | 170:e95d10626187 | 7319 | #define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7320 | #define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7321 | #define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7322 | #define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ |
AnnaBridge | 170:e95d10626187 | 7323 | #define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ |
AnnaBridge | 170:e95d10626187 | 7324 | #define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ |
AnnaBridge | 170:e95d10626187 | 7325 | #define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ |
AnnaBridge | 170:e95d10626187 | 7326 | #define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ |
AnnaBridge | 170:e95d10626187 | 7327 | #define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ |
AnnaBridge | 170:e95d10626187 | 7328 | #define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ |
AnnaBridge | 170:e95d10626187 | 7329 | #define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ |
AnnaBridge | 170:e95d10626187 | 7330 | #define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ |
AnnaBridge | 170:e95d10626187 | 7331 | #define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ |
AnnaBridge | 170:e95d10626187 | 7332 | #define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ |
AnnaBridge | 170:e95d10626187 | 7333 | |
AnnaBridge | 170:e95d10626187 | 7334 | /** @} */ |
AnnaBridge | 170:e95d10626187 | 7335 | /** @} End of group EFM32GG11B520F2048IQ64_AF_Pins */ |
AnnaBridge | 170:e95d10626187 | 7336 | |
AnnaBridge | 170:e95d10626187 | 7337 | /** @} End of group EFM32GG11B520F2048IQ64 */ |
AnnaBridge | 170:e95d10626187 | 7338 | |
AnnaBridge | 170:e95d10626187 | 7339 | /** @} End of group Parts */ |
AnnaBridge | 170:e95d10626187 | 7340 | |
AnnaBridge | 170:e95d10626187 | 7341 | #ifdef __cplusplus |
AnnaBridge | 170:e95d10626187 | 7342 | } |
AnnaBridge | 170:e95d10626187 | 7343 | #endif |
AnnaBridge | 170:e95d10626187 | 7344 | #endif /* EFM32GG11B520F2048IQ64_H */ |