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TARGET_DISCO_L072CZ_LRWAN1/TOOLCHAIN_IAR/stm32l072xx.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/stm32l072xx.h@167:84c0a372a020 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**
AnnaBridge 143:86740a56073b 2 ******************************************************************************
AnnaBridge 143:86740a56073b 3 * @file stm32l072xx.h
AnnaBridge 143:86740a56073b 4 * @author MCD Application Team
AnnaBridge 143:86740a56073b 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
AnnaBridge 143:86740a56073b 6 * This file contains all the peripheral register's definitions, bits
AnnaBridge 143:86740a56073b 7 * definitions and memory mapping for stm32l072xx devices.
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 * This file contains:
AnnaBridge 143:86740a56073b 10 * - Data structures and the address mapping for all peripherals
AnnaBridge 143:86740a56073b 11 * - Peripheral's registers declarations and bits definition
AnnaBridge 143:86740a56073b 12 * - Macros to access peripheral's registers hardware
AnnaBridge 143:86740a56073b 13 *
AnnaBridge 143:86740a56073b 14 ******************************************************************************
AnnaBridge 143:86740a56073b 15 * @attention
AnnaBridge 143:86740a56073b 16 *
AnnaBridge 143:86740a56073b 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 143:86740a56073b 18 *
AnnaBridge 143:86740a56073b 19 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 20 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 21 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 143:86740a56073b 22 * this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 143:86740a56073b 24 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 143:86740a56073b 25 * and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 143:86740a56073b 27 * may be used to endorse or promote products derived from this software
AnnaBridge 143:86740a56073b 28 * without specific prior written permission.
AnnaBridge 143:86740a56073b 29 *
AnnaBridge 143:86740a56073b 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 143:86740a56073b 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 143:86740a56073b 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 143:86740a56073b 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 143:86740a56073b 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 143:86740a56073b 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 143:86740a56073b 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 40 *
AnnaBridge 143:86740a56073b 41 ******************************************************************************
AnnaBridge 143:86740a56073b 42 */
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /** @addtogroup CMSIS
AnnaBridge 143:86740a56073b 45 * @{
AnnaBridge 143:86740a56073b 46 */
AnnaBridge 143:86740a56073b 47
AnnaBridge 143:86740a56073b 48 /** @addtogroup stm32l072xx
AnnaBridge 143:86740a56073b 49 * @{
AnnaBridge 143:86740a56073b 50 */
AnnaBridge 143:86740a56073b 51
AnnaBridge 143:86740a56073b 52 #ifndef __STM32L072xx_H
AnnaBridge 143:86740a56073b 53 #define __STM32L072xx_H
AnnaBridge 143:86740a56073b 54
AnnaBridge 143:86740a56073b 55 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 56 extern "C" {
AnnaBridge 143:86740a56073b 57 #endif
AnnaBridge 143:86740a56073b 58
AnnaBridge 143:86740a56073b 59
AnnaBridge 143:86740a56073b 60 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 143:86740a56073b 61 * @{
AnnaBridge 143:86740a56073b 62 */
AnnaBridge 143:86740a56073b 63 /**
AnnaBridge 143:86740a56073b 64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
AnnaBridge 143:86740a56073b 65 */
AnnaBridge 143:86740a56073b 66 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
AnnaBridge 143:86740a56073b 67 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
AnnaBridge 143:86740a56073b 68 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
AnnaBridge 143:86740a56073b 69 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
AnnaBridge 143:86740a56073b 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 143:86740a56073b 71
AnnaBridge 143:86740a56073b 72 /**
AnnaBridge 143:86740a56073b 73 * @}
AnnaBridge 143:86740a56073b 74 */
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 143:86740a56073b 77 * @{
AnnaBridge 143:86740a56073b 78 */
AnnaBridge 143:86740a56073b 79
AnnaBridge 143:86740a56073b 80 /**
AnnaBridge 143:86740a56073b 81 * @brief stm32l072xx Interrupt Number Definition, according to the selected device
AnnaBridge 143:86740a56073b 82 * in @ref Library_configuration_section
AnnaBridge 143:86740a56073b 83 */
AnnaBridge 143:86740a56073b 84
AnnaBridge 143:86740a56073b 85 /*!< Interrupt Number Definition */
AnnaBridge 143:86740a56073b 86 typedef enum
AnnaBridge 143:86740a56073b 87 {
AnnaBridge 143:86740a56073b 88 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
AnnaBridge 143:86740a56073b 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 143:86740a56073b 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
AnnaBridge 143:86740a56073b 91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
AnnaBridge 143:86740a56073b 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
AnnaBridge 143:86740a56073b 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
AnnaBridge 143:86740a56073b 94
AnnaBridge 143:86740a56073b 95 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
AnnaBridge 143:86740a56073b 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 143:86740a56073b 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
AnnaBridge 143:86740a56073b 98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
AnnaBridge 143:86740a56073b 99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
AnnaBridge 143:86740a56073b 100 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
AnnaBridge 143:86740a56073b 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
AnnaBridge 143:86740a56073b 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
AnnaBridge 143:86740a56073b 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
AnnaBridge 143:86740a56073b 104 TSC_IRQn = 8, /*!< TSC Interrupt */
AnnaBridge 143:86740a56073b 105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
AnnaBridge 143:86740a56073b 106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
AnnaBridge 143:86740a56073b 107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
AnnaBridge 143:86740a56073b 108 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
AnnaBridge 143:86740a56073b 109 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
AnnaBridge 143:86740a56073b 110 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
AnnaBridge 143:86740a56073b 111 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
AnnaBridge 143:86740a56073b 112 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
AnnaBridge 143:86740a56073b 113 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
AnnaBridge 143:86740a56073b 114 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
AnnaBridge 143:86740a56073b 115 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
AnnaBridge 143:86740a56073b 116 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
AnnaBridge 143:86740a56073b 117 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
AnnaBridge 143:86740a56073b 118 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
AnnaBridge 143:86740a56073b 119 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
AnnaBridge 143:86740a56073b 120 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
AnnaBridge 143:86740a56073b 121 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
AnnaBridge 143:86740a56073b 122 USART1_IRQn = 27, /*!< USART1 Interrupt */
AnnaBridge 143:86740a56073b 123 USART2_IRQn = 28, /*!< USART2 Interrupt */
AnnaBridge 143:86740a56073b 124 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
AnnaBridge 143:86740a56073b 125 USB_IRQn = 31, /*!< USB global Interrupt */
AnnaBridge 143:86740a56073b 126 } IRQn_Type;
AnnaBridge 143:86740a56073b 127
AnnaBridge 143:86740a56073b 128 /**
AnnaBridge 143:86740a56073b 129 * @}
AnnaBridge 143:86740a56073b 130 */
AnnaBridge 143:86740a56073b 131
AnnaBridge 143:86740a56073b 132 #include "core_cm0plus.h"
AnnaBridge 143:86740a56073b 133 #include "system_stm32l0xx.h"
AnnaBridge 143:86740a56073b 134 #include <stdint.h>
AnnaBridge 143:86740a56073b 135
AnnaBridge 143:86740a56073b 136 /** @addtogroup Peripheral_registers_structures
AnnaBridge 143:86740a56073b 137 * @{
AnnaBridge 143:86740a56073b 138 */
AnnaBridge 143:86740a56073b 139
AnnaBridge 143:86740a56073b 140 /**
AnnaBridge 143:86740a56073b 141 * @brief Analog to Digital Converter
AnnaBridge 143:86740a56073b 142 */
AnnaBridge 143:86740a56073b 143
AnnaBridge 143:86740a56073b 144 typedef struct
AnnaBridge 143:86740a56073b 145 {
AnnaBridge 143:86740a56073b 146 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
AnnaBridge 143:86740a56073b 147 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
AnnaBridge 143:86740a56073b 148 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
AnnaBridge 143:86740a56073b 149 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
AnnaBridge 143:86740a56073b 150 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
AnnaBridge 143:86740a56073b 151 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
AnnaBridge 143:86740a56073b 152 uint32_t RESERVED1; /*!< Reserved, 0x18 */
AnnaBridge 143:86740a56073b 153 uint32_t RESERVED2; /*!< Reserved, 0x1C */
AnnaBridge 143:86740a56073b 154 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
AnnaBridge 143:86740a56073b 155 uint32_t RESERVED3; /*!< Reserved, 0x24 */
AnnaBridge 143:86740a56073b 156 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
AnnaBridge 143:86740a56073b 157 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
AnnaBridge 143:86740a56073b 158 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
AnnaBridge 143:86740a56073b 159 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
AnnaBridge 143:86740a56073b 160 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
AnnaBridge 143:86740a56073b 161 } ADC_TypeDef;
AnnaBridge 143:86740a56073b 162
AnnaBridge 143:86740a56073b 163 typedef struct
AnnaBridge 143:86740a56073b 164 {
AnnaBridge 143:86740a56073b 165 __IO uint32_t CCR;
AnnaBridge 143:86740a56073b 166 } ADC_Common_TypeDef;
AnnaBridge 143:86740a56073b 167
AnnaBridge 143:86740a56073b 168
AnnaBridge 143:86740a56073b 169 /**
AnnaBridge 143:86740a56073b 170 * @brief Comparator
AnnaBridge 143:86740a56073b 171 */
AnnaBridge 143:86740a56073b 172
AnnaBridge 143:86740a56073b 173 typedef struct
AnnaBridge 143:86740a56073b 174 {
AnnaBridge 143:86740a56073b 175 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 176 } COMP_TypeDef;
AnnaBridge 143:86740a56073b 177
AnnaBridge 143:86740a56073b 178 typedef struct
AnnaBridge 143:86740a56073b 179 {
AnnaBridge 143:86740a56073b 180 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 181 } COMP_Common_TypeDef;
AnnaBridge 143:86740a56073b 182
AnnaBridge 143:86740a56073b 183
AnnaBridge 143:86740a56073b 184 /**
AnnaBridge 143:86740a56073b 185 * @brief CRC calculation unit
AnnaBridge 143:86740a56073b 186 */
AnnaBridge 143:86740a56073b 187
AnnaBridge 143:86740a56073b 188 typedef struct
AnnaBridge 143:86740a56073b 189 {
AnnaBridge 143:86740a56073b 190 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 191 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 192 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 143:86740a56073b 193 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 143:86740a56073b 194 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 195 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 143:86740a56073b 196 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 197 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 198 } CRC_TypeDef;
AnnaBridge 143:86740a56073b 199
AnnaBridge 143:86740a56073b 200 /**
AnnaBridge 143:86740a56073b 201 * @brief Clock Recovery System
AnnaBridge 143:86740a56073b 202 */
AnnaBridge 143:86740a56073b 203
AnnaBridge 143:86740a56073b 204 typedef struct
AnnaBridge 143:86740a56073b 205 {
AnnaBridge 143:86740a56073b 206 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 207 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 208 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 209 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 210 } CRS_TypeDef;
AnnaBridge 143:86740a56073b 211
AnnaBridge 143:86740a56073b 212 /**
AnnaBridge 143:86740a56073b 213 * @brief Digital to Analog Converter
AnnaBridge 143:86740a56073b 214 */
AnnaBridge 143:86740a56073b 215
AnnaBridge 143:86740a56073b 216 typedef struct
AnnaBridge 143:86740a56073b 217 {
AnnaBridge 143:86740a56073b 218 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 219 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 220 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 221 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 222 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 223 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 224 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 225 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 226 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 227 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 228 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 229 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 143:86740a56073b 230 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 143:86740a56073b 231 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 143:86740a56073b 232 } DAC_TypeDef;
AnnaBridge 143:86740a56073b 233
AnnaBridge 143:86740a56073b 234 /**
AnnaBridge 143:86740a56073b 235 * @brief Debug MCU
AnnaBridge 143:86740a56073b 236 */
AnnaBridge 143:86740a56073b 237
AnnaBridge 143:86740a56073b 238 typedef struct
AnnaBridge 143:86740a56073b 239 {
AnnaBridge 143:86740a56073b 240 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 241 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 242 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 243 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 244 }DBGMCU_TypeDef;
AnnaBridge 143:86740a56073b 245
AnnaBridge 143:86740a56073b 246 /**
AnnaBridge 143:86740a56073b 247 * @brief DMA Controller
AnnaBridge 143:86740a56073b 248 */
AnnaBridge 143:86740a56073b 249
AnnaBridge 143:86740a56073b 250 typedef struct
AnnaBridge 143:86740a56073b 251 {
AnnaBridge 143:86740a56073b 252 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 143:86740a56073b 253 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 143:86740a56073b 254 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 143:86740a56073b 255 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
AnnaBridge 143:86740a56073b 256 } DMA_Channel_TypeDef;
AnnaBridge 143:86740a56073b 257
AnnaBridge 143:86740a56073b 258 typedef struct
AnnaBridge 143:86740a56073b 259 {
AnnaBridge 143:86740a56073b 260 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 261 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 262 } DMA_TypeDef;
AnnaBridge 143:86740a56073b 263
AnnaBridge 143:86740a56073b 264 typedef struct
AnnaBridge 143:86740a56073b 265 {
AnnaBridge 143:86740a56073b 266 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
AnnaBridge 143:86740a56073b 267 } DMA_Request_TypeDef;
AnnaBridge 143:86740a56073b 268
AnnaBridge 143:86740a56073b 269 /**
AnnaBridge 143:86740a56073b 270 * @brief External Interrupt/Event Controller
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272
AnnaBridge 143:86740a56073b 273 typedef struct
AnnaBridge 143:86740a56073b 274 {
AnnaBridge 143:86740a56073b 275 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 276 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 277 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
AnnaBridge 143:86740a56073b 278 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 279 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 280 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 281 }EXTI_TypeDef;
AnnaBridge 143:86740a56073b 282
AnnaBridge 143:86740a56073b 283 /**
AnnaBridge 143:86740a56073b 284 * @brief FLASH Registers
AnnaBridge 143:86740a56073b 285 */
AnnaBridge 143:86740a56073b 286 typedef struct
AnnaBridge 143:86740a56073b 287 {
AnnaBridge 143:86740a56073b 288 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 289 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 290 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 291 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
AnnaBridge 143:86740a56073b 292 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 293 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 294 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 295 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
AnnaBridge 143:86740a56073b 296 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 297 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 298 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
AnnaBridge 143:86740a56073b 299 } FLASH_TypeDef;
AnnaBridge 143:86740a56073b 300
AnnaBridge 143:86740a56073b 301
AnnaBridge 143:86740a56073b 302 /**
AnnaBridge 143:86740a56073b 303 * @brief Option Bytes Registers
AnnaBridge 143:86740a56073b 304 */
AnnaBridge 143:86740a56073b 305 typedef struct
AnnaBridge 143:86740a56073b 306 {
AnnaBridge 143:86740a56073b 307 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 308 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 309 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
AnnaBridge 143:86740a56073b 310 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
AnnaBridge 143:86740a56073b 311 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
AnnaBridge 143:86740a56073b 312 } OB_TypeDef;
AnnaBridge 143:86740a56073b 313
AnnaBridge 143:86740a56073b 314
AnnaBridge 143:86740a56073b 315 /**
AnnaBridge 143:86740a56073b 316 * @brief General Purpose IO
AnnaBridge 143:86740a56073b 317 */
AnnaBridge 143:86740a56073b 318
AnnaBridge 143:86740a56073b 319 typedef struct
AnnaBridge 143:86740a56073b 320 {
AnnaBridge 143:86740a56073b 321 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 322 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 323 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 324 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 325 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 326 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 327 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 328 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 329 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
AnnaBridge 143:86740a56073b 330 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 331 }GPIO_TypeDef;
AnnaBridge 143:86740a56073b 332
AnnaBridge 143:86740a56073b 333 /**
AnnaBridge 143:86740a56073b 334 * @brief LPTIMIMER
AnnaBridge 143:86740a56073b 335 */
AnnaBridge 143:86740a56073b 336 typedef struct
AnnaBridge 143:86740a56073b 337 {
AnnaBridge 143:86740a56073b 338 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 339 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 340 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 341 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 342 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 343 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 344 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 345 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 346 } LPTIM_TypeDef;
AnnaBridge 143:86740a56073b 347
AnnaBridge 143:86740a56073b 348 /**
AnnaBridge 143:86740a56073b 349 * @brief SysTem Configuration
AnnaBridge 143:86740a56073b 350 */
AnnaBridge 143:86740a56073b 351
AnnaBridge 143:86740a56073b 352 typedef struct
AnnaBridge 143:86740a56073b 353 {
AnnaBridge 143:86740a56073b 354 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 355 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 356 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
AnnaBridge 143:86740a56073b 357 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
AnnaBridge 143:86740a56073b 358 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 359 } SYSCFG_TypeDef;
AnnaBridge 143:86740a56073b 360
AnnaBridge 143:86740a56073b 361
AnnaBridge 143:86740a56073b 362
AnnaBridge 143:86740a56073b 363 /**
AnnaBridge 143:86740a56073b 364 * @brief Inter-integrated Circuit Interface
AnnaBridge 143:86740a56073b 365 */
AnnaBridge 143:86740a56073b 366
AnnaBridge 143:86740a56073b 367 typedef struct
AnnaBridge 143:86740a56073b 368 {
AnnaBridge 143:86740a56073b 369 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 370 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 371 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 372 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 373 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 374 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 375 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 376 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 377 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 378 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 379 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 380 }I2C_TypeDef;
AnnaBridge 143:86740a56073b 381
AnnaBridge 143:86740a56073b 382
AnnaBridge 143:86740a56073b 383 /**
AnnaBridge 143:86740a56073b 384 * @brief Independent WATCHDOG
AnnaBridge 143:86740a56073b 385 */
AnnaBridge 143:86740a56073b 386 typedef struct
AnnaBridge 143:86740a56073b 387 {
AnnaBridge 143:86740a56073b 388 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 389 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 390 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 391 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 392 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 393 } IWDG_TypeDef;
AnnaBridge 143:86740a56073b 394
AnnaBridge 143:86740a56073b 395 /**
AnnaBridge 143:86740a56073b 396 * @brief MIFARE Firewall
AnnaBridge 143:86740a56073b 397 */
AnnaBridge 143:86740a56073b 398 typedef struct
AnnaBridge 143:86740a56073b 399 {
AnnaBridge 143:86740a56073b 400 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 401 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 402 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 403 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 404 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 405 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 406 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 407 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 408 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 409
AnnaBridge 143:86740a56073b 410 } FIREWALL_TypeDef;
AnnaBridge 143:86740a56073b 411
AnnaBridge 143:86740a56073b 412 /**
AnnaBridge 143:86740a56073b 413 * @brief Power Control
AnnaBridge 143:86740a56073b 414 */
AnnaBridge 143:86740a56073b 415 typedef struct
AnnaBridge 143:86740a56073b 416 {
AnnaBridge 143:86740a56073b 417 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 418 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 419 } PWR_TypeDef;
AnnaBridge 143:86740a56073b 420
AnnaBridge 143:86740a56073b 421 /**
AnnaBridge 143:86740a56073b 422 * @brief Reset and Clock Control
AnnaBridge 143:86740a56073b 423 */
AnnaBridge 143:86740a56073b 424 typedef struct
AnnaBridge 143:86740a56073b 425 {
AnnaBridge 143:86740a56073b 426 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 427 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 428 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 429 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 430 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 431 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 432 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 433 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 434 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 435 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 436 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 437 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
AnnaBridge 143:86740a56073b 438 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
AnnaBridge 143:86740a56073b 439 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
AnnaBridge 143:86740a56073b 440 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
AnnaBridge 143:86740a56073b 441 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
AnnaBridge 143:86740a56073b 442 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
AnnaBridge 143:86740a56073b 443 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
AnnaBridge 143:86740a56073b 444 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
AnnaBridge 143:86740a56073b 445 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
AnnaBridge 143:86740a56073b 446 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
AnnaBridge 143:86740a56073b 447 } RCC_TypeDef;
AnnaBridge 143:86740a56073b 448
AnnaBridge 143:86740a56073b 449 /**
AnnaBridge 143:86740a56073b 450 * @brief Random numbers generator
AnnaBridge 143:86740a56073b 451 */
AnnaBridge 143:86740a56073b 452 typedef struct
AnnaBridge 143:86740a56073b 453 {
AnnaBridge 143:86740a56073b 454 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 455 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 456 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 457 } RNG_TypeDef;
AnnaBridge 143:86740a56073b 458
AnnaBridge 143:86740a56073b 459 /**
AnnaBridge 143:86740a56073b 460 * @brief Real-Time Clock
AnnaBridge 143:86740a56073b 461 */
AnnaBridge 143:86740a56073b 462 typedef struct
AnnaBridge 143:86740a56073b 463 {
AnnaBridge 143:86740a56073b 464 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 465 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 466 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 467 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 468 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 469 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 470 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 471 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 472 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 473 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 474 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 475 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 143:86740a56073b 476 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 143:86740a56073b 477 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 143:86740a56073b 478 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 143:86740a56073b 479 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 143:86740a56073b 480 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
AnnaBridge 143:86740a56073b 481 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 143:86740a56073b 482 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 143:86740a56073b 483 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
AnnaBridge 143:86740a56073b 484 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 143:86740a56073b 485 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 143:86740a56073b 486 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 143:86740a56073b 487 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 143:86740a56073b 488 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 143:86740a56073b 489 } RTC_TypeDef;
AnnaBridge 143:86740a56073b 490
AnnaBridge 143:86740a56073b 491
AnnaBridge 143:86740a56073b 492 /**
AnnaBridge 143:86740a56073b 493 * @brief Serial Peripheral Interface
AnnaBridge 143:86740a56073b 494 */
AnnaBridge 143:86740a56073b 495 typedef struct
AnnaBridge 143:86740a56073b 496 {
AnnaBridge 143:86740a56073b 497 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 143:86740a56073b 498 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 499 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 500 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 501 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 143:86740a56073b 502 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 143:86740a56073b 503 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 143:86740a56073b 504 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 505 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 506 } SPI_TypeDef;
AnnaBridge 143:86740a56073b 507
AnnaBridge 143:86740a56073b 508 /**
AnnaBridge 143:86740a56073b 509 * @brief TIM
AnnaBridge 143:86740a56073b 510 */
AnnaBridge 143:86740a56073b 511 typedef struct
AnnaBridge 143:86740a56073b 512 {
AnnaBridge 143:86740a56073b 513 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 514 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 515 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 516 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 517 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 518 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 519 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 520 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 521 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 522 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 523 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 524 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 143:86740a56073b 525 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
AnnaBridge 143:86740a56073b 526 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 143:86740a56073b 527 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 143:86740a56073b 528 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 143:86740a56073b 529 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 143:86740a56073b 530 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
AnnaBridge 143:86740a56073b 531 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 143:86740a56073b 532 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
AnnaBridge 143:86740a56073b 533 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 143:86740a56073b 534 } TIM_TypeDef;
AnnaBridge 143:86740a56073b 535
AnnaBridge 143:86740a56073b 536 /**
AnnaBridge 143:86740a56073b 537 * @brief Touch Sensing Controller (TSC)
AnnaBridge 143:86740a56073b 538 */
AnnaBridge 143:86740a56073b 539 typedef struct
AnnaBridge 143:86740a56073b 540 {
AnnaBridge 143:86740a56073b 541 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 542 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 543 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 544 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 545 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 546 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 547 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 548 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 549 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 550 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 551 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 552 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
AnnaBridge 143:86740a56073b 553 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
AnnaBridge 143:86740a56073b 554 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
AnnaBridge 143:86740a56073b 555 } TSC_TypeDef;
AnnaBridge 143:86740a56073b 556
AnnaBridge 143:86740a56073b 557 /**
AnnaBridge 143:86740a56073b 558 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 143:86740a56073b 559 */
AnnaBridge 143:86740a56073b 560 typedef struct
AnnaBridge 143:86740a56073b 561 {
AnnaBridge 143:86740a56073b 562 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 563 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 564 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 565 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 566 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 567 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 568 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 569 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 570 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 143:86740a56073b 571 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 143:86740a56073b 572 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 143:86740a56073b 573 } USART_TypeDef;
AnnaBridge 143:86740a56073b 574
AnnaBridge 143:86740a56073b 575 /**
AnnaBridge 143:86740a56073b 576 * @brief Window WATCHDOG
AnnaBridge 143:86740a56073b 577 */
AnnaBridge 143:86740a56073b 578 typedef struct
AnnaBridge 143:86740a56073b 579 {
AnnaBridge 143:86740a56073b 580 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 581 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 582 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 583 } WWDG_TypeDef;
AnnaBridge 143:86740a56073b 584
AnnaBridge 143:86740a56073b 585 /**
AnnaBridge 143:86740a56073b 586 * @brief Universal Serial Bus Full Speed Device
AnnaBridge 143:86740a56073b 587 */
AnnaBridge 143:86740a56073b 588 typedef struct
AnnaBridge 143:86740a56073b 589 {
AnnaBridge 143:86740a56073b 590 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
AnnaBridge 143:86740a56073b 591 __IO uint16_t RESERVED0; /*!< Reserved */
AnnaBridge 143:86740a56073b 592 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
AnnaBridge 143:86740a56073b 593 __IO uint16_t RESERVED1; /*!< Reserved */
AnnaBridge 143:86740a56073b 594 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
AnnaBridge 143:86740a56073b 595 __IO uint16_t RESERVED2; /*!< Reserved */
AnnaBridge 143:86740a56073b 596 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
AnnaBridge 143:86740a56073b 597 __IO uint16_t RESERVED3; /*!< Reserved */
AnnaBridge 143:86740a56073b 598 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
AnnaBridge 143:86740a56073b 599 __IO uint16_t RESERVED4; /*!< Reserved */
AnnaBridge 143:86740a56073b 600 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
AnnaBridge 143:86740a56073b 601 __IO uint16_t RESERVED5; /*!< Reserved */
AnnaBridge 143:86740a56073b 602 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
AnnaBridge 143:86740a56073b 603 __IO uint16_t RESERVED6; /*!< Reserved */
AnnaBridge 143:86740a56073b 604 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
AnnaBridge 143:86740a56073b 605 __IO uint16_t RESERVED7[17]; /*!< Reserved */
AnnaBridge 143:86740a56073b 606 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
AnnaBridge 143:86740a56073b 607 __IO uint16_t RESERVED8; /*!< Reserved */
AnnaBridge 143:86740a56073b 608 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
AnnaBridge 143:86740a56073b 609 __IO uint16_t RESERVED9; /*!< Reserved */
AnnaBridge 143:86740a56073b 610 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
AnnaBridge 143:86740a56073b 611 __IO uint16_t RESERVEDA; /*!< Reserved */
AnnaBridge 143:86740a56073b 612 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
AnnaBridge 143:86740a56073b 613 __IO uint16_t RESERVEDB; /*!< Reserved */
AnnaBridge 143:86740a56073b 614 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
AnnaBridge 143:86740a56073b 615 __IO uint16_t RESERVEDC; /*!< Reserved */
AnnaBridge 143:86740a56073b 616 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
AnnaBridge 143:86740a56073b 617 __IO uint16_t RESERVEDD; /*!< Reserved */
AnnaBridge 143:86740a56073b 618 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
AnnaBridge 143:86740a56073b 619 __IO uint16_t RESERVEDE; /*!< Reserved */
AnnaBridge 143:86740a56073b 620 } USB_TypeDef;
AnnaBridge 143:86740a56073b 621
AnnaBridge 143:86740a56073b 622 /**
AnnaBridge 143:86740a56073b 623 * @}
AnnaBridge 143:86740a56073b 624 */
AnnaBridge 143:86740a56073b 625
AnnaBridge 143:86740a56073b 626 /** @addtogroup Peripheral_memory_map
AnnaBridge 143:86740a56073b 627 * @{
AnnaBridge 143:86740a56073b 628 */
AnnaBridge 143:86740a56073b 629 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
AnnaBridge 143:86740a56073b 630 #define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
AnnaBridge 143:86740a56073b 631 #define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
AnnaBridge 143:86740a56073b 632 #define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
AnnaBridge 143:86740a56073b 633 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
AnnaBridge 143:86740a56073b 634 #define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
AnnaBridge 143:86740a56073b 635 #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
AnnaBridge 143:86740a56073b 636 #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
AnnaBridge 143:86740a56073b 637 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
AnnaBridge 143:86740a56073b 638 #define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */
AnnaBridge 143:86740a56073b 639
AnnaBridge 143:86740a56073b 640 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
AnnaBridge 143:86740a56073b 641
AnnaBridge 143:86740a56073b 642 /*!< Peripheral memory map */
AnnaBridge 143:86740a56073b 643 #define APBPERIPH_BASE PERIPH_BASE
AnnaBridge 143:86740a56073b 644 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 143:86740a56073b 645 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 143:86740a56073b 646
AnnaBridge 143:86740a56073b 647 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
AnnaBridge 143:86740a56073b 648 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400U)
AnnaBridge 143:86740a56073b 649 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
AnnaBridge 143:86740a56073b 650 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400U)
AnnaBridge 143:86740a56073b 651 #define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
AnnaBridge 143:86740a56073b 652 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
AnnaBridge 143:86740a56073b 653 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
AnnaBridge 143:86740a56073b 654 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
AnnaBridge 143:86740a56073b 655 #define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
AnnaBridge 143:86740a56073b 656 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
AnnaBridge 143:86740a56073b 657 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00U)
AnnaBridge 143:86740a56073b 658 #define USART5_BASE (APBPERIPH_BASE + 0x00005000U)
AnnaBridge 143:86740a56073b 659 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
AnnaBridge 143:86740a56073b 660 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
AnnaBridge 143:86740a56073b 661 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
AnnaBridge 143:86740a56073b 662 #define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
AnnaBridge 143:86740a56073b 663 #define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
AnnaBridge 143:86740a56073b 664 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
AnnaBridge 143:86740a56073b 665 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800U)
AnnaBridge 143:86740a56073b 666
AnnaBridge 143:86740a56073b 667 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
AnnaBridge 143:86740a56073b 668 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
AnnaBridge 143:86740a56073b 669 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
AnnaBridge 143:86740a56073b 670 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
AnnaBridge 143:86740a56073b 671 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
AnnaBridge 143:86740a56073b 672 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
AnnaBridge 143:86740a56073b 673 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
AnnaBridge 143:86740a56073b 674 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
AnnaBridge 143:86740a56073b 675 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
AnnaBridge 143:86740a56073b 676 #define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
AnnaBridge 143:86740a56073b 677 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
AnnaBridge 143:86740a56073b 678 #define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
AnnaBridge 143:86740a56073b 679 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
AnnaBridge 143:86740a56073b 680
AnnaBridge 143:86740a56073b 681 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
AnnaBridge 143:86740a56073b 682 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
AnnaBridge 143:86740a56073b 683 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
AnnaBridge 143:86740a56073b 684 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
AnnaBridge 143:86740a56073b 685 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
AnnaBridge 143:86740a56073b 686 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
AnnaBridge 143:86740a56073b 687 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
AnnaBridge 143:86740a56073b 688 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
AnnaBridge 143:86740a56073b 689 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
AnnaBridge 143:86740a56073b 690
AnnaBridge 143:86740a56073b 691
AnnaBridge 143:86740a56073b 692 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
AnnaBridge 143:86740a56073b 693 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
AnnaBridge 143:86740a56073b 694 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
AnnaBridge 143:86740a56073b 695 #define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
AnnaBridge 143:86740a56073b 696 #define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
AnnaBridge 143:86740a56073b 697 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
AnnaBridge 143:86740a56073b 698 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
AnnaBridge 143:86740a56073b 699 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
AnnaBridge 143:86740a56073b 700
AnnaBridge 143:86740a56073b 701 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
AnnaBridge 143:86740a56073b 702 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
AnnaBridge 143:86740a56073b 703 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
AnnaBridge 143:86740a56073b 704 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
AnnaBridge 143:86740a56073b 705 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U)
AnnaBridge 143:86740a56073b 706 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
AnnaBridge 143:86740a56073b 707
AnnaBridge 143:86740a56073b 708 /**
AnnaBridge 143:86740a56073b 709 * @}
AnnaBridge 143:86740a56073b 710 */
AnnaBridge 143:86740a56073b 711
AnnaBridge 143:86740a56073b 712 /** @addtogroup Peripheral_declaration
AnnaBridge 143:86740a56073b 713 * @{
AnnaBridge 143:86740a56073b 714 */
AnnaBridge 143:86740a56073b 715
AnnaBridge 143:86740a56073b 716 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 143:86740a56073b 717 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 143:86740a56073b 718 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 143:86740a56073b 719 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 143:86740a56073b 720 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 143:86740a56073b 721 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 143:86740a56073b 722 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 143:86740a56073b 723 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 143:86740a56073b 724 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 143:86740a56073b 725 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
AnnaBridge 143:86740a56073b 726 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 143:86740a56073b 727 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 143:86740a56073b 728 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 143:86740a56073b 729 #define CRS ((CRS_TypeDef *) CRS_BASE)
AnnaBridge 143:86740a56073b 730 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 143:86740a56073b 731 #define DAC ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 143:86740a56073b 732 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 143:86740a56073b 733 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 143:86740a56073b 734 #define USART4 ((USART_TypeDef *) USART4_BASE)
AnnaBridge 143:86740a56073b 735 #define USART5 ((USART_TypeDef *) USART5_BASE)
AnnaBridge 143:86740a56073b 736
AnnaBridge 143:86740a56073b 737 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 143:86740a56073b 738 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
AnnaBridge 143:86740a56073b 739 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
AnnaBridge 143:86740a56073b 740 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 143:86740a56073b 741 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
AnnaBridge 143:86740a56073b 742 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
AnnaBridge 143:86740a56073b 743 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
AnnaBridge 143:86740a56073b 744 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 143:86740a56073b 745 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 143:86740a56073b 746 /* Legacy defines */
AnnaBridge 143:86740a56073b 747 #define ADC ADC1_COMMON
AnnaBridge 143:86740a56073b 748 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 143:86740a56073b 749 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 143:86740a56073b 750 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 143:86740a56073b 751
AnnaBridge 143:86740a56073b 752 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 143:86740a56073b 753 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
AnnaBridge 143:86740a56073b 754 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
AnnaBridge 143:86740a56073b 755 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
AnnaBridge 143:86740a56073b 756 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
AnnaBridge 143:86740a56073b 757 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
AnnaBridge 143:86740a56073b 758 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
AnnaBridge 143:86740a56073b 759 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
AnnaBridge 143:86740a56073b 760 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
AnnaBridge 143:86740a56073b 761
AnnaBridge 143:86740a56073b 762
AnnaBridge 143:86740a56073b 763 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 143:86740a56073b 764 #define OB ((OB_TypeDef *) OB_BASE)
AnnaBridge 143:86740a56073b 765 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 143:86740a56073b 766 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 143:86740a56073b 767 #define TSC ((TSC_TypeDef *) TSC_BASE)
AnnaBridge 143:86740a56073b 768 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 143:86740a56073b 769
AnnaBridge 143:86740a56073b 770 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 143:86740a56073b 771 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 143:86740a56073b 772 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 143:86740a56073b 773 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 143:86740a56073b 774 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 143:86740a56073b 775 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 143:86740a56073b 776
AnnaBridge 143:86740a56073b 777 #define USB ((USB_TypeDef *) USB_BASE)
AnnaBridge 143:86740a56073b 778
AnnaBridge 143:86740a56073b 779 /**
AnnaBridge 143:86740a56073b 780 * @}
AnnaBridge 143:86740a56073b 781 */
AnnaBridge 143:86740a56073b 782
AnnaBridge 143:86740a56073b 783 /** @addtogroup Exported_constants
AnnaBridge 143:86740a56073b 784 * @{
AnnaBridge 143:86740a56073b 785 */
AnnaBridge 143:86740a56073b 786
AnnaBridge 143:86740a56073b 787 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 143:86740a56073b 788 * @{
AnnaBridge 143:86740a56073b 789 */
AnnaBridge 143:86740a56073b 790
AnnaBridge 143:86740a56073b 791 /******************************************************************************/
AnnaBridge 143:86740a56073b 792 /* Peripheral Registers Bits Definition */
AnnaBridge 143:86740a56073b 793 /******************************************************************************/
AnnaBridge 143:86740a56073b 794 /******************************************************************************/
AnnaBridge 143:86740a56073b 795 /* */
AnnaBridge 143:86740a56073b 796 /* Analog to Digital Converter (ADC) */
AnnaBridge 143:86740a56073b 797 /* */
AnnaBridge 143:86740a56073b 798 /******************************************************************************/
AnnaBridge 143:86740a56073b 799 /******************** Bits definition for ADC_ISR register ******************/
AnnaBridge 143:86740a56073b 800 #define ADC_ISR_EOCAL_Pos (11U)
AnnaBridge 143:86740a56073b 801 #define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 802 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
AnnaBridge 143:86740a56073b 803 #define ADC_ISR_AWD_Pos (7U)
AnnaBridge 143:86740a56073b 804 #define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 805 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
AnnaBridge 143:86740a56073b 806 #define ADC_ISR_OVR_Pos (4U)
AnnaBridge 143:86740a56073b 807 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 808 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
AnnaBridge 143:86740a56073b 809 #define ADC_ISR_EOSEQ_Pos (3U)
AnnaBridge 143:86740a56073b 810 #define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 811 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
AnnaBridge 143:86740a56073b 812 #define ADC_ISR_EOC_Pos (2U)
AnnaBridge 143:86740a56073b 813 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 814 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
AnnaBridge 143:86740a56073b 815 #define ADC_ISR_EOSMP_Pos (1U)
AnnaBridge 143:86740a56073b 816 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 817 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
AnnaBridge 143:86740a56073b 818 #define ADC_ISR_ADRDY_Pos (0U)
AnnaBridge 143:86740a56073b 819 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 820 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
AnnaBridge 143:86740a56073b 821
AnnaBridge 143:86740a56073b 822 /* Old EOSEQ bit definition, maintained for legacy purpose */
AnnaBridge 143:86740a56073b 823 #define ADC_ISR_EOS ADC_ISR_EOSEQ
AnnaBridge 143:86740a56073b 824
AnnaBridge 143:86740a56073b 825 /******************** Bits definition for ADC_IER register ******************/
AnnaBridge 143:86740a56073b 826 #define ADC_IER_EOCALIE_Pos (11U)
AnnaBridge 143:86740a56073b 827 #define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 828 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
AnnaBridge 143:86740a56073b 829 #define ADC_IER_AWDIE_Pos (7U)
AnnaBridge 143:86740a56073b 830 #define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 831 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
AnnaBridge 143:86740a56073b 832 #define ADC_IER_OVRIE_Pos (4U)
AnnaBridge 143:86740a56073b 833 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 834 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
AnnaBridge 143:86740a56073b 835 #define ADC_IER_EOSEQIE_Pos (3U)
AnnaBridge 143:86740a56073b 836 #define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 837 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
AnnaBridge 143:86740a56073b 838 #define ADC_IER_EOCIE_Pos (2U)
AnnaBridge 143:86740a56073b 839 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 840 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
AnnaBridge 143:86740a56073b 841 #define ADC_IER_EOSMPIE_Pos (1U)
AnnaBridge 143:86740a56073b 842 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 843 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
AnnaBridge 143:86740a56073b 844 #define ADC_IER_ADRDYIE_Pos (0U)
AnnaBridge 143:86740a56073b 845 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 846 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
AnnaBridge 143:86740a56073b 847
AnnaBridge 143:86740a56073b 848 /* Old EOSEQIE bit definition, maintained for legacy purpose */
AnnaBridge 143:86740a56073b 849 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
AnnaBridge 143:86740a56073b 850
AnnaBridge 143:86740a56073b 851 /******************** Bits definition for ADC_CR register *******************/
AnnaBridge 143:86740a56073b 852 #define ADC_CR_ADCAL_Pos (31U)
AnnaBridge 143:86740a56073b 853 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 854 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
AnnaBridge 143:86740a56073b 855 #define ADC_CR_ADVREGEN_Pos (28U)
AnnaBridge 143:86740a56073b 856 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 857 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
AnnaBridge 143:86740a56073b 858 #define ADC_CR_ADSTP_Pos (4U)
AnnaBridge 143:86740a56073b 859 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 860 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
AnnaBridge 143:86740a56073b 861 #define ADC_CR_ADSTART_Pos (2U)
AnnaBridge 143:86740a56073b 862 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 863 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
AnnaBridge 143:86740a56073b 864 #define ADC_CR_ADDIS_Pos (1U)
AnnaBridge 143:86740a56073b 865 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 866 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
AnnaBridge 143:86740a56073b 867 #define ADC_CR_ADEN_Pos (0U)
AnnaBridge 143:86740a56073b 868 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 869 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
AnnaBridge 143:86740a56073b 870
AnnaBridge 143:86740a56073b 871 /******************* Bits definition for ADC_CFGR1 register *****************/
AnnaBridge 143:86740a56073b 872 #define ADC_CFGR1_AWDCH_Pos (26U)
AnnaBridge 143:86740a56073b 873 #define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
AnnaBridge 143:86740a56073b 874 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 143:86740a56073b 875 #define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 876 #define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 877 #define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 878 #define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 879 #define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 880 #define ADC_CFGR1_AWDEN_Pos (23U)
AnnaBridge 143:86740a56073b 881 #define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 882 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
AnnaBridge 143:86740a56073b 883 #define ADC_CFGR1_AWDSGL_Pos (22U)
AnnaBridge 143:86740a56073b 884 #define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 885 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
AnnaBridge 143:86740a56073b 886 #define ADC_CFGR1_DISCEN_Pos (16U)
AnnaBridge 143:86740a56073b 887 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 888 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
AnnaBridge 143:86740a56073b 889 #define ADC_CFGR1_AUTOFF_Pos (15U)
AnnaBridge 143:86740a56073b 890 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 891 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
AnnaBridge 143:86740a56073b 892 #define ADC_CFGR1_WAIT_Pos (14U)
AnnaBridge 143:86740a56073b 893 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 894 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
AnnaBridge 143:86740a56073b 895 #define ADC_CFGR1_CONT_Pos (13U)
AnnaBridge 143:86740a56073b 896 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 897 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
AnnaBridge 143:86740a56073b 898 #define ADC_CFGR1_OVRMOD_Pos (12U)
AnnaBridge 143:86740a56073b 899 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 900 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
AnnaBridge 143:86740a56073b 901 #define ADC_CFGR1_EXTEN_Pos (10U)
AnnaBridge 143:86740a56073b 902 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 903 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
AnnaBridge 143:86740a56073b 904 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 905 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 906 #define ADC_CFGR1_EXTSEL_Pos (6U)
AnnaBridge 143:86740a56073b 907 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
AnnaBridge 143:86740a56073b 908 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
AnnaBridge 143:86740a56073b 909 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 910 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 911 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 912 #define ADC_CFGR1_ALIGN_Pos (5U)
AnnaBridge 143:86740a56073b 913 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 914 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
AnnaBridge 143:86740a56073b 915 #define ADC_CFGR1_RES_Pos (3U)
AnnaBridge 143:86740a56073b 916 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
AnnaBridge 143:86740a56073b 917 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
AnnaBridge 143:86740a56073b 918 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 919 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 920 #define ADC_CFGR1_SCANDIR_Pos (2U)
AnnaBridge 143:86740a56073b 921 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 922 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
AnnaBridge 143:86740a56073b 923 #define ADC_CFGR1_DMACFG_Pos (1U)
AnnaBridge 143:86740a56073b 924 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 925 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
AnnaBridge 143:86740a56073b 926 #define ADC_CFGR1_DMAEN_Pos (0U)
AnnaBridge 143:86740a56073b 927 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 928 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
AnnaBridge 143:86740a56073b 929
AnnaBridge 143:86740a56073b 930 /* Old WAIT bit definition, maintained for legacy purpose */
AnnaBridge 143:86740a56073b 931 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
AnnaBridge 143:86740a56073b 932
AnnaBridge 143:86740a56073b 933 /******************* Bits definition for ADC_CFGR2 register *****************/
AnnaBridge 143:86740a56073b 934 #define ADC_CFGR2_TOVS_Pos (9U)
AnnaBridge 143:86740a56073b 935 #define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
AnnaBridge 143:86740a56073b 936 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
AnnaBridge 143:86740a56073b 937 #define ADC_CFGR2_OVSS_Pos (5U)
AnnaBridge 143:86740a56073b 938 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
AnnaBridge 143:86740a56073b 939 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
AnnaBridge 143:86740a56073b 940 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 941 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 942 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 943 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 944 #define ADC_CFGR2_OVSR_Pos (2U)
AnnaBridge 143:86740a56073b 945 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
AnnaBridge 143:86740a56073b 946 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
AnnaBridge 143:86740a56073b 947 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 948 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 949 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 950 #define ADC_CFGR2_OVSE_Pos (0U)
AnnaBridge 143:86740a56073b 951 #define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 952 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
AnnaBridge 143:86740a56073b 953 #define ADC_CFGR2_CKMODE_Pos (30U)
AnnaBridge 143:86740a56073b 954 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
AnnaBridge 143:86740a56073b 955 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
AnnaBridge 143:86740a56073b 956 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 957 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 958
AnnaBridge 143:86740a56073b 959
AnnaBridge 143:86740a56073b 960 /****************** Bit definition for ADC_SMPR register ********************/
AnnaBridge 143:86740a56073b 961 #define ADC_SMPR_SMP_Pos (0U)
AnnaBridge 143:86740a56073b 962 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 963 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
AnnaBridge 143:86740a56073b 964 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 965 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 966 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 967
AnnaBridge 143:86740a56073b 968 /* Legacy defines */
AnnaBridge 143:86740a56073b 969 #define ADC_SMPR_SMPR ADC_SMPR_SMP
AnnaBridge 143:86740a56073b 970 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
AnnaBridge 143:86740a56073b 971 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
AnnaBridge 143:86740a56073b 972 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
AnnaBridge 143:86740a56073b 973
AnnaBridge 143:86740a56073b 974 /******************* Bit definition for ADC_TR register ********************/
AnnaBridge 143:86740a56073b 975 #define ADC_TR_HT_Pos (16U)
AnnaBridge 143:86740a56073b 976 #define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
AnnaBridge 143:86740a56073b 977 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
AnnaBridge 143:86740a56073b 978 #define ADC_TR_LT_Pos (0U)
AnnaBridge 143:86740a56073b 979 #define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 980 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
AnnaBridge 143:86740a56073b 981
AnnaBridge 143:86740a56073b 982 /****************** Bit definition for ADC_CHSELR register ******************/
AnnaBridge 143:86740a56073b 983 #define ADC_CHSELR_CHSEL_Pos (0U)
AnnaBridge 143:86740a56073b 984 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
AnnaBridge 143:86740a56073b 985 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
AnnaBridge 143:86740a56073b 986 #define ADC_CHSELR_CHSEL18_Pos (18U)
AnnaBridge 143:86740a56073b 987 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 988 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
AnnaBridge 143:86740a56073b 989 #define ADC_CHSELR_CHSEL17_Pos (17U)
AnnaBridge 143:86740a56073b 990 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 991 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
AnnaBridge 143:86740a56073b 992 #define ADC_CHSELR_CHSEL15_Pos (15U)
AnnaBridge 143:86740a56073b 993 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 994 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
AnnaBridge 143:86740a56073b 995 #define ADC_CHSELR_CHSEL14_Pos (14U)
AnnaBridge 143:86740a56073b 996 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 997 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
AnnaBridge 143:86740a56073b 998 #define ADC_CHSELR_CHSEL13_Pos (13U)
AnnaBridge 143:86740a56073b 999 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1000 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
AnnaBridge 143:86740a56073b 1001 #define ADC_CHSELR_CHSEL12_Pos (12U)
AnnaBridge 143:86740a56073b 1002 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1003 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
AnnaBridge 143:86740a56073b 1004 #define ADC_CHSELR_CHSEL11_Pos (11U)
AnnaBridge 143:86740a56073b 1005 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1006 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
AnnaBridge 143:86740a56073b 1007 #define ADC_CHSELR_CHSEL10_Pos (10U)
AnnaBridge 143:86740a56073b 1008 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1009 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
AnnaBridge 143:86740a56073b 1010 #define ADC_CHSELR_CHSEL9_Pos (9U)
AnnaBridge 143:86740a56073b 1011 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1012 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
AnnaBridge 143:86740a56073b 1013 #define ADC_CHSELR_CHSEL8_Pos (8U)
AnnaBridge 143:86740a56073b 1014 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1015 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
AnnaBridge 143:86740a56073b 1016 #define ADC_CHSELR_CHSEL7_Pos (7U)
AnnaBridge 143:86740a56073b 1017 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1018 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
AnnaBridge 143:86740a56073b 1019 #define ADC_CHSELR_CHSEL6_Pos (6U)
AnnaBridge 143:86740a56073b 1020 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1021 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
AnnaBridge 143:86740a56073b 1022 #define ADC_CHSELR_CHSEL5_Pos (5U)
AnnaBridge 143:86740a56073b 1023 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1024 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
AnnaBridge 143:86740a56073b 1025 #define ADC_CHSELR_CHSEL4_Pos (4U)
AnnaBridge 143:86740a56073b 1026 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1027 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
AnnaBridge 143:86740a56073b 1028 #define ADC_CHSELR_CHSEL3_Pos (3U)
AnnaBridge 143:86740a56073b 1029 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1030 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
AnnaBridge 143:86740a56073b 1031 #define ADC_CHSELR_CHSEL2_Pos (2U)
AnnaBridge 143:86740a56073b 1032 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1033 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
AnnaBridge 143:86740a56073b 1034 #define ADC_CHSELR_CHSEL1_Pos (1U)
AnnaBridge 143:86740a56073b 1035 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1036 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
AnnaBridge 143:86740a56073b 1037 #define ADC_CHSELR_CHSEL0_Pos (0U)
AnnaBridge 143:86740a56073b 1038 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1039 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
AnnaBridge 143:86740a56073b 1040
AnnaBridge 143:86740a56073b 1041 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 143:86740a56073b 1042 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 143:86740a56073b 1043 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 1044 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
AnnaBridge 143:86740a56073b 1045
AnnaBridge 143:86740a56073b 1046 /******************** Bit definition for ADC_CALFACT register ********************/
AnnaBridge 143:86740a56073b 1047 #define ADC_CALFACT_CALFACT_Pos (0U)
AnnaBridge 143:86740a56073b 1048 #define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
AnnaBridge 143:86740a56073b 1049 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
AnnaBridge 143:86740a56073b 1050
AnnaBridge 143:86740a56073b 1051 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 143:86740a56073b 1052 #define ADC_CCR_LFMEN_Pos (25U)
AnnaBridge 143:86740a56073b 1053 #define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1054 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
AnnaBridge 143:86740a56073b 1055 #define ADC_CCR_TSEN_Pos (23U)
AnnaBridge 143:86740a56073b 1056 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1057 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
AnnaBridge 143:86740a56073b 1058 #define ADC_CCR_VREFEN_Pos (22U)
AnnaBridge 143:86740a56073b 1059 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1060 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
AnnaBridge 143:86740a56073b 1061 #define ADC_CCR_PRESC_Pos (18U)
AnnaBridge 143:86740a56073b 1062 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
AnnaBridge 143:86740a56073b 1063 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
AnnaBridge 143:86740a56073b 1064 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1065 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1066 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1067 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1068
AnnaBridge 143:86740a56073b 1069 /******************************************************************************/
AnnaBridge 143:86740a56073b 1070 /* */
AnnaBridge 143:86740a56073b 1071 /* Analog Comparators (COMP) */
AnnaBridge 143:86740a56073b 1072 /* */
AnnaBridge 143:86740a56073b 1073 /******************************************************************************/
AnnaBridge 143:86740a56073b 1074 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
AnnaBridge 143:86740a56073b 1075 /* COMP1 bits definition */
AnnaBridge 143:86740a56073b 1076 #define COMP_CSR_COMP1EN_Pos (0U)
AnnaBridge 143:86740a56073b 1077 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1078 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
AnnaBridge 143:86740a56073b 1079 #define COMP_CSR_COMP1INNSEL_Pos (4U)
AnnaBridge 143:86740a56073b 1080 #define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 1081 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
AnnaBridge 143:86740a56073b 1082 #define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1083 #define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1084 #define COMP_CSR_COMP1WM_Pos (8U)
AnnaBridge 143:86740a56073b 1085 #define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1086 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
AnnaBridge 143:86740a56073b 1087 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
AnnaBridge 143:86740a56073b 1088 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1089 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
AnnaBridge 143:86740a56073b 1090 #define COMP_CSR_COMP1POLARITY_Pos (15U)
AnnaBridge 143:86740a56073b 1091 #define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1092 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
AnnaBridge 143:86740a56073b 1093 #define COMP_CSR_COMP1VALUE_Pos (30U)
AnnaBridge 143:86740a56073b 1094 #define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 1095 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
AnnaBridge 143:86740a56073b 1096 #define COMP_CSR_COMP1LOCK_Pos (31U)
AnnaBridge 143:86740a56073b 1097 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1098 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
AnnaBridge 143:86740a56073b 1099 /* COMP2 bits definition */
AnnaBridge 143:86740a56073b 1100 #define COMP_CSR_COMP2EN_Pos (0U)
AnnaBridge 143:86740a56073b 1101 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1102 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
AnnaBridge 143:86740a56073b 1103 #define COMP_CSR_COMP2SPEED_Pos (3U)
AnnaBridge 143:86740a56073b 1104 #define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1105 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
AnnaBridge 143:86740a56073b 1106 #define COMP_CSR_COMP2INNSEL_Pos (4U)
AnnaBridge 143:86740a56073b 1107 #define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 1108 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
AnnaBridge 143:86740a56073b 1109 #define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1110 #define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1111 #define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1112 #define COMP_CSR_COMP2INPSEL_Pos (8U)
AnnaBridge 143:86740a56073b 1113 #define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
AnnaBridge 143:86740a56073b 1114 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
AnnaBridge 143:86740a56073b 1115 #define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1116 #define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1117 #define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1118 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
AnnaBridge 143:86740a56073b 1119 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1120 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
AnnaBridge 143:86740a56073b 1121 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
AnnaBridge 143:86740a56073b 1122 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1123 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
AnnaBridge 143:86740a56073b 1124 #define COMP_CSR_COMP2POLARITY_Pos (15U)
AnnaBridge 143:86740a56073b 1125 #define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1126 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
AnnaBridge 143:86740a56073b 1127 #define COMP_CSR_COMP2VALUE_Pos (30U)
AnnaBridge 143:86740a56073b 1128 #define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 1129 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
AnnaBridge 143:86740a56073b 1130 #define COMP_CSR_COMP2LOCK_Pos (31U)
AnnaBridge 143:86740a56073b 1131 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1132 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
AnnaBridge 143:86740a56073b 1133
AnnaBridge 143:86740a56073b 1134 /********************** Bit definition for COMP_CSR register common ****************/
AnnaBridge 143:86740a56073b 1135 #define COMP_CSR_COMPxEN_Pos (0U)
AnnaBridge 143:86740a56073b 1136 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1137 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
AnnaBridge 143:86740a56073b 1138 #define COMP_CSR_COMPxPOLARITY_Pos (15U)
AnnaBridge 143:86740a56073b 1139 #define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1140 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
AnnaBridge 143:86740a56073b 1141 #define COMP_CSR_COMPxOUTVALUE_Pos (30U)
AnnaBridge 143:86740a56073b 1142 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 1143 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
AnnaBridge 143:86740a56073b 1144 #define COMP_CSR_COMPxLOCK_Pos (31U)
AnnaBridge 143:86740a56073b 1145 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1146 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
AnnaBridge 143:86740a56073b 1147
AnnaBridge 143:86740a56073b 1148 /* Reference defines */
AnnaBridge 143:86740a56073b 1149 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
AnnaBridge 143:86740a56073b 1150
AnnaBridge 143:86740a56073b 1151 /******************************************************************************/
AnnaBridge 143:86740a56073b 1152 /* */
AnnaBridge 143:86740a56073b 1153 /* CRC calculation unit (CRC) */
AnnaBridge 143:86740a56073b 1154 /* */
AnnaBridge 143:86740a56073b 1155 /******************************************************************************/
AnnaBridge 143:86740a56073b 1156 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 143:86740a56073b 1157 #define CRC_DR_DR_Pos (0U)
AnnaBridge 143:86740a56073b 1158 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 1159 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 143:86740a56073b 1160
AnnaBridge 143:86740a56073b 1161 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 143:86740a56073b 1162 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
AnnaBridge 143:86740a56073b 1163
AnnaBridge 143:86740a56073b 1164 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 143:86740a56073b 1165 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 143:86740a56073b 1166 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1167 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 143:86740a56073b 1168 #define CRC_CR_POLYSIZE_Pos (3U)
AnnaBridge 143:86740a56073b 1169 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
AnnaBridge 143:86740a56073b 1170 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
AnnaBridge 143:86740a56073b 1171 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1172 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1173 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 143:86740a56073b 1174 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 143:86740a56073b 1175 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 143:86740a56073b 1176 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1177 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1178 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 143:86740a56073b 1179 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1180 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 143:86740a56073b 1181
AnnaBridge 143:86740a56073b 1182 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 143:86740a56073b 1183 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 143:86740a56073b 1184 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 1185 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 143:86740a56073b 1186
AnnaBridge 143:86740a56073b 1187 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 143:86740a56073b 1188 #define CRC_POL_POL_Pos (0U)
AnnaBridge 143:86740a56073b 1189 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 1190 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
AnnaBridge 143:86740a56073b 1191
AnnaBridge 143:86740a56073b 1192 /******************************************************************************/
AnnaBridge 143:86740a56073b 1193 /* */
AnnaBridge 143:86740a56073b 1194 /* CRS Clock Recovery System */
AnnaBridge 143:86740a56073b 1195 /* */
AnnaBridge 143:86740a56073b 1196 /******************************************************************************/
AnnaBridge 143:86740a56073b 1197
AnnaBridge 143:86740a56073b 1198 /******************* Bit definition for CRS_CR register *********************/
AnnaBridge 143:86740a56073b 1199 #define CRS_CR_SYNCOKIE_Pos (0U)
AnnaBridge 143:86740a56073b 1200 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1201 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
AnnaBridge 143:86740a56073b 1202 #define CRS_CR_SYNCWARNIE_Pos (1U)
AnnaBridge 143:86740a56073b 1203 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1204 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
AnnaBridge 143:86740a56073b 1205 #define CRS_CR_ERRIE_Pos (2U)
AnnaBridge 143:86740a56073b 1206 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1207 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
AnnaBridge 143:86740a56073b 1208 #define CRS_CR_ESYNCIE_Pos (3U)
AnnaBridge 143:86740a56073b 1209 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1210 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
AnnaBridge 143:86740a56073b 1211 #define CRS_CR_CEN_Pos (5U)
AnnaBridge 143:86740a56073b 1212 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1213 #define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
AnnaBridge 143:86740a56073b 1214 #define CRS_CR_AUTOTRIMEN_Pos (6U)
AnnaBridge 143:86740a56073b 1215 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1216 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
AnnaBridge 143:86740a56073b 1217 #define CRS_CR_SWSYNC_Pos (7U)
AnnaBridge 143:86740a56073b 1218 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1219 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
AnnaBridge 143:86740a56073b 1220 #define CRS_CR_TRIM_Pos (8U)
AnnaBridge 143:86740a56073b 1221 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
AnnaBridge 143:86740a56073b 1222 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
AnnaBridge 143:86740a56073b 1223
AnnaBridge 143:86740a56073b 1224 /******************* Bit definition for CRS_CFGR register *********************/
AnnaBridge 143:86740a56073b 1225 #define CRS_CFGR_RELOAD_Pos (0U)
AnnaBridge 143:86740a56073b 1226 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 1227 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
AnnaBridge 143:86740a56073b 1228 #define CRS_CFGR_FELIM_Pos (16U)
AnnaBridge 143:86740a56073b 1229 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
AnnaBridge 143:86740a56073b 1230 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
AnnaBridge 143:86740a56073b 1231
AnnaBridge 143:86740a56073b 1232 #define CRS_CFGR_SYNCDIV_Pos (24U)
AnnaBridge 143:86740a56073b 1233 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
AnnaBridge 143:86740a56073b 1234 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
AnnaBridge 143:86740a56073b 1235 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1236 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1237 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1238
AnnaBridge 143:86740a56073b 1239 #define CRS_CFGR_SYNCSRC_Pos (28U)
AnnaBridge 143:86740a56073b 1240 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 1241 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
AnnaBridge 143:86740a56073b 1242 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 1243 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 1244
AnnaBridge 143:86740a56073b 1245 #define CRS_CFGR_SYNCPOL_Pos (31U)
AnnaBridge 143:86740a56073b 1246 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1247 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
AnnaBridge 143:86740a56073b 1248
AnnaBridge 143:86740a56073b 1249 /******************* Bit definition for CRS_ISR register *********************/
AnnaBridge 143:86740a56073b 1250 #define CRS_ISR_SYNCOKF_Pos (0U)
AnnaBridge 143:86740a56073b 1251 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1252 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
AnnaBridge 143:86740a56073b 1253 #define CRS_ISR_SYNCWARNF_Pos (1U)
AnnaBridge 143:86740a56073b 1254 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1255 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
AnnaBridge 143:86740a56073b 1256 #define CRS_ISR_ERRF_Pos (2U)
AnnaBridge 143:86740a56073b 1257 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1258 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
AnnaBridge 143:86740a56073b 1259 #define CRS_ISR_ESYNCF_Pos (3U)
AnnaBridge 143:86740a56073b 1260 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1261 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
AnnaBridge 143:86740a56073b 1262 #define CRS_ISR_SYNCERR_Pos (8U)
AnnaBridge 143:86740a56073b 1263 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1264 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
AnnaBridge 143:86740a56073b 1265 #define CRS_ISR_SYNCMISS_Pos (9U)
AnnaBridge 143:86740a56073b 1266 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1267 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
AnnaBridge 143:86740a56073b 1268 #define CRS_ISR_TRIMOVF_Pos (10U)
AnnaBridge 143:86740a56073b 1269 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1270 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
AnnaBridge 143:86740a56073b 1271 #define CRS_ISR_FEDIR_Pos (15U)
AnnaBridge 143:86740a56073b 1272 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1273 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
AnnaBridge 143:86740a56073b 1274 #define CRS_ISR_FECAP_Pos (16U)
AnnaBridge 143:86740a56073b 1275 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 143:86740a56073b 1276 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
AnnaBridge 143:86740a56073b 1277
AnnaBridge 143:86740a56073b 1278 /******************* Bit definition for CRS_ICR register *********************/
AnnaBridge 143:86740a56073b 1279 #define CRS_ICR_SYNCOKC_Pos (0U)
AnnaBridge 143:86740a56073b 1280 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1281 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
AnnaBridge 143:86740a56073b 1282 #define CRS_ICR_SYNCWARNC_Pos (1U)
AnnaBridge 143:86740a56073b 1283 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1284 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
AnnaBridge 143:86740a56073b 1285 #define CRS_ICR_ERRC_Pos (2U)
AnnaBridge 143:86740a56073b 1286 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1287 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
AnnaBridge 143:86740a56073b 1288 #define CRS_ICR_ESYNCC_Pos (3U)
AnnaBridge 143:86740a56073b 1289 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1290 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
AnnaBridge 143:86740a56073b 1291
AnnaBridge 143:86740a56073b 1292 /******************************************************************************/
AnnaBridge 143:86740a56073b 1293 /* */
AnnaBridge 143:86740a56073b 1294 /* Digital to Analog Converter (DAC) */
AnnaBridge 143:86740a56073b 1295 /* */
AnnaBridge 143:86740a56073b 1296 /******************************************************************************/
AnnaBridge 143:86740a56073b 1297
AnnaBridge 143:86740a56073b 1298 /*
AnnaBridge 143:86740a56073b 1299 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
AnnaBridge 143:86740a56073b 1300 */
AnnaBridge 143:86740a56073b 1301 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
AnnaBridge 143:86740a56073b 1302
AnnaBridge 143:86740a56073b 1303 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 143:86740a56073b 1304 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 143:86740a56073b 1305 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1306 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
AnnaBridge 143:86740a56073b 1307 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 143:86740a56073b 1308 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1309 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
AnnaBridge 143:86740a56073b 1310 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 143:86740a56073b 1311 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1312 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
AnnaBridge 143:86740a56073b 1313
AnnaBridge 143:86740a56073b 1314 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 143:86740a56073b 1315 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 143:86740a56073b 1316 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 143:86740a56073b 1317 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1318 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1319 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1320
AnnaBridge 143:86740a56073b 1321 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 143:86740a56073b 1322 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 143:86740a56073b 1323 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 143:86740a56073b 1324 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1325 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1326
AnnaBridge 143:86740a56073b 1327 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 143:86740a56073b 1328 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 1329 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 143:86740a56073b 1330 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1331 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1332 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1333 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1334
AnnaBridge 143:86740a56073b 1335 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 143:86740a56073b 1336 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1337 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
AnnaBridge 143:86740a56073b 1338 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 143:86740a56073b 1339 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1340 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
AnnaBridge 143:86740a56073b 1341
AnnaBridge 143:86740a56073b 1342 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 143:86740a56073b 1343 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1344 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
AnnaBridge 143:86740a56073b 1345 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 143:86740a56073b 1346 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1347 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
AnnaBridge 143:86740a56073b 1348 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 143:86740a56073b 1349 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1350 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
AnnaBridge 143:86740a56073b 1351
AnnaBridge 143:86740a56073b 1352 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 143:86740a56073b 1353 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 143:86740a56073b 1354 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 143:86740a56073b 1355 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1356 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1357 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1358
AnnaBridge 143:86740a56073b 1359 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 143:86740a56073b 1360 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 1361 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 143:86740a56073b 1362 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1363 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1364
AnnaBridge 143:86740a56073b 1365 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 143:86740a56073b 1366 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 1367 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 143:86740a56073b 1368 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1369 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1370 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1371 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 1372
AnnaBridge 143:86740a56073b 1373 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 143:86740a56073b 1374 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 1375 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
AnnaBridge 143:86740a56073b 1376 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 143:86740a56073b 1377 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 1378 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
AnnaBridge 143:86740a56073b 1379
AnnaBridge 143:86740a56073b 1380 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 143:86740a56073b 1381 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 143:86740a56073b 1382 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1383 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
AnnaBridge 143:86740a56073b 1384 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 143:86740a56073b 1385 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1386 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
AnnaBridge 143:86740a56073b 1387
AnnaBridge 143:86740a56073b 1388 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 143:86740a56073b 1389 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1390 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 1391 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
AnnaBridge 143:86740a56073b 1392
AnnaBridge 143:86740a56073b 1393 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 143:86740a56073b 1394 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 143:86740a56073b 1395 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 143:86740a56073b 1396 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
AnnaBridge 143:86740a56073b 1397
AnnaBridge 143:86740a56073b 1398 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 143:86740a56073b 1399 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1400 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 1401 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
AnnaBridge 143:86740a56073b 1402
AnnaBridge 143:86740a56073b 1403 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 143:86740a56073b 1404 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1405 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 1406 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
AnnaBridge 143:86740a56073b 1407
AnnaBridge 143:86740a56073b 1408 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 143:86740a56073b 1409 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 143:86740a56073b 1410 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 143:86740a56073b 1411 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
AnnaBridge 143:86740a56073b 1412
AnnaBridge 143:86740a56073b 1413 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 143:86740a56073b 1414 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1415 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 1416 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
AnnaBridge 143:86740a56073b 1417
AnnaBridge 143:86740a56073b 1418 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 143:86740a56073b 1419 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1420 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 1421 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
AnnaBridge 143:86740a56073b 1422 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 143:86740a56073b 1423 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 143:86740a56073b 1424 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
AnnaBridge 143:86740a56073b 1425
AnnaBridge 143:86740a56073b 1426 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 143:86740a56073b 1427 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 143:86740a56073b 1428 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 143:86740a56073b 1429 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
AnnaBridge 143:86740a56073b 1430 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 143:86740a56073b 1431 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 143:86740a56073b 1432 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
AnnaBridge 143:86740a56073b 1433
AnnaBridge 143:86740a56073b 1434 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 143:86740a56073b 1435 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 143:86740a56073b 1436 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 1437 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
AnnaBridge 143:86740a56073b 1438 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 143:86740a56073b 1439 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 143:86740a56073b 1440 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
AnnaBridge 143:86740a56073b 1441
AnnaBridge 143:86740a56073b 1442 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 143:86740a56073b 1443 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
AnnaBridge 143:86740a56073b 1444
AnnaBridge 143:86740a56073b 1445 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 143:86740a56073b 1446 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 143:86740a56073b 1447 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 1448 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
AnnaBridge 143:86740a56073b 1449
AnnaBridge 143:86740a56073b 1450 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 143:86740a56073b 1451 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 143:86740a56073b 1452 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1453 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
AnnaBridge 143:86740a56073b 1454 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 143:86740a56073b 1455 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 1456 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
AnnaBridge 143:86740a56073b 1457
AnnaBridge 143:86740a56073b 1458 /******************************************************************************/
AnnaBridge 143:86740a56073b 1459 /* */
AnnaBridge 143:86740a56073b 1460 /* Debug MCU (DBGMCU) */
AnnaBridge 143:86740a56073b 1461 /* */
AnnaBridge 143:86740a56073b 1462 /******************************************************************************/
AnnaBridge 143:86740a56073b 1463
AnnaBridge 143:86740a56073b 1464 /**************** Bit definition for DBGMCU_IDCODE register *****************/
AnnaBridge 143:86740a56073b 1465 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 143:86740a56073b 1466 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 1467 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
AnnaBridge 143:86740a56073b 1468
AnnaBridge 143:86740a56073b 1469 #define DBGMCU_IDCODE_DIV_ID_Pos (12U)
AnnaBridge 143:86740a56073b 1470 #define DBGMCU_IDCODE_DIV_ID_Msk (0xFU << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 1471 #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
AnnaBridge 143:86740a56073b 1472 #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
AnnaBridge 143:86740a56073b 1473 #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3U << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
AnnaBridge 143:86740a56073b 1474 #define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
AnnaBridge 143:86740a56073b 1475 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 143:86740a56073b 1476 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 143:86740a56073b 1477 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
AnnaBridge 143:86740a56073b 1478 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1479 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1480 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1481 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1482 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1483 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1484 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1485 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1486 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1487 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1488 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1489 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 1490 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 1491 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 1492 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 1493 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1494
AnnaBridge 143:86740a56073b 1495 /****************** Bit definition for DBGMCU_CR register *******************/
AnnaBridge 143:86740a56073b 1496 #define DBGMCU_CR_DBG_Pos (0U)
AnnaBridge 143:86740a56073b 1497 #define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 1498 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
AnnaBridge 143:86740a56073b 1499 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 143:86740a56073b 1500 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1501 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
AnnaBridge 143:86740a56073b 1502 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 143:86740a56073b 1503 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1504 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
AnnaBridge 143:86740a56073b 1505 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 143:86740a56073b 1506 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1507 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
AnnaBridge 143:86740a56073b 1508
AnnaBridge 143:86740a56073b 1509 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
AnnaBridge 143:86740a56073b 1510 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 143:86740a56073b 1511 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1512 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
AnnaBridge 143:86740a56073b 1513 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 143:86740a56073b 1514 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1515 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 143:86740a56073b 1516 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 143:86740a56073b 1517 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1518 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
AnnaBridge 143:86740a56073b 1519 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 143:86740a56073b 1520 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1521 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 143:86740a56073b 1522 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 143:86740a56073b 1523 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1524 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
AnnaBridge 143:86740a56073b 1525 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 143:86740a56073b 1526 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1527 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
AnnaBridge 143:86740a56073b 1528 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 143:86740a56073b 1529 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1530 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
AnnaBridge 143:86740a56073b 1531 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
AnnaBridge 143:86740a56073b 1532 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1533 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 143:86740a56073b 1534 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
AnnaBridge 143:86740a56073b 1535 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1536 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 143:86740a56073b 1537 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
AnnaBridge 143:86740a56073b 1538 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1539 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 143:86740a56073b 1540 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
AnnaBridge 143:86740a56073b 1541 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 1542 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
AnnaBridge 143:86740a56073b 1543 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
AnnaBridge 143:86740a56073b 1544 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
AnnaBridge 143:86740a56073b 1545 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1546 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
AnnaBridge 143:86740a56073b 1547 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
AnnaBridge 143:86740a56073b 1548 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1549 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
AnnaBridge 143:86740a56073b 1550
AnnaBridge 143:86740a56073b 1551 /******************************************************************************/
AnnaBridge 143:86740a56073b 1552 /* */
AnnaBridge 143:86740a56073b 1553 /* DMA Controller (DMA) */
AnnaBridge 143:86740a56073b 1554 /* */
AnnaBridge 143:86740a56073b 1555 /******************************************************************************/
AnnaBridge 143:86740a56073b 1556
AnnaBridge 143:86740a56073b 1557 /******************* Bit definition for DMA_ISR register ********************/
AnnaBridge 143:86740a56073b 1558 #define DMA_ISR_GIF1_Pos (0U)
AnnaBridge 143:86740a56073b 1559 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1560 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 143:86740a56073b 1561 #define DMA_ISR_TCIF1_Pos (1U)
AnnaBridge 143:86740a56073b 1562 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1563 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1564 #define DMA_ISR_HTIF1_Pos (2U)
AnnaBridge 143:86740a56073b 1565 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1566 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 143:86740a56073b 1567 #define DMA_ISR_TEIF1_Pos (3U)
AnnaBridge 143:86740a56073b 1568 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1569 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 143:86740a56073b 1570 #define DMA_ISR_GIF2_Pos (4U)
AnnaBridge 143:86740a56073b 1571 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1572 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 143:86740a56073b 1573 #define DMA_ISR_TCIF2_Pos (5U)
AnnaBridge 143:86740a56073b 1574 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1575 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1576 #define DMA_ISR_HTIF2_Pos (6U)
AnnaBridge 143:86740a56073b 1577 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1578 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 143:86740a56073b 1579 #define DMA_ISR_TEIF2_Pos (7U)
AnnaBridge 143:86740a56073b 1580 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1581 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 143:86740a56073b 1582 #define DMA_ISR_GIF3_Pos (8U)
AnnaBridge 143:86740a56073b 1583 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1584 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 143:86740a56073b 1585 #define DMA_ISR_TCIF3_Pos (9U)
AnnaBridge 143:86740a56073b 1586 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1587 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1588 #define DMA_ISR_HTIF3_Pos (10U)
AnnaBridge 143:86740a56073b 1589 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1590 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 143:86740a56073b 1591 #define DMA_ISR_TEIF3_Pos (11U)
AnnaBridge 143:86740a56073b 1592 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1593 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 143:86740a56073b 1594 #define DMA_ISR_GIF4_Pos (12U)
AnnaBridge 143:86740a56073b 1595 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1596 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 143:86740a56073b 1597 #define DMA_ISR_TCIF4_Pos (13U)
AnnaBridge 143:86740a56073b 1598 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1599 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1600 #define DMA_ISR_HTIF4_Pos (14U)
AnnaBridge 143:86740a56073b 1601 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 1602 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 143:86740a56073b 1603 #define DMA_ISR_TEIF4_Pos (15U)
AnnaBridge 143:86740a56073b 1604 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1605 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 143:86740a56073b 1606 #define DMA_ISR_GIF5_Pos (16U)
AnnaBridge 143:86740a56073b 1607 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1608 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 143:86740a56073b 1609 #define DMA_ISR_TCIF5_Pos (17U)
AnnaBridge 143:86740a56073b 1610 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1611 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1612 #define DMA_ISR_HTIF5_Pos (18U)
AnnaBridge 143:86740a56073b 1613 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1614 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 143:86740a56073b 1615 #define DMA_ISR_TEIF5_Pos (19U)
AnnaBridge 143:86740a56073b 1616 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1617 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 143:86740a56073b 1618 #define DMA_ISR_GIF6_Pos (20U)
AnnaBridge 143:86740a56073b 1619 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1620 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
AnnaBridge 143:86740a56073b 1621 #define DMA_ISR_TCIF6_Pos (21U)
AnnaBridge 143:86740a56073b 1622 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1623 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1624 #define DMA_ISR_HTIF6_Pos (22U)
AnnaBridge 143:86740a56073b 1625 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1626 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
AnnaBridge 143:86740a56073b 1627 #define DMA_ISR_TEIF6_Pos (23U)
AnnaBridge 143:86740a56073b 1628 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1629 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
AnnaBridge 143:86740a56073b 1630 #define DMA_ISR_GIF7_Pos (24U)
AnnaBridge 143:86740a56073b 1631 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1632 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
AnnaBridge 143:86740a56073b 1633 #define DMA_ISR_TCIF7_Pos (25U)
AnnaBridge 143:86740a56073b 1634 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1635 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
AnnaBridge 143:86740a56073b 1636 #define DMA_ISR_HTIF7_Pos (26U)
AnnaBridge 143:86740a56073b 1637 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1638 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
AnnaBridge 143:86740a56073b 1639 #define DMA_ISR_TEIF7_Pos (27U)
AnnaBridge 143:86740a56073b 1640 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 1641 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
AnnaBridge 143:86740a56073b 1642
AnnaBridge 143:86740a56073b 1643 /******************* Bit definition for DMA_IFCR register *******************/
AnnaBridge 143:86740a56073b 1644 #define DMA_IFCR_CGIF1_Pos (0U)
AnnaBridge 143:86740a56073b 1645 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1646 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
AnnaBridge 143:86740a56073b 1647 #define DMA_IFCR_CTCIF1_Pos (1U)
AnnaBridge 143:86740a56073b 1648 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1649 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1650 #define DMA_IFCR_CHTIF1_Pos (2U)
AnnaBridge 143:86740a56073b 1651 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1652 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 143:86740a56073b 1653 #define DMA_IFCR_CTEIF1_Pos (3U)
AnnaBridge 143:86740a56073b 1654 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1655 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 143:86740a56073b 1656 #define DMA_IFCR_CGIF2_Pos (4U)
AnnaBridge 143:86740a56073b 1657 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1658 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 143:86740a56073b 1659 #define DMA_IFCR_CTCIF2_Pos (5U)
AnnaBridge 143:86740a56073b 1660 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1661 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1662 #define DMA_IFCR_CHTIF2_Pos (6U)
AnnaBridge 143:86740a56073b 1663 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1664 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 143:86740a56073b 1665 #define DMA_IFCR_CTEIF2_Pos (7U)
AnnaBridge 143:86740a56073b 1666 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1667 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 143:86740a56073b 1668 #define DMA_IFCR_CGIF3_Pos (8U)
AnnaBridge 143:86740a56073b 1669 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1670 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 143:86740a56073b 1671 #define DMA_IFCR_CTCIF3_Pos (9U)
AnnaBridge 143:86740a56073b 1672 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1673 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1674 #define DMA_IFCR_CHTIF3_Pos (10U)
AnnaBridge 143:86740a56073b 1675 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1676 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 143:86740a56073b 1677 #define DMA_IFCR_CTEIF3_Pos (11U)
AnnaBridge 143:86740a56073b 1678 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1679 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 143:86740a56073b 1680 #define DMA_IFCR_CGIF4_Pos (12U)
AnnaBridge 143:86740a56073b 1681 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1682 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 143:86740a56073b 1683 #define DMA_IFCR_CTCIF4_Pos (13U)
AnnaBridge 143:86740a56073b 1684 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1685 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1686 #define DMA_IFCR_CHTIF4_Pos (14U)
AnnaBridge 143:86740a56073b 1687 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 1688 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 143:86740a56073b 1689 #define DMA_IFCR_CTEIF4_Pos (15U)
AnnaBridge 143:86740a56073b 1690 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1691 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 143:86740a56073b 1692 #define DMA_IFCR_CGIF5_Pos (16U)
AnnaBridge 143:86740a56073b 1693 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1694 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 143:86740a56073b 1695 #define DMA_IFCR_CTCIF5_Pos (17U)
AnnaBridge 143:86740a56073b 1696 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1697 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1698 #define DMA_IFCR_CHTIF5_Pos (18U)
AnnaBridge 143:86740a56073b 1699 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1700 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 143:86740a56073b 1701 #define DMA_IFCR_CTEIF5_Pos (19U)
AnnaBridge 143:86740a56073b 1702 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1703 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 143:86740a56073b 1704 #define DMA_IFCR_CGIF6_Pos (20U)
AnnaBridge 143:86740a56073b 1705 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1706 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
AnnaBridge 143:86740a56073b 1707 #define DMA_IFCR_CTCIF6_Pos (21U)
AnnaBridge 143:86740a56073b 1708 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1709 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1710 #define DMA_IFCR_CHTIF6_Pos (22U)
AnnaBridge 143:86740a56073b 1711 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1712 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
AnnaBridge 143:86740a56073b 1713 #define DMA_IFCR_CTEIF6_Pos (23U)
AnnaBridge 143:86740a56073b 1714 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1715 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
AnnaBridge 143:86740a56073b 1716 #define DMA_IFCR_CGIF7_Pos (24U)
AnnaBridge 143:86740a56073b 1717 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1718 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
AnnaBridge 143:86740a56073b 1719 #define DMA_IFCR_CTCIF7_Pos (25U)
AnnaBridge 143:86740a56073b 1720 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1721 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
AnnaBridge 143:86740a56073b 1722 #define DMA_IFCR_CHTIF7_Pos (26U)
AnnaBridge 143:86740a56073b 1723 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1724 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
AnnaBridge 143:86740a56073b 1725 #define DMA_IFCR_CTEIF7_Pos (27U)
AnnaBridge 143:86740a56073b 1726 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 1727 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
AnnaBridge 143:86740a56073b 1728
AnnaBridge 143:86740a56073b 1729 /******************* Bit definition for DMA_CCR register ********************/
AnnaBridge 143:86740a56073b 1730 #define DMA_CCR_EN_Pos (0U)
AnnaBridge 143:86740a56073b 1731 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1732 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
AnnaBridge 143:86740a56073b 1733 #define DMA_CCR_TCIE_Pos (1U)
AnnaBridge 143:86740a56073b 1734 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1735 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 143:86740a56073b 1736 #define DMA_CCR_HTIE_Pos (2U)
AnnaBridge 143:86740a56073b 1737 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1738 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 143:86740a56073b 1739 #define DMA_CCR_TEIE_Pos (3U)
AnnaBridge 143:86740a56073b 1740 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1741 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 143:86740a56073b 1742 #define DMA_CCR_DIR_Pos (4U)
AnnaBridge 143:86740a56073b 1743 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1744 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 143:86740a56073b 1745 #define DMA_CCR_CIRC_Pos (5U)
AnnaBridge 143:86740a56073b 1746 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1747 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 143:86740a56073b 1748 #define DMA_CCR_PINC_Pos (6U)
AnnaBridge 143:86740a56073b 1749 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1750 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 143:86740a56073b 1751 #define DMA_CCR_MINC_Pos (7U)
AnnaBridge 143:86740a56073b 1752 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1753 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 143:86740a56073b 1754
AnnaBridge 143:86740a56073b 1755 #define DMA_CCR_PSIZE_Pos (8U)
AnnaBridge 143:86740a56073b 1756 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 1757 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 143:86740a56073b 1758 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1759 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1760
AnnaBridge 143:86740a56073b 1761 #define DMA_CCR_MSIZE_Pos (10U)
AnnaBridge 143:86740a56073b 1762 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 1763 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 143:86740a56073b 1764 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1765 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1766
AnnaBridge 143:86740a56073b 1767 #define DMA_CCR_PL_Pos (12U)
AnnaBridge 143:86740a56073b 1768 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 1769 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
AnnaBridge 143:86740a56073b 1770 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1771 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1772
AnnaBridge 143:86740a56073b 1773 #define DMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 143:86740a56073b 1774 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 1775 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 143:86740a56073b 1776
AnnaBridge 143:86740a56073b 1777 /****************** Bit definition for DMA_CNDTR register *******************/
AnnaBridge 143:86740a56073b 1778 #define DMA_CNDTR_NDT_Pos (0U)
AnnaBridge 143:86740a56073b 1779 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 1780 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 143:86740a56073b 1781
AnnaBridge 143:86740a56073b 1782 /****************** Bit definition for DMA_CPAR register ********************/
AnnaBridge 143:86740a56073b 1783 #define DMA_CPAR_PA_Pos (0U)
AnnaBridge 143:86740a56073b 1784 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 1785 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 143:86740a56073b 1786
AnnaBridge 143:86740a56073b 1787 /****************** Bit definition for DMA_CMAR register ********************/
AnnaBridge 143:86740a56073b 1788 #define DMA_CMAR_MA_Pos (0U)
AnnaBridge 143:86740a56073b 1789 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 1790 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
AnnaBridge 143:86740a56073b 1791
AnnaBridge 143:86740a56073b 1792
AnnaBridge 143:86740a56073b 1793 /******************* Bit definition for DMA_CSELR register *******************/
AnnaBridge 143:86740a56073b 1794 #define DMA_CSELR_C1S_Pos (0U)
AnnaBridge 143:86740a56073b 1795 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 1796 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
AnnaBridge 143:86740a56073b 1797 #define DMA_CSELR_C2S_Pos (4U)
AnnaBridge 143:86740a56073b 1798 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 1799 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
AnnaBridge 143:86740a56073b 1800 #define DMA_CSELR_C3S_Pos (8U)
AnnaBridge 143:86740a56073b 1801 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 1802 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
AnnaBridge 143:86740a56073b 1803 #define DMA_CSELR_C4S_Pos (12U)
AnnaBridge 143:86740a56073b 1804 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 1805 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
AnnaBridge 143:86740a56073b 1806 #define DMA_CSELR_C5S_Pos (16U)
AnnaBridge 143:86740a56073b 1807 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 1808 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
AnnaBridge 143:86740a56073b 1809 #define DMA_CSELR_C6S_Pos (20U)
AnnaBridge 143:86740a56073b 1810 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
AnnaBridge 143:86740a56073b 1811 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
AnnaBridge 143:86740a56073b 1812 #define DMA_CSELR_C7S_Pos (24U)
AnnaBridge 143:86740a56073b 1813 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 1814 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
AnnaBridge 143:86740a56073b 1815
AnnaBridge 143:86740a56073b 1816 /******************************************************************************/
AnnaBridge 143:86740a56073b 1817 /* */
AnnaBridge 143:86740a56073b 1818 /* External Interrupt/Event Controller (EXTI) */
AnnaBridge 143:86740a56073b 1819 /* */
AnnaBridge 143:86740a56073b 1820 /******************************************************************************/
AnnaBridge 143:86740a56073b 1821
AnnaBridge 143:86740a56073b 1822 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 143:86740a56073b 1823 #define EXTI_IMR_IM0_Pos (0U)
AnnaBridge 143:86740a56073b 1824 #define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1825 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 143:86740a56073b 1826 #define EXTI_IMR_IM1_Pos (1U)
AnnaBridge 143:86740a56073b 1827 #define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1828 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 143:86740a56073b 1829 #define EXTI_IMR_IM2_Pos (2U)
AnnaBridge 143:86740a56073b 1830 #define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1831 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 143:86740a56073b 1832 #define EXTI_IMR_IM3_Pos (3U)
AnnaBridge 143:86740a56073b 1833 #define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1834 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 143:86740a56073b 1835 #define EXTI_IMR_IM4_Pos (4U)
AnnaBridge 143:86740a56073b 1836 #define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1837 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 143:86740a56073b 1838 #define EXTI_IMR_IM5_Pos (5U)
AnnaBridge 143:86740a56073b 1839 #define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1840 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 143:86740a56073b 1841 #define EXTI_IMR_IM6_Pos (6U)
AnnaBridge 143:86740a56073b 1842 #define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1843 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 143:86740a56073b 1844 #define EXTI_IMR_IM7_Pos (7U)
AnnaBridge 143:86740a56073b 1845 #define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1846 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 143:86740a56073b 1847 #define EXTI_IMR_IM8_Pos (8U)
AnnaBridge 143:86740a56073b 1848 #define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1849 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 143:86740a56073b 1850 #define EXTI_IMR_IM9_Pos (9U)
AnnaBridge 143:86740a56073b 1851 #define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1852 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 143:86740a56073b 1853 #define EXTI_IMR_IM10_Pos (10U)
AnnaBridge 143:86740a56073b 1854 #define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1855 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 143:86740a56073b 1856 #define EXTI_IMR_IM11_Pos (11U)
AnnaBridge 143:86740a56073b 1857 #define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1858 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 143:86740a56073b 1859 #define EXTI_IMR_IM12_Pos (12U)
AnnaBridge 143:86740a56073b 1860 #define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1861 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 143:86740a56073b 1862 #define EXTI_IMR_IM13_Pos (13U)
AnnaBridge 143:86740a56073b 1863 #define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1864 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 143:86740a56073b 1865 #define EXTI_IMR_IM14_Pos (14U)
AnnaBridge 143:86740a56073b 1866 #define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 1867 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 143:86740a56073b 1868 #define EXTI_IMR_IM15_Pos (15U)
AnnaBridge 143:86740a56073b 1869 #define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1870 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 143:86740a56073b 1871 #define EXTI_IMR_IM16_Pos (16U)
AnnaBridge 143:86740a56073b 1872 #define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1873 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 143:86740a56073b 1874 #define EXTI_IMR_IM17_Pos (17U)
AnnaBridge 143:86740a56073b 1875 #define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1876 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 143:86740a56073b 1877 #define EXTI_IMR_IM18_Pos (18U)
AnnaBridge 143:86740a56073b 1878 #define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1879 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 143:86740a56073b 1880 #define EXTI_IMR_IM19_Pos (19U)
AnnaBridge 143:86740a56073b 1881 #define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1882 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 143:86740a56073b 1883 #define EXTI_IMR_IM20_Pos (20U)
AnnaBridge 143:86740a56073b 1884 #define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1885 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 143:86740a56073b 1886 #define EXTI_IMR_IM21_Pos (21U)
AnnaBridge 143:86740a56073b 1887 #define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1888 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 143:86740a56073b 1889 #define EXTI_IMR_IM22_Pos (22U)
AnnaBridge 143:86740a56073b 1890 #define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1891 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 143:86740a56073b 1892 #define EXTI_IMR_IM23_Pos (23U)
AnnaBridge 143:86740a56073b 1893 #define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1894 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 143:86740a56073b 1895 #define EXTI_IMR_IM24_Pos (24U)
AnnaBridge 143:86740a56073b 1896 #define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1897 #define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
AnnaBridge 143:86740a56073b 1898 #define EXTI_IMR_IM25_Pos (25U)
AnnaBridge 143:86740a56073b 1899 #define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1900 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
AnnaBridge 143:86740a56073b 1901 #define EXTI_IMR_IM26_Pos (26U)
AnnaBridge 143:86740a56073b 1902 #define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1903 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
AnnaBridge 143:86740a56073b 1904 #define EXTI_IMR_IM28_Pos (28U)
AnnaBridge 143:86740a56073b 1905 #define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 1906 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
AnnaBridge 143:86740a56073b 1907 #define EXTI_IMR_IM29_Pos (29U)
AnnaBridge 143:86740a56073b 1908 #define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 1909 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
AnnaBridge 143:86740a56073b 1910
AnnaBridge 143:86740a56073b 1911 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 143:86740a56073b 1912 #define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
AnnaBridge 143:86740a56073b 1913 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 143:86740a56073b 1914
AnnaBridge 143:86740a56073b 1915 /****************** Bit definition for EXTI_EMR register ********************/
AnnaBridge 143:86740a56073b 1916 #define EXTI_EMR_EM0_Pos (0U)
AnnaBridge 143:86740a56073b 1917 #define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 1918 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
AnnaBridge 143:86740a56073b 1919 #define EXTI_EMR_EM1_Pos (1U)
AnnaBridge 143:86740a56073b 1920 #define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 1921 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
AnnaBridge 143:86740a56073b 1922 #define EXTI_EMR_EM2_Pos (2U)
AnnaBridge 143:86740a56073b 1923 #define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 1924 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
AnnaBridge 143:86740a56073b 1925 #define EXTI_EMR_EM3_Pos (3U)
AnnaBridge 143:86740a56073b 1926 #define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 1927 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
AnnaBridge 143:86740a56073b 1928 #define EXTI_EMR_EM4_Pos (4U)
AnnaBridge 143:86740a56073b 1929 #define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 1930 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
AnnaBridge 143:86740a56073b 1931 #define EXTI_EMR_EM5_Pos (5U)
AnnaBridge 143:86740a56073b 1932 #define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 1933 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
AnnaBridge 143:86740a56073b 1934 #define EXTI_EMR_EM6_Pos (6U)
AnnaBridge 143:86740a56073b 1935 #define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 1936 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
AnnaBridge 143:86740a56073b 1937 #define EXTI_EMR_EM7_Pos (7U)
AnnaBridge 143:86740a56073b 1938 #define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 1939 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
AnnaBridge 143:86740a56073b 1940 #define EXTI_EMR_EM8_Pos (8U)
AnnaBridge 143:86740a56073b 1941 #define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 1942 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
AnnaBridge 143:86740a56073b 1943 #define EXTI_EMR_EM9_Pos (9U)
AnnaBridge 143:86740a56073b 1944 #define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 1945 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
AnnaBridge 143:86740a56073b 1946 #define EXTI_EMR_EM10_Pos (10U)
AnnaBridge 143:86740a56073b 1947 #define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 1948 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
AnnaBridge 143:86740a56073b 1949 #define EXTI_EMR_EM11_Pos (11U)
AnnaBridge 143:86740a56073b 1950 #define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 1951 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
AnnaBridge 143:86740a56073b 1952 #define EXTI_EMR_EM12_Pos (12U)
AnnaBridge 143:86740a56073b 1953 #define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 1954 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
AnnaBridge 143:86740a56073b 1955 #define EXTI_EMR_EM13_Pos (13U)
AnnaBridge 143:86740a56073b 1956 #define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 1957 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
AnnaBridge 143:86740a56073b 1958 #define EXTI_EMR_EM14_Pos (14U)
AnnaBridge 143:86740a56073b 1959 #define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 1960 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
AnnaBridge 143:86740a56073b 1961 #define EXTI_EMR_EM15_Pos (15U)
AnnaBridge 143:86740a56073b 1962 #define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 1963 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
AnnaBridge 143:86740a56073b 1964 #define EXTI_EMR_EM16_Pos (16U)
AnnaBridge 143:86740a56073b 1965 #define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 1966 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
AnnaBridge 143:86740a56073b 1967 #define EXTI_EMR_EM17_Pos (17U)
AnnaBridge 143:86740a56073b 1968 #define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 1969 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
AnnaBridge 143:86740a56073b 1970 #define EXTI_EMR_EM18_Pos (18U)
AnnaBridge 143:86740a56073b 1971 #define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 1972 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
AnnaBridge 143:86740a56073b 1973 #define EXTI_EMR_EM19_Pos (19U)
AnnaBridge 143:86740a56073b 1974 #define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 1975 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
AnnaBridge 143:86740a56073b 1976 #define EXTI_EMR_EM20_Pos (20U)
AnnaBridge 143:86740a56073b 1977 #define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 1978 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
AnnaBridge 143:86740a56073b 1979 #define EXTI_EMR_EM21_Pos (21U)
AnnaBridge 143:86740a56073b 1980 #define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 1981 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
AnnaBridge 143:86740a56073b 1982 #define EXTI_EMR_EM22_Pos (22U)
AnnaBridge 143:86740a56073b 1983 #define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 1984 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
AnnaBridge 143:86740a56073b 1985 #define EXTI_EMR_EM23_Pos (23U)
AnnaBridge 143:86740a56073b 1986 #define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 1987 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
AnnaBridge 143:86740a56073b 1988 #define EXTI_EMR_EM24_Pos (24U)
AnnaBridge 143:86740a56073b 1989 #define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 1990 #define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
AnnaBridge 143:86740a56073b 1991 #define EXTI_EMR_EM25_Pos (25U)
AnnaBridge 143:86740a56073b 1992 #define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 1993 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
AnnaBridge 143:86740a56073b 1994 #define EXTI_EMR_EM26_Pos (26U)
AnnaBridge 143:86740a56073b 1995 #define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 1996 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
AnnaBridge 143:86740a56073b 1997 #define EXTI_EMR_EM28_Pos (28U)
AnnaBridge 143:86740a56073b 1998 #define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 1999 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
AnnaBridge 143:86740a56073b 2000 #define EXTI_EMR_EM29_Pos (29U)
AnnaBridge 143:86740a56073b 2001 #define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 2002 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
AnnaBridge 143:86740a56073b 2003
AnnaBridge 143:86740a56073b 2004 /******************* Bit definition for EXTI_RTSR register ******************/
AnnaBridge 143:86740a56073b 2005 #define EXTI_RTSR_RT0_Pos (0U)
AnnaBridge 143:86740a56073b 2006 #define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2007 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 143:86740a56073b 2008 #define EXTI_RTSR_RT1_Pos (1U)
AnnaBridge 143:86740a56073b 2009 #define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2010 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 143:86740a56073b 2011 #define EXTI_RTSR_RT2_Pos (2U)
AnnaBridge 143:86740a56073b 2012 #define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2013 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 143:86740a56073b 2014 #define EXTI_RTSR_RT3_Pos (3U)
AnnaBridge 143:86740a56073b 2015 #define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2016 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 143:86740a56073b 2017 #define EXTI_RTSR_RT4_Pos (4U)
AnnaBridge 143:86740a56073b 2018 #define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2019 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 143:86740a56073b 2020 #define EXTI_RTSR_RT5_Pos (5U)
AnnaBridge 143:86740a56073b 2021 #define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2022 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 143:86740a56073b 2023 #define EXTI_RTSR_RT6_Pos (6U)
AnnaBridge 143:86740a56073b 2024 #define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2025 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 143:86740a56073b 2026 #define EXTI_RTSR_RT7_Pos (7U)
AnnaBridge 143:86740a56073b 2027 #define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2028 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 143:86740a56073b 2029 #define EXTI_RTSR_RT8_Pos (8U)
AnnaBridge 143:86740a56073b 2030 #define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2031 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 143:86740a56073b 2032 #define EXTI_RTSR_RT9_Pos (9U)
AnnaBridge 143:86740a56073b 2033 #define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2034 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 143:86740a56073b 2035 #define EXTI_RTSR_RT10_Pos (10U)
AnnaBridge 143:86740a56073b 2036 #define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2037 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 143:86740a56073b 2038 #define EXTI_RTSR_RT11_Pos (11U)
AnnaBridge 143:86740a56073b 2039 #define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2040 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 143:86740a56073b 2041 #define EXTI_RTSR_RT12_Pos (12U)
AnnaBridge 143:86740a56073b 2042 #define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2043 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 143:86740a56073b 2044 #define EXTI_RTSR_RT13_Pos (13U)
AnnaBridge 143:86740a56073b 2045 #define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2046 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 143:86740a56073b 2047 #define EXTI_RTSR_RT14_Pos (14U)
AnnaBridge 143:86740a56073b 2048 #define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2049 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 143:86740a56073b 2050 #define EXTI_RTSR_RT15_Pos (15U)
AnnaBridge 143:86740a56073b 2051 #define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2052 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 143:86740a56073b 2053 #define EXTI_RTSR_RT16_Pos (16U)
AnnaBridge 143:86740a56073b 2054 #define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2055 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 143:86740a56073b 2056 #define EXTI_RTSR_RT17_Pos (17U)
AnnaBridge 143:86740a56073b 2057 #define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2058 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 143:86740a56073b 2059 #define EXTI_RTSR_RT19_Pos (19U)
AnnaBridge 143:86740a56073b 2060 #define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2061 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 143:86740a56073b 2062 #define EXTI_RTSR_RT20_Pos (20U)
AnnaBridge 143:86740a56073b 2063 #define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2064 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 143:86740a56073b 2065 #define EXTI_RTSR_RT21_Pos (21U)
AnnaBridge 143:86740a56073b 2066 #define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2067 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 143:86740a56073b 2068 #define EXTI_RTSR_RT22_Pos (22U)
AnnaBridge 143:86740a56073b 2069 #define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2070 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 143:86740a56073b 2071
AnnaBridge 143:86740a56073b 2072 /* Legacy defines */
AnnaBridge 143:86740a56073b 2073 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0
AnnaBridge 143:86740a56073b 2074 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1
AnnaBridge 143:86740a56073b 2075 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2
AnnaBridge 143:86740a56073b 2076 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3
AnnaBridge 143:86740a56073b 2077 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4
AnnaBridge 143:86740a56073b 2078 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5
AnnaBridge 143:86740a56073b 2079 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6
AnnaBridge 143:86740a56073b 2080 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7
AnnaBridge 143:86740a56073b 2081 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8
AnnaBridge 143:86740a56073b 2082 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9
AnnaBridge 143:86740a56073b 2083 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10
AnnaBridge 143:86740a56073b 2084 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11
AnnaBridge 143:86740a56073b 2085 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12
AnnaBridge 143:86740a56073b 2086 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13
AnnaBridge 143:86740a56073b 2087 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14
AnnaBridge 143:86740a56073b 2088 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15
AnnaBridge 143:86740a56073b 2089 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16
AnnaBridge 143:86740a56073b 2090 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17
AnnaBridge 143:86740a56073b 2091 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19
AnnaBridge 143:86740a56073b 2092 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20
AnnaBridge 143:86740a56073b 2093 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21
AnnaBridge 143:86740a56073b 2094 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22
AnnaBridge 143:86740a56073b 2095
AnnaBridge 143:86740a56073b 2096 /******************* Bit definition for EXTI_FTSR register *******************/
AnnaBridge 143:86740a56073b 2097 #define EXTI_FTSR_FT0_Pos (0U)
AnnaBridge 143:86740a56073b 2098 #define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2099 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 143:86740a56073b 2100 #define EXTI_FTSR_FT1_Pos (1U)
AnnaBridge 143:86740a56073b 2101 #define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2102 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 143:86740a56073b 2103 #define EXTI_FTSR_FT2_Pos (2U)
AnnaBridge 143:86740a56073b 2104 #define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2105 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 143:86740a56073b 2106 #define EXTI_FTSR_FT3_Pos (3U)
AnnaBridge 143:86740a56073b 2107 #define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2108 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 143:86740a56073b 2109 #define EXTI_FTSR_FT4_Pos (4U)
AnnaBridge 143:86740a56073b 2110 #define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2111 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 143:86740a56073b 2112 #define EXTI_FTSR_FT5_Pos (5U)
AnnaBridge 143:86740a56073b 2113 #define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2114 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 143:86740a56073b 2115 #define EXTI_FTSR_FT6_Pos (6U)
AnnaBridge 143:86740a56073b 2116 #define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2117 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 143:86740a56073b 2118 #define EXTI_FTSR_FT7_Pos (7U)
AnnaBridge 143:86740a56073b 2119 #define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2120 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 143:86740a56073b 2121 #define EXTI_FTSR_FT8_Pos (8U)
AnnaBridge 143:86740a56073b 2122 #define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2123 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 143:86740a56073b 2124 #define EXTI_FTSR_FT9_Pos (9U)
AnnaBridge 143:86740a56073b 2125 #define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2126 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 143:86740a56073b 2127 #define EXTI_FTSR_FT10_Pos (10U)
AnnaBridge 143:86740a56073b 2128 #define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2129 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 143:86740a56073b 2130 #define EXTI_FTSR_FT11_Pos (11U)
AnnaBridge 143:86740a56073b 2131 #define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2132 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 143:86740a56073b 2133 #define EXTI_FTSR_FT12_Pos (12U)
AnnaBridge 143:86740a56073b 2134 #define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2135 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 143:86740a56073b 2136 #define EXTI_FTSR_FT13_Pos (13U)
AnnaBridge 143:86740a56073b 2137 #define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2138 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 143:86740a56073b 2139 #define EXTI_FTSR_FT14_Pos (14U)
AnnaBridge 143:86740a56073b 2140 #define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2141 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 143:86740a56073b 2142 #define EXTI_FTSR_FT15_Pos (15U)
AnnaBridge 143:86740a56073b 2143 #define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2144 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 143:86740a56073b 2145 #define EXTI_FTSR_FT16_Pos (16U)
AnnaBridge 143:86740a56073b 2146 #define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2147 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 143:86740a56073b 2148 #define EXTI_FTSR_FT17_Pos (17U)
AnnaBridge 143:86740a56073b 2149 #define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2150 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 143:86740a56073b 2151 #define EXTI_FTSR_FT19_Pos (19U)
AnnaBridge 143:86740a56073b 2152 #define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2153 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 143:86740a56073b 2154 #define EXTI_FTSR_FT20_Pos (20U)
AnnaBridge 143:86740a56073b 2155 #define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2156 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 143:86740a56073b 2157 #define EXTI_FTSR_FT21_Pos (21U)
AnnaBridge 143:86740a56073b 2158 #define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2159 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 143:86740a56073b 2160 #define EXTI_FTSR_FT22_Pos (22U)
AnnaBridge 143:86740a56073b 2161 #define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2162 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 143:86740a56073b 2163
AnnaBridge 143:86740a56073b 2164 /* Legacy defines */
AnnaBridge 143:86740a56073b 2165 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0
AnnaBridge 143:86740a56073b 2166 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1
AnnaBridge 143:86740a56073b 2167 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2
AnnaBridge 143:86740a56073b 2168 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3
AnnaBridge 143:86740a56073b 2169 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4
AnnaBridge 143:86740a56073b 2170 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5
AnnaBridge 143:86740a56073b 2171 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6
AnnaBridge 143:86740a56073b 2172 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7
AnnaBridge 143:86740a56073b 2173 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8
AnnaBridge 143:86740a56073b 2174 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9
AnnaBridge 143:86740a56073b 2175 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10
AnnaBridge 143:86740a56073b 2176 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11
AnnaBridge 143:86740a56073b 2177 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12
AnnaBridge 143:86740a56073b 2178 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13
AnnaBridge 143:86740a56073b 2179 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14
AnnaBridge 143:86740a56073b 2180 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15
AnnaBridge 143:86740a56073b 2181 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16
AnnaBridge 143:86740a56073b 2182 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17
AnnaBridge 143:86740a56073b 2183 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19
AnnaBridge 143:86740a56073b 2184 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20
AnnaBridge 143:86740a56073b 2185 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21
AnnaBridge 143:86740a56073b 2186 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22
AnnaBridge 143:86740a56073b 2187
AnnaBridge 143:86740a56073b 2188 /******************* Bit definition for EXTI_SWIER register *******************/
AnnaBridge 143:86740a56073b 2189 #define EXTI_SWIER_SWI0_Pos (0U)
AnnaBridge 143:86740a56073b 2190 #define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2191 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 143:86740a56073b 2192 #define EXTI_SWIER_SWI1_Pos (1U)
AnnaBridge 143:86740a56073b 2193 #define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2194 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 143:86740a56073b 2195 #define EXTI_SWIER_SWI2_Pos (2U)
AnnaBridge 143:86740a56073b 2196 #define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2197 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 143:86740a56073b 2198 #define EXTI_SWIER_SWI3_Pos (3U)
AnnaBridge 143:86740a56073b 2199 #define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2200 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 143:86740a56073b 2201 #define EXTI_SWIER_SWI4_Pos (4U)
AnnaBridge 143:86740a56073b 2202 #define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2203 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 143:86740a56073b 2204 #define EXTI_SWIER_SWI5_Pos (5U)
AnnaBridge 143:86740a56073b 2205 #define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2206 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 143:86740a56073b 2207 #define EXTI_SWIER_SWI6_Pos (6U)
AnnaBridge 143:86740a56073b 2208 #define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2209 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 143:86740a56073b 2210 #define EXTI_SWIER_SWI7_Pos (7U)
AnnaBridge 143:86740a56073b 2211 #define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2212 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 143:86740a56073b 2213 #define EXTI_SWIER_SWI8_Pos (8U)
AnnaBridge 143:86740a56073b 2214 #define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2215 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 143:86740a56073b 2216 #define EXTI_SWIER_SWI9_Pos (9U)
AnnaBridge 143:86740a56073b 2217 #define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2218 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 143:86740a56073b 2219 #define EXTI_SWIER_SWI10_Pos (10U)
AnnaBridge 143:86740a56073b 2220 #define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2221 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 143:86740a56073b 2222 #define EXTI_SWIER_SWI11_Pos (11U)
AnnaBridge 143:86740a56073b 2223 #define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2224 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 143:86740a56073b 2225 #define EXTI_SWIER_SWI12_Pos (12U)
AnnaBridge 143:86740a56073b 2226 #define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2227 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 143:86740a56073b 2228 #define EXTI_SWIER_SWI13_Pos (13U)
AnnaBridge 143:86740a56073b 2229 #define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2230 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 143:86740a56073b 2231 #define EXTI_SWIER_SWI14_Pos (14U)
AnnaBridge 143:86740a56073b 2232 #define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2233 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 143:86740a56073b 2234 #define EXTI_SWIER_SWI15_Pos (15U)
AnnaBridge 143:86740a56073b 2235 #define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2236 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 143:86740a56073b 2237 #define EXTI_SWIER_SWI16_Pos (16U)
AnnaBridge 143:86740a56073b 2238 #define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2239 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 143:86740a56073b 2240 #define EXTI_SWIER_SWI17_Pos (17U)
AnnaBridge 143:86740a56073b 2241 #define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2242 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 143:86740a56073b 2243 #define EXTI_SWIER_SWI19_Pos (19U)
AnnaBridge 143:86740a56073b 2244 #define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2245 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 143:86740a56073b 2246 #define EXTI_SWIER_SWI20_Pos (20U)
AnnaBridge 143:86740a56073b 2247 #define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2248 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 143:86740a56073b 2249 #define EXTI_SWIER_SWI21_Pos (21U)
AnnaBridge 143:86740a56073b 2250 #define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2251 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 143:86740a56073b 2252 #define EXTI_SWIER_SWI22_Pos (22U)
AnnaBridge 143:86740a56073b 2253 #define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2254 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 143:86740a56073b 2255
AnnaBridge 143:86740a56073b 2256 /* Legacy defines */
AnnaBridge 143:86740a56073b 2257 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
AnnaBridge 143:86740a56073b 2258 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
AnnaBridge 143:86740a56073b 2259 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
AnnaBridge 143:86740a56073b 2260 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
AnnaBridge 143:86740a56073b 2261 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
AnnaBridge 143:86740a56073b 2262 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
AnnaBridge 143:86740a56073b 2263 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
AnnaBridge 143:86740a56073b 2264 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
AnnaBridge 143:86740a56073b 2265 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
AnnaBridge 143:86740a56073b 2266 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
AnnaBridge 143:86740a56073b 2267 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
AnnaBridge 143:86740a56073b 2268 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
AnnaBridge 143:86740a56073b 2269 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
AnnaBridge 143:86740a56073b 2270 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
AnnaBridge 143:86740a56073b 2271 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
AnnaBridge 143:86740a56073b 2272 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
AnnaBridge 143:86740a56073b 2273 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
AnnaBridge 143:86740a56073b 2274 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
AnnaBridge 143:86740a56073b 2275 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
AnnaBridge 143:86740a56073b 2276 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
AnnaBridge 143:86740a56073b 2277 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
AnnaBridge 143:86740a56073b 2278 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
AnnaBridge 143:86740a56073b 2279
AnnaBridge 143:86740a56073b 2280 /****************** Bit definition for EXTI_PR register *********************/
AnnaBridge 143:86740a56073b 2281 #define EXTI_PR_PIF0_Pos (0U)
AnnaBridge 143:86740a56073b 2282 #define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2283 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
AnnaBridge 143:86740a56073b 2284 #define EXTI_PR_PIF1_Pos (1U)
AnnaBridge 143:86740a56073b 2285 #define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2286 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
AnnaBridge 143:86740a56073b 2287 #define EXTI_PR_PIF2_Pos (2U)
AnnaBridge 143:86740a56073b 2288 #define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2289 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
AnnaBridge 143:86740a56073b 2290 #define EXTI_PR_PIF3_Pos (3U)
AnnaBridge 143:86740a56073b 2291 #define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2292 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
AnnaBridge 143:86740a56073b 2293 #define EXTI_PR_PIF4_Pos (4U)
AnnaBridge 143:86740a56073b 2294 #define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2295 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
AnnaBridge 143:86740a56073b 2296 #define EXTI_PR_PIF5_Pos (5U)
AnnaBridge 143:86740a56073b 2297 #define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2298 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
AnnaBridge 143:86740a56073b 2299 #define EXTI_PR_PIF6_Pos (6U)
AnnaBridge 143:86740a56073b 2300 #define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2301 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
AnnaBridge 143:86740a56073b 2302 #define EXTI_PR_PIF7_Pos (7U)
AnnaBridge 143:86740a56073b 2303 #define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2304 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
AnnaBridge 143:86740a56073b 2305 #define EXTI_PR_PIF8_Pos (8U)
AnnaBridge 143:86740a56073b 2306 #define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2307 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
AnnaBridge 143:86740a56073b 2308 #define EXTI_PR_PIF9_Pos (9U)
AnnaBridge 143:86740a56073b 2309 #define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2310 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
AnnaBridge 143:86740a56073b 2311 #define EXTI_PR_PIF10_Pos (10U)
AnnaBridge 143:86740a56073b 2312 #define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2313 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
AnnaBridge 143:86740a56073b 2314 #define EXTI_PR_PIF11_Pos (11U)
AnnaBridge 143:86740a56073b 2315 #define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2316 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
AnnaBridge 143:86740a56073b 2317 #define EXTI_PR_PIF12_Pos (12U)
AnnaBridge 143:86740a56073b 2318 #define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2319 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
AnnaBridge 143:86740a56073b 2320 #define EXTI_PR_PIF13_Pos (13U)
AnnaBridge 143:86740a56073b 2321 #define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2322 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
AnnaBridge 143:86740a56073b 2323 #define EXTI_PR_PIF14_Pos (14U)
AnnaBridge 143:86740a56073b 2324 #define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2325 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
AnnaBridge 143:86740a56073b 2326 #define EXTI_PR_PIF15_Pos (15U)
AnnaBridge 143:86740a56073b 2327 #define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2328 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
AnnaBridge 143:86740a56073b 2329 #define EXTI_PR_PIF16_Pos (16U)
AnnaBridge 143:86740a56073b 2330 #define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2331 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
AnnaBridge 143:86740a56073b 2332 #define EXTI_PR_PIF17_Pos (17U)
AnnaBridge 143:86740a56073b 2333 #define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2334 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
AnnaBridge 143:86740a56073b 2335 #define EXTI_PR_PIF19_Pos (19U)
AnnaBridge 143:86740a56073b 2336 #define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2337 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
AnnaBridge 143:86740a56073b 2338 #define EXTI_PR_PIF20_Pos (20U)
AnnaBridge 143:86740a56073b 2339 #define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2340 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
AnnaBridge 143:86740a56073b 2341 #define EXTI_PR_PIF21_Pos (21U)
AnnaBridge 143:86740a56073b 2342 #define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2343 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
AnnaBridge 143:86740a56073b 2344 #define EXTI_PR_PIF22_Pos (22U)
AnnaBridge 143:86740a56073b 2345 #define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2346 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
AnnaBridge 143:86740a56073b 2347
AnnaBridge 143:86740a56073b 2348 /* Legacy defines */
AnnaBridge 143:86740a56073b 2349 #define EXTI_PR_PR0 EXTI_PR_PIF0
AnnaBridge 143:86740a56073b 2350 #define EXTI_PR_PR1 EXTI_PR_PIF1
AnnaBridge 143:86740a56073b 2351 #define EXTI_PR_PR2 EXTI_PR_PIF2
AnnaBridge 143:86740a56073b 2352 #define EXTI_PR_PR3 EXTI_PR_PIF3
AnnaBridge 143:86740a56073b 2353 #define EXTI_PR_PR4 EXTI_PR_PIF4
AnnaBridge 143:86740a56073b 2354 #define EXTI_PR_PR5 EXTI_PR_PIF5
AnnaBridge 143:86740a56073b 2355 #define EXTI_PR_PR6 EXTI_PR_PIF6
AnnaBridge 143:86740a56073b 2356 #define EXTI_PR_PR7 EXTI_PR_PIF7
AnnaBridge 143:86740a56073b 2357 #define EXTI_PR_PR8 EXTI_PR_PIF8
AnnaBridge 143:86740a56073b 2358 #define EXTI_PR_PR9 EXTI_PR_PIF9
AnnaBridge 143:86740a56073b 2359 #define EXTI_PR_PR10 EXTI_PR_PIF10
AnnaBridge 143:86740a56073b 2360 #define EXTI_PR_PR11 EXTI_PR_PIF11
AnnaBridge 143:86740a56073b 2361 #define EXTI_PR_PR12 EXTI_PR_PIF12
AnnaBridge 143:86740a56073b 2362 #define EXTI_PR_PR13 EXTI_PR_PIF13
AnnaBridge 143:86740a56073b 2363 #define EXTI_PR_PR14 EXTI_PR_PIF14
AnnaBridge 143:86740a56073b 2364 #define EXTI_PR_PR15 EXTI_PR_PIF15
AnnaBridge 143:86740a56073b 2365 #define EXTI_PR_PR16 EXTI_PR_PIF16
AnnaBridge 143:86740a56073b 2366 #define EXTI_PR_PR17 EXTI_PR_PIF17
AnnaBridge 143:86740a56073b 2367 #define EXTI_PR_PR19 EXTI_PR_PIF19
AnnaBridge 143:86740a56073b 2368 #define EXTI_PR_PR20 EXTI_PR_PIF20
AnnaBridge 143:86740a56073b 2369 #define EXTI_PR_PR21 EXTI_PR_PIF21
AnnaBridge 143:86740a56073b 2370 #define EXTI_PR_PR22 EXTI_PR_PIF22
AnnaBridge 143:86740a56073b 2371
AnnaBridge 143:86740a56073b 2372 /******************************************************************************/
AnnaBridge 143:86740a56073b 2373 /* */
AnnaBridge 143:86740a56073b 2374 /* FLASH and Option Bytes Registers */
AnnaBridge 143:86740a56073b 2375 /* */
AnnaBridge 143:86740a56073b 2376 /******************************************************************************/
AnnaBridge 143:86740a56073b 2377
AnnaBridge 143:86740a56073b 2378 /******************* Bit definition for FLASH_ACR register ******************/
AnnaBridge 143:86740a56073b 2379 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 143:86740a56073b 2380 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2381 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
AnnaBridge 143:86740a56073b 2382 #define FLASH_ACR_PRFTEN_Pos (1U)
AnnaBridge 143:86740a56073b 2383 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2384 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
AnnaBridge 143:86740a56073b 2385 #define FLASH_ACR_SLEEP_PD_Pos (3U)
AnnaBridge 143:86740a56073b 2386 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2387 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
AnnaBridge 143:86740a56073b 2388 #define FLASH_ACR_RUN_PD_Pos (4U)
AnnaBridge 143:86740a56073b 2389 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2390 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
AnnaBridge 143:86740a56073b 2391 #define FLASH_ACR_DISAB_BUF_Pos (5U)
AnnaBridge 143:86740a56073b 2392 #define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2393 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
AnnaBridge 143:86740a56073b 2394 #define FLASH_ACR_PRE_READ_Pos (6U)
AnnaBridge 143:86740a56073b 2395 #define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2396 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
AnnaBridge 143:86740a56073b 2397
AnnaBridge 143:86740a56073b 2398 /******************* Bit definition for FLASH_PECR register ******************/
AnnaBridge 143:86740a56073b 2399 #define FLASH_PECR_PELOCK_Pos (0U)
AnnaBridge 143:86740a56073b 2400 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2401 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
AnnaBridge 143:86740a56073b 2402 #define FLASH_PECR_PRGLOCK_Pos (1U)
AnnaBridge 143:86740a56073b 2403 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2404 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
AnnaBridge 143:86740a56073b 2405 #define FLASH_PECR_OPTLOCK_Pos (2U)
AnnaBridge 143:86740a56073b 2406 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2407 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
AnnaBridge 143:86740a56073b 2408 #define FLASH_PECR_PROG_Pos (3U)
AnnaBridge 143:86740a56073b 2409 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2410 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
AnnaBridge 143:86740a56073b 2411 #define FLASH_PECR_DATA_Pos (4U)
AnnaBridge 143:86740a56073b 2412 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2413 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
AnnaBridge 143:86740a56073b 2414 #define FLASH_PECR_FIX_Pos (8U)
AnnaBridge 143:86740a56073b 2415 #define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2416 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
AnnaBridge 143:86740a56073b 2417 #define FLASH_PECR_ERASE_Pos (9U)
AnnaBridge 143:86740a56073b 2418 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2419 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
AnnaBridge 143:86740a56073b 2420 #define FLASH_PECR_FPRG_Pos (10U)
AnnaBridge 143:86740a56073b 2421 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2422 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
AnnaBridge 143:86740a56073b 2423 #define FLASH_PECR_PARALLBANK_Pos (15U)
AnnaBridge 143:86740a56073b 2424 #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2425 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
AnnaBridge 143:86740a56073b 2426 #define FLASH_PECR_EOPIE_Pos (16U)
AnnaBridge 143:86740a56073b 2427 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2428 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
AnnaBridge 143:86740a56073b 2429 #define FLASH_PECR_ERRIE_Pos (17U)
AnnaBridge 143:86740a56073b 2430 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2431 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
AnnaBridge 143:86740a56073b 2432 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
AnnaBridge 143:86740a56073b 2433 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 2434 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
AnnaBridge 143:86740a56073b 2435 #define FLASH_PECR_HALF_ARRAY_Pos (19U)
AnnaBridge 143:86740a56073b 2436 #define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2437 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
AnnaBridge 143:86740a56073b 2438 #define FLASH_PECR_NZDISABLE_Pos (22U)
AnnaBridge 143:86740a56073b 2439 #define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2440 #define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
AnnaBridge 143:86740a56073b 2441
AnnaBridge 143:86740a56073b 2442 /****************** Bit definition for FLASH_PDKEYR register ******************/
AnnaBridge 143:86740a56073b 2443 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
AnnaBridge 143:86740a56073b 2444 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 2445 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
AnnaBridge 143:86740a56073b 2446
AnnaBridge 143:86740a56073b 2447 /****************** Bit definition for FLASH_PEKEYR register ******************/
AnnaBridge 143:86740a56073b 2448 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
AnnaBridge 143:86740a56073b 2449 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 2450 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
AnnaBridge 143:86740a56073b 2451
AnnaBridge 143:86740a56073b 2452 /****************** Bit definition for FLASH_PRGKEYR register ******************/
AnnaBridge 143:86740a56073b 2453 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
AnnaBridge 143:86740a56073b 2454 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 2455 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
AnnaBridge 143:86740a56073b 2456
AnnaBridge 143:86740a56073b 2457 /****************** Bit definition for FLASH_OPTKEYR register ******************/
AnnaBridge 143:86740a56073b 2458 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
AnnaBridge 143:86740a56073b 2459 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 2460 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
AnnaBridge 143:86740a56073b 2461
AnnaBridge 143:86740a56073b 2462 /****************** Bit definition for FLASH_SR register *******************/
AnnaBridge 143:86740a56073b 2463 #define FLASH_SR_BSY_Pos (0U)
AnnaBridge 143:86740a56073b 2464 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2465 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
AnnaBridge 143:86740a56073b 2466 #define FLASH_SR_EOP_Pos (1U)
AnnaBridge 143:86740a56073b 2467 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2468 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
AnnaBridge 143:86740a56073b 2469 #define FLASH_SR_HVOFF_Pos (2U)
AnnaBridge 143:86740a56073b 2470 #define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2471 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
AnnaBridge 143:86740a56073b 2472 #define FLASH_SR_READY_Pos (3U)
AnnaBridge 143:86740a56073b 2473 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2474 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
AnnaBridge 143:86740a56073b 2475
AnnaBridge 143:86740a56073b 2476 #define FLASH_SR_WRPERR_Pos (8U)
AnnaBridge 143:86740a56073b 2477 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2478 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
AnnaBridge 143:86740a56073b 2479 #define FLASH_SR_PGAERR_Pos (9U)
AnnaBridge 143:86740a56073b 2480 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2481 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
AnnaBridge 143:86740a56073b 2482 #define FLASH_SR_SIZERR_Pos (10U)
AnnaBridge 143:86740a56073b 2483 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2484 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
AnnaBridge 143:86740a56073b 2485 #define FLASH_SR_OPTVERR_Pos (11U)
AnnaBridge 143:86740a56073b 2486 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2487 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
AnnaBridge 143:86740a56073b 2488 #define FLASH_SR_RDERR_Pos (13U)
AnnaBridge 143:86740a56073b 2489 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2490 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
AnnaBridge 143:86740a56073b 2491 #define FLASH_SR_NOTZEROERR_Pos (16U)
AnnaBridge 143:86740a56073b 2492 #define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2493 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
AnnaBridge 143:86740a56073b 2494 #define FLASH_SR_FWWERR_Pos (17U)
AnnaBridge 143:86740a56073b 2495 #define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2496 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
AnnaBridge 143:86740a56073b 2497
AnnaBridge 143:86740a56073b 2498 /* Legacy defines */
AnnaBridge 143:86740a56073b 2499 #define FLASH_SR_FWWER FLASH_SR_FWWERR
AnnaBridge 143:86740a56073b 2500 #define FLASH_SR_ENHV FLASH_SR_HVOFF
AnnaBridge 143:86740a56073b 2501 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
AnnaBridge 143:86740a56073b 2502
AnnaBridge 143:86740a56073b 2503 /****************** Bit definition for FLASH_OPTR register *******************/
AnnaBridge 143:86740a56073b 2504 #define FLASH_OPTR_RDPROT_Pos (0U)
AnnaBridge 143:86740a56073b 2505 #define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 2506 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
AnnaBridge 143:86740a56073b 2507 #define FLASH_OPTR_WPRMOD_Pos (8U)
AnnaBridge 143:86740a56073b 2508 #define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2509 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
AnnaBridge 143:86740a56073b 2510 #define FLASH_OPTR_BOR_LEV_Pos (16U)
AnnaBridge 143:86740a56073b 2511 #define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 2512 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
AnnaBridge 143:86740a56073b 2513 #define FLASH_OPTR_IWDG_SW_Pos (20U)
AnnaBridge 143:86740a56073b 2514 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2515 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
AnnaBridge 143:86740a56073b 2516 #define FLASH_OPTR_nRST_STOP_Pos (21U)
AnnaBridge 143:86740a56073b 2517 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2518 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
AnnaBridge 143:86740a56073b 2519 #define FLASH_OPTR_nRST_STDBY_Pos (22U)
AnnaBridge 143:86740a56073b 2520 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2521 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
AnnaBridge 143:86740a56073b 2522 #define FLASH_OPTR_BFB2_Pos (23U)
AnnaBridge 143:86740a56073b 2523 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 2524 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
AnnaBridge 143:86740a56073b 2525 #define FLASH_OPTR_USER_Pos (20U)
AnnaBridge 143:86740a56073b 2526 #define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
AnnaBridge 143:86740a56073b 2527 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
AnnaBridge 143:86740a56073b 2528 #define FLASH_OPTR_BOOT1_Pos (31U)
AnnaBridge 143:86740a56073b 2529 #define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 2530 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
AnnaBridge 143:86740a56073b 2531
AnnaBridge 143:86740a56073b 2532 /****************** Bit definition for FLASH_WRPR register ******************/
AnnaBridge 143:86740a56073b 2533 #define FLASH_WRPR_WRP_Pos (0U)
AnnaBridge 143:86740a56073b 2534 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 2535 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
AnnaBridge 143:86740a56073b 2536
AnnaBridge 143:86740a56073b 2537 /******************************************************************************/
AnnaBridge 143:86740a56073b 2538 /* */
AnnaBridge 143:86740a56073b 2539 /* General Purpose IOs (GPIO) */
AnnaBridge 143:86740a56073b 2540 /* */
AnnaBridge 143:86740a56073b 2541 /******************************************************************************/
AnnaBridge 143:86740a56073b 2542 /******************* Bit definition for GPIO_MODER register *****************/
AnnaBridge 143:86740a56073b 2543 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 143:86740a56073b 2544 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 2545 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 143:86740a56073b 2546 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2547 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2548 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 143:86740a56073b 2549 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 2550 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 143:86740a56073b 2551 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2552 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2553 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 143:86740a56073b 2554 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 2555 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 143:86740a56073b 2556 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2557 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2558 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 143:86740a56073b 2559 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 143:86740a56073b 2560 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 143:86740a56073b 2561 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2562 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2563 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 143:86740a56073b 2564 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 2565 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 143:86740a56073b 2566 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2567 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2568 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 143:86740a56073b 2569 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 2570 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 143:86740a56073b 2571 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2572 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2573 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 143:86740a56073b 2574 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 2575 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 143:86740a56073b 2576 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2577 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2578 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 143:86740a56073b 2579 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 143:86740a56073b 2580 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 143:86740a56073b 2581 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2582 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2583 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 143:86740a56073b 2584 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 2585 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 143:86740a56073b 2586 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2587 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2588 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 143:86740a56073b 2589 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 143:86740a56073b 2590 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 143:86740a56073b 2591 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 2592 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2593 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 143:86740a56073b 2594 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 2595 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 143:86740a56073b 2596 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2597 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2598 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 143:86740a56073b 2599 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 2600 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 143:86740a56073b 2601 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2602 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 2603 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 143:86740a56073b 2604 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 143:86740a56073b 2605 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 143:86740a56073b 2606 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 2607 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 2608 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 143:86740a56073b 2609 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 143:86740a56073b 2610 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 143:86740a56073b 2611 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 2612 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 2613 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 143:86740a56073b 2614 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 2615 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 143:86740a56073b 2616 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 2617 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 2618 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 143:86740a56073b 2619 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 143:86740a56073b 2620 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 143:86740a56073b 2621 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 2622 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 2623
AnnaBridge 143:86740a56073b 2624 /****************** Bit definition for GPIO_OTYPER register *****************/
AnnaBridge 143:86740a56073b 2625 #define GPIO_OTYPER_OT_0 (0x00000001U)
AnnaBridge 143:86740a56073b 2626 #define GPIO_OTYPER_OT_1 (0x00000002U)
AnnaBridge 143:86740a56073b 2627 #define GPIO_OTYPER_OT_2 (0x00000004U)
AnnaBridge 143:86740a56073b 2628 #define GPIO_OTYPER_OT_3 (0x00000008U)
AnnaBridge 143:86740a56073b 2629 #define GPIO_OTYPER_OT_4 (0x00000010U)
AnnaBridge 143:86740a56073b 2630 #define GPIO_OTYPER_OT_5 (0x00000020U)
AnnaBridge 143:86740a56073b 2631 #define GPIO_OTYPER_OT_6 (0x00000040U)
AnnaBridge 143:86740a56073b 2632 #define GPIO_OTYPER_OT_7 (0x00000080U)
AnnaBridge 143:86740a56073b 2633 #define GPIO_OTYPER_OT_8 (0x00000100U)
AnnaBridge 143:86740a56073b 2634 #define GPIO_OTYPER_OT_9 (0x00000200U)
AnnaBridge 143:86740a56073b 2635 #define GPIO_OTYPER_OT_10 (0x00000400U)
AnnaBridge 143:86740a56073b 2636 #define GPIO_OTYPER_OT_11 (0x00000800U)
AnnaBridge 143:86740a56073b 2637 #define GPIO_OTYPER_OT_12 (0x00001000U)
AnnaBridge 143:86740a56073b 2638 #define GPIO_OTYPER_OT_13 (0x00002000U)
AnnaBridge 143:86740a56073b 2639 #define GPIO_OTYPER_OT_14 (0x00004000U)
AnnaBridge 143:86740a56073b 2640 #define GPIO_OTYPER_OT_15 (0x00008000U)
AnnaBridge 143:86740a56073b 2641
AnnaBridge 143:86740a56073b 2642 /**************** Bit definition for GPIO_OSPEEDR register ******************/
AnnaBridge 143:86740a56073b 2643 #define GPIO_OSPEEDER_OSPEED0_Pos (0U)
AnnaBridge 143:86740a56073b 2644 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 2645 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
AnnaBridge 143:86740a56073b 2646 #define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2647 #define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2648 #define GPIO_OSPEEDER_OSPEED1_Pos (2U)
AnnaBridge 143:86740a56073b 2649 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 2650 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
AnnaBridge 143:86740a56073b 2651 #define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2652 #define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2653 #define GPIO_OSPEEDER_OSPEED2_Pos (4U)
AnnaBridge 143:86740a56073b 2654 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 2655 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
AnnaBridge 143:86740a56073b 2656 #define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2657 #define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2658 #define GPIO_OSPEEDER_OSPEED3_Pos (6U)
AnnaBridge 143:86740a56073b 2659 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 143:86740a56073b 2660 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
AnnaBridge 143:86740a56073b 2661 #define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2662 #define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2663 #define GPIO_OSPEEDER_OSPEED4_Pos (8U)
AnnaBridge 143:86740a56073b 2664 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 2665 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
AnnaBridge 143:86740a56073b 2666 #define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2667 #define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2668 #define GPIO_OSPEEDER_OSPEED5_Pos (10U)
AnnaBridge 143:86740a56073b 2669 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 2670 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
AnnaBridge 143:86740a56073b 2671 #define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2672 #define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2673 #define GPIO_OSPEEDER_OSPEED6_Pos (12U)
AnnaBridge 143:86740a56073b 2674 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 2675 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
AnnaBridge 143:86740a56073b 2676 #define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2677 #define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2678 #define GPIO_OSPEEDER_OSPEED7_Pos (14U)
AnnaBridge 143:86740a56073b 2679 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 143:86740a56073b 2680 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
AnnaBridge 143:86740a56073b 2681 #define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2682 #define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2683 #define GPIO_OSPEEDER_OSPEED8_Pos (16U)
AnnaBridge 143:86740a56073b 2684 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 2685 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
AnnaBridge 143:86740a56073b 2686 #define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2687 #define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2688 #define GPIO_OSPEEDER_OSPEED9_Pos (18U)
AnnaBridge 143:86740a56073b 2689 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 143:86740a56073b 2690 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
AnnaBridge 143:86740a56073b 2691 #define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 2692 #define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2693 #define GPIO_OSPEEDER_OSPEED10_Pos (20U)
AnnaBridge 143:86740a56073b 2694 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 2695 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
AnnaBridge 143:86740a56073b 2696 #define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2697 #define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2698 #define GPIO_OSPEEDER_OSPEED11_Pos (22U)
AnnaBridge 143:86740a56073b 2699 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 2700 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
AnnaBridge 143:86740a56073b 2701 #define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2702 #define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 2703 #define GPIO_OSPEEDER_OSPEED12_Pos (24U)
AnnaBridge 143:86740a56073b 2704 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 143:86740a56073b 2705 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
AnnaBridge 143:86740a56073b 2706 #define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 2707 #define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 2708 #define GPIO_OSPEEDER_OSPEED13_Pos (26U)
AnnaBridge 143:86740a56073b 2709 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 143:86740a56073b 2710 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
AnnaBridge 143:86740a56073b 2711 #define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 2712 #define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 2713 #define GPIO_OSPEEDER_OSPEED14_Pos (28U)
AnnaBridge 143:86740a56073b 2714 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 2715 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
AnnaBridge 143:86740a56073b 2716 #define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 2717 #define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 2718 #define GPIO_OSPEEDER_OSPEED15_Pos (30U)
AnnaBridge 143:86740a56073b 2719 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 143:86740a56073b 2720 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
AnnaBridge 143:86740a56073b 2721 #define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 2722 #define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 2723
AnnaBridge 143:86740a56073b 2724 /******************* Bit definition for GPIO_PUPDR register ******************/
AnnaBridge 143:86740a56073b 2725 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 143:86740a56073b 2726 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 2727 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 143:86740a56073b 2728 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2729 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2730 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 143:86740a56073b 2731 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 2732 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 143:86740a56073b 2733 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2734 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2735 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 143:86740a56073b 2736 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 2737 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 143:86740a56073b 2738 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2739 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2740 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 143:86740a56073b 2741 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 143:86740a56073b 2742 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 143:86740a56073b 2743 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2744 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2745 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 143:86740a56073b 2746 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 2747 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 143:86740a56073b 2748 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2749 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2750 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 143:86740a56073b 2751 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 2752 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 143:86740a56073b 2753 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2754 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2755 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 143:86740a56073b 2756 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 2757 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 143:86740a56073b 2758 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2759 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2760 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 143:86740a56073b 2761 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 143:86740a56073b 2762 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 143:86740a56073b 2763 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2764 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2765 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 143:86740a56073b 2766 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 2767 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 143:86740a56073b 2768 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2769 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 2770 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 143:86740a56073b 2771 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 143:86740a56073b 2772 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 143:86740a56073b 2773 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 2774 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 2775 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 143:86740a56073b 2776 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 2777 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 143:86740a56073b 2778 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 2779 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 2780 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 143:86740a56073b 2781 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 2782 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 143:86740a56073b 2783 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 2784 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 2785 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 143:86740a56073b 2786 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 143:86740a56073b 2787 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 143:86740a56073b 2788 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 2789 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 2790 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 143:86740a56073b 2791 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 143:86740a56073b 2792 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 143:86740a56073b 2793 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 2794 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 2795 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 143:86740a56073b 2796 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 2797 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 143:86740a56073b 2798 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 2799 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 2800 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 143:86740a56073b 2801 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 143:86740a56073b 2802 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 143:86740a56073b 2803 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 2804 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 2805
AnnaBridge 143:86740a56073b 2806 /******************* Bit definition for GPIO_IDR register *******************/
AnnaBridge 143:86740a56073b 2807 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 143:86740a56073b 2808 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2809 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 143:86740a56073b 2810 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 143:86740a56073b 2811 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2812 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 143:86740a56073b 2813 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 143:86740a56073b 2814 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2815 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 143:86740a56073b 2816 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 143:86740a56073b 2817 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2818 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 143:86740a56073b 2819 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 143:86740a56073b 2820 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2821 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 143:86740a56073b 2822 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 143:86740a56073b 2823 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2824 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 143:86740a56073b 2825 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 143:86740a56073b 2826 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2827 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 143:86740a56073b 2828 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 143:86740a56073b 2829 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2830 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 143:86740a56073b 2831 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 143:86740a56073b 2832 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2833 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 143:86740a56073b 2834 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 143:86740a56073b 2835 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2836 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 143:86740a56073b 2837 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 143:86740a56073b 2838 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2839 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 143:86740a56073b 2840 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 143:86740a56073b 2841 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2842 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 143:86740a56073b 2843 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 143:86740a56073b 2844 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2845 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 143:86740a56073b 2846 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 143:86740a56073b 2847 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2848 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 143:86740a56073b 2849 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 143:86740a56073b 2850 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2851 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 143:86740a56073b 2852 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 143:86740a56073b 2853 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2854 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 143:86740a56073b 2855
AnnaBridge 143:86740a56073b 2856 /****************** Bit definition for GPIO_ODR register ********************/
AnnaBridge 143:86740a56073b 2857 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 143:86740a56073b 2858 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2859 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 143:86740a56073b 2860 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 143:86740a56073b 2861 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2862 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 143:86740a56073b 2863 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 143:86740a56073b 2864 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2865 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 143:86740a56073b 2866 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 143:86740a56073b 2867 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2868 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 143:86740a56073b 2869 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 143:86740a56073b 2870 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2871 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 143:86740a56073b 2872 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 143:86740a56073b 2873 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2874 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 143:86740a56073b 2875 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 143:86740a56073b 2876 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2877 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 143:86740a56073b 2878 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 143:86740a56073b 2879 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2880 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 143:86740a56073b 2881 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 143:86740a56073b 2882 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2883 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 143:86740a56073b 2884 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 143:86740a56073b 2885 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2886 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 143:86740a56073b 2887 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 143:86740a56073b 2888 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2889 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 143:86740a56073b 2890 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 143:86740a56073b 2891 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2892 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 143:86740a56073b 2893 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 143:86740a56073b 2894 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2895 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 143:86740a56073b 2896 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 143:86740a56073b 2897 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2898 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 143:86740a56073b 2899 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 143:86740a56073b 2900 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2901 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 143:86740a56073b 2902 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 143:86740a56073b 2903 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2904 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 143:86740a56073b 2905
AnnaBridge 143:86740a56073b 2906 /****************** Bit definition for GPIO_BSRR register ********************/
AnnaBridge 143:86740a56073b 2907 #define GPIO_BSRR_BS_0 (0x00000001U)
AnnaBridge 143:86740a56073b 2908 #define GPIO_BSRR_BS_1 (0x00000002U)
AnnaBridge 143:86740a56073b 2909 #define GPIO_BSRR_BS_2 (0x00000004U)
AnnaBridge 143:86740a56073b 2910 #define GPIO_BSRR_BS_3 (0x00000008U)
AnnaBridge 143:86740a56073b 2911 #define GPIO_BSRR_BS_4 (0x00000010U)
AnnaBridge 143:86740a56073b 2912 #define GPIO_BSRR_BS_5 (0x00000020U)
AnnaBridge 143:86740a56073b 2913 #define GPIO_BSRR_BS_6 (0x00000040U)
AnnaBridge 143:86740a56073b 2914 #define GPIO_BSRR_BS_7 (0x00000080U)
AnnaBridge 143:86740a56073b 2915 #define GPIO_BSRR_BS_8 (0x00000100U)
AnnaBridge 143:86740a56073b 2916 #define GPIO_BSRR_BS_9 (0x00000200U)
AnnaBridge 143:86740a56073b 2917 #define GPIO_BSRR_BS_10 (0x00000400U)
AnnaBridge 143:86740a56073b 2918 #define GPIO_BSRR_BS_11 (0x00000800U)
AnnaBridge 143:86740a56073b 2919 #define GPIO_BSRR_BS_12 (0x00001000U)
AnnaBridge 143:86740a56073b 2920 #define GPIO_BSRR_BS_13 (0x00002000U)
AnnaBridge 143:86740a56073b 2921 #define GPIO_BSRR_BS_14 (0x00004000U)
AnnaBridge 143:86740a56073b 2922 #define GPIO_BSRR_BS_15 (0x00008000U)
AnnaBridge 143:86740a56073b 2923 #define GPIO_BSRR_BR_0 (0x00010000U)
AnnaBridge 143:86740a56073b 2924 #define GPIO_BSRR_BR_1 (0x00020000U)
AnnaBridge 143:86740a56073b 2925 #define GPIO_BSRR_BR_2 (0x00040000U)
AnnaBridge 143:86740a56073b 2926 #define GPIO_BSRR_BR_3 (0x00080000U)
AnnaBridge 143:86740a56073b 2927 #define GPIO_BSRR_BR_4 (0x00100000U)
AnnaBridge 143:86740a56073b 2928 #define GPIO_BSRR_BR_5 (0x00200000U)
AnnaBridge 143:86740a56073b 2929 #define GPIO_BSRR_BR_6 (0x00400000U)
AnnaBridge 143:86740a56073b 2930 #define GPIO_BSRR_BR_7 (0x00800000U)
AnnaBridge 143:86740a56073b 2931 #define GPIO_BSRR_BR_8 (0x01000000U)
AnnaBridge 143:86740a56073b 2932 #define GPIO_BSRR_BR_9 (0x02000000U)
AnnaBridge 143:86740a56073b 2933 #define GPIO_BSRR_BR_10 (0x04000000U)
AnnaBridge 143:86740a56073b 2934 #define GPIO_BSRR_BR_11 (0x08000000U)
AnnaBridge 143:86740a56073b 2935 #define GPIO_BSRR_BR_12 (0x10000000U)
AnnaBridge 143:86740a56073b 2936 #define GPIO_BSRR_BR_13 (0x20000000U)
AnnaBridge 143:86740a56073b 2937 #define GPIO_BSRR_BR_14 (0x40000000U)
AnnaBridge 143:86740a56073b 2938 #define GPIO_BSRR_BR_15 (0x80000000U)
AnnaBridge 143:86740a56073b 2939
AnnaBridge 143:86740a56073b 2940 /****************** Bit definition for GPIO_LCKR register ********************/
AnnaBridge 143:86740a56073b 2941 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 143:86740a56073b 2942 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 2943 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 143:86740a56073b 2944 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 143:86740a56073b 2945 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 2946 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 143:86740a56073b 2947 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 143:86740a56073b 2948 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 2949 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 143:86740a56073b 2950 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 143:86740a56073b 2951 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 2952 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 143:86740a56073b 2953 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 143:86740a56073b 2954 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 2955 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 143:86740a56073b 2956 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 143:86740a56073b 2957 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 2958 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 143:86740a56073b 2959 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 143:86740a56073b 2960 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 2961 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 143:86740a56073b 2962 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 143:86740a56073b 2963 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 2964 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 143:86740a56073b 2965 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 143:86740a56073b 2966 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 2967 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 143:86740a56073b 2968 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 143:86740a56073b 2969 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 2970 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 143:86740a56073b 2971 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 143:86740a56073b 2972 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 2973 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 143:86740a56073b 2974 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 143:86740a56073b 2975 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 2976 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 143:86740a56073b 2977 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 143:86740a56073b 2978 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 2979 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 143:86740a56073b 2980 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 143:86740a56073b 2981 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 2982 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 143:86740a56073b 2983 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 143:86740a56073b 2984 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 2985 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 143:86740a56073b 2986 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 143:86740a56073b 2987 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 2988 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 143:86740a56073b 2989 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 143:86740a56073b 2990 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 2991 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 143:86740a56073b 2992
AnnaBridge 143:86740a56073b 2993 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 143:86740a56073b 2994 #define GPIO_AFRL_AFRL0_Pos (0U)
AnnaBridge 143:86740a56073b 2995 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 2996 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
AnnaBridge 143:86740a56073b 2997 #define GPIO_AFRL_AFRL1_Pos (4U)
AnnaBridge 143:86740a56073b 2998 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 2999 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
AnnaBridge 143:86740a56073b 3000 #define GPIO_AFRL_AFRL2_Pos (8U)
AnnaBridge 143:86740a56073b 3001 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 3002 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
AnnaBridge 143:86740a56073b 3003 #define GPIO_AFRL_AFRL3_Pos (12U)
AnnaBridge 143:86740a56073b 3004 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 3005 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
AnnaBridge 143:86740a56073b 3006 #define GPIO_AFRL_AFRL4_Pos (16U)
AnnaBridge 143:86740a56073b 3007 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 3008 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
AnnaBridge 143:86740a56073b 3009 #define GPIO_AFRL_AFRL5_Pos (20U)
AnnaBridge 143:86740a56073b 3010 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
AnnaBridge 143:86740a56073b 3011 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
AnnaBridge 143:86740a56073b 3012 #define GPIO_AFRL_AFRL6_Pos (24U)
AnnaBridge 143:86740a56073b 3013 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 3014 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
AnnaBridge 143:86740a56073b 3015 #define GPIO_AFRL_AFRL7_Pos (28U)
AnnaBridge 143:86740a56073b 3016 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
AnnaBridge 143:86740a56073b 3017 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
AnnaBridge 143:86740a56073b 3018
AnnaBridge 143:86740a56073b 3019 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 143:86740a56073b 3020 #define GPIO_AFRH_AFRH0_Pos (0U)
AnnaBridge 143:86740a56073b 3021 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 3022 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
AnnaBridge 143:86740a56073b 3023 #define GPIO_AFRH_AFRH1_Pos (4U)
AnnaBridge 143:86740a56073b 3024 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 3025 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
AnnaBridge 143:86740a56073b 3026 #define GPIO_AFRH_AFRH2_Pos (8U)
AnnaBridge 143:86740a56073b 3027 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 3028 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
AnnaBridge 143:86740a56073b 3029 #define GPIO_AFRH_AFRH3_Pos (12U)
AnnaBridge 143:86740a56073b 3030 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 3031 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
AnnaBridge 143:86740a56073b 3032 #define GPIO_AFRH_AFRH4_Pos (16U)
AnnaBridge 143:86740a56073b 3033 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 3034 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
AnnaBridge 143:86740a56073b 3035 #define GPIO_AFRH_AFRH5_Pos (20U)
AnnaBridge 143:86740a56073b 3036 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
AnnaBridge 143:86740a56073b 3037 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
AnnaBridge 143:86740a56073b 3038 #define GPIO_AFRH_AFRH6_Pos (24U)
AnnaBridge 143:86740a56073b 3039 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 3040 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
AnnaBridge 143:86740a56073b 3041 #define GPIO_AFRH_AFRH7_Pos (28U)
AnnaBridge 143:86740a56073b 3042 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
AnnaBridge 143:86740a56073b 3043 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
AnnaBridge 143:86740a56073b 3044
AnnaBridge 143:86740a56073b 3045 /****************** Bit definition for GPIO_BRR register *********************/
AnnaBridge 143:86740a56073b 3046 #define GPIO_BRR_BR_0 (0x00000001U)
AnnaBridge 143:86740a56073b 3047 #define GPIO_BRR_BR_1 (0x00000002U)
AnnaBridge 143:86740a56073b 3048 #define GPIO_BRR_BR_2 (0x00000004U)
AnnaBridge 143:86740a56073b 3049 #define GPIO_BRR_BR_3 (0x00000008U)
AnnaBridge 143:86740a56073b 3050 #define GPIO_BRR_BR_4 (0x00000010U)
AnnaBridge 143:86740a56073b 3051 #define GPIO_BRR_BR_5 (0x00000020U)
AnnaBridge 143:86740a56073b 3052 #define GPIO_BRR_BR_6 (0x00000040U)
AnnaBridge 143:86740a56073b 3053 #define GPIO_BRR_BR_7 (0x00000080U)
AnnaBridge 143:86740a56073b 3054 #define GPIO_BRR_BR_8 (0x00000100U)
AnnaBridge 143:86740a56073b 3055 #define GPIO_BRR_BR_9 (0x00000200U)
AnnaBridge 143:86740a56073b 3056 #define GPIO_BRR_BR_10 (0x00000400U)
AnnaBridge 143:86740a56073b 3057 #define GPIO_BRR_BR_11 (0x00000800U)
AnnaBridge 143:86740a56073b 3058 #define GPIO_BRR_BR_12 (0x00001000U)
AnnaBridge 143:86740a56073b 3059 #define GPIO_BRR_BR_13 (0x00002000U)
AnnaBridge 143:86740a56073b 3060 #define GPIO_BRR_BR_14 (0x00004000U)
AnnaBridge 143:86740a56073b 3061 #define GPIO_BRR_BR_15 (0x00008000U)
AnnaBridge 143:86740a56073b 3062
AnnaBridge 143:86740a56073b 3063 /******************************************************************************/
AnnaBridge 143:86740a56073b 3064 /* */
AnnaBridge 143:86740a56073b 3065 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 143:86740a56073b 3066 /* */
AnnaBridge 143:86740a56073b 3067 /******************************************************************************/
AnnaBridge 143:86740a56073b 3068
AnnaBridge 143:86740a56073b 3069 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 143:86740a56073b 3070 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 143:86740a56073b 3071 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3072 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 143:86740a56073b 3073 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 143:86740a56073b 3074 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3075 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 143:86740a56073b 3076 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 143:86740a56073b 3077 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3078 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 143:86740a56073b 3079 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 143:86740a56073b 3080 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3081 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 143:86740a56073b 3082 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 143:86740a56073b 3083 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3084 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 143:86740a56073b 3085 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 143:86740a56073b 3086 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3087 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 143:86740a56073b 3088 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 143:86740a56073b 3089 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3090 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 143:86740a56073b 3091 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 143:86740a56073b 3092 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3093 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 143:86740a56073b 3094 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 143:86740a56073b 3095 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 3096 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 143:86740a56073b 3097 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 143:86740a56073b 3098 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3099 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 143:86740a56073b 3100 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 143:86740a56073b 3101 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 3102 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 143:86740a56073b 3103 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 143:86740a56073b 3104 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3105 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 143:86740a56073b 3106 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 143:86740a56073b 3107 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 3108 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 143:86740a56073b 3109 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 143:86740a56073b 3110 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 3111 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 143:86740a56073b 3112 #define I2C_CR1_WUPEN_Pos (18U)
AnnaBridge 143:86740a56073b 3113 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 3114 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
AnnaBridge 143:86740a56073b 3115 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 143:86740a56073b 3116 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 3117 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 143:86740a56073b 3118 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 143:86740a56073b 3119 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 3120 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 143:86740a56073b 3121 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 143:86740a56073b 3122 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 3123 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 143:86740a56073b 3124 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 143:86740a56073b 3125 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 3126 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 143:86740a56073b 3127 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 143:86740a56073b 3128 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 3129 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 143:86740a56073b 3130
AnnaBridge 143:86740a56073b 3131 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 143:86740a56073b 3132 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 143:86740a56073b 3133 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 143:86740a56073b 3134 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 143:86740a56073b 3135 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 143:86740a56073b 3136 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3137 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 143:86740a56073b 3138 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 143:86740a56073b 3139 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3140 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 143:86740a56073b 3141 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 143:86740a56073b 3142 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3143 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 143:86740a56073b 3144 #define I2C_CR2_START_Pos (13U)
AnnaBridge 143:86740a56073b 3145 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3146 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 143:86740a56073b 3147 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 143:86740a56073b 3148 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 3149 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 143:86740a56073b 3150 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 143:86740a56073b 3151 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3152 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 143:86740a56073b 3153 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 143:86740a56073b 3154 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 143:86740a56073b 3155 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 143:86740a56073b 3156 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 143:86740a56073b 3157 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 3158 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 143:86740a56073b 3159 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 143:86740a56073b 3160 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 3161 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 143:86740a56073b 3162 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 143:86740a56073b 3163 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 3164 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 143:86740a56073b 3165
AnnaBridge 143:86740a56073b 3166 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 143:86740a56073b 3167 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 143:86740a56073b 3168 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 143:86740a56073b 3169 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 143:86740a56073b 3170 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 143:86740a56073b 3171 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3172 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 143:86740a56073b 3173 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 143:86740a56073b 3174 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3175 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 143:86740a56073b 3176
AnnaBridge 143:86740a56073b 3177 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 143:86740a56073b 3178 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 143:86740a56073b 3179 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 143:86740a56073b 3180 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 143:86740a56073b 3181 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 143:86740a56073b 3182 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 143:86740a56073b 3183 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 143:86740a56073b 3184 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
AnnaBridge 143:86740a56073b 3185 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 143:86740a56073b 3186 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3187 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 143:86740a56073b 3188 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 143:86740a56073b 3189 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3190 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 143:86740a56073b 3191 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 143:86740a56073b 3192 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 3193 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 143:86740a56073b 3194 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 143:86740a56073b 3195 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3196 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 143:86740a56073b 3197 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 143:86740a56073b 3198 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 143:86740a56073b 3199 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 143:86740a56073b 3200 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 143:86740a56073b 3201 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 143:86740a56073b 3202 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 143:86740a56073b 3203 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 143:86740a56073b 3204 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 143:86740a56073b 3205 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 143:86740a56073b 3206 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 143:86740a56073b 3207 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3208 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 143:86740a56073b 3209
AnnaBridge 143:86740a56073b 3210 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 143:86740a56073b 3211 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 143:86740a56073b 3212 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 3213 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 143:86740a56073b 3214 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 143:86740a56073b 3215 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 143:86740a56073b 3216 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 143:86740a56073b 3217 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 143:86740a56073b 3218 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 3219 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 143:86740a56073b 3220 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 143:86740a56073b 3221 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 143:86740a56073b 3222 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 143:86740a56073b 3223 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 143:86740a56073b 3224 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 143:86740a56073b 3225 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 143:86740a56073b 3226
AnnaBridge 143:86740a56073b 3227 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 143:86740a56073b 3228 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 143:86740a56073b 3229 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 3230 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 143:86740a56073b 3231 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 143:86740a56073b 3232 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3233 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 143:86740a56073b 3234 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 143:86740a56073b 3235 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3236 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 143:86740a56073b 3237 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 143:86740a56073b 3238 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 143:86740a56073b 3239 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
AnnaBridge 143:86740a56073b 3240 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 143:86740a56073b 3241 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 3242 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 143:86740a56073b 3243
AnnaBridge 143:86740a56073b 3244 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 143:86740a56073b 3245 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 143:86740a56073b 3246 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3247 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 143:86740a56073b 3248 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 143:86740a56073b 3249 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3250 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 143:86740a56073b 3251 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 143:86740a56073b 3252 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3253 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 143:86740a56073b 3254 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 143:86740a56073b 3255 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3256 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
AnnaBridge 143:86740a56073b 3257 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 143:86740a56073b 3258 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3259 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 143:86740a56073b 3260 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 143:86740a56073b 3261 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3262 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 143:86740a56073b 3263 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 143:86740a56073b 3264 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3265 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 143:86740a56073b 3266 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 143:86740a56073b 3267 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3268 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 143:86740a56073b 3269 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 143:86740a56073b 3270 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3271 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 143:86740a56073b 3272 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 143:86740a56073b 3273 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3274 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 143:86740a56073b 3275 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 143:86740a56073b 3276 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3277 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 143:86740a56073b 3278 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 143:86740a56073b 3279 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3280 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 143:86740a56073b 3281 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 143:86740a56073b 3282 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3283 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 143:86740a56073b 3284 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 143:86740a56073b 3285 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3286 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 143:86740a56073b 3287 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 143:86740a56073b 3288 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3289 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 143:86740a56073b 3290 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 143:86740a56073b 3291 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 3292 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 143:86740a56073b 3293 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 143:86740a56073b 3294 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 143:86740a56073b 3295 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 143:86740a56073b 3296
AnnaBridge 143:86740a56073b 3297 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 143:86740a56073b 3298 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 143:86740a56073b 3299 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3300 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 143:86740a56073b 3301 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 143:86740a56073b 3302 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3303 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 143:86740a56073b 3304 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 143:86740a56073b 3305 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3306 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 143:86740a56073b 3307 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 143:86740a56073b 3308 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3309 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 143:86740a56073b 3310 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 143:86740a56073b 3311 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3312 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 143:86740a56073b 3313 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 143:86740a56073b 3314 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3315 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 143:86740a56073b 3316 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 143:86740a56073b 3317 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3318 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 143:86740a56073b 3319 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 143:86740a56073b 3320 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3321 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 143:86740a56073b 3322 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 143:86740a56073b 3323 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3324 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 143:86740a56073b 3325
AnnaBridge 143:86740a56073b 3326 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 143:86740a56073b 3327 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 143:86740a56073b 3328 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 3329 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 143:86740a56073b 3330
AnnaBridge 143:86740a56073b 3331 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 143:86740a56073b 3332 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 143:86740a56073b 3333 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 3334 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 143:86740a56073b 3335
AnnaBridge 143:86740a56073b 3336 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 143:86740a56073b 3337 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 143:86740a56073b 3338 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 3339 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 143:86740a56073b 3340
AnnaBridge 143:86740a56073b 3341 /******************************************************************************/
AnnaBridge 143:86740a56073b 3342 /* */
AnnaBridge 143:86740a56073b 3343 /* Independent WATCHDOG (IWDG) */
AnnaBridge 143:86740a56073b 3344 /* */
AnnaBridge 143:86740a56073b 3345 /******************************************************************************/
AnnaBridge 143:86740a56073b 3346 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 143:86740a56073b 3347 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 143:86740a56073b 3348 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 3349 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
AnnaBridge 143:86740a56073b 3350
AnnaBridge 143:86740a56073b 3351 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 143:86740a56073b 3352 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 143:86740a56073b 3353 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 3354 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
AnnaBridge 143:86740a56073b 3355 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3356 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3357 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3358
AnnaBridge 143:86740a56073b 3359 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 143:86740a56073b 3360 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 143:86740a56073b 3361 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 3362 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
AnnaBridge 143:86740a56073b 3363
AnnaBridge 143:86740a56073b 3364 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 143:86740a56073b 3365 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 143:86740a56073b 3366 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3367 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 143:86740a56073b 3368 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 143:86740a56073b 3369 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3370 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 143:86740a56073b 3371 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 143:86740a56073b 3372 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3373 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 143:86740a56073b 3374
AnnaBridge 143:86740a56073b 3375 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 143:86740a56073b 3376 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 143:86740a56073b 3377 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 143:86740a56073b 3378 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 143:86740a56073b 3379
AnnaBridge 143:86740a56073b 3380 /******************************************************************************/
AnnaBridge 143:86740a56073b 3381 /* */
AnnaBridge 143:86740a56073b 3382 /* Low Power Timer (LPTTIM) */
AnnaBridge 143:86740a56073b 3383 /* */
AnnaBridge 143:86740a56073b 3384 /******************************************************************************/
AnnaBridge 143:86740a56073b 3385 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 143:86740a56073b 3386 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 143:86740a56073b 3387 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3388 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 143:86740a56073b 3389 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 143:86740a56073b 3390 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3391 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 143:86740a56073b 3392 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 143:86740a56073b 3393 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3394 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 143:86740a56073b 3395 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 143:86740a56073b 3396 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3397 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 143:86740a56073b 3398 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 143:86740a56073b 3399 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3400 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 143:86740a56073b 3401 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 143:86740a56073b 3402 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3403 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 143:86740a56073b 3404 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 143:86740a56073b 3405 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3406 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 143:86740a56073b 3407
AnnaBridge 143:86740a56073b 3408 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 143:86740a56073b 3409 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 143:86740a56073b 3410 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3411 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 143:86740a56073b 3412 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 143:86740a56073b 3413 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3414 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 143:86740a56073b 3415 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 143:86740a56073b 3416 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3417 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 143:86740a56073b 3418 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 143:86740a56073b 3419 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3420 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 143:86740a56073b 3421 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 143:86740a56073b 3422 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3423 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 143:86740a56073b 3424 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 143:86740a56073b 3425 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3426 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 143:86740a56073b 3427 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 143:86740a56073b 3428 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3429 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 143:86740a56073b 3430
AnnaBridge 143:86740a56073b 3431 /****************** Bit definition for LPTIM_IER register ********************/
AnnaBridge 143:86740a56073b 3432 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 143:86740a56073b 3433 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3434 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 143:86740a56073b 3435 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 143:86740a56073b 3436 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3437 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 143:86740a56073b 3438 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 143:86740a56073b 3439 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3440 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 143:86740a56073b 3441 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 143:86740a56073b 3442 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3443 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 143:86740a56073b 3444 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 143:86740a56073b 3445 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3446 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 143:86740a56073b 3447 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 143:86740a56073b 3448 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3449 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 143:86740a56073b 3450 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 143:86740a56073b 3451 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3452 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 143:86740a56073b 3453
AnnaBridge 143:86740a56073b 3454 /****************** Bit definition for LPTIM_CFGR register *******************/
AnnaBridge 143:86740a56073b 3455 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 143:86740a56073b 3456 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3457 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 143:86740a56073b 3458
AnnaBridge 143:86740a56073b 3459 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 143:86740a56073b 3460 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 143:86740a56073b 3461 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 143:86740a56073b 3462 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3463 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3464
AnnaBridge 143:86740a56073b 3465 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 143:86740a56073b 3466 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 143:86740a56073b 3467 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 143:86740a56073b 3468 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3469 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3470
AnnaBridge 143:86740a56073b 3471 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 143:86740a56073b 3472 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 143:86740a56073b 3473 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 143:86740a56073b 3474 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3475 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3476
AnnaBridge 143:86740a56073b 3477 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 143:86740a56073b 3478 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 143:86740a56073b 3479 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 143:86740a56073b 3480 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3481 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3482 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3483
AnnaBridge 143:86740a56073b 3484 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 143:86740a56073b 3485 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 143:86740a56073b 3486 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 143:86740a56073b 3487 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3488 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 3489 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3490
AnnaBridge 143:86740a56073b 3491 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 143:86740a56073b 3492 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 143:86740a56073b 3493 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 143:86740a56073b 3494 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 3495 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 3496
AnnaBridge 143:86740a56073b 3497 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 143:86740a56073b 3498 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 3499 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 143:86740a56073b 3500 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 143:86740a56073b 3501 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 3502 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 143:86740a56073b 3503 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 143:86740a56073b 3504 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 3505 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 143:86740a56073b 3506 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 143:86740a56073b 3507 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 3508 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 143:86740a56073b 3509 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 143:86740a56073b 3510 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 3511 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 143:86740a56073b 3512 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 143:86740a56073b 3513 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 3514 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 143:86740a56073b 3515
AnnaBridge 143:86740a56073b 3516 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 143:86740a56073b 3517 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 143:86740a56073b 3518 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3519 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 143:86740a56073b 3520 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 143:86740a56073b 3521 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3522 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 143:86740a56073b 3523 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 143:86740a56073b 3524 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3525 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 143:86740a56073b 3526
AnnaBridge 143:86740a56073b 3527 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 143:86740a56073b 3528 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 143:86740a56073b 3529 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 3530 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 143:86740a56073b 3531
AnnaBridge 143:86740a56073b 3532 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 143:86740a56073b 3533 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 143:86740a56073b 3534 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 3535 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 143:86740a56073b 3536
AnnaBridge 143:86740a56073b 3537 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 143:86740a56073b 3538 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 143:86740a56073b 3539 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 3540 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 143:86740a56073b 3541
AnnaBridge 143:86740a56073b 3542 /******************************************************************************/
AnnaBridge 143:86740a56073b 3543 /* */
AnnaBridge 143:86740a56073b 3544 /* MIFARE Firewall */
AnnaBridge 143:86740a56073b 3545 /* */
AnnaBridge 143:86740a56073b 3546 /******************************************************************************/
AnnaBridge 143:86740a56073b 3547
AnnaBridge 143:86740a56073b 3548 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
AnnaBridge 143:86740a56073b 3549 #define FW_CSSA_ADD_Pos (8U)
AnnaBridge 143:86740a56073b 3550 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
AnnaBridge 143:86740a56073b 3551 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
AnnaBridge 143:86740a56073b 3552 #define FW_CSL_LENG_Pos (8U)
AnnaBridge 143:86740a56073b 3553 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
AnnaBridge 143:86740a56073b 3554 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
AnnaBridge 143:86740a56073b 3555 #define FW_NVDSSA_ADD_Pos (8U)
AnnaBridge 143:86740a56073b 3556 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
AnnaBridge 143:86740a56073b 3557 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
AnnaBridge 143:86740a56073b 3558 #define FW_NVDSL_LENG_Pos (8U)
AnnaBridge 143:86740a56073b 3559 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
AnnaBridge 143:86740a56073b 3560 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
AnnaBridge 143:86740a56073b 3561 #define FW_VDSSA_ADD_Pos (6U)
AnnaBridge 143:86740a56073b 3562 #define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
AnnaBridge 143:86740a56073b 3563 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
AnnaBridge 143:86740a56073b 3564 #define FW_VDSL_LENG_Pos (6U)
AnnaBridge 143:86740a56073b 3565 #define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
AnnaBridge 143:86740a56073b 3566 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
AnnaBridge 143:86740a56073b 3567
AnnaBridge 143:86740a56073b 3568 /**************************Bit definition for CR register *********************/
AnnaBridge 143:86740a56073b 3569 #define FW_CR_FPA_Pos (0U)
AnnaBridge 143:86740a56073b 3570 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3571 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
AnnaBridge 143:86740a56073b 3572 #define FW_CR_VDS_Pos (1U)
AnnaBridge 143:86740a56073b 3573 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3574 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
AnnaBridge 143:86740a56073b 3575 #define FW_CR_VDE_Pos (2U)
AnnaBridge 143:86740a56073b 3576 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3577 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
AnnaBridge 143:86740a56073b 3578
AnnaBridge 143:86740a56073b 3579 /******************************************************************************/
AnnaBridge 143:86740a56073b 3580 /* */
AnnaBridge 143:86740a56073b 3581 /* Power Control (PWR) */
AnnaBridge 143:86740a56073b 3582 /* */
AnnaBridge 143:86740a56073b 3583 /******************************************************************************/
AnnaBridge 143:86740a56073b 3584
AnnaBridge 143:86740a56073b 3585 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
AnnaBridge 143:86740a56073b 3586
AnnaBridge 143:86740a56073b 3587 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 143:86740a56073b 3588 #define PWR_CR_LPSDSR_Pos (0U)
AnnaBridge 143:86740a56073b 3589 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3590 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
AnnaBridge 143:86740a56073b 3591 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 143:86740a56073b 3592 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3593 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 143:86740a56073b 3594 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 143:86740a56073b 3595 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3596 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 143:86740a56073b 3597 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 143:86740a56073b 3598 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3599 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 143:86740a56073b 3600 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 143:86740a56073b 3601 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3602 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 143:86740a56073b 3603
AnnaBridge 143:86740a56073b 3604 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 143:86740a56073b 3605 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 143:86740a56073b 3606 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 143:86740a56073b 3607 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3608 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3609 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3610
AnnaBridge 143:86740a56073b 3611 /*!< PVD level configuration */
AnnaBridge 143:86740a56073b 3612 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
AnnaBridge 143:86740a56073b 3613 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
AnnaBridge 143:86740a56073b 3614 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
AnnaBridge 143:86740a56073b 3615 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
AnnaBridge 143:86740a56073b 3616 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
AnnaBridge 143:86740a56073b 3617 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
AnnaBridge 143:86740a56073b 3618 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
AnnaBridge 143:86740a56073b 3619 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
AnnaBridge 143:86740a56073b 3620
AnnaBridge 143:86740a56073b 3621 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 143:86740a56073b 3622 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3623 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 143:86740a56073b 3624 #define PWR_CR_ULP_Pos (9U)
AnnaBridge 143:86740a56073b 3625 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3626 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
AnnaBridge 143:86740a56073b 3627 #define PWR_CR_FWU_Pos (10U)
AnnaBridge 143:86740a56073b 3628 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3629 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
AnnaBridge 143:86740a56073b 3630
AnnaBridge 143:86740a56073b 3631 #define PWR_CR_VOS_Pos (11U)
AnnaBridge 143:86740a56073b 3632 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
AnnaBridge 143:86740a56073b 3633 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
AnnaBridge 143:86740a56073b 3634 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3635 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3636 #define PWR_CR_DSEEKOFF_Pos (13U)
AnnaBridge 143:86740a56073b 3637 #define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3638 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
AnnaBridge 143:86740a56073b 3639 #define PWR_CR_LPRUN_Pos (14U)
AnnaBridge 143:86740a56073b 3640 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 3641 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
AnnaBridge 143:86740a56073b 3642
AnnaBridge 143:86740a56073b 3643 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 143:86740a56073b 3644 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 143:86740a56073b 3645 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3646 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 143:86740a56073b 3647 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 143:86740a56073b 3648 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3649 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 143:86740a56073b 3650 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 143:86740a56073b 3651 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3652 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 143:86740a56073b 3653 #define PWR_CSR_VREFINTRDYF_Pos (3U)
AnnaBridge 143:86740a56073b 3654 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3655 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
AnnaBridge 143:86740a56073b 3656 #define PWR_CSR_VOSF_Pos (4U)
AnnaBridge 143:86740a56073b 3657 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3658 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
AnnaBridge 143:86740a56073b 3659 #define PWR_CSR_REGLPF_Pos (5U)
AnnaBridge 143:86740a56073b 3660 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3661 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
AnnaBridge 143:86740a56073b 3662
AnnaBridge 143:86740a56073b 3663 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 143:86740a56073b 3664 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3665 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 143:86740a56073b 3666 #define PWR_CSR_EWUP2_Pos (9U)
AnnaBridge 143:86740a56073b 3667 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3668 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 143:86740a56073b 3669 #define PWR_CSR_EWUP3_Pos (10U)
AnnaBridge 143:86740a56073b 3670 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3671 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
AnnaBridge 143:86740a56073b 3672
AnnaBridge 143:86740a56073b 3673 /******************************************************************************/
AnnaBridge 143:86740a56073b 3674 /* */
AnnaBridge 143:86740a56073b 3675 /* Reset and Clock Control */
AnnaBridge 143:86740a56073b 3676 /* */
AnnaBridge 143:86740a56073b 3677 /******************************************************************************/
AnnaBridge 143:86740a56073b 3678
AnnaBridge 143:86740a56073b 3679 #define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
AnnaBridge 143:86740a56073b 3680 #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
AnnaBridge 143:86740a56073b 3681
AnnaBridge 143:86740a56073b 3682 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 143:86740a56073b 3683 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 143:86740a56073b 3684 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3685 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
AnnaBridge 143:86740a56073b 3686 #define RCC_CR_HSIKERON_Pos (1U)
AnnaBridge 143:86740a56073b 3687 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3688 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
AnnaBridge 143:86740a56073b 3689 #define RCC_CR_HSIRDY_Pos (2U)
AnnaBridge 143:86740a56073b 3690 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3691 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
AnnaBridge 143:86740a56073b 3692 #define RCC_CR_HSIDIVEN_Pos (3U)
AnnaBridge 143:86740a56073b 3693 #define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3694 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
AnnaBridge 143:86740a56073b 3695 #define RCC_CR_HSIDIVF_Pos (4U)
AnnaBridge 143:86740a56073b 3696 #define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3697 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
AnnaBridge 143:86740a56073b 3698 #define RCC_CR_HSIOUTEN_Pos (5U)
AnnaBridge 143:86740a56073b 3699 #define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3700 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
AnnaBridge 143:86740a56073b 3701 #define RCC_CR_MSION_Pos (8U)
AnnaBridge 143:86740a56073b 3702 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3703 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
AnnaBridge 143:86740a56073b 3704 #define RCC_CR_MSIRDY_Pos (9U)
AnnaBridge 143:86740a56073b 3705 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3706 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
AnnaBridge 143:86740a56073b 3707 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 143:86740a56073b 3708 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 3709 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
AnnaBridge 143:86740a56073b 3710 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 143:86740a56073b 3711 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 3712 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
AnnaBridge 143:86740a56073b 3713 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 143:86740a56073b 3714 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 3715 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
AnnaBridge 143:86740a56073b 3716 #define RCC_CR_CSSHSEON_Pos (19U)
AnnaBridge 143:86740a56073b 3717 #define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 3718 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
AnnaBridge 143:86740a56073b 3719 #define RCC_CR_RTCPRE_Pos (20U)
AnnaBridge 143:86740a56073b 3720 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 3721 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
AnnaBridge 143:86740a56073b 3722 #define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 3723 #define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 3724 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 143:86740a56073b 3725 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 3726 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
AnnaBridge 143:86740a56073b 3727 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 143:86740a56073b 3728 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 3729 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
AnnaBridge 143:86740a56073b 3730
AnnaBridge 143:86740a56073b 3731 /* Reference defines */
AnnaBridge 143:86740a56073b 3732 #define RCC_CR_CSSON RCC_CR_CSSHSEON
AnnaBridge 143:86740a56073b 3733
AnnaBridge 143:86740a56073b 3734 /******************** Bit definition for RCC_ICSCR register *****************/
AnnaBridge 143:86740a56073b 3735 #define RCC_ICSCR_HSICAL_Pos (0U)
AnnaBridge 143:86740a56073b 3736 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 3737 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
AnnaBridge 143:86740a56073b 3738 #define RCC_ICSCR_HSITRIM_Pos (8U)
AnnaBridge 143:86740a56073b 3739 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
AnnaBridge 143:86740a56073b 3740 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
AnnaBridge 143:86740a56073b 3741
AnnaBridge 143:86740a56073b 3742 #define RCC_ICSCR_MSIRANGE_Pos (13U)
AnnaBridge 143:86740a56073b 3743 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
AnnaBridge 143:86740a56073b 3744 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
AnnaBridge 143:86740a56073b 3745 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
AnnaBridge 143:86740a56073b 3746 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3747 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 3748 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
AnnaBridge 143:86740a56073b 3749 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3750 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
AnnaBridge 143:86740a56073b 3751 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
AnnaBridge 143:86740a56073b 3752 #define RCC_ICSCR_MSICAL_Pos (16U)
AnnaBridge 143:86740a56073b 3753 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
AnnaBridge 143:86740a56073b 3754 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
AnnaBridge 143:86740a56073b 3755 #define RCC_ICSCR_MSITRIM_Pos (24U)
AnnaBridge 143:86740a56073b 3756 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
AnnaBridge 143:86740a56073b 3757 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
AnnaBridge 143:86740a56073b 3758
AnnaBridge 143:86740a56073b 3759 /******************** Bit definition for RCC_CRRCR register *****************/
AnnaBridge 143:86740a56073b 3760 #define RCC_CRRCR_HSI48ON_Pos (0U)
AnnaBridge 143:86740a56073b 3761 #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3762 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
AnnaBridge 143:86740a56073b 3763 #define RCC_CRRCR_HSI48RDY_Pos (1U)
AnnaBridge 143:86740a56073b 3764 #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3765 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
AnnaBridge 143:86740a56073b 3766 #define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U)
AnnaBridge 143:86740a56073b 3767 #define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1U << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3768 #define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */
AnnaBridge 143:86740a56073b 3769 #define RCC_CRRCR_HSI48CAL_Pos (8U)
AnnaBridge 143:86740a56073b 3770 #define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 143:86740a56073b 3771 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
AnnaBridge 143:86740a56073b 3772
AnnaBridge 143:86740a56073b 3773 /******************* Bit definition for RCC_CFGR register *******************/
AnnaBridge 143:86740a56073b 3774 /*!< SW configuration */
AnnaBridge 143:86740a56073b 3775 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 143:86740a56073b 3776 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 3777 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 143:86740a56073b 3778 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3779 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3780
AnnaBridge 143:86740a56073b 3781 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
AnnaBridge 143:86740a56073b 3782 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
AnnaBridge 143:86740a56073b 3783 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
AnnaBridge 143:86740a56073b 3784 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
AnnaBridge 143:86740a56073b 3785
AnnaBridge 143:86740a56073b 3786 /*!< SWS configuration */
AnnaBridge 143:86740a56073b 3787 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 143:86740a56073b 3788 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 3789 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 143:86740a56073b 3790 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3791 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3792
AnnaBridge 143:86740a56073b 3793 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
AnnaBridge 143:86740a56073b 3794 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
AnnaBridge 143:86740a56073b 3795 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
AnnaBridge 143:86740a56073b 3796 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
AnnaBridge 143:86740a56073b 3797
AnnaBridge 143:86740a56073b 3798 /*!< HPRE configuration */
AnnaBridge 143:86740a56073b 3799 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 143:86740a56073b 3800 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 3801 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 143:86740a56073b 3802 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3803 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3804 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3805 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3806
AnnaBridge 143:86740a56073b 3807 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
AnnaBridge 143:86740a56073b 3808 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
AnnaBridge 143:86740a56073b 3809 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
AnnaBridge 143:86740a56073b 3810 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
AnnaBridge 143:86740a56073b 3811 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
AnnaBridge 143:86740a56073b 3812 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
AnnaBridge 143:86740a56073b 3813 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
AnnaBridge 143:86740a56073b 3814 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
AnnaBridge 143:86740a56073b 3815 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
AnnaBridge 143:86740a56073b 3816
AnnaBridge 143:86740a56073b 3817 /*!< PPRE1 configuration */
AnnaBridge 143:86740a56073b 3818 #define RCC_CFGR_PPRE1_Pos (8U)
AnnaBridge 143:86740a56073b 3819 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
AnnaBridge 143:86740a56073b 3820 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 143:86740a56073b 3821 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 3822 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 3823 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 3824
AnnaBridge 143:86740a56073b 3825 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 143:86740a56073b 3826 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
AnnaBridge 143:86740a56073b 3827 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
AnnaBridge 143:86740a56073b 3828 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
AnnaBridge 143:86740a56073b 3829 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
AnnaBridge 143:86740a56073b 3830
AnnaBridge 143:86740a56073b 3831 /*!< PPRE2 configuration */
AnnaBridge 143:86740a56073b 3832 #define RCC_CFGR_PPRE2_Pos (11U)
AnnaBridge 143:86740a56073b 3833 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
AnnaBridge 143:86740a56073b 3834 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 143:86740a56073b 3835 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 3836 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 3837 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 3838
AnnaBridge 143:86740a56073b 3839 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 143:86740a56073b 3840 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
AnnaBridge 143:86740a56073b 3841 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
AnnaBridge 143:86740a56073b 3842 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
AnnaBridge 143:86740a56073b 3843 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
AnnaBridge 143:86740a56073b 3844
AnnaBridge 143:86740a56073b 3845 #define RCC_CFGR_STOPWUCK_Pos (15U)
AnnaBridge 143:86740a56073b 3846 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 3847 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
AnnaBridge 143:86740a56073b 3848
AnnaBridge 143:86740a56073b 3849 /*!< PLL entry clock source*/
AnnaBridge 143:86740a56073b 3850 #define RCC_CFGR_PLLSRC_Pos (16U)
AnnaBridge 143:86740a56073b 3851 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 3852 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
AnnaBridge 143:86740a56073b 3853
AnnaBridge 143:86740a56073b 3854 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
AnnaBridge 143:86740a56073b 3855 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
AnnaBridge 143:86740a56073b 3856
AnnaBridge 143:86740a56073b 3857
AnnaBridge 143:86740a56073b 3858 /*!< PLLMUL configuration */
AnnaBridge 143:86740a56073b 3859 #define RCC_CFGR_PLLMUL_Pos (18U)
AnnaBridge 143:86740a56073b 3860 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
AnnaBridge 143:86740a56073b 3861 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
AnnaBridge 143:86740a56073b 3862 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 3863 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 3864 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 3865 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 3866
AnnaBridge 143:86740a56073b 3867 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
AnnaBridge 143:86740a56073b 3868 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
AnnaBridge 143:86740a56073b 3869 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
AnnaBridge 143:86740a56073b 3870 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
AnnaBridge 143:86740a56073b 3871 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
AnnaBridge 143:86740a56073b 3872 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
AnnaBridge 143:86740a56073b 3873 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
AnnaBridge 143:86740a56073b 3874 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
AnnaBridge 143:86740a56073b 3875 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
AnnaBridge 143:86740a56073b 3876
AnnaBridge 143:86740a56073b 3877 /*!< PLLDIV configuration */
AnnaBridge 143:86740a56073b 3878 #define RCC_CFGR_PLLDIV_Pos (22U)
AnnaBridge 143:86740a56073b 3879 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 3880 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
AnnaBridge 143:86740a56073b 3881 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 3882 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 3883
AnnaBridge 143:86740a56073b 3884 #define RCC_CFGR_PLLDIV2_Pos (22U)
AnnaBridge 143:86740a56073b 3885 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 3886 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
AnnaBridge 143:86740a56073b 3887 #define RCC_CFGR_PLLDIV3_Pos (23U)
AnnaBridge 143:86740a56073b 3888 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 3889 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
AnnaBridge 143:86740a56073b 3890 #define RCC_CFGR_PLLDIV4_Pos (22U)
AnnaBridge 143:86740a56073b 3891 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
AnnaBridge 143:86740a56073b 3892 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
AnnaBridge 143:86740a56073b 3893
AnnaBridge 143:86740a56073b 3894 /*!< MCO configuration */
AnnaBridge 143:86740a56073b 3895 #define RCC_CFGR_MCOSEL_Pos (24U)
AnnaBridge 143:86740a56073b 3896 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 3897 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
AnnaBridge 143:86740a56073b 3898 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 3899 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 3900 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 3901 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 3902
AnnaBridge 143:86740a56073b 3903 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 143:86740a56073b 3904 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
AnnaBridge 143:86740a56073b 3905 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 3906 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
AnnaBridge 143:86740a56073b 3907 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
AnnaBridge 143:86740a56073b 3908 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 3909 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
AnnaBridge 143:86740a56073b 3910 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
AnnaBridge 143:86740a56073b 3911 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
AnnaBridge 143:86740a56073b 3912 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
AnnaBridge 143:86740a56073b 3913 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
AnnaBridge 143:86740a56073b 3914 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 3915 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
AnnaBridge 143:86740a56073b 3916 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
AnnaBridge 143:86740a56073b 3917 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
AnnaBridge 143:86740a56073b 3918 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
AnnaBridge 143:86740a56073b 3919 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
AnnaBridge 143:86740a56073b 3920 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
AnnaBridge 143:86740a56073b 3921 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
AnnaBridge 143:86740a56073b 3922 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
AnnaBridge 143:86740a56073b 3923 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
AnnaBridge 143:86740a56073b 3924 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
AnnaBridge 143:86740a56073b 3925 #define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
AnnaBridge 143:86740a56073b 3926 #define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 3927 #define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
AnnaBridge 143:86740a56073b 3928
AnnaBridge 143:86740a56073b 3929 #define RCC_CFGR_MCOPRE_Pos (28U)
AnnaBridge 143:86740a56073b 3930 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
AnnaBridge 143:86740a56073b 3931 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
AnnaBridge 143:86740a56073b 3932 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 3933 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 3934 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 3935
AnnaBridge 143:86740a56073b 3936 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3937 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
AnnaBridge 143:86740a56073b 3938 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
AnnaBridge 143:86740a56073b 3939 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
AnnaBridge 143:86740a56073b 3940 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
AnnaBridge 143:86740a56073b 3941
AnnaBridge 143:86740a56073b 3942 /* Legacy defines */
AnnaBridge 143:86740a56073b 3943 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
AnnaBridge 143:86740a56073b 3944 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
AnnaBridge 143:86740a56073b 3945 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
AnnaBridge 143:86740a56073b 3946 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
AnnaBridge 143:86740a56073b 3947 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
AnnaBridge 143:86740a56073b 3948 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
AnnaBridge 143:86740a56073b 3949 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
AnnaBridge 143:86740a56073b 3950 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
AnnaBridge 143:86740a56073b 3951 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
AnnaBridge 143:86740a56073b 3952
AnnaBridge 143:86740a56073b 3953 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
AnnaBridge 143:86740a56073b 3954 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3955 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3956 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3957 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3958 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
AnnaBridge 143:86740a56073b 3959
AnnaBridge 143:86740a56073b 3960 /*!<****************** Bit definition for RCC_CIER register ********************/
AnnaBridge 143:86740a56073b 3961 #define RCC_CIER_LSIRDYIE_Pos (0U)
AnnaBridge 143:86740a56073b 3962 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3963 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3964 #define RCC_CIER_LSERDYIE_Pos (1U)
AnnaBridge 143:86740a56073b 3965 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3966 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3967 #define RCC_CIER_HSIRDYIE_Pos (2U)
AnnaBridge 143:86740a56073b 3968 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3969 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3970 #define RCC_CIER_HSERDYIE_Pos (3U)
AnnaBridge 143:86740a56073b 3971 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 3972 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3973 #define RCC_CIER_PLLRDYIE_Pos (4U)
AnnaBridge 143:86740a56073b 3974 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 3975 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3976 #define RCC_CIER_MSIRDYIE_Pos (5U)
AnnaBridge 143:86740a56073b 3977 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 3978 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3979 #define RCC_CIER_HSI48RDYIE_Pos (6U)
AnnaBridge 143:86740a56073b 3980 #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 3981 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
AnnaBridge 143:86740a56073b 3982 #define RCC_CIER_CSSLSE_Pos (7U)
AnnaBridge 143:86740a56073b 3983 #define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 3984 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
AnnaBridge 143:86740a56073b 3985
AnnaBridge 143:86740a56073b 3986 /* Reference defines */
AnnaBridge 143:86740a56073b 3987 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
AnnaBridge 143:86740a56073b 3988
AnnaBridge 143:86740a56073b 3989 /*!<****************** Bit definition for RCC_CIFR register ********************/
AnnaBridge 143:86740a56073b 3990 #define RCC_CIFR_LSIRDYF_Pos (0U)
AnnaBridge 143:86740a56073b 3991 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 3992 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
AnnaBridge 143:86740a56073b 3993 #define RCC_CIFR_LSERDYF_Pos (1U)
AnnaBridge 143:86740a56073b 3994 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 3995 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
AnnaBridge 143:86740a56073b 3996 #define RCC_CIFR_HSIRDYF_Pos (2U)
AnnaBridge 143:86740a56073b 3997 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 3998 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
AnnaBridge 143:86740a56073b 3999 #define RCC_CIFR_HSERDYF_Pos (3U)
AnnaBridge 143:86740a56073b 4000 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4001 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
AnnaBridge 143:86740a56073b 4002 #define RCC_CIFR_PLLRDYF_Pos (4U)
AnnaBridge 143:86740a56073b 4003 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4004 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
AnnaBridge 143:86740a56073b 4005 #define RCC_CIFR_MSIRDYF_Pos (5U)
AnnaBridge 143:86740a56073b 4006 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4007 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
AnnaBridge 143:86740a56073b 4008 #define RCC_CIFR_HSI48RDYF_Pos (6U)
AnnaBridge 143:86740a56073b 4009 #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4010 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
AnnaBridge 143:86740a56073b 4011 #define RCC_CIFR_CSSLSEF_Pos (7U)
AnnaBridge 143:86740a56073b 4012 #define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4013 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
AnnaBridge 143:86740a56073b 4014 #define RCC_CIFR_CSSHSEF_Pos (8U)
AnnaBridge 143:86740a56073b 4015 #define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4016 #define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
AnnaBridge 143:86740a56073b 4017
AnnaBridge 143:86740a56073b 4018 /* Reference defines */
AnnaBridge 143:86740a56073b 4019 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
AnnaBridge 143:86740a56073b 4020 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
AnnaBridge 143:86740a56073b 4021
AnnaBridge 143:86740a56073b 4022 /*!<****************** Bit definition for RCC_CICR register ********************/
AnnaBridge 143:86740a56073b 4023 #define RCC_CICR_LSIRDYC_Pos (0U)
AnnaBridge 143:86740a56073b 4024 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4025 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4026 #define RCC_CICR_LSERDYC_Pos (1U)
AnnaBridge 143:86740a56073b 4027 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4028 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4029 #define RCC_CICR_HSIRDYC_Pos (2U)
AnnaBridge 143:86740a56073b 4030 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4031 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4032 #define RCC_CICR_HSERDYC_Pos (3U)
AnnaBridge 143:86740a56073b 4033 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4034 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4035 #define RCC_CICR_PLLRDYC_Pos (4U)
AnnaBridge 143:86740a56073b 4036 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4037 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4038 #define RCC_CICR_MSIRDYC_Pos (5U)
AnnaBridge 143:86740a56073b 4039 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4040 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4041 #define RCC_CICR_HSI48RDYC_Pos (6U)
AnnaBridge 143:86740a56073b 4042 #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4043 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
AnnaBridge 143:86740a56073b 4044 #define RCC_CICR_CSSLSEC_Pos (7U)
AnnaBridge 143:86740a56073b 4045 #define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4046 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
AnnaBridge 143:86740a56073b 4047 #define RCC_CICR_CSSHSEC_Pos (8U)
AnnaBridge 143:86740a56073b 4048 #define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4049 #define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
AnnaBridge 143:86740a56073b 4050
AnnaBridge 143:86740a56073b 4051 /* Reference defines */
AnnaBridge 143:86740a56073b 4052 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
AnnaBridge 143:86740a56073b 4053 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC
AnnaBridge 143:86740a56073b 4054 /***************** Bit definition for RCC_IOPRSTR register ******************/
AnnaBridge 143:86740a56073b 4055 #define RCC_IOPRSTR_IOPARST_Pos (0U)
AnnaBridge 143:86740a56073b 4056 #define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4057 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
AnnaBridge 143:86740a56073b 4058 #define RCC_IOPRSTR_IOPBRST_Pos (1U)
AnnaBridge 143:86740a56073b 4059 #define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4060 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
AnnaBridge 143:86740a56073b 4061 #define RCC_IOPRSTR_IOPCRST_Pos (2U)
AnnaBridge 143:86740a56073b 4062 #define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4063 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
AnnaBridge 143:86740a56073b 4064 #define RCC_IOPRSTR_IOPDRST_Pos (3U)
AnnaBridge 143:86740a56073b 4065 #define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4066 #define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
AnnaBridge 143:86740a56073b 4067 #define RCC_IOPRSTR_IOPERST_Pos (4U)
AnnaBridge 143:86740a56073b 4068 #define RCC_IOPRSTR_IOPERST_Msk (0x1U << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4069 #define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
AnnaBridge 143:86740a56073b 4070 #define RCC_IOPRSTR_IOPHRST_Pos (7U)
AnnaBridge 143:86740a56073b 4071 #define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4072 #define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
AnnaBridge 143:86740a56073b 4073
AnnaBridge 143:86740a56073b 4074 /* Reference defines */
AnnaBridge 143:86740a56073b 4075 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
AnnaBridge 143:86740a56073b 4076 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
AnnaBridge 143:86740a56073b 4077 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
AnnaBridge 143:86740a56073b 4078 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
AnnaBridge 143:86740a56073b 4079 #define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
AnnaBridge 143:86740a56073b 4080 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
AnnaBridge 143:86740a56073b 4081
AnnaBridge 143:86740a56073b 4082
AnnaBridge 143:86740a56073b 4083 /****************** Bit definition for RCC_AHBRST register ******************/
AnnaBridge 143:86740a56073b 4084 #define RCC_AHBRSTR_DMARST_Pos (0U)
AnnaBridge 143:86740a56073b 4085 #define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4086 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
AnnaBridge 143:86740a56073b 4087 #define RCC_AHBRSTR_MIFRST_Pos (8U)
AnnaBridge 143:86740a56073b 4088 #define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4089 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */
AnnaBridge 143:86740a56073b 4090 #define RCC_AHBRSTR_CRCRST_Pos (12U)
AnnaBridge 143:86740a56073b 4091 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4092 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
AnnaBridge 143:86740a56073b 4093 #define RCC_AHBRSTR_TSCRST_Pos (16U)
AnnaBridge 143:86740a56073b 4094 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4095 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
AnnaBridge 143:86740a56073b 4096 #define RCC_AHBRSTR_RNGRST_Pos (20U)
AnnaBridge 143:86740a56073b 4097 #define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4098 #define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
AnnaBridge 143:86740a56073b 4099
AnnaBridge 143:86740a56073b 4100 /* Reference defines */
AnnaBridge 143:86740a56073b 4101 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
AnnaBridge 143:86740a56073b 4102
AnnaBridge 143:86740a56073b 4103 /***************** Bit definition for RCC_APB2RSTR register *****************/
AnnaBridge 143:86740a56073b 4104 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
AnnaBridge 143:86740a56073b 4105 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4106 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
AnnaBridge 143:86740a56073b 4107 #define RCC_APB2RSTR_TIM21RST_Pos (2U)
AnnaBridge 143:86740a56073b 4108 #define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4109 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */
AnnaBridge 143:86740a56073b 4110 #define RCC_APB2RSTR_TIM22RST_Pos (5U)
AnnaBridge 143:86740a56073b 4111 #define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4112 #define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */
AnnaBridge 143:86740a56073b 4113 #define RCC_APB2RSTR_ADCRST_Pos (9U)
AnnaBridge 143:86740a56073b 4114 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4115 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */
AnnaBridge 143:86740a56073b 4116 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 143:86740a56073b 4117 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4118 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
AnnaBridge 143:86740a56073b 4119 #define RCC_APB2RSTR_USART1RST_Pos (14U)
AnnaBridge 143:86740a56073b 4120 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4121 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
AnnaBridge 143:86740a56073b 4122 #define RCC_APB2RSTR_DBGRST_Pos (22U)
AnnaBridge 143:86740a56073b 4123 #define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4124 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */
AnnaBridge 143:86740a56073b 4125
AnnaBridge 143:86740a56073b 4126 /* Reference defines */
AnnaBridge 143:86740a56073b 4127 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
AnnaBridge 143:86740a56073b 4128 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
AnnaBridge 143:86740a56073b 4129
AnnaBridge 143:86740a56073b 4130 /***************** Bit definition for RCC_APB1RSTR register *****************/
AnnaBridge 143:86740a56073b 4131 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 143:86740a56073b 4132 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4133 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
AnnaBridge 143:86740a56073b 4134 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 143:86740a56073b 4135 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4136 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
AnnaBridge 143:86740a56073b 4137 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 143:86740a56073b 4138 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4139 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
AnnaBridge 143:86740a56073b 4140 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 143:86740a56073b 4141 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4142 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */
AnnaBridge 143:86740a56073b 4143 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 143:86740a56073b 4144 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4145 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
AnnaBridge 143:86740a56073b 4146 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 143:86740a56073b 4147 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4148 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
AnnaBridge 143:86740a56073b 4149 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 143:86740a56073b 4150 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4151 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
AnnaBridge 143:86740a56073b 4152 #define RCC_APB1RSTR_LPUART1RST_Pos (18U)
AnnaBridge 143:86740a56073b 4153 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4154 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */
AnnaBridge 143:86740a56073b 4155 #define RCC_APB1RSTR_USART4RST_Pos (19U)
AnnaBridge 143:86740a56073b 4156 #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4157 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 clock reset */
AnnaBridge 143:86740a56073b 4158 #define RCC_APB1RSTR_USART5RST_Pos (20U)
AnnaBridge 143:86740a56073b 4159 #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4160 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 clock reset */
AnnaBridge 143:86740a56073b 4161 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 143:86740a56073b 4162 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4163 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
AnnaBridge 143:86740a56073b 4164 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 143:86740a56073b 4165 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4166 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
AnnaBridge 143:86740a56073b 4167 #define RCC_APB1RSTR_USBRST_Pos (23U)
AnnaBridge 143:86740a56073b 4168 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4169 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */
AnnaBridge 143:86740a56073b 4170 #define RCC_APB1RSTR_CRSRST_Pos (27U)
AnnaBridge 143:86740a56073b 4171 #define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4172 #define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */
AnnaBridge 143:86740a56073b 4173 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 143:86740a56073b 4174 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4175 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
AnnaBridge 143:86740a56073b 4176 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 143:86740a56073b 4177 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4178 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
AnnaBridge 143:86740a56073b 4179 #define RCC_APB1RSTR_I2C3RST_Pos (30U)
AnnaBridge 143:86740a56073b 4180 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4181 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */
AnnaBridge 143:86740a56073b 4182 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
AnnaBridge 143:86740a56073b 4183 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4184 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */
AnnaBridge 143:86740a56073b 4185
AnnaBridge 143:86740a56073b 4186 /***************** Bit definition for RCC_IOPENR register ******************/
AnnaBridge 143:86740a56073b 4187 #define RCC_IOPENR_IOPAEN_Pos (0U)
AnnaBridge 143:86740a56073b 4188 #define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4189 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
AnnaBridge 143:86740a56073b 4190 #define RCC_IOPENR_IOPBEN_Pos (1U)
AnnaBridge 143:86740a56073b 4191 #define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4192 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
AnnaBridge 143:86740a56073b 4193 #define RCC_IOPENR_IOPCEN_Pos (2U)
AnnaBridge 143:86740a56073b 4194 #define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4195 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
AnnaBridge 143:86740a56073b 4196 #define RCC_IOPENR_IOPDEN_Pos (3U)
AnnaBridge 143:86740a56073b 4197 #define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4198 #define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
AnnaBridge 143:86740a56073b 4199 #define RCC_IOPENR_IOPEEN_Pos (4U)
AnnaBridge 143:86740a56073b 4200 #define RCC_IOPENR_IOPEEN_Msk (0x1U << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4201 #define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
AnnaBridge 143:86740a56073b 4202 #define RCC_IOPENR_IOPHEN_Pos (7U)
AnnaBridge 143:86740a56073b 4203 #define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4204 #define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
AnnaBridge 143:86740a56073b 4205
AnnaBridge 143:86740a56073b 4206 /* Reference defines */
AnnaBridge 143:86740a56073b 4207 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
AnnaBridge 143:86740a56073b 4208 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
AnnaBridge 143:86740a56073b 4209 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
AnnaBridge 143:86740a56073b 4210 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
AnnaBridge 143:86740a56073b 4211 #define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
AnnaBridge 143:86740a56073b 4212 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
AnnaBridge 143:86740a56073b 4213
AnnaBridge 143:86740a56073b 4214 /***************** Bit definition for RCC_AHBENR register ******************/
AnnaBridge 143:86740a56073b 4215 #define RCC_AHBENR_DMAEN_Pos (0U)
AnnaBridge 143:86740a56073b 4216 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4217 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
AnnaBridge 143:86740a56073b 4218 #define RCC_AHBENR_MIFEN_Pos (8U)
AnnaBridge 143:86740a56073b 4219 #define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4220 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
AnnaBridge 143:86740a56073b 4221 #define RCC_AHBENR_CRCEN_Pos (12U)
AnnaBridge 143:86740a56073b 4222 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4223 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
AnnaBridge 143:86740a56073b 4224 #define RCC_AHBENR_TSCEN_Pos (16U)
AnnaBridge 143:86740a56073b 4225 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4226 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
AnnaBridge 143:86740a56073b 4227 #define RCC_AHBENR_RNGEN_Pos (20U)
AnnaBridge 143:86740a56073b 4228 #define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4229 #define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
AnnaBridge 143:86740a56073b 4230
AnnaBridge 143:86740a56073b 4231 /* Reference defines */
AnnaBridge 143:86740a56073b 4232 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
AnnaBridge 143:86740a56073b 4233
AnnaBridge 143:86740a56073b 4234 /***************** Bit definition for RCC_APB2ENR register ******************/
AnnaBridge 143:86740a56073b 4235 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
AnnaBridge 143:86740a56073b 4236 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4237 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
AnnaBridge 143:86740a56073b 4238 #define RCC_APB2ENR_TIM21EN_Pos (2U)
AnnaBridge 143:86740a56073b 4239 #define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4240 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
AnnaBridge 143:86740a56073b 4241 #define RCC_APB2ENR_TIM22EN_Pos (5U)
AnnaBridge 143:86740a56073b 4242 #define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4243 #define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
AnnaBridge 143:86740a56073b 4244 #define RCC_APB2ENR_FWEN_Pos (7U)
AnnaBridge 143:86740a56073b 4245 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4246 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
AnnaBridge 143:86740a56073b 4247 #define RCC_APB2ENR_ADCEN_Pos (9U)
AnnaBridge 143:86740a56073b 4248 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4249 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
AnnaBridge 143:86740a56073b 4250 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 143:86740a56073b 4251 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4252 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
AnnaBridge 143:86740a56073b 4253 #define RCC_APB2ENR_USART1EN_Pos (14U)
AnnaBridge 143:86740a56073b 4254 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4255 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
AnnaBridge 143:86740a56073b 4256 #define RCC_APB2ENR_DBGEN_Pos (22U)
AnnaBridge 143:86740a56073b 4257 #define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4258 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
AnnaBridge 143:86740a56073b 4259
AnnaBridge 143:86740a56073b 4260 /* Reference defines */
AnnaBridge 143:86740a56073b 4261
AnnaBridge 143:86740a56073b 4262 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
AnnaBridge 143:86740a56073b 4263 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
AnnaBridge 143:86740a56073b 4264 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
AnnaBridge 143:86740a56073b 4265
AnnaBridge 143:86740a56073b 4266 /***************** Bit definition for RCC_APB1ENR register ******************/
AnnaBridge 143:86740a56073b 4267 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 143:86740a56073b 4268 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4269 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
AnnaBridge 143:86740a56073b 4270 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 143:86740a56073b 4271 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4272 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
AnnaBridge 143:86740a56073b 4273 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 143:86740a56073b 4274 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4275 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
AnnaBridge 143:86740a56073b 4276 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 143:86740a56073b 4277 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4278 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
AnnaBridge 143:86740a56073b 4279 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 143:86740a56073b 4280 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4281 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
AnnaBridge 143:86740a56073b 4282 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 143:86740a56073b 4283 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4284 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
AnnaBridge 143:86740a56073b 4285 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 143:86740a56073b 4286 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4287 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
AnnaBridge 143:86740a56073b 4288 #define RCC_APB1ENR_LPUART1EN_Pos (18U)
AnnaBridge 143:86740a56073b 4289 #define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4290 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
AnnaBridge 143:86740a56073b 4291 #define RCC_APB1ENR_USART4EN_Pos (19U)
AnnaBridge 143:86740a56073b 4292 #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4293 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
AnnaBridge 143:86740a56073b 4294 #define RCC_APB1ENR_USART5EN_Pos (20U)
AnnaBridge 143:86740a56073b 4295 #define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4296 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
AnnaBridge 143:86740a56073b 4297 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 143:86740a56073b 4298 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4299 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
AnnaBridge 143:86740a56073b 4300 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 143:86740a56073b 4301 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4302 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
AnnaBridge 143:86740a56073b 4303 #define RCC_APB1ENR_USBEN_Pos (23U)
AnnaBridge 143:86740a56073b 4304 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4305 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
AnnaBridge 143:86740a56073b 4306 #define RCC_APB1ENR_CRSEN_Pos (27U)
AnnaBridge 143:86740a56073b 4307 #define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4308 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
AnnaBridge 143:86740a56073b 4309 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 143:86740a56073b 4310 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4311 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
AnnaBridge 143:86740a56073b 4312 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 143:86740a56073b 4313 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4314 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
AnnaBridge 143:86740a56073b 4315 #define RCC_APB1ENR_I2C3EN_Pos (30U)
AnnaBridge 143:86740a56073b 4316 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4317 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
AnnaBridge 143:86740a56073b 4318 #define RCC_APB1ENR_LPTIM1EN_Pos (31U)
AnnaBridge 143:86740a56073b 4319 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4320 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
AnnaBridge 143:86740a56073b 4321
AnnaBridge 143:86740a56073b 4322 /****************** Bit definition for RCC_IOPSMENR register ****************/
AnnaBridge 143:86740a56073b 4323 #define RCC_IOPSMENR_IOPASMEN_Pos (0U)
AnnaBridge 143:86740a56073b 4324 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4325 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4326 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
AnnaBridge 143:86740a56073b 4327 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4328 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4329 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
AnnaBridge 143:86740a56073b 4330 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4331 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4332 #define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
AnnaBridge 143:86740a56073b 4333 #define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4334 #define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4335 #define RCC_IOPSMENR_IOPESMEN_Pos (4U)
AnnaBridge 143:86740a56073b 4336 #define RCC_IOPSMENR_IOPESMEN_Msk (0x1U << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4337 #define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4338 #define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
AnnaBridge 143:86740a56073b 4339 #define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4340 #define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4341
AnnaBridge 143:86740a56073b 4342 /* Reference defines */
AnnaBridge 143:86740a56073b 4343 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4344 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4345 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4346 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4347 #define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4348 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4349
AnnaBridge 143:86740a56073b 4350 /***************** Bit definition for RCC_AHBSMENR register ******************/
AnnaBridge 143:86740a56073b 4351 #define RCC_AHBSMENR_DMASMEN_Pos (0U)
AnnaBridge 143:86740a56073b 4352 #define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4353 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4354 #define RCC_AHBSMENR_MIFSMEN_Pos (8U)
AnnaBridge 143:86740a56073b 4355 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4356 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
AnnaBridge 143:86740a56073b 4357 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
AnnaBridge 143:86740a56073b 4358 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4359 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4360 #define RCC_AHBSMENR_CRCSMEN_Pos (12U)
AnnaBridge 143:86740a56073b 4361 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4362 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4363 #define RCC_AHBSMENR_TSCSMEN_Pos (16U)
AnnaBridge 143:86740a56073b 4364 #define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4365 #define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4366 #define RCC_AHBSMENR_RNGSMEN_Pos (20U)
AnnaBridge 143:86740a56073b 4367 #define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4368 #define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4369
AnnaBridge 143:86740a56073b 4370 /* Reference defines */
AnnaBridge 143:86740a56073b 4371 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4372
AnnaBridge 143:86740a56073b 4373 /***************** Bit definition for RCC_APB2SMENR register ******************/
AnnaBridge 143:86740a56073b 4374 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
AnnaBridge 143:86740a56073b 4375 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4376 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4377 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
AnnaBridge 143:86740a56073b 4378 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4379 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4380 #define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
AnnaBridge 143:86740a56073b 4381 #define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4382 #define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4383 #define RCC_APB2SMENR_ADCSMEN_Pos (9U)
AnnaBridge 143:86740a56073b 4384 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4385 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4386 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
AnnaBridge 143:86740a56073b 4387 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4388 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4389 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
AnnaBridge 143:86740a56073b 4390 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4391 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4392 #define RCC_APB2SMENR_DBGSMEN_Pos (22U)
AnnaBridge 143:86740a56073b 4393 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4394 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4395
AnnaBridge 143:86740a56073b 4396 /* Reference defines */
AnnaBridge 143:86740a56073b 4397 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4398 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4399
AnnaBridge 143:86740a56073b 4400 /***************** Bit definition for RCC_APB1SMENR register ******************/
AnnaBridge 143:86740a56073b 4401 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
AnnaBridge 143:86740a56073b 4402 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4403 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4404 #define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
AnnaBridge 143:86740a56073b 4405 #define RCC_APB1SMENR_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4406 #define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4407 #define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
AnnaBridge 143:86740a56073b 4408 #define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4409 #define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4410 #define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
AnnaBridge 143:86740a56073b 4411 #define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4412 #define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4413 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
AnnaBridge 143:86740a56073b 4414 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4415 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4416 #define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
AnnaBridge 143:86740a56073b 4417 #define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4418 #define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4419 #define RCC_APB1SMENR_USART2SMEN_Pos (17U)
AnnaBridge 143:86740a56073b 4420 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4421 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4422 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
AnnaBridge 143:86740a56073b 4423 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4424 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4425 #define RCC_APB1SMENR_USART4SMEN_Pos (19U)
AnnaBridge 143:86740a56073b 4426 #define RCC_APB1SMENR_USART4SMEN_Msk (0x1U << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4427 #define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4428 #define RCC_APB1SMENR_USART5SMEN_Pos (20U)
AnnaBridge 143:86740a56073b 4429 #define RCC_APB1SMENR_USART5SMEN_Msk (0x1U << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4430 #define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4431 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
AnnaBridge 143:86740a56073b 4432 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4433 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4434 #define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
AnnaBridge 143:86740a56073b 4435 #define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4436 #define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4437 #define RCC_APB1SMENR_USBSMEN_Pos (23U)
AnnaBridge 143:86740a56073b 4438 #define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4439 #define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4440 #define RCC_APB1SMENR_CRSSMEN_Pos (27U)
AnnaBridge 143:86740a56073b 4441 #define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4442 #define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4443 #define RCC_APB1SMENR_PWRSMEN_Pos (28U)
AnnaBridge 143:86740a56073b 4444 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4445 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4446 #define RCC_APB1SMENR_DACSMEN_Pos (29U)
AnnaBridge 143:86740a56073b 4447 #define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4448 #define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4449 #define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
AnnaBridge 143:86740a56073b 4450 #define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4451 #define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4452 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
AnnaBridge 143:86740a56073b 4453 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4454 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
AnnaBridge 143:86740a56073b 4455
AnnaBridge 143:86740a56073b 4456 /******************* Bit definition for RCC_CCIPR register *******************/
AnnaBridge 143:86740a56073b 4457 /*!< USART1 Clock source selection */
AnnaBridge 143:86740a56073b 4458 #define RCC_CCIPR_USART1SEL_Pos (0U)
AnnaBridge 143:86740a56073b 4459 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 4460 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
AnnaBridge 143:86740a56073b 4461 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4462 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4463
AnnaBridge 143:86740a56073b 4464 /*!< USART2 Clock source selection */
AnnaBridge 143:86740a56073b 4465 #define RCC_CCIPR_USART2SEL_Pos (2U)
AnnaBridge 143:86740a56073b 4466 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 4467 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
AnnaBridge 143:86740a56073b 4468 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4469 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4470
AnnaBridge 143:86740a56073b 4471 /*!< LPUART1 Clock source selection */
AnnaBridge 143:86740a56073b 4472 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
AnnaBridge 143:86740a56073b 4473 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 4474 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
AnnaBridge 143:86740a56073b 4475 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
AnnaBridge 143:86740a56073b 4476 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
AnnaBridge 143:86740a56073b 4477
AnnaBridge 143:86740a56073b 4478 /*!< I2C1 Clock source selection */
AnnaBridge 143:86740a56073b 4479 #define RCC_CCIPR_I2C1SEL_Pos (12U)
AnnaBridge 143:86740a56073b 4480 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 4481 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
AnnaBridge 143:86740a56073b 4482 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4483 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4484
AnnaBridge 143:86740a56073b 4485 /*!< I2C3 Clock source selection */
AnnaBridge 143:86740a56073b 4486 #define RCC_CCIPR_I2C3SEL_Pos (16U)
AnnaBridge 143:86740a56073b 4487 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 4488 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
AnnaBridge 143:86740a56073b 4489 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4490 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4491
AnnaBridge 143:86740a56073b 4492 /*!< LPTIM1 Clock source selection */
AnnaBridge 143:86740a56073b 4493 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
AnnaBridge 143:86740a56073b 4494 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
AnnaBridge 143:86740a56073b 4495 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
AnnaBridge 143:86740a56073b 4496 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4497 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4498
AnnaBridge 143:86740a56073b 4499 /*!< HSI48 Clock source selection */
AnnaBridge 143:86740a56073b 4500 #define RCC_CCIPR_HSI48SEL_Pos (26U)
AnnaBridge 143:86740a56073b 4501 #define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 4502 #define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
AnnaBridge 143:86740a56073b 4503
AnnaBridge 143:86740a56073b 4504 /* Legacy defines */
AnnaBridge 143:86740a56073b 4505 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
AnnaBridge 143:86740a56073b 4506
AnnaBridge 143:86740a56073b 4507 /******************* Bit definition for RCC_CSR register *******************/
AnnaBridge 143:86740a56073b 4508 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 143:86740a56073b 4509 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4510 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
AnnaBridge 143:86740a56073b 4511 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 143:86740a56073b 4512 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4513 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
AnnaBridge 143:86740a56073b 4514
AnnaBridge 143:86740a56073b 4515 #define RCC_CSR_LSEON_Pos (8U)
AnnaBridge 143:86740a56073b 4516 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4517 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
AnnaBridge 143:86740a56073b 4518 #define RCC_CSR_LSERDY_Pos (9U)
AnnaBridge 143:86740a56073b 4519 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4520 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
AnnaBridge 143:86740a56073b 4521 #define RCC_CSR_LSEBYP_Pos (10U)
AnnaBridge 143:86740a56073b 4522 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4523 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
AnnaBridge 143:86740a56073b 4524
AnnaBridge 143:86740a56073b 4525 #define RCC_CSR_LSEDRV_Pos (11U)
AnnaBridge 143:86740a56073b 4526 #define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
AnnaBridge 143:86740a56073b 4527 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
AnnaBridge 143:86740a56073b 4528 #define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4529 #define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4530
AnnaBridge 143:86740a56073b 4531 #define RCC_CSR_LSECSSON_Pos (13U)
AnnaBridge 143:86740a56073b 4532 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4533 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
AnnaBridge 143:86740a56073b 4534 #define RCC_CSR_LSECSSD_Pos (14U)
AnnaBridge 143:86740a56073b 4535 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4536 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
AnnaBridge 143:86740a56073b 4537
AnnaBridge 143:86740a56073b 4538 /*!< RTC congiguration */
AnnaBridge 143:86740a56073b 4539 #define RCC_CSR_RTCSEL_Pos (16U)
AnnaBridge 143:86740a56073b 4540 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 4541 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
AnnaBridge 143:86740a56073b 4542 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4543 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4544
AnnaBridge 143:86740a56073b 4545 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 143:86740a56073b 4546 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
AnnaBridge 143:86740a56073b 4547 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4548 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 143:86740a56073b 4549 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
AnnaBridge 143:86740a56073b 4550 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4551 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 143:86740a56073b 4552 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
AnnaBridge 143:86740a56073b 4553 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
AnnaBridge 143:86740a56073b 4554 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
AnnaBridge 143:86740a56073b 4555
AnnaBridge 143:86740a56073b 4556 #define RCC_CSR_RTCEN_Pos (18U)
AnnaBridge 143:86740a56073b 4557 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4558 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
AnnaBridge 143:86740a56073b 4559 #define RCC_CSR_RTCRST_Pos (19U)
AnnaBridge 143:86740a56073b 4560 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4561 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
AnnaBridge 143:86740a56073b 4562
AnnaBridge 143:86740a56073b 4563 #define RCC_CSR_RMVF_Pos (23U)
AnnaBridge 143:86740a56073b 4564 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4565 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
AnnaBridge 143:86740a56073b 4566 #define RCC_CSR_FWRSTF_Pos (24U)
AnnaBridge 143:86740a56073b 4567 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 4568 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
AnnaBridge 143:86740a56073b 4569 #define RCC_CSR_OBLRSTF_Pos (25U)
AnnaBridge 143:86740a56073b 4570 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 4571 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
AnnaBridge 143:86740a56073b 4572 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 143:86740a56073b 4573 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 4574 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
AnnaBridge 143:86740a56073b 4575 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 143:86740a56073b 4576 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4577 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
AnnaBridge 143:86740a56073b 4578 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 143:86740a56073b 4579 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4580 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
AnnaBridge 143:86740a56073b 4581 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 143:86740a56073b 4582 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4583 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
AnnaBridge 143:86740a56073b 4584 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 143:86740a56073b 4585 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4586 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
AnnaBridge 143:86740a56073b 4587 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 143:86740a56073b 4588 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4589 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
AnnaBridge 143:86740a56073b 4590
AnnaBridge 143:86740a56073b 4591 /* Reference defines */
AnnaBridge 143:86740a56073b 4592 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
AnnaBridge 143:86740a56073b 4593
AnnaBridge 143:86740a56073b 4594
AnnaBridge 143:86740a56073b 4595 /******************************************************************************/
AnnaBridge 143:86740a56073b 4596 /* */
AnnaBridge 143:86740a56073b 4597 /* RNG */
AnnaBridge 143:86740a56073b 4598 /* */
AnnaBridge 143:86740a56073b 4599 /******************************************************************************/
AnnaBridge 143:86740a56073b 4600 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 143:86740a56073b 4601 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 143:86740a56073b 4602 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4603 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 143:86740a56073b 4604 #define RNG_CR_IE_Pos (3U)
AnnaBridge 143:86740a56073b 4605 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4606 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 143:86740a56073b 4607
AnnaBridge 143:86740a56073b 4608 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 143:86740a56073b 4609 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 143:86740a56073b 4610 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4611 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 143:86740a56073b 4612 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 143:86740a56073b 4613 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4614 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 143:86740a56073b 4615 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 143:86740a56073b 4616 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4617 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 143:86740a56073b 4618 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 143:86740a56073b 4619 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4620 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 143:86740a56073b 4621 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 143:86740a56073b 4622 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4623 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 143:86740a56073b 4624
AnnaBridge 143:86740a56073b 4625 /******************************************************************************/
AnnaBridge 143:86740a56073b 4626 /* */
AnnaBridge 143:86740a56073b 4627 /* Real-Time Clock (RTC) */
AnnaBridge 143:86740a56073b 4628 /* */
AnnaBridge 143:86740a56073b 4629 /******************************************************************************/
AnnaBridge 143:86740a56073b 4630 /*
AnnaBridge 143:86740a56073b 4631 * @brief Specific device feature definitions
AnnaBridge 143:86740a56073b 4632 */
AnnaBridge 143:86740a56073b 4633 #define RTC_TAMPER1_SUPPORT
AnnaBridge 143:86740a56073b 4634 #define RTC_TAMPER2_SUPPORT
AnnaBridge 143:86740a56073b 4635 #define RTC_TAMPER3_SUPPORT
AnnaBridge 143:86740a56073b 4636 #define RTC_WAKEUP_SUPPORT
AnnaBridge 143:86740a56073b 4637 #define RTC_BACKUP_SUPPORT
AnnaBridge 143:86740a56073b 4638
AnnaBridge 143:86740a56073b 4639 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 143:86740a56073b 4640 #define RTC_TR_PM_Pos (22U)
AnnaBridge 143:86740a56073b 4641 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4642 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */
AnnaBridge 143:86740a56073b 4643 #define RTC_TR_HT_Pos (20U)
AnnaBridge 143:86740a56073b 4644 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 4645 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */
AnnaBridge 143:86740a56073b 4646 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4647 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4648 #define RTC_TR_HU_Pos (16U)
AnnaBridge 143:86740a56073b 4649 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 4650 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */
AnnaBridge 143:86740a56073b 4651 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4652 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4653 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4654 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4655 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 143:86740a56073b 4656 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 4657 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
AnnaBridge 143:86740a56073b 4658 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4659 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4660 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4661 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 143:86740a56073b 4662 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 4663 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
AnnaBridge 143:86740a56073b 4664 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4665 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4666 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4667 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4668 #define RTC_TR_ST_Pos (4U)
AnnaBridge 143:86740a56073b 4669 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 4670 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */
AnnaBridge 143:86740a56073b 4671 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4672 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4673 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4674 #define RTC_TR_SU_Pos (0U)
AnnaBridge 143:86740a56073b 4675 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 4676 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */
AnnaBridge 143:86740a56073b 4677 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4678 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4679 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4680 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4681
AnnaBridge 143:86740a56073b 4682 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 143:86740a56073b 4683 #define RTC_DR_YT_Pos (20U)
AnnaBridge 143:86740a56073b 4684 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 143:86740a56073b 4685 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */
AnnaBridge 143:86740a56073b 4686 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4687 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4688 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4689 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4690 #define RTC_DR_YU_Pos (16U)
AnnaBridge 143:86740a56073b 4691 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 4692 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */
AnnaBridge 143:86740a56073b 4693 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4694 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4695 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4696 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4697 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 143:86740a56073b 4698 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 143:86740a56073b 4699 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
AnnaBridge 143:86740a56073b 4700 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4701 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4702 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 4703 #define RTC_DR_MT_Pos (12U)
AnnaBridge 143:86740a56073b 4704 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4705 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */
AnnaBridge 143:86740a56073b 4706 #define RTC_DR_MU_Pos (8U)
AnnaBridge 143:86740a56073b 4707 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 4708 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */
AnnaBridge 143:86740a56073b 4709 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4710 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4711 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4712 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4713 #define RTC_DR_DT_Pos (4U)
AnnaBridge 143:86740a56073b 4714 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 4715 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */
AnnaBridge 143:86740a56073b 4716 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4717 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4718 #define RTC_DR_DU_Pos (0U)
AnnaBridge 143:86740a56073b 4719 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 4720 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */
AnnaBridge 143:86740a56073b 4721 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4722 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4723 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4724 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4725
AnnaBridge 143:86740a56073b 4726 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 143:86740a56073b 4727 #define RTC_CR_COE_Pos (23U)
AnnaBridge 143:86740a56073b 4728 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4729 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */
AnnaBridge 143:86740a56073b 4730 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 143:86740a56073b 4731 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 143:86740a56073b 4732 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
AnnaBridge 143:86740a56073b 4733 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4734 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4735 #define RTC_CR_POL_Pos (20U)
AnnaBridge 143:86740a56073b 4736 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4737 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */
AnnaBridge 143:86740a56073b 4738 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 143:86740a56073b 4739 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4740 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
AnnaBridge 143:86740a56073b 4741 #define RTC_CR_BCK_Pos (18U)
AnnaBridge 143:86740a56073b 4742 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4743 #define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */
AnnaBridge 143:86740a56073b 4744 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 143:86740a56073b 4745 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4746 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
AnnaBridge 143:86740a56073b 4747 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 143:86740a56073b 4748 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4749 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
AnnaBridge 143:86740a56073b 4750 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 143:86740a56073b 4751 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 4752 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
AnnaBridge 143:86740a56073b 4753 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 143:86740a56073b 4754 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4755 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
AnnaBridge 143:86740a56073b 4756 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 143:86740a56073b 4757 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4758 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
AnnaBridge 143:86740a56073b 4759 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 143:86740a56073b 4760 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4761 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
AnnaBridge 143:86740a56073b 4762 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 143:86740a56073b 4763 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4764 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
AnnaBridge 143:86740a56073b 4765 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 143:86740a56073b 4766 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4767 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
AnnaBridge 143:86740a56073b 4768 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 143:86740a56073b 4769 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4770 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
AnnaBridge 143:86740a56073b 4771 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 143:86740a56073b 4772 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4773 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
AnnaBridge 143:86740a56073b 4774 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 143:86740a56073b 4775 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4776 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
AnnaBridge 143:86740a56073b 4777 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 143:86740a56073b 4778 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4779 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
AnnaBridge 143:86740a56073b 4780 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 143:86740a56073b 4781 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4782 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
AnnaBridge 143:86740a56073b 4783 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 143:86740a56073b 4784 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4785 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
AnnaBridge 143:86740a56073b 4786 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 143:86740a56073b 4787 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 4788 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
AnnaBridge 143:86740a56073b 4789 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4790 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4791 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4792
AnnaBridge 143:86740a56073b 4793 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 143:86740a56073b 4794 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 143:86740a56073b 4795 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4796 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
AnnaBridge 143:86740a56073b 4797 #define RTC_ISR_TAMP3F_Pos (15U)
AnnaBridge 143:86740a56073b 4798 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 4799 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
AnnaBridge 143:86740a56073b 4800 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 143:86740a56073b 4801 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4802 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
AnnaBridge 143:86740a56073b 4803 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 143:86740a56073b 4804 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4805 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
AnnaBridge 143:86740a56073b 4806 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 143:86740a56073b 4807 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4808 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
AnnaBridge 143:86740a56073b 4809 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 143:86740a56073b 4810 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4811 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
AnnaBridge 143:86740a56073b 4812 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 143:86740a56073b 4813 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4814 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
AnnaBridge 143:86740a56073b 4815 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 143:86740a56073b 4816 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4817 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
AnnaBridge 143:86740a56073b 4818 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 143:86740a56073b 4819 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4820 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
AnnaBridge 143:86740a56073b 4821 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 143:86740a56073b 4822 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4823 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
AnnaBridge 143:86740a56073b 4824 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 143:86740a56073b 4825 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4826 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
AnnaBridge 143:86740a56073b 4827 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 143:86740a56073b 4828 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4829 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
AnnaBridge 143:86740a56073b 4830 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 143:86740a56073b 4831 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4832 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
AnnaBridge 143:86740a56073b 4833 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 143:86740a56073b 4834 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4835 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
AnnaBridge 143:86740a56073b 4836 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 143:86740a56073b 4837 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4838 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
AnnaBridge 143:86740a56073b 4839 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 143:86740a56073b 4840 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4841 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
AnnaBridge 143:86740a56073b 4842 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 143:86740a56073b 4843 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4844 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
AnnaBridge 143:86740a56073b 4845
AnnaBridge 143:86740a56073b 4846 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 143:86740a56073b 4847 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 143:86740a56073b 4848 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 143:86740a56073b 4849 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
AnnaBridge 143:86740a56073b 4850 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 143:86740a56073b 4851 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 143:86740a56073b 4852 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
AnnaBridge 143:86740a56073b 4853
AnnaBridge 143:86740a56073b 4854 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 143:86740a56073b 4855 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 143:86740a56073b 4856 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 4857 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 143:86740a56073b 4858
AnnaBridge 143:86740a56073b 4859 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 143:86740a56073b 4860 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 143:86740a56073b 4861 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4862 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
AnnaBridge 143:86740a56073b 4863 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 143:86740a56073b 4864 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4865 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
AnnaBridge 143:86740a56073b 4866 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 143:86740a56073b 4867 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 4868 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
AnnaBridge 143:86740a56073b 4869 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4870 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4871 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 143:86740a56073b 4872 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 4873 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
AnnaBridge 143:86740a56073b 4874 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 4875 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 4876 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 4877 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4878 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 143:86740a56073b 4879 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4880 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
AnnaBridge 143:86740a56073b 4881 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 143:86740a56073b 4882 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4883 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
AnnaBridge 143:86740a56073b 4884 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 143:86740a56073b 4885 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 4886 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
AnnaBridge 143:86740a56073b 4887 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4888 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4889 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 143:86740a56073b 4890 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 4891 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
AnnaBridge 143:86740a56073b 4892 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4893 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4894 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4895 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4896 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 143:86740a56073b 4897 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 4898 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
AnnaBridge 143:86740a56073b 4899 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 143:86740a56073b 4900 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 4901 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
AnnaBridge 143:86740a56073b 4902 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4903 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4904 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4905 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 143:86740a56073b 4906 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 4907 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
AnnaBridge 143:86740a56073b 4908 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4909 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4910 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4911 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4912 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 143:86740a56073b 4913 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4914 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
AnnaBridge 143:86740a56073b 4915 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 143:86740a56073b 4916 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 4917 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
AnnaBridge 143:86740a56073b 4918 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4919 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4920 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4921 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 143:86740a56073b 4922 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 4923 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
AnnaBridge 143:86740a56073b 4924 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4925 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4926 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4927 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4928
AnnaBridge 143:86740a56073b 4929 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 143:86740a56073b 4930 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 143:86740a56073b 4931 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 4932 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
AnnaBridge 143:86740a56073b 4933 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 143:86740a56073b 4934 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 4935 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
AnnaBridge 143:86740a56073b 4936 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 143:86740a56073b 4937 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 143:86740a56073b 4938 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
AnnaBridge 143:86740a56073b 4939 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 4940 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 4941 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 143:86740a56073b 4942 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 4943 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
AnnaBridge 143:86740a56073b 4944 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 4945 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 4946 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 4947 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 4948 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 143:86740a56073b 4949 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 4950 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
AnnaBridge 143:86740a56073b 4951 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 143:86740a56073b 4952 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 4953 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
AnnaBridge 143:86740a56073b 4954 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 143:86740a56073b 4955 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 4956 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
AnnaBridge 143:86740a56073b 4957 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 4958 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 4959 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 143:86740a56073b 4960 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 4961 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
AnnaBridge 143:86740a56073b 4962 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 4963 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 4964 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 4965 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 4966 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 143:86740a56073b 4967 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 4968 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
AnnaBridge 143:86740a56073b 4969 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 143:86740a56073b 4970 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 4971 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
AnnaBridge 143:86740a56073b 4972 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 4973 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 4974 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 4975 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 143:86740a56073b 4976 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 4977 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
AnnaBridge 143:86740a56073b 4978 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 4979 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 4980 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 4981 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 4982 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 143:86740a56073b 4983 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 4984 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
AnnaBridge 143:86740a56073b 4985 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 143:86740a56073b 4986 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 4987 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
AnnaBridge 143:86740a56073b 4988 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 4989 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 4990 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 4991 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 143:86740a56073b 4992 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 4993 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
AnnaBridge 143:86740a56073b 4994 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 4995 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 4996 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 4997 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 4998
AnnaBridge 143:86740a56073b 4999 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 143:86740a56073b 5000 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 143:86740a56073b 5001 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 5002 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
AnnaBridge 143:86740a56073b 5003
AnnaBridge 143:86740a56073b 5004 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 143:86740a56073b 5005 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 143:86740a56073b 5006 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5007 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
AnnaBridge 143:86740a56073b 5008
AnnaBridge 143:86740a56073b 5009 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 143:86740a56073b 5010 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 143:86740a56073b 5011 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 143:86740a56073b 5012 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
AnnaBridge 143:86740a56073b 5013 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 143:86740a56073b 5014 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 5015 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
AnnaBridge 143:86740a56073b 5016
AnnaBridge 143:86740a56073b 5017 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 143:86740a56073b 5018 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 143:86740a56073b 5019 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 5020 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
AnnaBridge 143:86740a56073b 5021 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 143:86740a56073b 5022 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 5023 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
AnnaBridge 143:86740a56073b 5024 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 5025 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 5026 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 143:86740a56073b 5027 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 143:86740a56073b 5028 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
AnnaBridge 143:86740a56073b 5029 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 5030 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 5031 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 5032 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 5033 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 143:86740a56073b 5034 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 5035 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
AnnaBridge 143:86740a56073b 5036 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5037 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5038 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5039 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 143:86740a56073b 5040 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5041 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
AnnaBridge 143:86740a56073b 5042 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5043 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5044 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5045 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5046 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 143:86740a56073b 5047 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 5048 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
AnnaBridge 143:86740a56073b 5049 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5050 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5051 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5052 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 143:86740a56073b 5053 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5054 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
AnnaBridge 143:86740a56073b 5055 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5056 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5057 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5058 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5059
AnnaBridge 143:86740a56073b 5060 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 143:86740a56073b 5061 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 143:86740a56073b 5062 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 143:86740a56073b 5063 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
AnnaBridge 143:86740a56073b 5064 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5065 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5066 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5067 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 143:86740a56073b 5068 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5069 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
AnnaBridge 143:86740a56073b 5070 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 143:86740a56073b 5071 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5072 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
AnnaBridge 143:86740a56073b 5073 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5074 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5075 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5076 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5077 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 143:86740a56073b 5078 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 5079 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
AnnaBridge 143:86740a56073b 5080 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5081 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5082 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 143:86740a56073b 5083 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5084 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
AnnaBridge 143:86740a56073b 5085 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5086 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5087 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5088 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5089
AnnaBridge 143:86740a56073b 5090 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 143:86740a56073b 5091 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 143:86740a56073b 5092 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5093 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 143:86740a56073b 5094
AnnaBridge 143:86740a56073b 5095 /******************** Bits definition for RTC_CALR register *****************/
AnnaBridge 143:86740a56073b 5096 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 143:86740a56073b 5097 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5098 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
AnnaBridge 143:86740a56073b 5099 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 143:86740a56073b 5100 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5101 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
AnnaBridge 143:86740a56073b 5102 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 143:86740a56073b 5103 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5104 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
AnnaBridge 143:86740a56073b 5105 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 143:86740a56073b 5106 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 143:86740a56073b 5107 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
AnnaBridge 143:86740a56073b 5108 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5109 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5110 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5111 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5112 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5113 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5114 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5115 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5116 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5117
AnnaBridge 143:86740a56073b 5118 /* Legacy defines */
AnnaBridge 143:86740a56073b 5119 #define RTC_CAL_CALP RTC_CALR_CALP
AnnaBridge 143:86740a56073b 5120 #define RTC_CAL_CALW8 RTC_CALR_CALW8
AnnaBridge 143:86740a56073b 5121 #define RTC_CAL_CALW16 RTC_CALR_CALW16
AnnaBridge 143:86740a56073b 5122 #define RTC_CAL_CALM RTC_CALR_CALM
AnnaBridge 143:86740a56073b 5123 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
AnnaBridge 143:86740a56073b 5124 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
AnnaBridge 143:86740a56073b 5125 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
AnnaBridge 143:86740a56073b 5126 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
AnnaBridge 143:86740a56073b 5127 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
AnnaBridge 143:86740a56073b 5128 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
AnnaBridge 143:86740a56073b 5129 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
AnnaBridge 143:86740a56073b 5130 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
AnnaBridge 143:86740a56073b 5131 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
AnnaBridge 143:86740a56073b 5132
AnnaBridge 143:86740a56073b 5133 /******************** Bits definition for RTC_TAMPCR register ****************/
AnnaBridge 143:86740a56073b 5134 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
AnnaBridge 143:86740a56073b 5135 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 5136 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
AnnaBridge 143:86740a56073b 5137 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
AnnaBridge 143:86740a56073b 5138 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 5139 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
AnnaBridge 143:86740a56073b 5140 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
AnnaBridge 143:86740a56073b 5141 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 5142 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
AnnaBridge 143:86740a56073b 5143 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
AnnaBridge 143:86740a56073b 5144 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 5145 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
AnnaBridge 143:86740a56073b 5146 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
AnnaBridge 143:86740a56073b 5147 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 5148 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
AnnaBridge 143:86740a56073b 5149 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
AnnaBridge 143:86740a56073b 5150 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 5151 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
AnnaBridge 143:86740a56073b 5152 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
AnnaBridge 143:86740a56073b 5153 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 5154 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
AnnaBridge 143:86740a56073b 5155 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
AnnaBridge 143:86740a56073b 5156 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 5157 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
AnnaBridge 143:86740a56073b 5158 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
AnnaBridge 143:86740a56073b 5159 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 5160 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
AnnaBridge 143:86740a56073b 5161 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
AnnaBridge 143:86740a56073b 5162 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5163 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
AnnaBridge 143:86740a56073b 5164 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
AnnaBridge 143:86740a56073b 5165 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 143:86740a56073b 5166 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
AnnaBridge 143:86740a56073b 5167 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5168 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5169 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
AnnaBridge 143:86740a56073b 5170 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 143:86740a56073b 5171 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
AnnaBridge 143:86740a56073b 5172 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5173 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5174 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
AnnaBridge 143:86740a56073b 5175 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 143:86740a56073b 5176 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
AnnaBridge 143:86740a56073b 5177 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5178 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5179 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5180 #define RTC_TAMPCR_TAMPTS_Pos (7U)
AnnaBridge 143:86740a56073b 5181 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5182 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
AnnaBridge 143:86740a56073b 5183 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
AnnaBridge 143:86740a56073b 5184 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5185 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
AnnaBridge 143:86740a56073b 5186 #define RTC_TAMPCR_TAMP3E_Pos (5U)
AnnaBridge 143:86740a56073b 5187 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5188 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
AnnaBridge 143:86740a56073b 5189 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
AnnaBridge 143:86740a56073b 5190 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5191 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
AnnaBridge 143:86740a56073b 5192 #define RTC_TAMPCR_TAMP2E_Pos (3U)
AnnaBridge 143:86740a56073b 5193 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5194 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
AnnaBridge 143:86740a56073b 5195 #define RTC_TAMPCR_TAMPIE_Pos (2U)
AnnaBridge 143:86740a56073b 5196 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5197 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
AnnaBridge 143:86740a56073b 5198 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
AnnaBridge 143:86740a56073b 5199 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5200 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
AnnaBridge 143:86740a56073b 5201 #define RTC_TAMPCR_TAMP1E_Pos (0U)
AnnaBridge 143:86740a56073b 5202 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5203 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
AnnaBridge 143:86740a56073b 5204
AnnaBridge 143:86740a56073b 5205 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 143:86740a56073b 5206 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 143:86740a56073b 5207 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 5208 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 143:86740a56073b 5209 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 5210 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 5211 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 5212 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 5213 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 143:86740a56073b 5214 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 143:86740a56073b 5215 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 143:86740a56073b 5216
AnnaBridge 143:86740a56073b 5217 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 143:86740a56073b 5218 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 143:86740a56073b 5219 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 5220 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 143:86740a56073b 5221 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 5222 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 5223 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 5224 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 5225 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 143:86740a56073b 5226 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 143:86740a56073b 5227 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 143:86740a56073b 5228
AnnaBridge 143:86740a56073b 5229 /******************** Bits definition for RTC_OR register ****************/
AnnaBridge 143:86740a56073b 5230 #define RTC_OR_OUT_RMP_Pos (1U)
AnnaBridge 143:86740a56073b 5231 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5232 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
AnnaBridge 143:86740a56073b 5233 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
AnnaBridge 143:86740a56073b 5234 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5235 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
AnnaBridge 143:86740a56073b 5236
AnnaBridge 143:86740a56073b 5237 /* Legacy defines */
AnnaBridge 143:86740a56073b 5238 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
AnnaBridge 143:86740a56073b 5239
AnnaBridge 143:86740a56073b 5240 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 143:86740a56073b 5241 #define RTC_BKP0R_Pos (0U)
AnnaBridge 143:86740a56073b 5242 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 5243 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */
AnnaBridge 143:86740a56073b 5244
AnnaBridge 143:86740a56073b 5245 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 143:86740a56073b 5246 #define RTC_BKP1R_Pos (0U)
AnnaBridge 143:86740a56073b 5247 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 5248 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */
AnnaBridge 143:86740a56073b 5249
AnnaBridge 143:86740a56073b 5250 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 143:86740a56073b 5251 #define RTC_BKP2R_Pos (0U)
AnnaBridge 143:86740a56073b 5252 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 5253 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */
AnnaBridge 143:86740a56073b 5254
AnnaBridge 143:86740a56073b 5255 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 143:86740a56073b 5256 #define RTC_BKP3R_Pos (0U)
AnnaBridge 143:86740a56073b 5257 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 5258 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */
AnnaBridge 143:86740a56073b 5259
AnnaBridge 143:86740a56073b 5260 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 143:86740a56073b 5261 #define RTC_BKP4R_Pos (0U)
AnnaBridge 143:86740a56073b 5262 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 143:86740a56073b 5263 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */
AnnaBridge 143:86740a56073b 5264
AnnaBridge 143:86740a56073b 5265 /******************** Number of backup registers ******************************/
AnnaBridge 143:86740a56073b 5266 #define RTC_BKP_NUMBER (0x00000005U) /*!< */
AnnaBridge 143:86740a56073b 5267
AnnaBridge 143:86740a56073b 5268 /******************************************************************************/
AnnaBridge 143:86740a56073b 5269 /* */
AnnaBridge 143:86740a56073b 5270 /* Serial Peripheral Interface (SPI) */
AnnaBridge 143:86740a56073b 5271 /* */
AnnaBridge 143:86740a56073b 5272 /******************************************************************************/
AnnaBridge 143:86740a56073b 5273
AnnaBridge 143:86740a56073b 5274 /*
AnnaBridge 143:86740a56073b 5275 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
AnnaBridge 143:86740a56073b 5276 */
AnnaBridge 143:86740a56073b 5277 #define SPI_I2S_SUPPORT /*!< I2S support */
AnnaBridge 143:86740a56073b 5278
AnnaBridge 143:86740a56073b 5279 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 143:86740a56073b 5280 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 143:86740a56073b 5281 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5282 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
AnnaBridge 143:86740a56073b 5283 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 143:86740a56073b 5284 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5285 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 143:86740a56073b 5286 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 143:86740a56073b 5287 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5288 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
AnnaBridge 143:86740a56073b 5289 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 143:86740a56073b 5290 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 143:86740a56073b 5291 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 143:86740a56073b 5292 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5293 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5294 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5295 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 143:86740a56073b 5296 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5297 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
AnnaBridge 143:86740a56073b 5298 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 143:86740a56073b 5299 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5300 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
AnnaBridge 143:86740a56073b 5301 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 143:86740a56073b 5302 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5303 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
AnnaBridge 143:86740a56073b 5304 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 143:86740a56073b 5305 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5306 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
AnnaBridge 143:86740a56073b 5307 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 143:86740a56073b 5308 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5309 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
AnnaBridge 143:86740a56073b 5310 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 143:86740a56073b 5311 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5312 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
AnnaBridge 143:86740a56073b 5313 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 143:86740a56073b 5314 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5315 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
AnnaBridge 143:86740a56073b 5316 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 143:86740a56073b 5317 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5318 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
AnnaBridge 143:86740a56073b 5319 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 143:86740a56073b 5320 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5321 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
AnnaBridge 143:86740a56073b 5322 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 143:86740a56073b 5323 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5324 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
AnnaBridge 143:86740a56073b 5325
AnnaBridge 143:86740a56073b 5326 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 143:86740a56073b 5327 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 143:86740a56073b 5328 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5329 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 143:86740a56073b 5330 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 143:86740a56073b 5331 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5332 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 143:86740a56073b 5333 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 143:86740a56073b 5334 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5335 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 143:86740a56073b 5336 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 143:86740a56073b 5337 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5338 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
AnnaBridge 143:86740a56073b 5339 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 143:86740a56073b 5340 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5341 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 143:86740a56073b 5342 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 143:86740a56073b 5343 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5344 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 143:86740a56073b 5345 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 143:86740a56073b 5346 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5347 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 143:86740a56073b 5348
AnnaBridge 143:86740a56073b 5349 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 143:86740a56073b 5350 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 143:86740a56073b 5351 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5352 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 143:86740a56073b 5353 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 143:86740a56073b 5354 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5355 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 143:86740a56073b 5356 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 143:86740a56073b 5357 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5358 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
AnnaBridge 143:86740a56073b 5359 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 143:86740a56073b 5360 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5361 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
AnnaBridge 143:86740a56073b 5362 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 143:86740a56073b 5363 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5364 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 143:86740a56073b 5365 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 143:86740a56073b 5366 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5367 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 143:86740a56073b 5368 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 143:86740a56073b 5369 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5370 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 143:86740a56073b 5371 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 143:86740a56073b 5372 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5373 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 143:86740a56073b 5374 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 143:86740a56073b 5375 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5376 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
AnnaBridge 143:86740a56073b 5377
AnnaBridge 143:86740a56073b 5378 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 143:86740a56073b 5379 #define SPI_DR_DR_Pos (0U)
AnnaBridge 143:86740a56073b 5380 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5381 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
AnnaBridge 143:86740a56073b 5382
AnnaBridge 143:86740a56073b 5383 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 143:86740a56073b 5384 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 143:86740a56073b 5385 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5386 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
AnnaBridge 143:86740a56073b 5387
AnnaBridge 143:86740a56073b 5388 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 143:86740a56073b 5389 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 143:86740a56073b 5390 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5391 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
AnnaBridge 143:86740a56073b 5392
AnnaBridge 143:86740a56073b 5393 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 143:86740a56073b 5394 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 143:86740a56073b 5395 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 5396 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
AnnaBridge 143:86740a56073b 5397
AnnaBridge 143:86740a56073b 5398 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 143:86740a56073b 5399 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 143:86740a56073b 5400 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5401 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 143:86740a56073b 5402 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 143:86740a56073b 5403 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 143:86740a56073b 5404 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 143:86740a56073b 5405 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5406 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5407 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 143:86740a56073b 5408 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5409 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 143:86740a56073b 5410 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 143:86740a56073b 5411 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 5412 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 143:86740a56073b 5413 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5414 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5415 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 143:86740a56073b 5416 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5417 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 143:86740a56073b 5418 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 143:86740a56073b 5419 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 5420 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 143:86740a56073b 5421 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5422 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5423 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 143:86740a56073b 5424 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5425 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 143:86740a56073b 5426 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 143:86740a56073b 5427 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5428 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 143:86740a56073b 5429 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
AnnaBridge 143:86740a56073b 5430 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5431 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
AnnaBridge 143:86740a56073b 5432 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 143:86740a56073b 5433 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 143:86740a56073b 5434 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 5435 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 143:86740a56073b 5436 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 143:86740a56073b 5437 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5438 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 143:86740a56073b 5439 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 143:86740a56073b 5440 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5441 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 143:86740a56073b 5442
AnnaBridge 143:86740a56073b 5443 /******************************************************************************/
AnnaBridge 143:86740a56073b 5444 /* */
AnnaBridge 143:86740a56073b 5445 /* System Configuration (SYSCFG) */
AnnaBridge 143:86740a56073b 5446 /* */
AnnaBridge 143:86740a56073b 5447 /******************************************************************************/
AnnaBridge 143:86740a56073b 5448 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
AnnaBridge 143:86740a56073b 5449 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
AnnaBridge 143:86740a56073b 5450 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 5451 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 143:86740a56073b 5452 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5453 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5454 #define SYSCFG_CFGR1_UFB_Pos (3U)
AnnaBridge 143:86740a56073b 5455 #define SYSCFG_CFGR1_UFB_Msk (0x1U << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5456 #define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
AnnaBridge 143:86740a56073b 5457 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
AnnaBridge 143:86740a56073b 5458 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 5459 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
AnnaBridge 143:86740a56073b 5460 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5461 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5462
AnnaBridge 143:86740a56073b 5463 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
AnnaBridge 143:86740a56073b 5464 #define SYSCFG_CFGR2_FWDISEN_Pos (0U)
AnnaBridge 143:86740a56073b 5465 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5466 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
AnnaBridge 143:86740a56073b 5467 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
AnnaBridge 143:86740a56073b 5468 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5469 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
AnnaBridge 143:86740a56073b 5470 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
AnnaBridge 143:86740a56073b 5471 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5472 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
AnnaBridge 143:86740a56073b 5473 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
AnnaBridge 143:86740a56073b 5474 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5475 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
AnnaBridge 143:86740a56073b 5476 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
AnnaBridge 143:86740a56073b 5477 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5478 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
AnnaBridge 143:86740a56073b 5479 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
AnnaBridge 143:86740a56073b 5480 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5481 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
AnnaBridge 143:86740a56073b 5482 #define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
AnnaBridge 143:86740a56073b 5483 #define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5484 #define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
AnnaBridge 143:86740a56073b 5485 #define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
AnnaBridge 143:86740a56073b 5486 #define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5487 #define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
AnnaBridge 143:86740a56073b 5488
AnnaBridge 143:86740a56073b 5489 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 143:86740a56073b 5490 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 143:86740a56073b 5491 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5492 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
AnnaBridge 143:86740a56073b 5493 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 143:86740a56073b 5494 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 5495 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
AnnaBridge 143:86740a56073b 5496 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 143:86740a56073b 5497 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5498 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
AnnaBridge 143:86740a56073b 5499 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 143:86740a56073b 5500 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 5501 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
AnnaBridge 143:86740a56073b 5502
AnnaBridge 143:86740a56073b 5503 /**
AnnaBridge 143:86740a56073b 5504 * @brief EXTI0 configuration
AnnaBridge 143:86740a56073b 5505 */
AnnaBridge 143:86740a56073b 5506 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
AnnaBridge 143:86740a56073b 5507 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
AnnaBridge 143:86740a56073b 5508 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
AnnaBridge 143:86740a56073b 5509 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
AnnaBridge 143:86740a56073b 5510 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
AnnaBridge 143:86740a56073b 5511 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
AnnaBridge 143:86740a56073b 5512
AnnaBridge 143:86740a56073b 5513 /**
AnnaBridge 143:86740a56073b 5514 * @brief EXTI1 configuration
AnnaBridge 143:86740a56073b 5515 */
AnnaBridge 143:86740a56073b 5516 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
AnnaBridge 143:86740a56073b 5517 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
AnnaBridge 143:86740a56073b 5518 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
AnnaBridge 143:86740a56073b 5519 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
AnnaBridge 143:86740a56073b 5520 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
AnnaBridge 143:86740a56073b 5521 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
AnnaBridge 143:86740a56073b 5522
AnnaBridge 143:86740a56073b 5523 /**
AnnaBridge 143:86740a56073b 5524 * @brief EXTI2 configuration
AnnaBridge 143:86740a56073b 5525 */
AnnaBridge 143:86740a56073b 5526 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
AnnaBridge 143:86740a56073b 5527 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
AnnaBridge 143:86740a56073b 5528 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
AnnaBridge 143:86740a56073b 5529 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
AnnaBridge 143:86740a56073b 5530 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
AnnaBridge 143:86740a56073b 5531
AnnaBridge 143:86740a56073b 5532 /**
AnnaBridge 143:86740a56073b 5533 * @brief EXTI3 configuration
AnnaBridge 143:86740a56073b 5534 */
AnnaBridge 143:86740a56073b 5535 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
AnnaBridge 143:86740a56073b 5536 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
AnnaBridge 143:86740a56073b 5537 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
AnnaBridge 143:86740a56073b 5538 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
AnnaBridge 143:86740a56073b 5539 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
AnnaBridge 143:86740a56073b 5540
AnnaBridge 143:86740a56073b 5541 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
AnnaBridge 143:86740a56073b 5542 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 143:86740a56073b 5543 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5544 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
AnnaBridge 143:86740a56073b 5545 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 143:86740a56073b 5546 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 5547 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
AnnaBridge 143:86740a56073b 5548 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 143:86740a56073b 5549 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5550 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
AnnaBridge 143:86740a56073b 5551 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 143:86740a56073b 5552 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 5553 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
AnnaBridge 143:86740a56073b 5554
AnnaBridge 143:86740a56073b 5555 /**
AnnaBridge 143:86740a56073b 5556 * @brief EXTI4 configuration
AnnaBridge 143:86740a56073b 5557 */
AnnaBridge 143:86740a56073b 5558 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
AnnaBridge 143:86740a56073b 5559 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
AnnaBridge 143:86740a56073b 5560 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
AnnaBridge 143:86740a56073b 5561 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
AnnaBridge 143:86740a56073b 5562 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
AnnaBridge 143:86740a56073b 5563
AnnaBridge 143:86740a56073b 5564 /**
AnnaBridge 143:86740a56073b 5565 * @brief EXTI5 configuration
AnnaBridge 143:86740a56073b 5566 */
AnnaBridge 143:86740a56073b 5567 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
AnnaBridge 143:86740a56073b 5568 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
AnnaBridge 143:86740a56073b 5569 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
AnnaBridge 143:86740a56073b 5570 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
AnnaBridge 143:86740a56073b 5571 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
AnnaBridge 143:86740a56073b 5572
AnnaBridge 143:86740a56073b 5573 /**
AnnaBridge 143:86740a56073b 5574 * @brief EXTI6 configuration
AnnaBridge 143:86740a56073b 5575 */
AnnaBridge 143:86740a56073b 5576 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
AnnaBridge 143:86740a56073b 5577 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
AnnaBridge 143:86740a56073b 5578 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
AnnaBridge 143:86740a56073b 5579 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
AnnaBridge 143:86740a56073b 5580 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
AnnaBridge 143:86740a56073b 5581
AnnaBridge 143:86740a56073b 5582 /**
AnnaBridge 143:86740a56073b 5583 * @brief EXTI7 configuration
AnnaBridge 143:86740a56073b 5584 */
AnnaBridge 143:86740a56073b 5585 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
AnnaBridge 143:86740a56073b 5586 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
AnnaBridge 143:86740a56073b 5587 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
AnnaBridge 143:86740a56073b 5588 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
AnnaBridge 143:86740a56073b 5589 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
AnnaBridge 143:86740a56073b 5590
AnnaBridge 143:86740a56073b 5591 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
AnnaBridge 143:86740a56073b 5592 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 143:86740a56073b 5593 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5594 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
AnnaBridge 143:86740a56073b 5595 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 143:86740a56073b 5596 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 5597 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
AnnaBridge 143:86740a56073b 5598 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 143:86740a56073b 5599 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5600 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
AnnaBridge 143:86740a56073b 5601 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 143:86740a56073b 5602 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 5603 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
AnnaBridge 143:86740a56073b 5604
AnnaBridge 143:86740a56073b 5605 /**
AnnaBridge 143:86740a56073b 5606 * @brief EXTI8 configuration
AnnaBridge 143:86740a56073b 5607 */
AnnaBridge 143:86740a56073b 5608 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
AnnaBridge 143:86740a56073b 5609 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
AnnaBridge 143:86740a56073b 5610 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
AnnaBridge 143:86740a56073b 5611 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
AnnaBridge 143:86740a56073b 5612 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
AnnaBridge 143:86740a56073b 5613
AnnaBridge 143:86740a56073b 5614 /**
AnnaBridge 143:86740a56073b 5615 * @brief EXTI9 configuration
AnnaBridge 143:86740a56073b 5616 */
AnnaBridge 143:86740a56073b 5617 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
AnnaBridge 143:86740a56073b 5618 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
AnnaBridge 143:86740a56073b 5619 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
AnnaBridge 143:86740a56073b 5620 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
AnnaBridge 143:86740a56073b 5621 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
AnnaBridge 143:86740a56073b 5622 #define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
AnnaBridge 143:86740a56073b 5623
AnnaBridge 143:86740a56073b 5624 /**
AnnaBridge 143:86740a56073b 5625 * @brief EXTI10 configuration
AnnaBridge 143:86740a56073b 5626 */
AnnaBridge 143:86740a56073b 5627 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
AnnaBridge 143:86740a56073b 5628 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
AnnaBridge 143:86740a56073b 5629 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
AnnaBridge 143:86740a56073b 5630 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
AnnaBridge 143:86740a56073b 5631 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
AnnaBridge 143:86740a56073b 5632 #define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
AnnaBridge 143:86740a56073b 5633
AnnaBridge 143:86740a56073b 5634 /**
AnnaBridge 143:86740a56073b 5635 * @brief EXTI11 configuration
AnnaBridge 143:86740a56073b 5636 */
AnnaBridge 143:86740a56073b 5637 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
AnnaBridge 143:86740a56073b 5638 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
AnnaBridge 143:86740a56073b 5639 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
AnnaBridge 143:86740a56073b 5640 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
AnnaBridge 143:86740a56073b 5641 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
AnnaBridge 143:86740a56073b 5642
AnnaBridge 143:86740a56073b 5643 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
AnnaBridge 143:86740a56073b 5644 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 143:86740a56073b 5645 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 5646 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
AnnaBridge 143:86740a56073b 5647 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 143:86740a56073b 5648 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 5649 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
AnnaBridge 143:86740a56073b 5650 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 143:86740a56073b 5651 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5652 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
AnnaBridge 143:86740a56073b 5653 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 143:86740a56073b 5654 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 5655 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
AnnaBridge 143:86740a56073b 5656
AnnaBridge 143:86740a56073b 5657 /**
AnnaBridge 143:86740a56073b 5658 * @brief EXTI12 configuration
AnnaBridge 143:86740a56073b 5659 */
AnnaBridge 143:86740a56073b 5660 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
AnnaBridge 143:86740a56073b 5661 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
AnnaBridge 143:86740a56073b 5662 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
AnnaBridge 143:86740a56073b 5663 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
AnnaBridge 143:86740a56073b 5664 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
AnnaBridge 143:86740a56073b 5665
AnnaBridge 143:86740a56073b 5666 /**
AnnaBridge 143:86740a56073b 5667 * @brief EXTI13 configuration
AnnaBridge 143:86740a56073b 5668 */
AnnaBridge 143:86740a56073b 5669 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
AnnaBridge 143:86740a56073b 5670 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
AnnaBridge 143:86740a56073b 5671 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
AnnaBridge 143:86740a56073b 5672 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
AnnaBridge 143:86740a56073b 5673 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
AnnaBridge 143:86740a56073b 5674
AnnaBridge 143:86740a56073b 5675 /**
AnnaBridge 143:86740a56073b 5676 * @brief EXTI14 configuration
AnnaBridge 143:86740a56073b 5677 */
AnnaBridge 143:86740a56073b 5678 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
AnnaBridge 143:86740a56073b 5679 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
AnnaBridge 143:86740a56073b 5680 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
AnnaBridge 143:86740a56073b 5681 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
AnnaBridge 143:86740a56073b 5682 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
AnnaBridge 143:86740a56073b 5683
AnnaBridge 143:86740a56073b 5684 /**
AnnaBridge 143:86740a56073b 5685 * @brief EXTI15 configuration
AnnaBridge 143:86740a56073b 5686 */
AnnaBridge 143:86740a56073b 5687 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
AnnaBridge 143:86740a56073b 5688 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
AnnaBridge 143:86740a56073b 5689 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
AnnaBridge 143:86740a56073b 5690 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
AnnaBridge 143:86740a56073b 5691 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
AnnaBridge 143:86740a56073b 5692
AnnaBridge 143:86740a56073b 5693
AnnaBridge 143:86740a56073b 5694 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
AnnaBridge 143:86740a56073b 5695 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
AnnaBridge 143:86740a56073b 5696 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
AnnaBridge 143:86740a56073b 5697 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
AnnaBridge 143:86740a56073b 5698 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5699 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5700 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
AnnaBridge 143:86740a56073b 5701 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5702 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
AnnaBridge 143:86740a56073b 5703 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
AnnaBridge 143:86740a56073b 5704 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5705 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
AnnaBridge 143:86740a56073b 5706 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
AnnaBridge 143:86740a56073b 5707 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5708 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
AnnaBridge 143:86740a56073b 5709 #define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
AnnaBridge 143:86740a56073b 5710 #define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5711 #define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
AnnaBridge 143:86740a56073b 5712 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
AnnaBridge 143:86740a56073b 5713 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 5714 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
AnnaBridge 143:86740a56073b 5715 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
AnnaBridge 143:86740a56073b 5716 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 5717 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
AnnaBridge 143:86740a56073b 5718
AnnaBridge 143:86740a56073b 5719 /* Legacy defines */
AnnaBridge 143:86740a56073b 5720
AnnaBridge 143:86740a56073b 5721 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
AnnaBridge 143:86740a56073b 5722 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
AnnaBridge 143:86740a56073b 5723 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
AnnaBridge 143:86740a56073b 5724 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5725 #define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5726 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5727 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5728 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5729 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
AnnaBridge 143:86740a56073b 5730
AnnaBridge 143:86740a56073b 5731 /******************************************************************************/
AnnaBridge 143:86740a56073b 5732 /* */
AnnaBridge 143:86740a56073b 5733 /* Timers (TIM) */
AnnaBridge 143:86740a56073b 5734 /* */
AnnaBridge 143:86740a56073b 5735 /******************************************************************************/
AnnaBridge 143:86740a56073b 5736 /*
AnnaBridge 143:86740a56073b 5737 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
AnnaBridge 143:86740a56073b 5738 */
AnnaBridge 143:86740a56073b 5739 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
AnnaBridge 143:86740a56073b 5740 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
AnnaBridge 143:86740a56073b 5741 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
AnnaBridge 143:86740a56073b 5742 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
AnnaBridge 143:86740a56073b 5743 #else
AnnaBridge 143:86740a56073b 5744 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
AnnaBridge 143:86740a56073b 5745 #endif
AnnaBridge 143:86740a56073b 5746
AnnaBridge 143:86740a56073b 5747 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 143:86740a56073b 5748 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 143:86740a56073b 5749 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5750 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 143:86740a56073b 5751 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 143:86740a56073b 5752 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5753 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 143:86740a56073b 5754 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 143:86740a56073b 5755 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5756 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 143:86740a56073b 5757 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 143:86740a56073b 5758 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5759 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 143:86740a56073b 5760 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 143:86740a56073b 5761 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5762 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 143:86740a56073b 5763
AnnaBridge 143:86740a56073b 5764 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 143:86740a56073b 5765 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 143:86740a56073b 5766 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 143:86740a56073b 5767 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5768 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5769
AnnaBridge 143:86740a56073b 5770 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 143:86740a56073b 5771 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5772 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 143:86740a56073b 5773
AnnaBridge 143:86740a56073b 5774 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 143:86740a56073b 5775 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 5776 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 143:86740a56073b 5777 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5778 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5779
AnnaBridge 143:86740a56073b 5780 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 143:86740a56073b 5781 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 143:86740a56073b 5782 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5783 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 143:86740a56073b 5784
AnnaBridge 143:86740a56073b 5785 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 143:86740a56073b 5786 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 5787 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 143:86740a56073b 5788 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5789 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5790 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5791
AnnaBridge 143:86740a56073b 5792 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 143:86740a56073b 5793 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5794 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 143:86740a56073b 5795
AnnaBridge 143:86740a56073b 5796 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 143:86740a56073b 5797 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 143:86740a56073b 5798 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 5799 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 143:86740a56073b 5800 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5801 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5802 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5803
AnnaBridge 143:86740a56073b 5804 #define TIM_SMCR_OCCS_Pos (3U)
AnnaBridge 143:86740a56073b 5805 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5806 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
AnnaBridge 143:86740a56073b 5807
AnnaBridge 143:86740a56073b 5808 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 143:86740a56073b 5809 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 5810 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 143:86740a56073b 5811 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5812 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5813 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5814
AnnaBridge 143:86740a56073b 5815 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 143:86740a56073b 5816 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5817 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 143:86740a56073b 5818
AnnaBridge 143:86740a56073b 5819 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 143:86740a56073b 5820 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 143:86740a56073b 5821 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 143:86740a56073b 5822 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5823 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5824 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5825 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5826
AnnaBridge 143:86740a56073b 5827 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 143:86740a56073b 5828 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 5829 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 143:86740a56073b 5830 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5831 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5832
AnnaBridge 143:86740a56073b 5833 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 143:86740a56073b 5834 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5835 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 143:86740a56073b 5836 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 143:86740a56073b 5837 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5838 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 143:86740a56073b 5839
AnnaBridge 143:86740a56073b 5840 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 143:86740a56073b 5841 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 143:86740a56073b 5842 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5843 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 143:86740a56073b 5844 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 143:86740a56073b 5845 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5846 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 143:86740a56073b 5847 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 143:86740a56073b 5848 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5849 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 143:86740a56073b 5850 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 143:86740a56073b 5851 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5852 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 143:86740a56073b 5853 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 143:86740a56073b 5854 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5855 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 143:86740a56073b 5856 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 143:86740a56073b 5857 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5858 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 143:86740a56073b 5859 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 143:86740a56073b 5860 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5861 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 143:86740a56073b 5862 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 143:86740a56073b 5863 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5864 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 143:86740a56073b 5865 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 143:86740a56073b 5866 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5867 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 143:86740a56073b 5868 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 143:86740a56073b 5869 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5870 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 143:86740a56073b 5871 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 143:86740a56073b 5872 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5873 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 143:86740a56073b 5874 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 143:86740a56073b 5875 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5876 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 143:86740a56073b 5877
AnnaBridge 143:86740a56073b 5878 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 143:86740a56073b 5879 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 143:86740a56073b 5880 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5881 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 143:86740a56073b 5882 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 143:86740a56073b 5883 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5884 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 143:86740a56073b 5885 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 143:86740a56073b 5886 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5887 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 143:86740a56073b 5888 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 143:86740a56073b 5889 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5890 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 143:86740a56073b 5891 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 143:86740a56073b 5892 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5893 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 143:86740a56073b 5894 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 143:86740a56073b 5895 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5896 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 143:86740a56073b 5897 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 143:86740a56073b 5898 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5899 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 143:86740a56073b 5900 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 143:86740a56073b 5901 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5902 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 143:86740a56073b 5903 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 143:86740a56073b 5904 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5905 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 143:86740a56073b 5906 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 143:86740a56073b 5907 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5908 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 143:86740a56073b 5909
AnnaBridge 143:86740a56073b 5910 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 143:86740a56073b 5911 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 143:86740a56073b 5912 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5913 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 143:86740a56073b 5914 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 143:86740a56073b 5915 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5916 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 143:86740a56073b 5917 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 143:86740a56073b 5918 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5919 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 143:86740a56073b 5920 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 143:86740a56073b 5921 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5922 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 143:86740a56073b 5923 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 143:86740a56073b 5924 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5925 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 143:86740a56073b 5926 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 143:86740a56073b 5927 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5928 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 143:86740a56073b 5929
AnnaBridge 143:86740a56073b 5930 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 143:86740a56073b 5931 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 143:86740a56073b 5932 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 5933 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 143:86740a56073b 5934 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 5935 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 5936
AnnaBridge 143:86740a56073b 5937 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 143:86740a56073b 5938 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5939 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 143:86740a56073b 5940 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 143:86740a56073b 5941 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5942 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 143:86740a56073b 5943
AnnaBridge 143:86740a56073b 5944 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 143:86740a56073b 5945 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 5946 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 143:86740a56073b 5947 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5948 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5949 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5950
AnnaBridge 143:86740a56073b 5951 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 143:86740a56073b 5952 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5953 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 143:86740a56073b 5954
AnnaBridge 143:86740a56073b 5955 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 143:86740a56073b 5956 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 5957 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 143:86740a56073b 5958 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 5959 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 5960
AnnaBridge 143:86740a56073b 5961 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 143:86740a56073b 5962 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5963 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 143:86740a56073b 5964 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 143:86740a56073b 5965 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 5966 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 143:86740a56073b 5967
AnnaBridge 143:86740a56073b 5968 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 143:86740a56073b 5969 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 5970 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 143:86740a56073b 5971 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 5972 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 5973 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 5974
AnnaBridge 143:86740a56073b 5975 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 143:86740a56073b 5976 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 5977 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 143:86740a56073b 5978
AnnaBridge 143:86740a56073b 5979 /*----------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 5980
AnnaBridge 143:86740a56073b 5981 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 143:86740a56073b 5982 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 5983 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 143:86740a56073b 5984 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 5985 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 5986
AnnaBridge 143:86740a56073b 5987 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 143:86740a56073b 5988 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 5989 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 143:86740a56073b 5990 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 5991 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 5992 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 5993 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 5994
AnnaBridge 143:86740a56073b 5995 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 143:86740a56073b 5996 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 5997 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 143:86740a56073b 5998 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 5999 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6000
AnnaBridge 143:86740a56073b 6001 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 143:86740a56073b 6002 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 6003 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 143:86740a56073b 6004 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6005 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6006 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6007 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6008
AnnaBridge 143:86740a56073b 6009 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 143:86740a56073b 6010 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 143:86740a56073b 6011 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 6012 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 143:86740a56073b 6013 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6014 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6015
AnnaBridge 143:86740a56073b 6016 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 143:86740a56073b 6017 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6018 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 143:86740a56073b 6019 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 143:86740a56073b 6020 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6021 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 143:86740a56073b 6022
AnnaBridge 143:86740a56073b 6023 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 143:86740a56073b 6024 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 143:86740a56073b 6025 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 143:86740a56073b 6026 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6027 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6028 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6029
AnnaBridge 143:86740a56073b 6030 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 143:86740a56073b 6031 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6032 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 143:86740a56073b 6033
AnnaBridge 143:86740a56073b 6034 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 143:86740a56073b 6035 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 143:86740a56073b 6036 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 143:86740a56073b 6037 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6038 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6039
AnnaBridge 143:86740a56073b 6040 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 143:86740a56073b 6041 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6042 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 143:86740a56073b 6043 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 143:86740a56073b 6044 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6045 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 143:86740a56073b 6046
AnnaBridge 143:86740a56073b 6047 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 143:86740a56073b 6048 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 6049 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 143:86740a56073b 6050 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6051 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6052 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6053
AnnaBridge 143:86740a56073b 6054 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 143:86740a56073b 6055 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6056 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 143:86740a56073b 6057
AnnaBridge 143:86740a56073b 6058 /*----------------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 6059
AnnaBridge 143:86740a56073b 6060 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 143:86740a56073b 6061 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 6062 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 143:86740a56073b 6063 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6064 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6065
AnnaBridge 143:86740a56073b 6066 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 143:86740a56073b 6067 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 143:86740a56073b 6068 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 143:86740a56073b 6069 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6070 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6071 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6072 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6073
AnnaBridge 143:86740a56073b 6074 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 143:86740a56073b 6075 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 143:86740a56073b 6076 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 143:86740a56073b 6077 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6078 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6079
AnnaBridge 143:86740a56073b 6080 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 143:86740a56073b 6081 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 143:86740a56073b 6082 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 143:86740a56073b 6083 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6084 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6085 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6086 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6087
AnnaBridge 143:86740a56073b 6088 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 143:86740a56073b 6089 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 143:86740a56073b 6090 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6091 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 143:86740a56073b 6092 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 143:86740a56073b 6093 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6094 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 143:86740a56073b 6095 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 143:86740a56073b 6096 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6097 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 143:86740a56073b 6098 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 143:86740a56073b 6099 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6100 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 143:86740a56073b 6101 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 143:86740a56073b 6102 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6103 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 143:86740a56073b 6104 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 143:86740a56073b 6105 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6106 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 143:86740a56073b 6107 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 143:86740a56073b 6108 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6109 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 143:86740a56073b 6110 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 143:86740a56073b 6111 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6112 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 143:86740a56073b 6113 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 143:86740a56073b 6114 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6115 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 143:86740a56073b 6116 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 143:86740a56073b 6117 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6118 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 143:86740a56073b 6119 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 143:86740a56073b 6120 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6121 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 143:86740a56073b 6122 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 143:86740a56073b 6123 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6124 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 143:86740a56073b 6125
AnnaBridge 143:86740a56073b 6126 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 143:86740a56073b 6127 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 143:86740a56073b 6128 #define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6129 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 143:86740a56073b 6130
AnnaBridge 143:86740a56073b 6131 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 143:86740a56073b 6132 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 143:86740a56073b 6133 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6134 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 143:86740a56073b 6135
AnnaBridge 143:86740a56073b 6136 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 143:86740a56073b 6137 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 143:86740a56073b 6138 #define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6139 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 143:86740a56073b 6140
AnnaBridge 143:86740a56073b 6141 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 143:86740a56073b 6142 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 143:86740a56073b 6143 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6144 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 143:86740a56073b 6145
AnnaBridge 143:86740a56073b 6146 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 143:86740a56073b 6147 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 143:86740a56073b 6148 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6149 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 143:86740a56073b 6150
AnnaBridge 143:86740a56073b 6151 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 143:86740a56073b 6152 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 143:86740a56073b 6153 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6154 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 143:86740a56073b 6155
AnnaBridge 143:86740a56073b 6156 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 143:86740a56073b 6157 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 143:86740a56073b 6158 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6159 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 143:86740a56073b 6160
AnnaBridge 143:86740a56073b 6161 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 143:86740a56073b 6162 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 143:86740a56073b 6163 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 143:86740a56073b 6164 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 143:86740a56073b 6165 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6166 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6167 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6168 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6169 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6170
AnnaBridge 143:86740a56073b 6171 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 143:86740a56073b 6172 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 143:86740a56073b 6173 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 143:86740a56073b 6174 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6175 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6176 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6177 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6178 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6179
AnnaBridge 143:86740a56073b 6180 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 143:86740a56073b 6181 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 143:86740a56073b 6182 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 143:86740a56073b 6183 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 143:86740a56073b 6184
AnnaBridge 143:86740a56073b 6185 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 143:86740a56073b 6186 #define TIM2_OR_ETR_RMP_Pos (0U)
AnnaBridge 143:86740a56073b 6187 #define TIM2_OR_ETR_RMP_Msk (0x7U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
AnnaBridge 143:86740a56073b 6188 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
AnnaBridge 143:86740a56073b 6189 #define TIM2_OR_ETR_RMP_0 (0x1U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6190 #define TIM2_OR_ETR_RMP_1 (0x2U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6191 #define TIM2_OR_ETR_RMP_2 (0x4U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6192 #define TIM2_OR_TI4_RMP_Pos (3U)
AnnaBridge 143:86740a56073b 6193 #define TIM2_OR_TI4_RMP_Msk (0x3U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
AnnaBridge 143:86740a56073b 6194 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
AnnaBridge 143:86740a56073b 6195 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6196 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6197
AnnaBridge 143:86740a56073b 6198 #define TIM21_OR_ETR_RMP_Pos (0U)
AnnaBridge 143:86740a56073b 6199 #define TIM21_OR_ETR_RMP_Msk (0x3U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 6200 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
AnnaBridge 143:86740a56073b 6201 #define TIM21_OR_ETR_RMP_0 (0x1U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6202 #define TIM21_OR_ETR_RMP_1 (0x2U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6203 #define TIM21_OR_TI1_RMP_Pos (2U)
AnnaBridge 143:86740a56073b 6204 #define TIM21_OR_TI1_RMP_Msk (0x7U << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
AnnaBridge 143:86740a56073b 6205 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
AnnaBridge 143:86740a56073b 6206 #define TIM21_OR_TI1_RMP_0 (0x1U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6207 #define TIM21_OR_TI1_RMP_1 (0x2U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6208 #define TIM21_OR_TI1_RMP_2 (0x4U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6209 #define TIM21_OR_TI2_RMP_Pos (5U)
AnnaBridge 143:86740a56073b 6210 #define TIM21_OR_TI2_RMP_Msk (0x1U << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6211 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
AnnaBridge 143:86740a56073b 6212
AnnaBridge 143:86740a56073b 6213 #define TIM22_OR_ETR_RMP_Pos (0U)
AnnaBridge 143:86740a56073b 6214 #define TIM22_OR_ETR_RMP_Msk (0x3U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 6215 #define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
AnnaBridge 143:86740a56073b 6216 #define TIM22_OR_ETR_RMP_0 (0x1U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6217 #define TIM22_OR_ETR_RMP_1 (0x2U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6218 #define TIM22_OR_TI1_RMP_Pos (2U)
AnnaBridge 143:86740a56073b 6219 #define TIM22_OR_TI1_RMP_Msk (0x3U << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
AnnaBridge 143:86740a56073b 6220 #define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
AnnaBridge 143:86740a56073b 6221 #define TIM22_OR_TI1_RMP_0 (0x1U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6222 #define TIM22_OR_TI1_RMP_1 (0x2U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6223
AnnaBridge 143:86740a56073b 6224 #define TIM3_OR_ETR_RMP_Pos (0U)
AnnaBridge 143:86740a56073b 6225 #define TIM3_OR_ETR_RMP_Msk (0x3U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 143:86740a56073b 6226 #define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
AnnaBridge 143:86740a56073b 6227 #define TIM3_OR_ETR_RMP_0 (0x1U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6228 #define TIM3_OR_ETR_RMP_1 (0x2U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6229 #define TIM3_OR_TI1_RMP_Pos (2U)
AnnaBridge 143:86740a56073b 6230 #define TIM3_OR_TI1_RMP_Msk (0x1U << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6231 #define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
AnnaBridge 143:86740a56073b 6232 #define TIM3_OR_TI2_RMP_Pos (3U)
AnnaBridge 143:86740a56073b 6233 #define TIM3_OR_TI2_RMP_Msk (0x1U << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6234 #define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
AnnaBridge 143:86740a56073b 6235 #define TIM3_OR_TI4_RMP_Pos (4U)
AnnaBridge 143:86740a56073b 6236 #define TIM3_OR_TI4_RMP_Msk (0x1U << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6237 #define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
AnnaBridge 143:86740a56073b 6238
AnnaBridge 143:86740a56073b 6239
AnnaBridge 143:86740a56073b 6240 /******************************************************************************/
AnnaBridge 143:86740a56073b 6241 /* */
AnnaBridge 143:86740a56073b 6242 /* Touch Sensing Controller (TSC) */
AnnaBridge 143:86740a56073b 6243 /* */
AnnaBridge 143:86740a56073b 6244 /******************************************************************************/
AnnaBridge 143:86740a56073b 6245 /******************* Bit definition for TSC_CR register *********************/
AnnaBridge 143:86740a56073b 6246 #define TSC_CR_TSCE_Pos (0U)
AnnaBridge 143:86740a56073b 6247 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6248 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
AnnaBridge 143:86740a56073b 6249 #define TSC_CR_START_Pos (1U)
AnnaBridge 143:86740a56073b 6250 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6251 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
AnnaBridge 143:86740a56073b 6252 #define TSC_CR_AM_Pos (2U)
AnnaBridge 143:86740a56073b 6253 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6254 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
AnnaBridge 143:86740a56073b 6255 #define TSC_CR_SYNCPOL_Pos (3U)
AnnaBridge 143:86740a56073b 6256 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6257 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
AnnaBridge 143:86740a56073b 6258 #define TSC_CR_IODEF_Pos (4U)
AnnaBridge 143:86740a56073b 6259 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6260 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
AnnaBridge 143:86740a56073b 6261
AnnaBridge 143:86740a56073b 6262 #define TSC_CR_MCV_Pos (5U)
AnnaBridge 143:86740a56073b 6263 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
AnnaBridge 143:86740a56073b 6264 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
AnnaBridge 143:86740a56073b 6265 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6266 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6267 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6268
AnnaBridge 143:86740a56073b 6269 #define TSC_CR_PGPSC_Pos (12U)
AnnaBridge 143:86740a56073b 6270 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
AnnaBridge 143:86740a56073b 6271 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
AnnaBridge 143:86740a56073b 6272 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6273 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6274 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6275
AnnaBridge 143:86740a56073b 6276 #define TSC_CR_SSPSC_Pos (15U)
AnnaBridge 143:86740a56073b 6277 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6278 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
AnnaBridge 143:86740a56073b 6279 #define TSC_CR_SSE_Pos (16U)
AnnaBridge 143:86740a56073b 6280 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6281 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
AnnaBridge 143:86740a56073b 6282
AnnaBridge 143:86740a56073b 6283 #define TSC_CR_SSD_Pos (17U)
AnnaBridge 143:86740a56073b 6284 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
AnnaBridge 143:86740a56073b 6285 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
AnnaBridge 143:86740a56073b 6286 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6287 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6288 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6289 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6290 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6291 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6292 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6293
AnnaBridge 143:86740a56073b 6294 #define TSC_CR_CTPL_Pos (24U)
AnnaBridge 143:86740a56073b 6295 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
AnnaBridge 143:86740a56073b 6296 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
AnnaBridge 143:86740a56073b 6297 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6298 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6299 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6300 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6301
AnnaBridge 143:86740a56073b 6302 #define TSC_CR_CTPH_Pos (28U)
AnnaBridge 143:86740a56073b 6303 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
AnnaBridge 143:86740a56073b 6304 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
AnnaBridge 143:86740a56073b 6305 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6306 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 6307 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 6308 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 6309
AnnaBridge 143:86740a56073b 6310 /******************* Bit definition for TSC_IER register ********************/
AnnaBridge 143:86740a56073b 6311 #define TSC_IER_EOAIE_Pos (0U)
AnnaBridge 143:86740a56073b 6312 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6313 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
AnnaBridge 143:86740a56073b 6314 #define TSC_IER_MCEIE_Pos (1U)
AnnaBridge 143:86740a56073b 6315 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6316 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
AnnaBridge 143:86740a56073b 6317
AnnaBridge 143:86740a56073b 6318 /******************* Bit definition for TSC_ICR register ********************/
AnnaBridge 143:86740a56073b 6319 #define TSC_ICR_EOAIC_Pos (0U)
AnnaBridge 143:86740a56073b 6320 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6321 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
AnnaBridge 143:86740a56073b 6322 #define TSC_ICR_MCEIC_Pos (1U)
AnnaBridge 143:86740a56073b 6323 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6324 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
AnnaBridge 143:86740a56073b 6325
AnnaBridge 143:86740a56073b 6326 /******************* Bit definition for TSC_ISR register ********************/
AnnaBridge 143:86740a56073b 6327 #define TSC_ISR_EOAF_Pos (0U)
AnnaBridge 143:86740a56073b 6328 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6329 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
AnnaBridge 143:86740a56073b 6330 #define TSC_ISR_MCEF_Pos (1U)
AnnaBridge 143:86740a56073b 6331 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6332 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
AnnaBridge 143:86740a56073b 6333
AnnaBridge 143:86740a56073b 6334 /******************* Bit definition for TSC_IOHCR register ******************/
AnnaBridge 143:86740a56073b 6335 #define TSC_IOHCR_G1_IO1_Pos (0U)
AnnaBridge 143:86740a56073b 6336 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6337 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6338 #define TSC_IOHCR_G1_IO2_Pos (1U)
AnnaBridge 143:86740a56073b 6339 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6340 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6341 #define TSC_IOHCR_G1_IO3_Pos (2U)
AnnaBridge 143:86740a56073b 6342 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6343 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6344 #define TSC_IOHCR_G1_IO4_Pos (3U)
AnnaBridge 143:86740a56073b 6345 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6346 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6347 #define TSC_IOHCR_G2_IO1_Pos (4U)
AnnaBridge 143:86740a56073b 6348 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6349 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6350 #define TSC_IOHCR_G2_IO2_Pos (5U)
AnnaBridge 143:86740a56073b 6351 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6352 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6353 #define TSC_IOHCR_G2_IO3_Pos (6U)
AnnaBridge 143:86740a56073b 6354 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6355 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6356 #define TSC_IOHCR_G2_IO4_Pos (7U)
AnnaBridge 143:86740a56073b 6357 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6358 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6359 #define TSC_IOHCR_G3_IO1_Pos (8U)
AnnaBridge 143:86740a56073b 6360 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6361 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6362 #define TSC_IOHCR_G3_IO2_Pos (9U)
AnnaBridge 143:86740a56073b 6363 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6364 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6365 #define TSC_IOHCR_G3_IO3_Pos (10U)
AnnaBridge 143:86740a56073b 6366 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6367 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6368 #define TSC_IOHCR_G3_IO4_Pos (11U)
AnnaBridge 143:86740a56073b 6369 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6370 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6371 #define TSC_IOHCR_G4_IO1_Pos (12U)
AnnaBridge 143:86740a56073b 6372 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6373 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6374 #define TSC_IOHCR_G4_IO2_Pos (13U)
AnnaBridge 143:86740a56073b 6375 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6376 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6377 #define TSC_IOHCR_G4_IO3_Pos (14U)
AnnaBridge 143:86740a56073b 6378 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6379 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6380 #define TSC_IOHCR_G4_IO4_Pos (15U)
AnnaBridge 143:86740a56073b 6381 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6382 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6383 #define TSC_IOHCR_G5_IO1_Pos (16U)
AnnaBridge 143:86740a56073b 6384 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6385 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6386 #define TSC_IOHCR_G5_IO2_Pos (17U)
AnnaBridge 143:86740a56073b 6387 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6388 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6389 #define TSC_IOHCR_G5_IO3_Pos (18U)
AnnaBridge 143:86740a56073b 6390 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6391 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6392 #define TSC_IOHCR_G5_IO4_Pos (19U)
AnnaBridge 143:86740a56073b 6393 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6394 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6395 #define TSC_IOHCR_G6_IO1_Pos (20U)
AnnaBridge 143:86740a56073b 6396 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6397 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6398 #define TSC_IOHCR_G6_IO2_Pos (21U)
AnnaBridge 143:86740a56073b 6399 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6400 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6401 #define TSC_IOHCR_G6_IO3_Pos (22U)
AnnaBridge 143:86740a56073b 6402 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6403 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6404 #define TSC_IOHCR_G6_IO4_Pos (23U)
AnnaBridge 143:86740a56073b 6405 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6406 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6407 #define TSC_IOHCR_G7_IO1_Pos (24U)
AnnaBridge 143:86740a56073b 6408 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6409 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6410 #define TSC_IOHCR_G7_IO2_Pos (25U)
AnnaBridge 143:86740a56073b 6411 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6412 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6413 #define TSC_IOHCR_G7_IO3_Pos (26U)
AnnaBridge 143:86740a56073b 6414 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6415 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6416 #define TSC_IOHCR_G7_IO4_Pos (27U)
AnnaBridge 143:86740a56073b 6417 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6418 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6419 #define TSC_IOHCR_G8_IO1_Pos (28U)
AnnaBridge 143:86740a56073b 6420 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6421 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6422 #define TSC_IOHCR_G8_IO2_Pos (29U)
AnnaBridge 143:86740a56073b 6423 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 6424 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6425 #define TSC_IOHCR_G8_IO3_Pos (30U)
AnnaBridge 143:86740a56073b 6426 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 6427 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6428 #define TSC_IOHCR_G8_IO4_Pos (31U)
AnnaBridge 143:86740a56073b 6429 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 6430 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
AnnaBridge 143:86740a56073b 6431
AnnaBridge 143:86740a56073b 6432 /******************* Bit definition for TSC_IOASCR register *****************/
AnnaBridge 143:86740a56073b 6433 #define TSC_IOASCR_G1_IO1_Pos (0U)
AnnaBridge 143:86740a56073b 6434 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6435 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6436 #define TSC_IOASCR_G1_IO2_Pos (1U)
AnnaBridge 143:86740a56073b 6437 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6438 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6439 #define TSC_IOASCR_G1_IO3_Pos (2U)
AnnaBridge 143:86740a56073b 6440 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6441 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6442 #define TSC_IOASCR_G1_IO4_Pos (3U)
AnnaBridge 143:86740a56073b 6443 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6444 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6445 #define TSC_IOASCR_G2_IO1_Pos (4U)
AnnaBridge 143:86740a56073b 6446 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6447 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6448 #define TSC_IOASCR_G2_IO2_Pos (5U)
AnnaBridge 143:86740a56073b 6449 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6450 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6451 #define TSC_IOASCR_G2_IO3_Pos (6U)
AnnaBridge 143:86740a56073b 6452 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6453 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6454 #define TSC_IOASCR_G2_IO4_Pos (7U)
AnnaBridge 143:86740a56073b 6455 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6456 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6457 #define TSC_IOASCR_G3_IO1_Pos (8U)
AnnaBridge 143:86740a56073b 6458 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6459 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6460 #define TSC_IOASCR_G3_IO2_Pos (9U)
AnnaBridge 143:86740a56073b 6461 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6462 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6463 #define TSC_IOASCR_G3_IO3_Pos (10U)
AnnaBridge 143:86740a56073b 6464 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6465 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6466 #define TSC_IOASCR_G3_IO4_Pos (11U)
AnnaBridge 143:86740a56073b 6467 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6468 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6469 #define TSC_IOASCR_G4_IO1_Pos (12U)
AnnaBridge 143:86740a56073b 6470 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6471 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6472 #define TSC_IOASCR_G4_IO2_Pos (13U)
AnnaBridge 143:86740a56073b 6473 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6474 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6475 #define TSC_IOASCR_G4_IO3_Pos (14U)
AnnaBridge 143:86740a56073b 6476 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6477 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6478 #define TSC_IOASCR_G4_IO4_Pos (15U)
AnnaBridge 143:86740a56073b 6479 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6480 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6481 #define TSC_IOASCR_G5_IO1_Pos (16U)
AnnaBridge 143:86740a56073b 6482 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6483 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6484 #define TSC_IOASCR_G5_IO2_Pos (17U)
AnnaBridge 143:86740a56073b 6485 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6486 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6487 #define TSC_IOASCR_G5_IO3_Pos (18U)
AnnaBridge 143:86740a56073b 6488 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6489 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6490 #define TSC_IOASCR_G5_IO4_Pos (19U)
AnnaBridge 143:86740a56073b 6491 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6492 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6493 #define TSC_IOASCR_G6_IO1_Pos (20U)
AnnaBridge 143:86740a56073b 6494 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6495 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6496 #define TSC_IOASCR_G6_IO2_Pos (21U)
AnnaBridge 143:86740a56073b 6497 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6498 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6499 #define TSC_IOASCR_G6_IO3_Pos (22U)
AnnaBridge 143:86740a56073b 6500 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6501 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6502 #define TSC_IOASCR_G6_IO4_Pos (23U)
AnnaBridge 143:86740a56073b 6503 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6504 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6505 #define TSC_IOASCR_G7_IO1_Pos (24U)
AnnaBridge 143:86740a56073b 6506 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6507 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6508 #define TSC_IOASCR_G7_IO2_Pos (25U)
AnnaBridge 143:86740a56073b 6509 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6510 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6511 #define TSC_IOASCR_G7_IO3_Pos (26U)
AnnaBridge 143:86740a56073b 6512 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6513 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6514 #define TSC_IOASCR_G7_IO4_Pos (27U)
AnnaBridge 143:86740a56073b 6515 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6516 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6517 #define TSC_IOASCR_G8_IO1_Pos (28U)
AnnaBridge 143:86740a56073b 6518 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6519 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
AnnaBridge 143:86740a56073b 6520 #define TSC_IOASCR_G8_IO2_Pos (29U)
AnnaBridge 143:86740a56073b 6521 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 6522 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
AnnaBridge 143:86740a56073b 6523 #define TSC_IOASCR_G8_IO3_Pos (30U)
AnnaBridge 143:86740a56073b 6524 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 6525 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
AnnaBridge 143:86740a56073b 6526 #define TSC_IOASCR_G8_IO4_Pos (31U)
AnnaBridge 143:86740a56073b 6527 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 6528 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
AnnaBridge 143:86740a56073b 6529
AnnaBridge 143:86740a56073b 6530 /******************* Bit definition for TSC_IOSCR register ******************/
AnnaBridge 143:86740a56073b 6531 #define TSC_IOSCR_G1_IO1_Pos (0U)
AnnaBridge 143:86740a56073b 6532 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6533 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6534 #define TSC_IOSCR_G1_IO2_Pos (1U)
AnnaBridge 143:86740a56073b 6535 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6536 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6537 #define TSC_IOSCR_G1_IO3_Pos (2U)
AnnaBridge 143:86740a56073b 6538 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6539 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6540 #define TSC_IOSCR_G1_IO4_Pos (3U)
AnnaBridge 143:86740a56073b 6541 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6542 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6543 #define TSC_IOSCR_G2_IO1_Pos (4U)
AnnaBridge 143:86740a56073b 6544 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6545 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6546 #define TSC_IOSCR_G2_IO2_Pos (5U)
AnnaBridge 143:86740a56073b 6547 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6548 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6549 #define TSC_IOSCR_G2_IO3_Pos (6U)
AnnaBridge 143:86740a56073b 6550 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6551 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6552 #define TSC_IOSCR_G2_IO4_Pos (7U)
AnnaBridge 143:86740a56073b 6553 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6554 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6555 #define TSC_IOSCR_G3_IO1_Pos (8U)
AnnaBridge 143:86740a56073b 6556 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6557 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6558 #define TSC_IOSCR_G3_IO2_Pos (9U)
AnnaBridge 143:86740a56073b 6559 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6560 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6561 #define TSC_IOSCR_G3_IO3_Pos (10U)
AnnaBridge 143:86740a56073b 6562 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6563 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6564 #define TSC_IOSCR_G3_IO4_Pos (11U)
AnnaBridge 143:86740a56073b 6565 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6566 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6567 #define TSC_IOSCR_G4_IO1_Pos (12U)
AnnaBridge 143:86740a56073b 6568 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6569 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6570 #define TSC_IOSCR_G4_IO2_Pos (13U)
AnnaBridge 143:86740a56073b 6571 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6572 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6573 #define TSC_IOSCR_G4_IO3_Pos (14U)
AnnaBridge 143:86740a56073b 6574 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6575 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6576 #define TSC_IOSCR_G4_IO4_Pos (15U)
AnnaBridge 143:86740a56073b 6577 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6578 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6579 #define TSC_IOSCR_G5_IO1_Pos (16U)
AnnaBridge 143:86740a56073b 6580 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6581 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6582 #define TSC_IOSCR_G5_IO2_Pos (17U)
AnnaBridge 143:86740a56073b 6583 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6584 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6585 #define TSC_IOSCR_G5_IO3_Pos (18U)
AnnaBridge 143:86740a56073b 6586 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6587 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6588 #define TSC_IOSCR_G5_IO4_Pos (19U)
AnnaBridge 143:86740a56073b 6589 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6590 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6591 #define TSC_IOSCR_G6_IO1_Pos (20U)
AnnaBridge 143:86740a56073b 6592 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6593 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6594 #define TSC_IOSCR_G6_IO2_Pos (21U)
AnnaBridge 143:86740a56073b 6595 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6596 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6597 #define TSC_IOSCR_G6_IO3_Pos (22U)
AnnaBridge 143:86740a56073b 6598 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6599 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6600 #define TSC_IOSCR_G6_IO4_Pos (23U)
AnnaBridge 143:86740a56073b 6601 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6602 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6603 #define TSC_IOSCR_G7_IO1_Pos (24U)
AnnaBridge 143:86740a56073b 6604 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6605 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6606 #define TSC_IOSCR_G7_IO2_Pos (25U)
AnnaBridge 143:86740a56073b 6607 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6608 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6609 #define TSC_IOSCR_G7_IO3_Pos (26U)
AnnaBridge 143:86740a56073b 6610 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6611 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6612 #define TSC_IOSCR_G7_IO4_Pos (27U)
AnnaBridge 143:86740a56073b 6613 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6614 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6615 #define TSC_IOSCR_G8_IO1_Pos (28U)
AnnaBridge 143:86740a56073b 6616 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6617 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
AnnaBridge 143:86740a56073b 6618 #define TSC_IOSCR_G8_IO2_Pos (29U)
AnnaBridge 143:86740a56073b 6619 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 6620 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
AnnaBridge 143:86740a56073b 6621 #define TSC_IOSCR_G8_IO3_Pos (30U)
AnnaBridge 143:86740a56073b 6622 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 6623 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
AnnaBridge 143:86740a56073b 6624 #define TSC_IOSCR_G8_IO4_Pos (31U)
AnnaBridge 143:86740a56073b 6625 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 6626 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
AnnaBridge 143:86740a56073b 6627
AnnaBridge 143:86740a56073b 6628 /******************* Bit definition for TSC_IOCCR register ******************/
AnnaBridge 143:86740a56073b 6629 #define TSC_IOCCR_G1_IO1_Pos (0U)
AnnaBridge 143:86740a56073b 6630 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6631 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
AnnaBridge 143:86740a56073b 6632 #define TSC_IOCCR_G1_IO2_Pos (1U)
AnnaBridge 143:86740a56073b 6633 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6634 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
AnnaBridge 143:86740a56073b 6635 #define TSC_IOCCR_G1_IO3_Pos (2U)
AnnaBridge 143:86740a56073b 6636 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6637 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
AnnaBridge 143:86740a56073b 6638 #define TSC_IOCCR_G1_IO4_Pos (3U)
AnnaBridge 143:86740a56073b 6639 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6640 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
AnnaBridge 143:86740a56073b 6641 #define TSC_IOCCR_G2_IO1_Pos (4U)
AnnaBridge 143:86740a56073b 6642 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6643 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
AnnaBridge 143:86740a56073b 6644 #define TSC_IOCCR_G2_IO2_Pos (5U)
AnnaBridge 143:86740a56073b 6645 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6646 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
AnnaBridge 143:86740a56073b 6647 #define TSC_IOCCR_G2_IO3_Pos (6U)
AnnaBridge 143:86740a56073b 6648 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6649 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
AnnaBridge 143:86740a56073b 6650 #define TSC_IOCCR_G2_IO4_Pos (7U)
AnnaBridge 143:86740a56073b 6651 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6652 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
AnnaBridge 143:86740a56073b 6653 #define TSC_IOCCR_G3_IO1_Pos (8U)
AnnaBridge 143:86740a56073b 6654 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6655 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
AnnaBridge 143:86740a56073b 6656 #define TSC_IOCCR_G3_IO2_Pos (9U)
AnnaBridge 143:86740a56073b 6657 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6658 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
AnnaBridge 143:86740a56073b 6659 #define TSC_IOCCR_G3_IO3_Pos (10U)
AnnaBridge 143:86740a56073b 6660 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6661 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
AnnaBridge 143:86740a56073b 6662 #define TSC_IOCCR_G3_IO4_Pos (11U)
AnnaBridge 143:86740a56073b 6663 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6664 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
AnnaBridge 143:86740a56073b 6665 #define TSC_IOCCR_G4_IO1_Pos (12U)
AnnaBridge 143:86740a56073b 6666 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6667 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
AnnaBridge 143:86740a56073b 6668 #define TSC_IOCCR_G4_IO2_Pos (13U)
AnnaBridge 143:86740a56073b 6669 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6670 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
AnnaBridge 143:86740a56073b 6671 #define TSC_IOCCR_G4_IO3_Pos (14U)
AnnaBridge 143:86740a56073b 6672 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6673 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
AnnaBridge 143:86740a56073b 6674 #define TSC_IOCCR_G4_IO4_Pos (15U)
AnnaBridge 143:86740a56073b 6675 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6676 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
AnnaBridge 143:86740a56073b 6677 #define TSC_IOCCR_G5_IO1_Pos (16U)
AnnaBridge 143:86740a56073b 6678 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6679 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
AnnaBridge 143:86740a56073b 6680 #define TSC_IOCCR_G5_IO2_Pos (17U)
AnnaBridge 143:86740a56073b 6681 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6682 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
AnnaBridge 143:86740a56073b 6683 #define TSC_IOCCR_G5_IO3_Pos (18U)
AnnaBridge 143:86740a56073b 6684 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6685 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
AnnaBridge 143:86740a56073b 6686 #define TSC_IOCCR_G5_IO4_Pos (19U)
AnnaBridge 143:86740a56073b 6687 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6688 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
AnnaBridge 143:86740a56073b 6689 #define TSC_IOCCR_G6_IO1_Pos (20U)
AnnaBridge 143:86740a56073b 6690 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6691 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
AnnaBridge 143:86740a56073b 6692 #define TSC_IOCCR_G6_IO2_Pos (21U)
AnnaBridge 143:86740a56073b 6693 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6694 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
AnnaBridge 143:86740a56073b 6695 #define TSC_IOCCR_G6_IO3_Pos (22U)
AnnaBridge 143:86740a56073b 6696 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6697 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
AnnaBridge 143:86740a56073b 6698 #define TSC_IOCCR_G6_IO4_Pos (23U)
AnnaBridge 143:86740a56073b 6699 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6700 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
AnnaBridge 143:86740a56073b 6701 #define TSC_IOCCR_G7_IO1_Pos (24U)
AnnaBridge 143:86740a56073b 6702 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6703 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
AnnaBridge 143:86740a56073b 6704 #define TSC_IOCCR_G7_IO2_Pos (25U)
AnnaBridge 143:86740a56073b 6705 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6706 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
AnnaBridge 143:86740a56073b 6707 #define TSC_IOCCR_G7_IO3_Pos (26U)
AnnaBridge 143:86740a56073b 6708 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6709 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
AnnaBridge 143:86740a56073b 6710 #define TSC_IOCCR_G7_IO4_Pos (27U)
AnnaBridge 143:86740a56073b 6711 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6712 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
AnnaBridge 143:86740a56073b 6713 #define TSC_IOCCR_G8_IO1_Pos (28U)
AnnaBridge 143:86740a56073b 6714 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6715 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
AnnaBridge 143:86740a56073b 6716 #define TSC_IOCCR_G8_IO2_Pos (29U)
AnnaBridge 143:86740a56073b 6717 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
AnnaBridge 143:86740a56073b 6718 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
AnnaBridge 143:86740a56073b 6719 #define TSC_IOCCR_G8_IO3_Pos (30U)
AnnaBridge 143:86740a56073b 6720 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
AnnaBridge 143:86740a56073b 6721 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
AnnaBridge 143:86740a56073b 6722 #define TSC_IOCCR_G8_IO4_Pos (31U)
AnnaBridge 143:86740a56073b 6723 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
AnnaBridge 143:86740a56073b 6724 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
AnnaBridge 143:86740a56073b 6725
AnnaBridge 143:86740a56073b 6726 /******************* Bit definition for TSC_IOGCSR register *****************/
AnnaBridge 143:86740a56073b 6727 #define TSC_IOGCSR_G1E_Pos (0U)
AnnaBridge 143:86740a56073b 6728 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6729 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
AnnaBridge 143:86740a56073b 6730 #define TSC_IOGCSR_G2E_Pos (1U)
AnnaBridge 143:86740a56073b 6731 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6732 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
AnnaBridge 143:86740a56073b 6733 #define TSC_IOGCSR_G3E_Pos (2U)
AnnaBridge 143:86740a56073b 6734 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6735 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
AnnaBridge 143:86740a56073b 6736 #define TSC_IOGCSR_G4E_Pos (3U)
AnnaBridge 143:86740a56073b 6737 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6738 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
AnnaBridge 143:86740a56073b 6739 #define TSC_IOGCSR_G5E_Pos (4U)
AnnaBridge 143:86740a56073b 6740 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6741 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
AnnaBridge 143:86740a56073b 6742 #define TSC_IOGCSR_G6E_Pos (5U)
AnnaBridge 143:86740a56073b 6743 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6744 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
AnnaBridge 143:86740a56073b 6745 #define TSC_IOGCSR_G7E_Pos (6U)
AnnaBridge 143:86740a56073b 6746 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6747 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
AnnaBridge 143:86740a56073b 6748 #define TSC_IOGCSR_G8E_Pos (7U)
AnnaBridge 143:86740a56073b 6749 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6750 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
AnnaBridge 143:86740a56073b 6751 #define TSC_IOGCSR_G1S_Pos (16U)
AnnaBridge 143:86740a56073b 6752 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6753 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
AnnaBridge 143:86740a56073b 6754 #define TSC_IOGCSR_G2S_Pos (17U)
AnnaBridge 143:86740a56073b 6755 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6756 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
AnnaBridge 143:86740a56073b 6757 #define TSC_IOGCSR_G3S_Pos (18U)
AnnaBridge 143:86740a56073b 6758 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6759 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
AnnaBridge 143:86740a56073b 6760 #define TSC_IOGCSR_G4S_Pos (19U)
AnnaBridge 143:86740a56073b 6761 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6762 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
AnnaBridge 143:86740a56073b 6763 #define TSC_IOGCSR_G5S_Pos (20U)
AnnaBridge 143:86740a56073b 6764 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6765 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
AnnaBridge 143:86740a56073b 6766 #define TSC_IOGCSR_G6S_Pos (21U)
AnnaBridge 143:86740a56073b 6767 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6768 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
AnnaBridge 143:86740a56073b 6769 #define TSC_IOGCSR_G7S_Pos (22U)
AnnaBridge 143:86740a56073b 6770 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6771 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
AnnaBridge 143:86740a56073b 6772 #define TSC_IOGCSR_G8S_Pos (23U)
AnnaBridge 143:86740a56073b 6773 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6774 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
AnnaBridge 143:86740a56073b 6775
AnnaBridge 143:86740a56073b 6776 /******************* Bit definition for TSC_IOGXCR register *****************/
AnnaBridge 143:86740a56073b 6777 #define TSC_IOGXCR_CNT_Pos (0U)
AnnaBridge 143:86740a56073b 6778 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
AnnaBridge 143:86740a56073b 6779 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
AnnaBridge 143:86740a56073b 6780
AnnaBridge 143:86740a56073b 6781 /******************************************************************************/
AnnaBridge 143:86740a56073b 6782 /* */
AnnaBridge 143:86740a56073b 6783 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 143:86740a56073b 6784 /* */
AnnaBridge 143:86740a56073b 6785 /******************************************************************************/
AnnaBridge 143:86740a56073b 6786
AnnaBridge 143:86740a56073b 6787 /*
AnnaBridge 143:86740a56073b 6788 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
AnnaBridge 143:86740a56073b 6789 */
AnnaBridge 143:86740a56073b 6790 /* Note: No specific macro feature on this device */
AnnaBridge 143:86740a56073b 6791
AnnaBridge 143:86740a56073b 6792 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 143:86740a56073b 6793 #define USART_CR1_UE_Pos (0U)
AnnaBridge 143:86740a56073b 6794 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6795 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 143:86740a56073b 6796 #define USART_CR1_UESM_Pos (1U)
AnnaBridge 143:86740a56073b 6797 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6798 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
AnnaBridge 143:86740a56073b 6799 #define USART_CR1_RE_Pos (2U)
AnnaBridge 143:86740a56073b 6800 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6801 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 143:86740a56073b 6802 #define USART_CR1_TE_Pos (3U)
AnnaBridge 143:86740a56073b 6803 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6804 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 143:86740a56073b 6805 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 143:86740a56073b 6806 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6807 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 143:86740a56073b 6808 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 143:86740a56073b 6809 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6810 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 143:86740a56073b 6811 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 143:86740a56073b 6812 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6813 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 143:86740a56073b 6814 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 143:86740a56073b 6815 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6816 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
AnnaBridge 143:86740a56073b 6817 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 143:86740a56073b 6818 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6819 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 143:86740a56073b 6820 #define USART_CR1_PS_Pos (9U)
AnnaBridge 143:86740a56073b 6821 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6822 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 143:86740a56073b 6823 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 143:86740a56073b 6824 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6825 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 143:86740a56073b 6826 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 143:86740a56073b 6827 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6828 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 143:86740a56073b 6829 #define USART_CR1_M_Pos (12U)
AnnaBridge 143:86740a56073b 6830 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
AnnaBridge 143:86740a56073b 6831 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
AnnaBridge 143:86740a56073b 6832 #define USART_CR1_M0_Pos (12U)
AnnaBridge 143:86740a56073b 6833 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6834 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
AnnaBridge 143:86740a56073b 6835 #define USART_CR1_MME_Pos (13U)
AnnaBridge 143:86740a56073b 6836 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6837 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 143:86740a56073b 6838 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 143:86740a56073b 6839 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6840 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 143:86740a56073b 6841 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 143:86740a56073b 6842 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6843 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 143:86740a56073b 6844 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 143:86740a56073b 6845 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 143:86740a56073b 6846 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 143:86740a56073b 6847 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6848 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6849 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6850 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6851 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6852 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 143:86740a56073b 6853 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 143:86740a56073b 6854 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 143:86740a56073b 6855 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6856 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6857 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6858 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 143:86740a56073b 6859 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 143:86740a56073b 6860 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 143:86740a56073b 6861 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 143:86740a56073b 6862 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 143:86740a56073b 6863 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 143:86740a56073b 6864 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 143:86740a56073b 6865 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 143:86740a56073b 6866 #define USART_CR1_M1_Pos (28U)
AnnaBridge 143:86740a56073b 6867 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
AnnaBridge 143:86740a56073b 6868 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
AnnaBridge 143:86740a56073b 6869 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 143:86740a56073b 6870 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 143:86740a56073b 6871 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6872 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 143:86740a56073b 6873 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 143:86740a56073b 6874 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6875 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 143:86740a56073b 6876 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 143:86740a56073b 6877 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6878 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 143:86740a56073b 6879 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 143:86740a56073b 6880 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6881 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 143:86740a56073b 6882 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 143:86740a56073b 6883 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6884 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 143:86740a56073b 6885 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 143:86740a56073b 6886 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6887 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 143:86740a56073b 6888 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 143:86740a56073b 6889 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6890 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 143:86740a56073b 6891 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 143:86740a56073b 6892 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 143:86740a56073b 6893 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 143:86740a56073b 6894 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6895 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6896 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 143:86740a56073b 6897 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6898 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 143:86740a56073b 6899 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 143:86740a56073b 6900 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6901 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 143:86740a56073b 6902 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 143:86740a56073b 6903 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 6904 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 143:86740a56073b 6905 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 143:86740a56073b 6906 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6907 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 143:86740a56073b 6908 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 143:86740a56073b 6909 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6910 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 143:86740a56073b 6911 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 143:86740a56073b 6912 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6913 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 143:86740a56073b 6914 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 143:86740a56073b 6915 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6916 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
AnnaBridge 143:86740a56073b 6917 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 143:86740a56073b 6918 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 143:86740a56073b 6919 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 143:86740a56073b 6920 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6921 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6922 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 143:86740a56073b 6923 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6924 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 143:86740a56073b 6925 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 143:86740a56073b 6926 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 143:86740a56073b 6927 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 143:86740a56073b 6928
AnnaBridge 143:86740a56073b 6929 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 143:86740a56073b 6930 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 143:86740a56073b 6931 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 6932 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 143:86740a56073b 6933 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 143:86740a56073b 6934 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 6935 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 143:86740a56073b 6936 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 143:86740a56073b 6937 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 6938 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 143:86740a56073b 6939 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 143:86740a56073b 6940 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 6941 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 143:86740a56073b 6942 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 143:86740a56073b 6943 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 6944 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 143:86740a56073b 6945 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 143:86740a56073b 6946 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 6947 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 143:86740a56073b 6948 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 143:86740a56073b 6949 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 6950 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 143:86740a56073b 6951 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 143:86740a56073b 6952 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 6953 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 143:86740a56073b 6954 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 143:86740a56073b 6955 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 6956 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 143:86740a56073b 6957 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 143:86740a56073b 6958 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 6959 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 143:86740a56073b 6960 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 143:86740a56073b 6961 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 6962 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 143:86740a56073b 6963 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 143:86740a56073b 6964 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 6965 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 143:86740a56073b 6966 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 143:86740a56073b 6967 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 6968 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 143:86740a56073b 6969 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 143:86740a56073b 6970 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 143:86740a56073b 6971 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 143:86740a56073b 6972 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 143:86740a56073b 6973 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 6974 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 143:86740a56073b 6975 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 143:86740a56073b 6976 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 6977 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 143:86740a56073b 6978 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 143:86740a56073b 6979 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 143:86740a56073b 6980 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 143:86740a56073b 6981 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 6982 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 6983 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 6984 #define USART_CR3_WUS_Pos (20U)
AnnaBridge 143:86740a56073b 6985 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
AnnaBridge 143:86740a56073b 6986 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
AnnaBridge 143:86740a56073b 6987 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 6988 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 6989 #define USART_CR3_WUFIE_Pos (22U)
AnnaBridge 143:86740a56073b 6990 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 6991 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
AnnaBridge 143:86740a56073b 6992 #define USART_CR3_UCESM_Pos (23U)
AnnaBridge 143:86740a56073b 6993 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
AnnaBridge 143:86740a56073b 6994 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
AnnaBridge 143:86740a56073b 6995
AnnaBridge 143:86740a56073b 6996 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 143:86740a56073b 6997 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 143:86740a56073b 6998 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 143:86740a56073b 6999 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 143:86740a56073b 7000 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 143:86740a56073b 7001 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 143:86740a56073b 7002 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 143:86740a56073b 7003
AnnaBridge 143:86740a56073b 7004 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 143:86740a56073b 7005 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 143:86740a56073b 7006 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 143:86740a56073b 7007 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 143:86740a56073b 7008 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 143:86740a56073b 7009 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 143:86740a56073b 7010 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 143:86740a56073b 7011
AnnaBridge 143:86740a56073b 7012
AnnaBridge 143:86740a56073b 7013 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 143:86740a56073b 7014 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 143:86740a56073b 7015 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 143:86740a56073b 7016 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 143:86740a56073b 7017 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 143:86740a56073b 7018 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 143:86740a56073b 7019 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 143:86740a56073b 7020
AnnaBridge 143:86740a56073b 7021 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 143:86740a56073b 7022 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 143:86740a56073b 7023 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7024 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 143:86740a56073b 7025 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 143:86740a56073b 7026 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 7027 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 143:86740a56073b 7028 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 143:86740a56073b 7029 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 7030 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 143:86740a56073b 7031 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 143:86740a56073b 7032 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 7033 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 143:86740a56073b 7034 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 143:86740a56073b 7035 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 7036 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 143:86740a56073b 7037
AnnaBridge 143:86740a56073b 7038 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 143:86740a56073b 7039 #define USART_ISR_PE_Pos (0U)
AnnaBridge 143:86740a56073b 7040 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7041 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 143:86740a56073b 7042 #define USART_ISR_FE_Pos (1U)
AnnaBridge 143:86740a56073b 7043 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 7044 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 143:86740a56073b 7045 #define USART_ISR_NE_Pos (2U)
AnnaBridge 143:86740a56073b 7046 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 7047 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
AnnaBridge 143:86740a56073b 7048 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 143:86740a56073b 7049 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 7050 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 143:86740a56073b 7051 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 143:86740a56073b 7052 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 7053 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 143:86740a56073b 7054 #define USART_ISR_RXNE_Pos (5U)
AnnaBridge 143:86740a56073b 7055 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 7056 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 143:86740a56073b 7057 #define USART_ISR_TC_Pos (6U)
AnnaBridge 143:86740a56073b 7058 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 7059 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 143:86740a56073b 7060 #define USART_ISR_TXE_Pos (7U)
AnnaBridge 143:86740a56073b 7061 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 7062 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 143:86740a56073b 7063 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 143:86740a56073b 7064 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 7065 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 143:86740a56073b 7066 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 143:86740a56073b 7067 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 7068 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 143:86740a56073b 7069 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 143:86740a56073b 7070 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 143:86740a56073b 7071 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 143:86740a56073b 7072 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 143:86740a56073b 7073 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 7074 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 143:86740a56073b 7075 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 143:86740a56073b 7076 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 7077 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 143:86740a56073b 7078 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 143:86740a56073b 7079 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 143:86740a56073b 7080 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 143:86740a56073b 7081 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 143:86740a56073b 7082 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 143:86740a56073b 7083 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 143:86740a56073b 7084 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 143:86740a56073b 7085 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 143:86740a56073b 7086 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 143:86740a56073b 7087 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 143:86740a56073b 7088 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 7089 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 143:86740a56073b 7090 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 143:86740a56073b 7091 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 143:86740a56073b 7092 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 143:86740a56073b 7093 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 143:86740a56073b 7094 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 143:86740a56073b 7095 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 143:86740a56073b 7096 #define USART_ISR_WUF_Pos (20U)
AnnaBridge 143:86740a56073b 7097 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 7098 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
AnnaBridge 143:86740a56073b 7099 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 143:86740a56073b 7100 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 143:86740a56073b 7101 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 143:86740a56073b 7102 #define USART_ISR_REACK_Pos (22U)
AnnaBridge 143:86740a56073b 7103 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
AnnaBridge 143:86740a56073b 7104 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
AnnaBridge 143:86740a56073b 7105
AnnaBridge 143:86740a56073b 7106 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 143:86740a56073b 7107 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 143:86740a56073b 7108 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7109 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 143:86740a56073b 7110 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 143:86740a56073b 7111 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 7112 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 143:86740a56073b 7113 #define USART_ICR_NCF_Pos (2U)
AnnaBridge 143:86740a56073b 7114 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 7115 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
AnnaBridge 143:86740a56073b 7116 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 143:86740a56073b 7117 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 7118 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 143:86740a56073b 7119 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 143:86740a56073b 7120 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 7121 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 143:86740a56073b 7122 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 143:86740a56073b 7123 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 7124 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 143:86740a56073b 7125 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 143:86740a56073b 7126 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 7127 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 143:86740a56073b 7128 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 143:86740a56073b 7129 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 7130 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 143:86740a56073b 7131 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 143:86740a56073b 7132 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 143:86740a56073b 7133 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 143:86740a56073b 7134 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 143:86740a56073b 7135 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 143:86740a56073b 7136 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 143:86740a56073b 7137 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 143:86740a56073b 7138 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 143:86740a56073b 7139 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 143:86740a56073b 7140 #define USART_ICR_WUCF_Pos (20U)
AnnaBridge 143:86740a56073b 7141 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
AnnaBridge 143:86740a56073b 7142 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 143:86740a56073b 7143
AnnaBridge 143:86740a56073b 7144 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 143:86740a56073b 7145 #define USART_RDR_RDR_Pos (0U)
AnnaBridge 143:86740a56073b 7146 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
AnnaBridge 143:86740a56073b 7147 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 143:86740a56073b 7148
AnnaBridge 143:86740a56073b 7149 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 143:86740a56073b 7150 #define USART_TDR_TDR_Pos (0U)
AnnaBridge 143:86740a56073b 7151 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
AnnaBridge 143:86740a56073b 7152 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 143:86740a56073b 7153
AnnaBridge 143:86740a56073b 7154 /******************************************************************************/
AnnaBridge 143:86740a56073b 7155 /* */
AnnaBridge 143:86740a56073b 7156 /* USB Device General registers */
AnnaBridge 143:86740a56073b 7157 /* */
AnnaBridge 143:86740a56073b 7158 /******************************************************************************/
AnnaBridge 143:86740a56073b 7159 #define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
AnnaBridge 143:86740a56073b 7160 #define USB_PMAADDR_Pos (13U)
AnnaBridge 143:86740a56073b 7161 #define USB_PMAADDR_Msk (0x20003U << USB_PMAADDR_Pos) /*!< 0x40006000 */
AnnaBridge 143:86740a56073b 7162 #define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
AnnaBridge 143:86740a56073b 7163
AnnaBridge 143:86740a56073b 7164 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
AnnaBridge 143:86740a56073b 7165 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
AnnaBridge 143:86740a56073b 7166 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
AnnaBridge 143:86740a56073b 7167 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
AnnaBridge 143:86740a56073b 7168 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
AnnaBridge 143:86740a56073b 7169 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
AnnaBridge 143:86740a56073b 7170 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
AnnaBridge 143:86740a56073b 7171
AnnaBridge 143:86740a56073b 7172 /**************************** ISTR interrupt events *************************/
AnnaBridge 143:86740a56073b 7173 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
AnnaBridge 143:86740a56073b 7174 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
AnnaBridge 143:86740a56073b 7175 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
AnnaBridge 143:86740a56073b 7176 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
AnnaBridge 143:86740a56073b 7177 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
AnnaBridge 143:86740a56073b 7178 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
AnnaBridge 143:86740a56073b 7179 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
AnnaBridge 143:86740a56073b 7180 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
AnnaBridge 143:86740a56073b 7181 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
AnnaBridge 143:86740a56073b 7182 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
AnnaBridge 143:86740a56073b 7183 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
AnnaBridge 143:86740a56073b 7184
AnnaBridge 143:86740a56073b 7185 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
AnnaBridge 143:86740a56073b 7186 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
AnnaBridge 143:86740a56073b 7187 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
AnnaBridge 143:86740a56073b 7188 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
AnnaBridge 143:86740a56073b 7189 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
AnnaBridge 143:86740a56073b 7190 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
AnnaBridge 143:86740a56073b 7191 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
AnnaBridge 143:86740a56073b 7192 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
AnnaBridge 143:86740a56073b 7193 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
AnnaBridge 143:86740a56073b 7194 /************************* CNTR control register bits definitions ***********/
AnnaBridge 143:86740a56073b 7195 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
AnnaBridge 143:86740a56073b 7196 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
AnnaBridge 143:86740a56073b 7197 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
AnnaBridge 143:86740a56073b 7198 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
AnnaBridge 143:86740a56073b 7199 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
AnnaBridge 143:86740a56073b 7200 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
AnnaBridge 143:86740a56073b 7201 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
AnnaBridge 143:86740a56073b 7202 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
AnnaBridge 143:86740a56073b 7203 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
AnnaBridge 143:86740a56073b 7204 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
AnnaBridge 143:86740a56073b 7205 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
AnnaBridge 143:86740a56073b 7206 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
AnnaBridge 143:86740a56073b 7207 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
AnnaBridge 143:86740a56073b 7208 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
AnnaBridge 143:86740a56073b 7209 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
AnnaBridge 143:86740a56073b 7210 /************************* BCDR control register bits definitions ***********/
AnnaBridge 143:86740a56073b 7211 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
AnnaBridge 143:86740a56073b 7212 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
AnnaBridge 143:86740a56073b 7213 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
AnnaBridge 143:86740a56073b 7214 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
AnnaBridge 143:86740a56073b 7215 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
AnnaBridge 143:86740a56073b 7216 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
AnnaBridge 143:86740a56073b 7217 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
AnnaBridge 143:86740a56073b 7218 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
AnnaBridge 143:86740a56073b 7219 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
AnnaBridge 143:86740a56073b 7220 /*************************** LPM register bits definitions ******************/
AnnaBridge 143:86740a56073b 7221 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 143:86740a56073b 7222 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 143:86740a56073b 7223 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
AnnaBridge 143:86740a56073b 7224 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
AnnaBridge 143:86740a56073b 7225 /******************** FNR Frame Number Register bit definitions ************/
AnnaBridge 143:86740a56073b 7226 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
AnnaBridge 143:86740a56073b 7227 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
AnnaBridge 143:86740a56073b 7228 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
AnnaBridge 143:86740a56073b 7229 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
AnnaBridge 143:86740a56073b 7230 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
AnnaBridge 143:86740a56073b 7231 /******************** DADDR Device ADDRess bit definitions ****************/
AnnaBridge 143:86740a56073b 7232 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
AnnaBridge 143:86740a56073b 7233 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
AnnaBridge 143:86740a56073b 7234 /****************************** Endpoint register *************************/
AnnaBridge 143:86740a56073b 7235 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
AnnaBridge 143:86740a56073b 7236 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
AnnaBridge 143:86740a56073b 7237 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
AnnaBridge 143:86740a56073b 7238 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
AnnaBridge 143:86740a56073b 7239 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
AnnaBridge 143:86740a56073b 7240 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
AnnaBridge 143:86740a56073b 7241 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
AnnaBridge 143:86740a56073b 7242 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
AnnaBridge 143:86740a56073b 7243 /* bit positions */
AnnaBridge 143:86740a56073b 7244 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
AnnaBridge 143:86740a56073b 7245 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
AnnaBridge 143:86740a56073b 7246 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
AnnaBridge 143:86740a56073b 7247 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
AnnaBridge 143:86740a56073b 7248 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
AnnaBridge 143:86740a56073b 7249 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
AnnaBridge 143:86740a56073b 7250 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
AnnaBridge 143:86740a56073b 7251 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
AnnaBridge 143:86740a56073b 7252 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
AnnaBridge 143:86740a56073b 7253 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
AnnaBridge 143:86740a56073b 7254
AnnaBridge 143:86740a56073b 7255 /* EndPoint REGister MASK (no toggle fields) */
AnnaBridge 143:86740a56073b 7256 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
AnnaBridge 143:86740a56073b 7257 /*!< EP_TYPE[1:0] EndPoint TYPE */
AnnaBridge 143:86740a56073b 7258 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
AnnaBridge 143:86740a56073b 7259 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
AnnaBridge 143:86740a56073b 7260 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
AnnaBridge 143:86740a56073b 7261 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
AnnaBridge 143:86740a56073b 7262 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
AnnaBridge 143:86740a56073b 7263 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
AnnaBridge 143:86740a56073b 7264
AnnaBridge 143:86740a56073b 7265 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
AnnaBridge 143:86740a56073b 7266 /*!< STAT_TX[1:0] STATus for TX transfer */
AnnaBridge 143:86740a56073b 7267 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
AnnaBridge 143:86740a56073b 7268 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
AnnaBridge 143:86740a56073b 7269 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
AnnaBridge 143:86740a56073b 7270 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
AnnaBridge 143:86740a56073b 7271 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
AnnaBridge 143:86740a56073b 7272 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
AnnaBridge 143:86740a56073b 7273 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
AnnaBridge 143:86740a56073b 7274 /*!< STAT_RX[1:0] STATus for RX transfer */
AnnaBridge 143:86740a56073b 7275 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
AnnaBridge 143:86740a56073b 7276 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
AnnaBridge 143:86740a56073b 7277 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
AnnaBridge 143:86740a56073b 7278 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
AnnaBridge 143:86740a56073b 7279 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 143:86740a56073b 7280 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 143:86740a56073b 7281 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
AnnaBridge 143:86740a56073b 7282
AnnaBridge 143:86740a56073b 7283 /******************************************************************************/
AnnaBridge 143:86740a56073b 7284 /* */
AnnaBridge 143:86740a56073b 7285 /* Window WATCHDOG (WWDG) */
AnnaBridge 143:86740a56073b 7286 /* */
AnnaBridge 143:86740a56073b 7287 /******************************************************************************/
AnnaBridge 143:86740a56073b 7288
AnnaBridge 143:86740a56073b 7289 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 143:86740a56073b 7290 #define WWDG_CR_T_Pos (0U)
AnnaBridge 143:86740a56073b 7291 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 143:86740a56073b 7292 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 143:86740a56073b 7293 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7294 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 7295 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 7296 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 7297 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 7298 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 7299 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 7300
AnnaBridge 143:86740a56073b 7301 /* Legacy defines */
AnnaBridge 143:86740a56073b 7302 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 143:86740a56073b 7303 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 143:86740a56073b 7304 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 143:86740a56073b 7305 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 143:86740a56073b 7306 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 143:86740a56073b 7307 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 143:86740a56073b 7308 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 143:86740a56073b 7309
AnnaBridge 143:86740a56073b 7310 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 143:86740a56073b 7311 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 7312 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
AnnaBridge 143:86740a56073b 7313
AnnaBridge 143:86740a56073b 7314 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 143:86740a56073b 7315 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 143:86740a56073b 7316 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 143:86740a56073b 7317 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
AnnaBridge 143:86740a56073b 7318 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7319 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 143:86740a56073b 7320 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 143:86740a56073b 7321 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 143:86740a56073b 7322 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 143:86740a56073b 7323 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 143:86740a56073b 7324 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 143:86740a56073b 7325
AnnaBridge 143:86740a56073b 7326 /* Legacy defines */
AnnaBridge 143:86740a56073b 7327 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 143:86740a56073b 7328 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 143:86740a56073b 7329 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 143:86740a56073b 7330 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 143:86740a56073b 7331 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 143:86740a56073b 7332 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 143:86740a56073b 7333 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 143:86740a56073b 7334
AnnaBridge 143:86740a56073b 7335 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 143:86740a56073b 7336 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 143:86740a56073b 7337 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
AnnaBridge 143:86740a56073b 7338 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
AnnaBridge 143:86740a56073b 7339 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
AnnaBridge 143:86740a56073b 7340
AnnaBridge 143:86740a56073b 7341 /* Legacy defines */
AnnaBridge 143:86740a56073b 7342 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 143:86740a56073b 7343 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 143:86740a56073b 7344
AnnaBridge 143:86740a56073b 7345 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 143:86740a56073b 7346 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 143:86740a56073b 7347 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
AnnaBridge 143:86740a56073b 7348
AnnaBridge 143:86740a56073b 7349 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 143:86740a56073b 7350 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 143:86740a56073b 7351 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 143:86740a56073b 7352 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
AnnaBridge 143:86740a56073b 7353
AnnaBridge 143:86740a56073b 7354 /**
AnnaBridge 143:86740a56073b 7355 * @}
AnnaBridge 143:86740a56073b 7356 */
AnnaBridge 143:86740a56073b 7357
AnnaBridge 143:86740a56073b 7358 /**
AnnaBridge 143:86740a56073b 7359 * @}
AnnaBridge 143:86740a56073b 7360 */
AnnaBridge 143:86740a56073b 7361
AnnaBridge 143:86740a56073b 7362 /** @addtogroup Exported_macros
AnnaBridge 143:86740a56073b 7363 * @{
AnnaBridge 143:86740a56073b 7364 */
AnnaBridge 143:86740a56073b 7365
AnnaBridge 143:86740a56073b 7366 /******************************* ADC Instances ********************************/
AnnaBridge 143:86740a56073b 7367 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 143:86740a56073b 7368 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 143:86740a56073b 7369
AnnaBridge 143:86740a56073b 7370 /******************************* COMP Instances *******************************/
AnnaBridge 143:86740a56073b 7371 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
AnnaBridge 143:86740a56073b 7372 ((INSTANCE) == COMP2))
AnnaBridge 143:86740a56073b 7373
AnnaBridge 143:86740a56073b 7374 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
AnnaBridge 143:86740a56073b 7375
AnnaBridge 143:86740a56073b 7376 /******************************* CRC Instances ********************************/
AnnaBridge 143:86740a56073b 7377 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 143:86740a56073b 7378
AnnaBridge 143:86740a56073b 7379 /******************************* DAC Instances *********************************/
AnnaBridge 143:86740a56073b 7380 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
AnnaBridge 143:86740a56073b 7381
AnnaBridge 143:86740a56073b 7382 /******************************* DMA Instances *********************************/
AnnaBridge 143:86740a56073b 7383 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
AnnaBridge 143:86740a56073b 7384 ((INSTANCE) == DMA1_Channel2) || \
AnnaBridge 143:86740a56073b 7385 ((INSTANCE) == DMA1_Channel3) || \
AnnaBridge 143:86740a56073b 7386 ((INSTANCE) == DMA1_Channel4) || \
AnnaBridge 143:86740a56073b 7387 ((INSTANCE) == DMA1_Channel5) || \
AnnaBridge 143:86740a56073b 7388 ((INSTANCE) == DMA1_Channel6) || \
AnnaBridge 143:86740a56073b 7389 ((INSTANCE) == DMA1_Channel7))
AnnaBridge 143:86740a56073b 7390
AnnaBridge 143:86740a56073b 7391 /******************************* GPIO Instances *******************************/
AnnaBridge 143:86740a56073b 7392 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 143:86740a56073b 7393 ((INSTANCE) == GPIOB) || \
AnnaBridge 143:86740a56073b 7394 ((INSTANCE) == GPIOC) || \
AnnaBridge 143:86740a56073b 7395 ((INSTANCE) == GPIOD) || \
AnnaBridge 143:86740a56073b 7396 ((INSTANCE) == GPIOE) || \
AnnaBridge 143:86740a56073b 7397 ((INSTANCE) == GPIOH))
AnnaBridge 143:86740a56073b 7398
AnnaBridge 143:86740a56073b 7399 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 143:86740a56073b 7400 ((INSTANCE) == GPIOB) || \
AnnaBridge 143:86740a56073b 7401 ((INSTANCE) == GPIOC) || \
AnnaBridge 143:86740a56073b 7402 ((INSTANCE) == GPIOD) || \
AnnaBridge 143:86740a56073b 7403 ((INSTANCE) == GPIOE) || \
AnnaBridge 143:86740a56073b 7404 ((INSTANCE) == GPIOH))
AnnaBridge 143:86740a56073b 7405
AnnaBridge 143:86740a56073b 7406 /******************************** I2C Instances *******************************/
AnnaBridge 143:86740a56073b 7407 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 143:86740a56073b 7408 ((INSTANCE) == I2C2) || \
AnnaBridge 143:86740a56073b 7409 ((INSTANCE) == I2C3))
AnnaBridge 143:86740a56073b 7410
AnnaBridge 143:86740a56073b 7411 /****************** I2C Instances : wakeup capability from stop modes *********/
AnnaBridge 143:86740a56073b 7412 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 143:86740a56073b 7413 ((INSTANCE) == I2C3))
AnnaBridge 143:86740a56073b 7414
AnnaBridge 143:86740a56073b 7415
AnnaBridge 143:86740a56073b 7416 /******************************** I2S Instances *******************************/
AnnaBridge 143:86740a56073b 7417 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
AnnaBridge 143:86740a56073b 7418
AnnaBridge 143:86740a56073b 7419 /******************************* RNG Instances ********************************/
AnnaBridge 143:86740a56073b 7420 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 143:86740a56073b 7421
AnnaBridge 143:86740a56073b 7422 /****************************** RTC Instances *********************************/
AnnaBridge 143:86740a56073b 7423 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 143:86740a56073b 7424
AnnaBridge 143:86740a56073b 7425 /******************************** SMBUS Instances *****************************/
AnnaBridge 143:86740a56073b 7426 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 143:86740a56073b 7427 ((INSTANCE) == I2C3))
AnnaBridge 143:86740a56073b 7428
AnnaBridge 143:86740a56073b 7429 /******************************** SPI Instances *******************************/
AnnaBridge 143:86740a56073b 7430 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 143:86740a56073b 7431 ((INSTANCE) == SPI2))
AnnaBridge 143:86740a56073b 7432
AnnaBridge 143:86740a56073b 7433 /****************** LPTIM Instances : All supported instances *****************/
AnnaBridge 143:86740a56073b 7434 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
AnnaBridge 143:86740a56073b 7435
AnnaBridge 143:86740a56073b 7436 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 143:86740a56073b 7437 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7438 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7439 ((INSTANCE) == TIM6) || \
AnnaBridge 143:86740a56073b 7440 ((INSTANCE) == TIM7) || \
AnnaBridge 143:86740a56073b 7441 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7442 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7443
AnnaBridge 143:86740a56073b 7444 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 143:86740a56073b 7445 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7446 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7447 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7448 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7449
AnnaBridge 143:86740a56073b 7450 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 143:86740a56073b 7451 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7452 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7453 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7454 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7455
AnnaBridge 143:86740a56073b 7456 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 143:86740a56073b 7457 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7458 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7459 ((INSTANCE) == TIM21))
AnnaBridge 143:86740a56073b 7460
AnnaBridge 143:86740a56073b 7461 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 143:86740a56073b 7462 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7463 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7464 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7465 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7466
AnnaBridge 143:86740a56073b 7467 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 143:86740a56073b 7468 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7469 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7470 ((INSTANCE) == TIM21))
AnnaBridge 143:86740a56073b 7471
AnnaBridge 143:86740a56073b 7472 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 143:86740a56073b 7473 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7474 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7475 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7476 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7477
AnnaBridge 143:86740a56073b 7478 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 143:86740a56073b 7479 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7480 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7481 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7482 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7483
AnnaBridge 143:86740a56073b 7484 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 143:86740a56073b 7485 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7486 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7487 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7488 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7489
AnnaBridge 143:86740a56073b 7490 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 143:86740a56073b 7491 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7492 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7493
AnnaBridge 143:86740a56073b 7494 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 143:86740a56073b 7495 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7496 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7497
AnnaBridge 143:86740a56073b 7498 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 143:86740a56073b 7499
AnnaBridge 143:86740a56073b 7500 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 143:86740a56073b 7501 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7502 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7503
AnnaBridge 143:86740a56073b 7504 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 143:86740a56073b 7505 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7506 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7507 ((INSTANCE) == TIM6) || \
AnnaBridge 143:86740a56073b 7508 ((INSTANCE) == TIM7))
AnnaBridge 143:86740a56073b 7509
AnnaBridge 143:86740a56073b 7510 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 143:86740a56073b 7511 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7512 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7513
AnnaBridge 143:86740a56073b 7514 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 143:86740a56073b 7515 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7516 (INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7517
AnnaBridge 143:86740a56073b 7518 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 143:86740a56073b 7519 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7520 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7521
AnnaBridge 143:86740a56073b 7522 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 143:86740a56073b 7523 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7524 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7525 ((INSTANCE) == TIM6) || \
AnnaBridge 143:86740a56073b 7526 ((INSTANCE) == TIM7) || \
AnnaBridge 143:86740a56073b 7527 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7528 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7529
AnnaBridge 143:86740a56073b 7530 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 143:86740a56073b 7531 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7532 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7533 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7534 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7535
AnnaBridge 143:86740a56073b 7536 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 143:86740a56073b 7537
AnnaBridge 143:86740a56073b 7538 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 143:86740a56073b 7539 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7540 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7541 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7542 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7543
AnnaBridge 143:86740a56073b 7544 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 143:86740a56073b 7545 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7546 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7547 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7548 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7549
AnnaBridge 143:86740a56073b 7550 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 143:86740a56073b 7551 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7552 ((INSTANCE) == TIM3) || \
AnnaBridge 143:86740a56073b 7553 ((INSTANCE) == TIM21) || \
AnnaBridge 143:86740a56073b 7554 ((INSTANCE) == TIM22))
AnnaBridge 143:86740a56073b 7555
AnnaBridge 143:86740a56073b 7556 /******************* TIM Instances : output(s) OCXEC register *****************/
AnnaBridge 143:86740a56073b 7557 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7558 ((INSTANCE) == TIM3))
AnnaBridge 143:86740a56073b 7559
AnnaBridge 143:86740a56073b 7560 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 143:86740a56073b 7561 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 143:86740a56073b 7562 (((((INSTANCE) == TIM2) || \
AnnaBridge 143:86740a56073b 7563 ((INSTANCE) == TIM3)) \
AnnaBridge 143:86740a56073b 7564 && \
AnnaBridge 143:86740a56073b 7565 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 143:86740a56073b 7566 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 143:86740a56073b 7567 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 143:86740a56073b 7568 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 143:86740a56073b 7569 || \
AnnaBridge 143:86740a56073b 7570 (((INSTANCE) == TIM21) && \
AnnaBridge 143:86740a56073b 7571 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 143:86740a56073b 7572 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 143:86740a56073b 7573 || \
AnnaBridge 143:86740a56073b 7574 (((INSTANCE) == TIM22) && \
AnnaBridge 143:86740a56073b 7575 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 143:86740a56073b 7576 ((CHANNEL) == TIM_CHANNEL_2))))
AnnaBridge 143:86740a56073b 7577
AnnaBridge 143:86740a56073b 7578 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 143:86740a56073b 7579 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7580 ((INSTANCE) == USART2) || \
AnnaBridge 143:86740a56073b 7581 ((INSTANCE) == USART4) || \
AnnaBridge 143:86740a56073b 7582 ((INSTANCE) == USART5) || \
AnnaBridge 143:86740a56073b 7583 ((INSTANCE) == LPUART1))
AnnaBridge 143:86740a56073b 7584
AnnaBridge 143:86740a56073b 7585 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 143:86740a56073b 7586 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7587 ((INSTANCE) == USART2) || \
AnnaBridge 143:86740a56073b 7588 ((INSTANCE) == USART4) || \
AnnaBridge 143:86740a56073b 7589 ((INSTANCE) == USART5))
AnnaBridge 143:86740a56073b 7590
AnnaBridge 143:86740a56073b 7591 /****************** USART Instances : Auto Baud Rate detection ****************/
AnnaBridge 143:86740a56073b 7592
AnnaBridge 143:86740a56073b 7593 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7594 ((INSTANCE) == USART2))
AnnaBridge 143:86740a56073b 7595
AnnaBridge 143:86740a56073b 7596 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 143:86740a56073b 7597 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7598 ((INSTANCE) == USART2) || \
AnnaBridge 143:86740a56073b 7599 ((INSTANCE) == USART4) || \
AnnaBridge 143:86740a56073b 7600 ((INSTANCE) == USART5) || \
AnnaBridge 143:86740a56073b 7601 ((INSTANCE) == LPUART1))
AnnaBridge 143:86740a56073b 7602
AnnaBridge 143:86740a56073b 7603 /******************** UART Instances : LIN mode **********************/
AnnaBridge 143:86740a56073b 7604 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7605 ((INSTANCE) == USART2))
AnnaBridge 143:86740a56073b 7606
AnnaBridge 143:86740a56073b 7607 /******************** UART Instances : Wake-up from Stop mode **********************/
AnnaBridge 143:86740a56073b 7608 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7609 ((INSTANCE) == USART2) || \
AnnaBridge 143:86740a56073b 7610 ((INSTANCE) == LPUART1))
AnnaBridge 143:86740a56073b 7611 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 143:86740a56073b 7612 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7613 ((INSTANCE) == USART2) || \
AnnaBridge 143:86740a56073b 7614 ((INSTANCE) == USART4) || \
AnnaBridge 143:86740a56073b 7615 ((INSTANCE) == USART5) || \
AnnaBridge 143:86740a56073b 7616 ((INSTANCE) == LPUART1))
AnnaBridge 143:86740a56073b 7617
AnnaBridge 143:86740a56073b 7618 /********************* UART Instances : Smard card mode ***********************/
AnnaBridge 143:86740a56073b 7619 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7620 ((INSTANCE) == USART2))
AnnaBridge 143:86740a56073b 7621
AnnaBridge 143:86740a56073b 7622 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 143:86740a56073b 7623 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 143:86740a56073b 7624 ((INSTANCE) == USART2))
AnnaBridge 143:86740a56073b 7625
AnnaBridge 143:86740a56073b 7626 /******************** LPUART Instance *****************************************/
AnnaBridge 143:86740a56073b 7627 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
AnnaBridge 143:86740a56073b 7628
AnnaBridge 143:86740a56073b 7629 /****************************** IWDG Instances ********************************/
AnnaBridge 143:86740a56073b 7630 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 143:86740a56073b 7631
AnnaBridge 143:86740a56073b 7632 /****************************** USB Instances ********************************/
AnnaBridge 143:86740a56073b 7633 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
AnnaBridge 143:86740a56073b 7634
AnnaBridge 143:86740a56073b 7635 /****************************** WWDG Instances ********************************/
AnnaBridge 143:86740a56073b 7636 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 143:86740a56073b 7637
AnnaBridge 143:86740a56073b 7638 /**
AnnaBridge 143:86740a56073b 7639 * @}
AnnaBridge 143:86740a56073b 7640 */
AnnaBridge 143:86740a56073b 7641
AnnaBridge 143:86740a56073b 7642 /******************************************************************************/
AnnaBridge 143:86740a56073b 7643 /* For a painless codes migration between the STM32L0xx device product */
AnnaBridge 143:86740a56073b 7644 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 143:86740a56073b 7645 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 143:86740a56073b 7646 /* No need to update developed interrupt code when moving across */
AnnaBridge 143:86740a56073b 7647 /* product lines within the same STM32L0 Family */
AnnaBridge 143:86740a56073b 7648 /******************************************************************************/
AnnaBridge 143:86740a56073b 7649
AnnaBridge 143:86740a56073b 7650 /* Aliases for __IRQn */
AnnaBridge 143:86740a56073b 7651
AnnaBridge 143:86740a56073b 7652 #define LPUART1_IRQn RNG_LPUART1_IRQn
AnnaBridge 143:86740a56073b 7653 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
AnnaBridge 143:86740a56073b 7654 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
AnnaBridge 143:86740a56073b 7655 #define TIM6_IRQn TIM6_DAC_IRQn
AnnaBridge 143:86740a56073b 7656 #define RCC_IRQn RCC_CRS_IRQn
AnnaBridge 143:86740a56073b 7657
AnnaBridge 143:86740a56073b 7658 /* Aliases for __IRQHandler */
AnnaBridge 143:86740a56073b 7659 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
AnnaBridge 143:86740a56073b 7660 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
AnnaBridge 143:86740a56073b 7661 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
AnnaBridge 143:86740a56073b 7662 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
AnnaBridge 143:86740a56073b 7663 #define RCC_IRQHandler RCC_CRS_IRQHandler
AnnaBridge 143:86740a56073b 7664
AnnaBridge 143:86740a56073b 7665 /**
AnnaBridge 143:86740a56073b 7666 * @}
AnnaBridge 143:86740a56073b 7667 */
AnnaBridge 143:86740a56073b 7668
AnnaBridge 143:86740a56073b 7669 /**
AnnaBridge 143:86740a56073b 7670 * @}
AnnaBridge 143:86740a56073b 7671 */
AnnaBridge 143:86740a56073b 7672
AnnaBridge 143:86740a56073b 7673 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 7674 }
AnnaBridge 143:86740a56073b 7675 #endif /* __cplusplus */
AnnaBridge 143:86740a56073b 7676
AnnaBridge 143:86740a56073b 7677 #endif /* __STM32L072xx_H */
AnnaBridge 143:86740a56073b 7678
AnnaBridge 143:86740a56073b 7679
AnnaBridge 143:86740a56073b 7680
AnnaBridge 143:86740a56073b 7681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/