File content as of revision 171:3a7713b1edbc:

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#ifndef _MXC_TPU_REGS_H_
#define _MXC_TPU_REGS_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>
#include "mxc_device.h"

/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif


/*
   Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
   access to each register in module.
*/

/*                                                          Offset          Register Description
                                                            =============   ============================================================================ */
typedef struct {
    __I  uint32_t rsv000[4];                            /*  0x0000-0x000C                                                                                */
    __IO uint32_t sks0;                                 /*  0x0010          TPU Secure Key Storage Register 0 (Cleared on Tamper Detect)                 */
    __IO uint32_t sks1;                                 /*  0x0014          TPU Secure Key Storage Register 1 (Cleared on Tamper Detect)                 */
    __IO uint32_t sks2;                                 /*  0x0018          TPU Secure Key Storage Register 2 (Cleared on Tamper Detect)                 */
    __IO uint32_t sks3;                                 /*  0x001C          TPU Secure Key Storage Register 3 (Cleared on Tamper Detect)                 */
} mxc_tpu_tsr_regs_t;


/*
   Register offsets for module TPU.
*/

#define MXC_R_TPU_TSR_OFFS_SKS0                             ((uint32_t)0x00000010UL)
#define MXC_R_TPU_TSR_OFFS_SKS1                             ((uint32_t)0x00000014UL)
#define MXC_R_TPU_TSR_OFFS_SKS2                             ((uint32_t)0x00000018UL)
#define MXC_R_TPU_TSR_OFFS_SKS3                             ((uint32_t)0x0000001CUL)



#ifdef __cplusplus
}
#endif

#endif   /* _MXC_TPU_REGS_H_ */