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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h
- Revision:
- 122:f9eeca106725
- Parent:
- 110:165afa46840b
--- a/TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F411RE/stm32f4xx_hal_dma.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -108,7 +108,7 @@
@note The burst mode is possible only if the address Increment mode is enabled. */
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+ It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_Peripheral_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
@@ -120,17 +120,12 @@
*/
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
- HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
- HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
- HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
- HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
- HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
- HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
+ HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
}HAL_DMA_StateTypeDef;
/**
@@ -138,11 +133,25 @@
*/
typedef enum
{
- HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
@@ -155,21 +164,26 @@
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
- void *Parent; /*!< Parent object state */
+ void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
-
+
+ void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
+
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
- uint32_t StreamIndex; /*!< DMA Stream Index */
+ uint32_t StreamIndex; /*!< DMA Stream Index */
+
}DMA_HandleTypeDef;
/**
@@ -187,11 +201,14 @@
* @brief DMA Error Code
* @{
*/
-#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
-#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
-#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
+#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
+#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
+#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
/**
* @}
*/
@@ -200,14 +217,14 @@
* @brief DMA channel selection
* @{
*/
-#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
/**
* @}
*/
@@ -216,19 +233,19 @@
* @brief DMA data transfer direction
* @{
*/
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
/**
* @}
- */
+ */
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
/**
* @}
*/
@@ -238,7 +255,7 @@
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
/**
* @}
*/
@@ -247,7 +264,7 @@
* @brief DMA peripheral data size
* @{
*/
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
@@ -258,7 +275,7 @@
* @brief DMA memory data size
* @{
*/
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
/**
@@ -269,7 +286,7 @@
* @brief DMA mode
* @{
*/
-#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
/**
@@ -280,7 +297,7 @@
* @brief DMA priority levels
* @{
*/
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
@@ -292,7 +309,7 @@
* @brief DMA FIFO direct mode
* @{
*/
-#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
/**
* @}
@@ -302,7 +319,7 @@
* @brief DMA FIFO level
* @{
*/
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
@@ -314,7 +331,7 @@
* @brief DMA memory burst
* @{
*/
-#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
@@ -326,10 +343,10 @@
* @brief DMA peripheral burst
* @{
*/
-#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
-#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
/**
* @}
*/
@@ -342,7 +359,7 @@
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE ((uint32_t)0x00000080)
+#define DMA_IT_FE ((uint32_t)0x00000080U)
/**
* @}
*/
@@ -351,26 +368,26 @@
* @brief DMA flag definitions
* @{
*/
-#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
-#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
-#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
-#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
-#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
-#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
-#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
-#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
-#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
-#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
-#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
-#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
-#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
-#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
-#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
-#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
-#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
-#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
-#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
-#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
/**
* @}
*/
@@ -654,8 +671,13 @@
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
/**
* @}
*/
@@ -699,7 +721,7 @@
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
