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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_DISCO_L476VG/stm32l4xx_ll_fmc.h
- Revision:
- 122:f9eeca106725
- Parent:
- 107:4f6c30876dfa
--- a/TARGET_DISCO_L476VG/stm32l4xx_ll_fmc.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_DISCO_L476VG/stm32l4xx_ll_fmc.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 26-June-2015
+ * @version V1.5.1
+ * @date 31-May-2016
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_LL_FMC_H
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
@@ -52,7 +54,7 @@
/** @addtogroup FMC_LL FMC Low Layer
* @{
- */
+ */
/** @addtogroup FMC_LL_Private_Macros FMC Low Layer Private Macros
* @{
@@ -78,17 +80,14 @@
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
- ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
-
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
@@ -96,7 +95,7 @@
((__MODE__) == FMC_ACCESS_MODE_D))
-#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
@@ -131,14 +130,14 @@
/**
* @}
*/
-
+
/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
* @{
*/
#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
/**
* @}
- */
+ */
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
@@ -147,14 +146,14 @@
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
@@ -162,7 +161,7 @@
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-/** @defgroup FMC_Address_Setup_Time
+/** @defgroup FMC_Address_Setup_Time
* @{
*/
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
@@ -170,7 +169,7 @@
* @}
*/
-/** @defgroup FMC_Address_Hold_Time
+/** @defgroup FMC_Address_Hold_Time
* @{
*/
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
@@ -178,7 +177,7 @@
* @}
*/
-/** @defgroup FMC_Data_Setup_Time
+/** @defgroup FMC_Data_Setup_Time
* @{
*/
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
@@ -186,7 +185,7 @@
* @}
*/
-/** @defgroup FMC_Bus_Turn_around_Duration
+/** @defgroup FMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
@@ -194,7 +193,7 @@
* @}
*/
-/** @defgroup FMC_CLK_Division
+/** @defgroup FMC_CLK_Division
* @{
*/
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
@@ -202,13 +201,13 @@
* @}
*/
-/** @defgroup FMC_Data_Latency
+/** @defgroup FMC_Data_Latency
* @{
*/
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
/**
* @}
- */
+ */
/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
* @{
@@ -218,7 +217,7 @@
* @}
*/
-/** @defgroup FMC_TAR_Setup_Time
+/** @defgroup FMC_TAR_Setup_Time
* @{
*/
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
@@ -226,7 +225,7 @@
* @}
*/
-/** @defgroup FMC_Setup_Time
+/** @defgroup FMC_Setup_Time
* @{
*/
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
@@ -234,7 +233,7 @@
* @}
*/
-/** @defgroup FMC_Wait_Setup_Time
+/** @defgroup FMC_Wait_Setup_Time
* @{
*/
#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
@@ -242,7 +241,7 @@
* @}
*/
-/** @defgroup FMC_Hold_Setup_Time
+/** @defgroup FMC_Hold_Setup_Time
* @{
*/
#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
@@ -250,19 +249,19 @@
* @}
*/
-/** @defgroup FMC_HiZ_Setup_Time
+/** @defgroup FMC_HiZ_Setup_Time
* @{
*/
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
- */
-
+ */
+
/**
* @}
- */
+ */
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Typedef FMC Low Layer Exported Typedef
* @{
*/
@@ -274,16 +273,16 @@
#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
#define FMC_NAND_DEVICE FMC_Bank3_R
-/**
+/**
* @brief FMC_NORSRAM Configuration Structure definition
- */
+ */
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
+ multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
@@ -303,14 +302,14 @@
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
+ valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
+ signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
@@ -324,39 +323,40 @@
This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Write_FIFO */
+ This parameter can be a value of @ref FMC_Write_FIFO.
+ @note This Parameter is not available for STM32L47x/L48x devices. */
uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FMC_Page_Size */
}FMC_NORSRAM_InitTypeDef;
-/**
- * @brief FMC_NORSRAM Timing parameters structure definition
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
+ the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
@@ -364,9 +364,9 @@
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
@@ -377,13 +377,13 @@
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
}FMC_NORSRAM_TimingTypeDef;
-/**
- * @brief FMC_NAND Configuration Structure definition
- */
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
@@ -410,7 +410,7 @@
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FMC_NAND_InitTypeDef;
-/**
+/**
* @brief FMC_NAND Timing parameters structure definition
*/
typedef struct
@@ -424,7 +424,7 @@
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
+ memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
@@ -443,7 +443,7 @@
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
@@ -506,12 +506,12 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
/**
* @}
*/
-
+
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
@@ -566,7 +566,7 @@
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
/**
* @}
- */
+ */
/** @defgroup FMC_Page_Size FMC Page Size
* @{
@@ -574,10 +574,11 @@
#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
/**
* @}
- */
+ */
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
@@ -587,7 +588,7 @@
/**
* @}
*/
-
+
/** @defgroup FMC_Continous_Clock FMC Continous Clock
* @{
*/
@@ -597,33 +598,24 @@
* @}
*/
-/** @defgroup FMC_Write_FIFO FMC Write FIFO
- * @{
- */
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
-/**
- * @}
- */
-
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0|FMC_BTRx_ACCMOD_1))
/**
* @}
- */
+ */
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/** @defgroup FMC_NAND_Controller FMC NAND Exported constants
* @{
@@ -631,7 +623,7 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
- */
+ */
#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
/**
* @}
@@ -687,27 +679,27 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
* @brief FMC Interrupt definition
* @{
- */
+ */
#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN)
#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN)
#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN)
/**
* @}
*/
-
+
/** @defgroup FMC_Flag_definition FMC Flag definition
* @brief FMC Flag definition
* @{
- */
+ */
#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS)
#define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS)
#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS)
@@ -720,116 +712,116 @@
/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
* @{
- */
-
+ */
+
/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
-
+
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __BANK__: FMC_NORSRAM Bank
* @retval none
- */
+ */
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __BANK__: FMC_NORSRAM Bank
* @retval none
- */
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
/**
* @}
- */
+ */
/** @defgroup FMC_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
-
+
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __BANK__: FMC_NAND Bank
* @retval none
- */
+ */
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __BANK__: FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
/**
* @}
- */
-
+ */
+
/** @defgroup FMC_Interrupt FMC Interrupt
* @brief macros to handle FMC interrupts
* @{
- */
+ */
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
- */
+ */
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __BANK__: FMC_NAND Bank
* @param __INTERRUPT__: FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__))
-
+
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __BANK__: FMC_NAND Bank
* @param __FLAG__: FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
* @param __FLAG__: FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
-#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__))
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__))
/* Exported functions --------------------------------------------------------*/
@@ -848,9 +840,9 @@
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
- */
+ */
-/** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions
+/** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* FMC_NORSRAM Control functions */
@@ -858,7 +850,7 @@
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
- */
+ */
/* FMC_NAND Controller functions **********************************************/
/** @addtogroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
@@ -871,9 +863,9 @@
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
- */
+ */
-/** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions
* @{
*/
/* FMC_NAND Control functions */
@@ -882,20 +874,22 @@
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
/**
* @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+ */
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
#ifdef __cplusplus
}
#endif
