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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_DISCO_L476VG/stm32l4xx_hal_dma.h
- Revision:
- 122:f9eeca106725
- Parent:
- 107:4f6c30876dfa
--- a/TARGET_DISCO_L476VG/stm32l4xx_hal_dma.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_DISCO_L476VG/stm32l4xx_hal_dma.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 26-June-2015
+ * @version V1.5.1
+ * @date 31-May-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,7 @@
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
@@ -93,27 +94,14 @@
} DMA_InitTypeDef;
/**
- * @brief DMA Configuration enumeration values definition
- */
-typedef enum
-{
- DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
- DMA_PRIORITY = 1 /*!< Control related priority level Parameter in DMA_InitTypeDef */
-
-} DMA_ControlTypeDef;
-
-/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
- HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04 /*!< DMA error state */
-
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
@@ -123,35 +111,51 @@
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
-
}HAL_DMA_LevelCompleteTypeDef;
+/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
+
+}HAL_DMA_CallbackIDTypeDef;
+
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
- HAL_LockTypeDef Lock; /*!< DMA locking object */
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
- __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
- void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
- void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
}DMA_HandleTypeDef;
-
/**
* @}
*/
@@ -162,17 +166,19 @@
* @{
*/
-/** @defgroup DMA_Error_Code
+/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
-#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
/**
* @}
*/
-/** @defgroup DMA_request
+/** @defgroup DMA_request DMA request
* @{
*/
#define DMA_REQUEST_0 ((uint32_t)0x00000000)
@@ -188,98 +194,89 @@
* @}
*/
-/** @defgroup DMA_Data_transfer_direction
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
-/** @defgroup DMA_Peripheral_data_size
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
-
/**
* @}
*/
-/** @defgroup DMA_Memory_data_size
+/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
-
/**
* @}
*/
-/** @defgroup DMA_mode
+/** @defgroup DMA_mode DMA mode
* @{
*/
-#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
-
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
/**
* @}
*/
-/** @defgroup DMA_Priority_level
+/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
-
/**
* @}
*/
-/** @defgroup DMA_interrupt_enable_definitions
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
-
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
-
/**
* @}
*/
-/** @defgroup DMA_flag_definitions
+/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
-
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
@@ -308,8 +305,6 @@
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
-
-
/**
* @}
*/
@@ -323,7 +318,7 @@
* @{
*/
-/** @brief Reset DMA handle state.
+/** @brief Reset DMA handle state.
* @param __HANDLE__: DMA handle
* @retval None
*/
@@ -432,11 +427,11 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
- * @arg DMA_ISR_GIFx: Global interrupt flag
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * @arg DMA_FLAG_GLx: Global interrupt flag
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
@@ -447,11 +442,11 @@
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag
- * @arg DMA_FLAG_TEIFx: Transfer error flag
- * @arg DMA_ISR_GIFx: Global interrupt flag
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * @arg DMA_FLAG_GLx: Global interrupt flag
+ * Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
@@ -494,6 +489,13 @@
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
+ * @brief Return the number of remaining data units in the current DMA Channel transfer.
+ * @param __HANDLE__: DMA handle
+ * @retval The number of remaining data units in the current DMA Channel transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
* @}
*/
@@ -502,13 +504,13 @@
/** @addtogroup DMA_Exported_Functions
* @{
*/
-
+
/** @addtogroup DMA_Exported_Functions_Group1
* @{
- */
+ */
+/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-
/**
* @}
*/
@@ -516,11 +518,15 @@
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
+/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
@@ -528,19 +534,18 @@
/** @addtogroup DMA_Exported_Functions_Group3
* @{
- */
-
+ */
+/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
/**
* @}
- */
+ */
- /**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
@@ -571,7 +576,6 @@
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
-
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
