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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_DISCO_F746NG/stm32f7xx_hal_nand.h
- Revision:
- 122:f9eeca106725
- Parent:
- 116:c0f6e94411f5
--- a/TARGET_DISCO_F746NG/stm32f7xx_hal_nand.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_DISCO_F746NG/stm32f7xx_hal_nand.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_nand.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 09-December-2015
+ * @version V1.1.0
+ * @date 22-April-2016
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
*/
typedef enum
{
- HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
}HAL_NAND_StateTypeDef;
/**
@@ -179,10 +179,15 @@
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@@ -223,33 +228,33 @@
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE ((uint32_t)0x80000000)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
+#define NAND_DEVICE ((uint32_t)0x80000000U)
+#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+#define NAND_CMD_AREA_A ((uint8_t)0x00U)
+#define NAND_CMD_AREA_B ((uint8_t)0x01U)
+#define NAND_CMD_AREA_C ((uint8_t)0x50U)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
+#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
+#define NAND_CMD_READID ((uint8_t)0x90U)
+#define NAND_CMD_STATUS ((uint8_t)0x70U)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
+#define NAND_CMD_RESET ((uint8_t)0xFFU)
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
-#define NAND_BUSY ((uint32_t)0x00000000)
-#define NAND_ERROR ((uint32_t)0x00000001)
-#define NAND_READY ((uint32_t)0x00000040)
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
+#define NAND_BUSY ((uint32_t)0x00000000U)
+#define NAND_ERROR ((uint32_t)0x00000001U)
+#define NAND_READY ((uint32_t)0x00000040U)
/**
* @}
*/
