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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_DISCO_F469NI/stm32f4xx_hal_i2c.h
- Revision:
- 122:f9eeca106725
- Parent:
- 110:165afa46840b
--- a/TARGET_DISCO_F469NI/stm32f4xx_hal_i2c.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_DISCO_F469NI/stm32f4xx_hal_i2c.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -91,48 +91,117 @@
}I2C_InitTypeDef;
/**
- * @brief HAL State structures definition
+ * @brief HAL State structure definition
+ * @note HAL I2C State value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : Abort (Abort user request on going)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
+ * b4 (not used)
+ * x : Should be set to 0
+ * b3
+ * 0 : Ready or Busy (No Listen mode ongoing)
+ * 1 : Listen (IP in Address Listen Mode)
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
*/
typedef enum
{
- HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
- HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
- HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
- HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
- HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
/**
+ * @brief HAL Mode structure definition
+ * @note HAL I2C Mode value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6
+ * 0 : None
+ * 1 : Memory (HAL I2C communication is in Memory Mode)
+ * b5
+ * 0 : None
+ * 1 : Slave (HAL I2C communication is in Slave Mode)
+ * b4
+ * 0 : None
+ * 1 : Master (HAL I2C communication is in Master Mode)
+ * b3-b2-b1-b0 (not used)
+ * xxxx : Should be set to 0000
+ */
+typedef enum
+{
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
+
+}HAL_I2C_ModeTypeDef;
+
+/**
* @brief I2C handle Structure definition
*/
typedef struct
{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< I2C transfer options */
+
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
+ context for internal usage */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
- __IO uint32_t ErrorCode; /*!< I2C Error code */
+ __IO uint32_t EventCount; /*!< I2C Event counter */
+
+}I2C_HandleTypeDef;
-}I2C_HandleTypeDef;
/**
* @}
*/
@@ -146,13 +215,13 @@
* @brief I2C Error Code
* @{
*/
-#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
-#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout Error */
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
/**
* @}
*/
@@ -160,7 +229,7 @@
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
-#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
* @}
@@ -169,8 +238,8 @@
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
-#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
/**
* @}
*/
@@ -178,7 +247,7 @@
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
-#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
@@ -187,7 +256,7 @@
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
-#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
@@ -196,7 +265,7 @@
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
-#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
@@ -205,8 +274,28 @@
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
-#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+ * @{
+ */
+#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
+#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+ * @{
+ */
+#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
+#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
+#define I2C_LAST_FRAME ((uint32_t)0x00000008U)
/**
* @}
*/
@@ -224,27 +313,27 @@
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
-#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
-#define I2C_FLAG_PECERR ((uint32_t)0x00011000)
-#define I2C_FLAG_OVR ((uint32_t)0x00010800)
-#define I2C_FLAG_AF ((uint32_t)0x00010400)
-#define I2C_FLAG_ARLO ((uint32_t)0x00010200)
-#define I2C_FLAG_BERR ((uint32_t)0x00010100)
-#define I2C_FLAG_TXE ((uint32_t)0x00010080)
-#define I2C_FLAG_RXNE ((uint32_t)0x00010040)
-#define I2C_FLAG_STOPF ((uint32_t)0x00010010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
-#define I2C_FLAG_BTF ((uint32_t)0x00010004)
-#define I2C_FLAG_ADDR ((uint32_t)0x00010002)
-#define I2C_FLAG_SB ((uint32_t)0x00010001)
-#define I2C_FLAG_DUALF ((uint32_t)0x00100080)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
-#define I2C_FLAG_TRA ((uint32_t)0x00100004)
-#define I2C_FLAG_BUSY ((uint32_t)0x00100002)
-#define I2C_FLAG_MSL ((uint32_t)0x00100001)
+#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
+#define I2C_FLAG_PECERR ((uint32_t)0x00011000U)
+#define I2C_FLAG_OVR ((uint32_t)0x00010800U)
+#define I2C_FLAG_AF ((uint32_t)0x00010400U)
+#define I2C_FLAG_ARLO ((uint32_t)0x00010200U)
+#define I2C_FLAG_BERR ((uint32_t)0x00010100U)
+#define I2C_FLAG_TXE ((uint32_t)0x00010080U)
+#define I2C_FLAG_RXNE ((uint32_t)0x00010040U)
+#define I2C_FLAG_STOPF ((uint32_t)0x00010010U)
+#define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
+#define I2C_FLAG_BTF ((uint32_t)0x00010004U)
+#define I2C_FLAG_ADDR ((uint32_t)0x00010002U)
+#define I2C_FLAG_SB ((uint32_t)0x00010001U)
+#define I2C_FLAG_DUALF ((uint32_t)0x00100080U)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
+#define I2C_FLAG_TRA ((uint32_t)0x00100004U)
+#define I2C_FLAG_BUSY ((uint32_t)0x00100002U)
+#define I2C_FLAG_MSL ((uint32_t)0x00100001U)
/**
* @}
*/
@@ -319,7 +408,7 @@
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
@@ -345,7 +434,7 @@
*/
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
tmpreg = (__HANDLE__)->Instance->SR2; \
UNUSED(tmpreg); \
@@ -358,13 +447,24 @@
*/
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR1; \
(__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
UNUSED(tmpreg); \
} while(0)
+/** @brief Enable the I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+
+/** @brief Disable the I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
/**
@@ -412,6 +512,14 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@@ -427,9 +535,12 @@
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
@@ -437,8 +548,9 @@
/** @addtogroup I2C_Exported_Functions_Group3
* @{
*/
-/* Peripheral Control and State functions **************************************/
+/* Peripheral State, Mode and Errors functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
@@ -454,7 +566,7 @@
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
-#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
/**
* @}
*/
@@ -464,23 +576,23 @@
* @{
*/
-#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
* @{
@@ -497,9 +609,13 @@
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_NEXT_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME))
/**
* @}
*/
