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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_B96B_F446VE/stm32f4xx_hal_lptim.h
- Revision:
- 122:f9eeca106725
- Parent:
- 112:6f327212ef96
--- a/TARGET_B96B_F446VE/stm32f4xx_hal_lptim.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_B96B_F446VE/stm32f4xx_hal_lptim.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -146,11 +146,11 @@
*/
typedef enum __HAL_LPTIM_StateTypeDef
{
- HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
- HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */
+ HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
}HAL_LPTIM_StateTypeDef;
/**
@@ -182,7 +182,7 @@
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
@@ -191,7 +191,7 @@
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
-#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
+#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x00000000U)
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
@@ -207,7 +207,7 @@
* @{
*/
-#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
+#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
/**
* @}
@@ -216,7 +216,7 @@
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
@@ -228,7 +228,7 @@
* @{
*/
-#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
+#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
@@ -238,8 +238,8 @@
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
-#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
-#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
+#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
+#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
@@ -262,7 +262,7 @@
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
@@ -274,7 +274,7 @@
* @{
*/
-#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
+#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
@@ -284,7 +284,7 @@
* @{
*/
-#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
+#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
@@ -323,7 +323,7 @@
/** @defgroup LPTIM_Option Register Definition
* @{
*/
-#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000)
+#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000U)
#define LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0
#define LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1
#define LPTIM_OP_TIM_DAC LPTIM_OR_OR
@@ -524,14 +524,18 @@
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
+ }while(0)
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+ }while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
@@ -712,7 +716,7 @@
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
@@ -720,13 +724,13 @@
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
-#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
-#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)
+#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
-#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)
+#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
/**
* @}
