Diff: TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf

Revision:

170:e95d10626187

Parent:

161:aa5281ff4a02

--- a/TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf	Fri Jun 22 15:38:59 2018 +0100
+++ b/TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf	Thu Sep 06 13:39:34 2018 +0100
@@ -1,51 +1,60 @@
 /*
 ** ###################################################################
-**     Processors:          MIMXRT1052CVL5A
-**                          MIMXRT1052DVL6A
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
-**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
 **     Version:             rev. 0.1, 2017-01-10
-**     Build:               b170927
+**     Build:               b180509
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
+**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
 **
-**     1. Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
 **
-**     2. Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
 **
-**     3. Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
 **
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
 **
 ** ###################################################################
 */
+
 define symbol __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
 define symbol __stack_size__=0x8000;
 define symbol __heap_size__=0x10000;
 
@@ -58,6 +67,9 @@
 define symbol m_text_start             = 0x60002400;
 define symbol m_text_end               = 0x63FFFFFF;
 
+define symbol m_text2_start            = 0x00000000;
+define symbol m_text2_end              = 0x0001FFFF;
+
 define symbol m_interrupts_ram_start   = 0x20000000;
 define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;
 
@@ -67,6 +79,17 @@
 define symbol m_data2_start            = 0x20200000;
 define symbol m_data2_end              = 0x2023FFFF;
 
+define symbol m_data3_start            = 0x80000000;
+define symbol m_data3_end              = 0x81DFFFFF;
+
+define symbol m_ncache_start           = 0x81E00000;
+define symbol m_ncache_end             = 0x81FFFFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x60000000;
+define symbol m_boot_hdr_ivt_start           = 0x60001000;
+define symbol m_boot_hdr_boot_data_start     = 0x60001020;
+define symbol m_boot_hdr_dcd_data_start      = 0x60001030;
+
 /* Sizes */
 if (isdefinedsymbol(__stack_size__)) {
   define symbol __size_cstack__        = __stack_size__;
@@ -88,26 +111,38 @@
 define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
                           | mem:[from m_text_start to m_text_end];
 
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region TEXT2_region = mem:[from m_text2_start to m_text2_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end];
 define region DATA2_region = mem:[from m_data2_start to m_data2_end];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region DATA3_region  = mem:[from m_data3_start to m_data3_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
+define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
 define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
 
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block RW        { readwrite };
-define block ZI        { zi };
-define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+define block RW        { first readwrite, section m_usb_dma_init_data  };
+define block ZI        with alignment = 32  { first  zi, section m_usb_dma_noninit_data };
+define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000  { section NonCacheable , section NonCacheable.init };
 
 initialize by copy { readwrite, section .textrw };
 do not initialize  { section .noinit };
 
 place at address mem: m_interrupts_start    { readonly section .intvec };
 
+place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+
+keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+
 place in TEXT_region                        { readonly };
-place in DATA_region                        { block RW };
-place in DATA_region                        { block ZI };
-place in DATA_region                        { last block HEAP };
-place in DATA_region                        { block NCACHE_VAR };
+place in DATA3_region                        { block RW };
+place in DATA3_region                        { block ZI };
+place in DATA3_region                        { last block HEAP };
 place in CSTACK_region                      { block CSTACK };
+place in NCACHE_region                      { block NCACHE_VAR };
+place in TEXT2_region                       { section .textrw};
 place in m_interrupts_ram_region            { section m_interrupts_ram };