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Revision:
99:dbbf35b96557
Parent:
92:4fc01daae5a5
Child:
106:ba1f97679dad
--- a/TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h	Wed Apr 29 10:16:23 2015 +0100
+++ b/TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h	Wed May 13 08:08:21 2015 +0200
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32f4xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    19-June-2014
+  * @version V1.3.0
+  * @date    09-March-2015
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -50,13 +50,12 @@
   * @{
   */
 
-/** @addtogroup SDMMC
+/** @addtogroup SDMMC_LL
   * @{
   */ 
 
 /* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup SDIO_Exported_Types SDIO Exported Types
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
   * @{
   */
   
@@ -143,12 +142,11 @@
   */
   
 /* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SDIO_Exported_Constants
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
   * @{
   */
 
-/** @defgroup SDIO_Clock_Edge 
+/** @defgroup SDIO_Clock_Edge Clock Edge
   * @{
   */
 #define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
@@ -160,7 +158,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Clock_Bypass 
+/** @defgroup SDIO_Clock_Bypass Clock Bypass
   * @{
   */
 #define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
@@ -172,7 +170,7 @@
   * @}
   */ 
 
-/** @defgroup SDIO_Clock_Power_Save 
+/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
   * @{
   */
 #define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
@@ -184,7 +182,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Bus_Wide 
+/** @defgroup SDIO_Bus_Wide Bus Width
   * @{
   */
 #define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
@@ -198,7 +196,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Hardware_Flow_Control 
+/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
   * @{
   */
 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
@@ -210,7 +208,7 @@
   * @}
   */
   
-/** @defgroup SDIO_Clock_Division
+/** @defgroup SDIO_Clock_Division Clock Division
   * @{
   */
 #define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
@@ -218,7 +216,7 @@
   * @}
   */  
     
-/** @defgroup SDIO_Command_Index
+/** @defgroup SDIO_Command_Index Command Index
   * @{
   */
 #define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
@@ -226,7 +224,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Response_Type
+/** @defgroup SDIO_Response_Type Response Type
   * @{
   */
 #define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
@@ -240,7 +238,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Wait_Interrupt_State
+/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
   * @{
   */
 #define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
@@ -254,7 +252,7 @@
   * @}
   */
 
-/** @defgroup SDIO_CPSM_State
+/** @defgroup SDIO_CPSM_State CPSM State
   * @{
   */
 #define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
@@ -266,7 +264,7 @@
   * @}
   */  
 
-/** @defgroup SDIO_Response_Registers
+/** @defgroup SDIO_Response_Registers Response Register
   * @{
   */
 #define SDIO_RESP1                          ((uint32_t)0x00000000)
@@ -282,7 +280,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Data_Length 
+/** @defgroup SDIO_Data_Length Data Lenght
   * @{
   */
 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
@@ -290,7 +288,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Data_Block_Size 
+/** @defgroup SDIO_Data_Block_Size Data Block Size
   * @{
   */
 #define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
@@ -328,7 +326,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Transfer_Direction 
+/** @defgroup SDIO_Transfer_Direction Transfer Direction
   * @{
   */
 #define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
@@ -340,7 +338,7 @@
   * @}
   */
 
-/** @defgroup SDIO_Transfer_Type 
+/** @defgroup SDIO_Transfer_Type Transfer Type
   * @{
   */
 #define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
@@ -352,7 +350,7 @@
   * @}
   */
 
-/** @defgroup SDIO_DPSM_State 
+/** @defgroup SDIO_DPSM_State DPSM State
   * @{
   */
 #define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
@@ -364,11 +362,11 @@
   * @}
   */
   
-/** @defgroup SDIO_Read_Wait_Mode 
+/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
   * @{
   */
-#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000001)
+#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000001)
 
 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
                                      ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
@@ -376,7 +374,7 @@
   * @}
   */  
 
-/** @defgroup SDIO_Interrupt_sources
+/** @defgroup SDIO_Interrupt_sources Interrupt Sources
   * @{
   */
 #define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
@@ -403,13 +401,11 @@
 #define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
 #define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
 #define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
-
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
 /**
   * @}
   */ 
 
-/** @defgroup SDIO_Flags 
+/** @defgroup SDIO_Flags Flags
   * @{
   */
 #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
@@ -436,124 +432,77 @@
 #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
 #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
 #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
-
-#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
-                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
-                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
-                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
-                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
-                            ((FLAG)  == SDIO_FLAG_RXOVERR)  || \
-                            ((FLAG)  == SDIO_FLAG_CMDREND)  || \
-                            ((FLAG)  == SDIO_FLAG_CMDSENT)  || \
-                            ((FLAG)  == SDIO_FLAG_DATAEND)  || \
-                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
-                            ((FLAG)  == SDIO_FLAG_DBCKEND)  || \
-                            ((FLAG)  == SDIO_FLAG_CMDACT)   || \
-                            ((FLAG)  == SDIO_FLAG_TXACT)    || \
-                            ((FLAG)  == SDIO_FLAG_RXACT)    || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOF)  || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOF)  || \
-                            ((FLAG)  == SDIO_FLAG_TXFIFOE)  || \
-                            ((FLAG)  == SDIO_FLAG_RXFIFOE)  || \
-                            ((FLAG)  == SDIO_FLAG_TXDAVL)   || \
-                            ((FLAG)  == SDIO_FLAG_RXDAVL)   || \
-                            ((FLAG)  == SDIO_FLAG_SDIOIT)   || \
-                            ((FLAG)  == SDIO_FLAG_CEATAEND))
-
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
-
-#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
-                            ((IT)  == SDIO_IT_DCRCFAIL) || \
-                            ((IT)  == SDIO_IT_CTIMEOUT) || \
-                            ((IT)  == SDIO_IT_DTIMEOUT) || \
-                            ((IT)  == SDIO_IT_TXUNDERR) || \
-                            ((IT)  == SDIO_IT_RXOVERR)  || \
-                            ((IT)  == SDIO_IT_CMDREND)  || \
-                            ((IT)  == SDIO_IT_CMDSENT)  || \
-                            ((IT)  == SDIO_IT_DATAEND)  || \
-                            ((IT)  == SDIO_IT_STBITERR) || \
-                            ((IT)  == SDIO_IT_DBCKEND)  || \
-                            ((IT)  == SDIO_IT_CMDACT)   || \
-                            ((IT)  == SDIO_IT_TXACT)    || \
-                            ((IT)  == SDIO_IT_RXACT)    || \
-                            ((IT)  == SDIO_IT_TXFIFOHE) || \
-                            ((IT)  == SDIO_IT_RXFIFOHF) || \
-                            ((IT)  == SDIO_IT_TXFIFOF)  || \
-                            ((IT)  == SDIO_IT_RXFIFOF)  || \
-                            ((IT)  == SDIO_IT_TXFIFOE)  || \
-                            ((IT)  == SDIO_IT_RXFIFOE)  || \
-                            ((IT)  == SDIO_IT_TXDAVL)   || \
-                            ((IT)  == SDIO_IT_RXDAVL)   || \
-                            ((IT)  == SDIO_IT_SDIOIT)   || \
-                            ((IT)  == SDIO_IT_CEATAEND))
-
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */
 
 /**
   * @}
   */
-
-
-/** @defgroup SDIO_Instance_definition 
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
   * @{
-  */ 
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+  */
 
-/**
-  * @}
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
+  * @{
   */
-  
-/* Exported macro ------------------------------------------------------------*/
 /* ------------ SDIO registers bit address in the alias region -------------- */
 #define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
 
 /* --- CLKCR Register ---*/
 /* Alias word address of CLKEN bit */
 #define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
-#define CLKEN_BitNumber           0x08
-#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+#define CLKEN_BITNUMBER           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
 
 /* --- CMD Register ---*/
 /* Alias word address of SDIOSUSPEND bit */
 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BitNumber     0x0B
-#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+#define SDIOSUSPEND_BITNUMBER     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
 
 /* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BitNumber      0x0C
-#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+#define ENCMDCOMPL_BITNUMBER      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
 
 /* Alias word address of NIEN bit */
-#define NIEN_BitNumber            0x0D
-#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+#define NIEN_BITNUMBER            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
 
 /* Alias word address of ATACMD bit */
-#define ATACMD_BitNumber          0x0E
-#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+#define ATACMD_BITNUMBER          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
 
 /* --- DCTRL Register ---*/
 /* Alias word address of DMAEN bit */
 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
-#define DMAEN_BitNumber           0x03
-#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+#define DMAEN_BITNUMBER           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
 
 /* Alias word address of RWSTART bit */
-#define RWSTART_BitNumber         0x08
-#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+#define RWSTART_BITNUMBER         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
 
 /* Alias word address of RWSTOP bit */
-#define RWSTOP_BitNumber          0x09
-#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+#define RWSTOP_BITNUMBER          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
 
 /* Alias word address of RWMOD bit */
-#define RWMOD_BitNumber           0x0A
-#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+#define RWMOD_BITNUMBER           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
 
 /* Alias word address of SDIOEN bit */
-#define SDIOEN_BitNumber          0x0B
-#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+#define SDIOEN_BITNUMBER          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
 
 /* ---------------------- SDIO registers bit mask --------------------------- */
 /* --- CLKCR Register ---*/
@@ -577,41 +526,40 @@
 /* SDIO RESP Registers Address */
 #define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
 
-/* SDIO Intialization Frequency (400KHz max) */
+/* SDIO Initialization Frequency (400KHz max) */
 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
 
 /* SDIO Data Transfer Frequency (25MHz max) */
 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+/**
+  * @}
+  */
 
-/** @defgroup SDIO_Interrupt_Clock
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
- 
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+  * @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+
 /**
   * @brief  Enable the SDIO device.
-  * @param  None   
   * @retval None
   */ 
 #define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SDIO device.
-  * @param  None  
   * @retval None
   */
 #define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
 
 /**
   * @brief  Enable the SDIO DMA transfer.
-  * @param  None  
   * @retval None
   */ 
 #define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SDIO DMA transfer.
-  * @param  None   
   * @retval None
   */
 #define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
@@ -798,102 +746,89 @@
 
 /**
   * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
 
 /**
   * @brief  Disable Start the SD I/O Read Wait operations.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
 
 /**
   * @brief  Enable Start the SD I/O Read Wait operation.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
 
 /**
   * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
 
 /**
   * @brief  Enable the SD I/O Mode Operation.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SD I/O Mode Operation.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
 
 /**
   * @brief  Enable the SD I/O Suspend command sending.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
 
 /**
   * @brief  Disable the SD I/O Suspend command sending.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-    
+
+#if !defined(STM32F446xx)   
 /**
   * @brief  Enable the command completion signal.
-  * @param  None  
   * @retval None
   */    
 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
 
 /**
   * @brief  Disable the command completion signal.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
 
 /**
   * @brief  Enable the CE-ATA interrupt.
-  * @param  None  
   * @retval None
   */    
 #define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
 
 /**
   * @brief  Disable the CE-ATA interrupt.
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
 
 /**
   * @brief  Enable send CE-ATA command (CMD61).
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
 
 /**
   * @brief  Disable send CE-ATA command (CMD61).
-  * @param  None  
   * @retval None
   */  
 #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-  
+#endif /* !defined(STM32F446xx)  */
 /**
   * @}
   */
@@ -903,12 +838,12 @@
   */  
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDIO_Exported_Functions
+/** @addtogroup SDMMC_LL_Exported_Functions
   * @{
   */
   
 /* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDIO_Group1
+/** @addtogroup HAL_SDMMC_LL_Group1
   * @{
   */
 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
@@ -917,7 +852,7 @@
   */
   
 /* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDIO_Group2
+/** @addtogroup HAL_SDMMC_LL_Group2
   * @{
   */
 /* Blocking mode: Polling */
@@ -928,7 +863,7 @@
   */
   
 /* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDIO_Group3
+/** @addtogroup HAL_SDMMC_LL_Group3
   * @{
   */
 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);