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Diff: TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h
- Revision:
- 165:d1b4690b3f8b
- Parent:
- 128:9bcdf88f62b0
--- a/TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h Tue Mar 20 16:15:49 2018 +0000
+++ b/TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h Thu Apr 19 14:31:27 2018 +0100
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32l1xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 01-July-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -68,10 +66,10 @@
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
-#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
/**
* @}
*/
@@ -100,63 +98,63 @@
/* --- CR Register ---*/
/* Alias word address of HSION bit */
#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
/* Alias word address of MSION bit */
#define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION)
-#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_MSION_BIT_NUMBER * 4)))
+#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
/* Alias word address of HSEON bit */
#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
/* Alias word address of CSSON bit */
#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
/* Alias word address of PLLON bit */
#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
/* --- CSR Register ---*/
/* Alias word address of LSION bit */
#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
/* Alias word address of RMVF bit */
#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
/* Alias word address of LSEON bit */
#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON)
-#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
+#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
/* Alias word address of LSEON bit */
#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP)
-#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
+#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
/* Alias word address of RTCEN bit */
#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN)
-#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
+#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
/* Alias word address of RTCRST bit */
#define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST)
-#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCRST_BIT_NUMBER * 4)))
+#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
/**
* @}
*/
/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1)
-#define CSR_REG_INDEX ((uint8_t)2)
+#define CR_REG_INDEX ((uint8_t)1U)
+#define CSR_REG_INDEX ((uint8_t)2U)
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
+#define RCC_FLAG_MASK ((uint8_t)0x1FU)
/**
* @}
@@ -178,8 +176,8 @@
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
((__RANGE__) == RCC_MSIRANGE_1) || \
((__RANGE__) == RCC_MSIRANGE_2) || \
@@ -282,7 +280,7 @@
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
@@ -291,7 +289,7 @@
This parameter can be a value of @ref RCC_MSI_Config */
uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
uint32_t MSIClockRange; /*!< The MSI frequency range.
This parameter can be a value of @ref RCC_MSI_Clock_Range */
@@ -344,12 +342,12 @@
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
-#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
-#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
+#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
+#define RCC_OSCILLATORTYPE_MSI (0x00000010U)
/**
* @}
*/
@@ -357,9 +355,9 @@
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
-#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
-#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
-#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
+#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
+#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */
+#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */
/**
* @}
*/
@@ -367,9 +365,9 @@
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
-#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
-#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
-#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
+#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
+#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */
+#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */
/**
* @}
@@ -378,10 +376,10 @@
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
-#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
/**
* @}
@@ -406,7 +404,7 @@
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
-#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
/**
@@ -416,10 +414,10 @@
/** @defgroup RCC_MSI_Config MSI Config
* @{
*/
-#define RCC_MSI_OFF ((uint32_t)0x00000000)
-#define RCC_MSI_ON ((uint32_t)0x00000001)
+#define RCC_MSI_OFF (0x00000000U)
+#define RCC_MSI_ON (0x00000001U)
-#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */
+#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */
/**
* @}
@@ -428,9 +426,9 @@
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
-#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
-#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
-#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
+#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
+#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
/**
* @}
@@ -439,10 +437,10 @@
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
/**
* @}
@@ -505,7 +503,7 @@
/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
* @{
*/
-#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */
+#define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */
#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
@@ -516,7 +514,7 @@
/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
* @{
*/
-#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */
#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */
@@ -561,7 +559,7 @@
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
-#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO1 (0x00000000U)
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
/**
@@ -620,22 +618,22 @@
* @{
*/
/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
-#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
-#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
/**
* @}
@@ -664,56 +662,56 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
@@ -742,105 +740,105 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_COMP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
@@ -876,49 +874,49 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
@@ -1422,7 +1420,7 @@
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1470,7 +1468,7 @@
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1701,12 +1699,12 @@
{ \
MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
} \
- } while (0)
+ } while (0U)
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
- } while (0)
+ } while (0U)
/** @brief Macro to get the RTC clock source.
* @retval The clock source can be one of the following values:
@@ -1840,7 +1838,7 @@
* @note (*) This bit is available in high and medium+ density devices only.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
/**
* @}
@@ -1878,6 +1876,10 @@
/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
void HAL_RCC_DisableCSS(void);
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
@@ -1886,12 +1888,6 @@
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
/**
* @}
*/
