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TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h@165:d1b4690b3f8b, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 14:31:27 2018 +0100
Revision:
165:d1b4690b3f8b
Parent:
128:9bcdf88f62b0 
mbed library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_rcc.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @brief Header file of RCC HAL module.
<> 128:9bcdf88f62b0 6 ******************************************************************************
<> 128:9bcdf88f62b0 7 * @attention
<> 128:9bcdf88f62b0 8 *
AnnaBridge 165:d1b4690b3f8b 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 12 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 14 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 17 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 19 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 20 * without specific prior written permission.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 32 *
<> 128:9bcdf88f62b0 33 ******************************************************************************
<> 128:9bcdf88f62b0 34 */
<> 128:9bcdf88f62b0 35
<> 128:9bcdf88f62b0 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 37 #ifndef __STM32L1xx_HAL_RCC_H
<> 128:9bcdf88f62b0 38 #define __STM32L1xx_HAL_RCC_H
<> 128:9bcdf88f62b0 39
<> 128:9bcdf88f62b0 40 #ifdef __cplusplus
<> 128:9bcdf88f62b0 41 extern "C" {
<> 128:9bcdf88f62b0 42 #endif
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 45 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 48 * @{
<> 128:9bcdf88f62b0 49 */
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** @addtogroup RCC
<> 128:9bcdf88f62b0 52 * @{
<> 128:9bcdf88f62b0 53 */
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @addtogroup RCC_Private_Constants
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /** @defgroup RCC_Timeout RCC Timeout
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /* Disable Backup domain write protection state change timeout */
<> 128:9bcdf88f62b0 64 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
<> 128:9bcdf88f62b0 65 /* LSE state change timeout */
<> 128:9bcdf88f62b0 66 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<> 128:9bcdf88f62b0 67 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
<> 128:9bcdf88f62b0 68 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 165:d1b4690b3f8b 69 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 165:d1b4690b3f8b 70 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 165:d1b4690b3f8b 71 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 165:d1b4690b3f8b 72 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
<> 128:9bcdf88f62b0 73 /**
<> 128:9bcdf88f62b0 74 * @}
<> 128:9bcdf88f62b0 75 */
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 /** @defgroup RCC_Register_Offset Register offsets
<> 128:9bcdf88f62b0 78 * @{
<> 128:9bcdf88f62b0 79 */
<> 128:9bcdf88f62b0 80 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<> 128:9bcdf88f62b0 81 #define RCC_CR_OFFSET 0x00
<> 128:9bcdf88f62b0 82 #define RCC_CFGR_OFFSET 0x08
<> 128:9bcdf88f62b0 83 #define RCC_CIR_OFFSET 0x0C
<> 128:9bcdf88f62b0 84 #define RCC_CSR_OFFSET 0x34
<> 128:9bcdf88f62b0 85 /**
<> 128:9bcdf88f62b0 86 * @}
<> 128:9bcdf88f62b0 87 */
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
<> 128:9bcdf88f62b0 90 * @brief RCC registers bit address in the alias region
<> 128:9bcdf88f62b0 91 * @{
<> 128:9bcdf88f62b0 92 */
<> 128:9bcdf88f62b0 93 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
<> 128:9bcdf88f62b0 94 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
<> 128:9bcdf88f62b0 95 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
<> 128:9bcdf88f62b0 96 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /* --- CR Register ---*/
<> 128:9bcdf88f62b0 99 /* Alias word address of HSION bit */
<> 128:9bcdf88f62b0 100 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
AnnaBridge 165:d1b4690b3f8b 101 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 102 /* Alias word address of MSION bit */
<> 128:9bcdf88f62b0 103 #define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION)
AnnaBridge 165:d1b4690b3f8b 104 #define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 105 /* Alias word address of HSEON bit */
<> 128:9bcdf88f62b0 106 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
AnnaBridge 165:d1b4690b3f8b 107 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 108 /* Alias word address of CSSON bit */
<> 128:9bcdf88f62b0 109 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
AnnaBridge 165:d1b4690b3f8b 110 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 111 /* Alias word address of PLLON bit */
<> 128:9bcdf88f62b0 112 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
AnnaBridge 165:d1b4690b3f8b 113 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 /* --- CSR Register ---*/
<> 128:9bcdf88f62b0 116 /* Alias word address of LSION bit */
<> 128:9bcdf88f62b0 117 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
AnnaBridge 165:d1b4690b3f8b 118 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 /* Alias word address of RMVF bit */
<> 128:9bcdf88f62b0 121 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
AnnaBridge 165:d1b4690b3f8b 122 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124 /* Alias word address of LSEON bit */
<> 128:9bcdf88f62b0 125 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON)
AnnaBridge 165:d1b4690b3f8b 126 #define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128 /* Alias word address of LSEON bit */
<> 128:9bcdf88f62b0 129 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP)
AnnaBridge 165:d1b4690b3f8b 130 #define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 /* Alias word address of RTCEN bit */
<> 128:9bcdf88f62b0 133 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN)
AnnaBridge 165:d1b4690b3f8b 134 #define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 /* Alias word address of RTCRST bit */
<> 128:9bcdf88f62b0 137 #define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST)
AnnaBridge 165:d1b4690b3f8b 138 #define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 /**
<> 128:9bcdf88f62b0 141 * @}
<> 128:9bcdf88f62b0 142 */
<> 128:9bcdf88f62b0 143
<> 128:9bcdf88f62b0 144 /* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge 165:d1b4690b3f8b 145 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge 165:d1b4690b3f8b 148 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
<> 128:9bcdf88f62b0 149
<> 128:9bcdf88f62b0 150 /* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge 165:d1b4690b3f8b 151 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /* Defines used for Flags */
AnnaBridge 165:d1b4690b3f8b 154 #define CR_REG_INDEX ((uint8_t)1U)
AnnaBridge 165:d1b4690b3f8b 155 #define CSR_REG_INDEX ((uint8_t)2U)
<> 128:9bcdf88f62b0 156
AnnaBridge 165:d1b4690b3f8b 157 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
<> 128:9bcdf88f62b0 158
<> 128:9bcdf88f62b0 159 /**
<> 128:9bcdf88f62b0 160 * @}
<> 128:9bcdf88f62b0 161 */
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 /** @addtogroup RCC_Private_Macros
<> 128:9bcdf88f62b0 164 * @{
<> 128:9bcdf88f62b0 165 */
<> 128:9bcdf88f62b0 166 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
<> 128:9bcdf88f62b0 167 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
<> 128:9bcdf88f62b0 168 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
<> 128:9bcdf88f62b0 169 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
<> 128:9bcdf88f62b0 170 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
<> 128:9bcdf88f62b0 171 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
<> 128:9bcdf88f62b0 172 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
<> 128:9bcdf88f62b0 173 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
<> 128:9bcdf88f62b0 174 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
<> 128:9bcdf88f62b0 175 ((__HSE__) == RCC_HSE_BYPASS))
<> 128:9bcdf88f62b0 176 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
<> 128:9bcdf88f62b0 177 ((__LSE__) == RCC_LSE_BYPASS))
<> 128:9bcdf88f62b0 178 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
AnnaBridge 165:d1b4690b3f8b 179 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge 165:d1b4690b3f8b 180 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
<> 128:9bcdf88f62b0 181 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
<> 128:9bcdf88f62b0 182 ((__RANGE__) == RCC_MSIRANGE_1) || \
<> 128:9bcdf88f62b0 183 ((__RANGE__) == RCC_MSIRANGE_2) || \
<> 128:9bcdf88f62b0 184 ((__RANGE__) == RCC_MSIRANGE_3) || \
<> 128:9bcdf88f62b0 185 ((__RANGE__) == RCC_MSIRANGE_4) || \
<> 128:9bcdf88f62b0 186 ((__RANGE__) == RCC_MSIRANGE_5) || \
<> 128:9bcdf88f62b0 187 ((__RANGE__) == RCC_MSIRANGE_6))
<> 128:9bcdf88f62b0 188 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
<> 128:9bcdf88f62b0 189 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
<> 128:9bcdf88f62b0 190
<> 128:9bcdf88f62b0 191 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
<> 128:9bcdf88f62b0 192 ((__PLL__) == RCC_PLL_ON))
<> 128:9bcdf88f62b0 193 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
<> 128:9bcdf88f62b0 194 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
<> 128:9bcdf88f62b0 195
<> 128:9bcdf88f62b0 196 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \
<> 128:9bcdf88f62b0 197 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \
<> 128:9bcdf88f62b0 198 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
<> 128:9bcdf88f62b0 199 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
<> 128:9bcdf88f62b0 200 ((__MUL__) == RCC_PLL_MUL48))
<> 128:9bcdf88f62b0 201 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
<> 128:9bcdf88f62b0 202 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
<> 128:9bcdf88f62b0 203 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
<> 128:9bcdf88f62b0 204 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
<> 128:9bcdf88f62b0 205 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
<> 128:9bcdf88f62b0 206 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
<> 128:9bcdf88f62b0 207 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
<> 128:9bcdf88f62b0 208 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<> 128:9bcdf88f62b0 209 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \
<> 128:9bcdf88f62b0 210 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
<> 128:9bcdf88f62b0 211 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
<> 128:9bcdf88f62b0 212 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<> 128:9bcdf88f62b0 213 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
<> 128:9bcdf88f62b0 214 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
<> 128:9bcdf88f62b0 215 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
<> 128:9bcdf88f62b0 216 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
<> 128:9bcdf88f62b0 217 ((__HCLK__) == RCC_SYSCLK_DIV512))
<> 128:9bcdf88f62b0 218 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
<> 128:9bcdf88f62b0 219 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
<> 128:9bcdf88f62b0 220 ((__PCLK__) == RCC_HCLK_DIV16))
<> 128:9bcdf88f62b0 221 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
<> 128:9bcdf88f62b0 222 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
<> 128:9bcdf88f62b0 223 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
<> 128:9bcdf88f62b0 224 ((__DIV__) == RCC_MCODIV_16))
<> 128:9bcdf88f62b0 225 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
<> 128:9bcdf88f62b0 226 || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
<> 128:9bcdf88f62b0 227 || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
<> 128:9bcdf88f62b0 228 || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
<> 128:9bcdf88f62b0 229 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
<> 128:9bcdf88f62b0 230 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
<> 128:9bcdf88f62b0 231 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
<> 128:9bcdf88f62b0 232 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
<> 128:9bcdf88f62b0 233 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
<> 128:9bcdf88f62b0 234 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
<> 128:9bcdf88f62b0 235 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237 /**
<> 128:9bcdf88f62b0 238 * @}
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 242
<> 128:9bcdf88f62b0 243 /** @defgroup RCC_Exported_Types RCC Exported Types
<> 128:9bcdf88f62b0 244 * @{
<> 128:9bcdf88f62b0 245 */
<> 128:9bcdf88f62b0 246
<> 128:9bcdf88f62b0 247 /**
<> 128:9bcdf88f62b0 248 * @brief RCC PLL configuration structure definition
<> 128:9bcdf88f62b0 249 */
<> 128:9bcdf88f62b0 250 typedef struct
<> 128:9bcdf88f62b0 251 {
<> 128:9bcdf88f62b0 252 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
<> 128:9bcdf88f62b0 253 This parameter can be a value of @ref RCC_PLL_Config */
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
<> 128:9bcdf88f62b0 256 This parameter must be a value of @ref RCC_PLL_Clock_Source */
<> 128:9bcdf88f62b0 257
<> 128:9bcdf88f62b0 258 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
<> 128:9bcdf88f62b0 259 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
<> 128:9bcdf88f62b0 260
<> 128:9bcdf88f62b0 261 uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
<> 128:9bcdf88f62b0 262 This parameter must be a value of @ref RCC_PLL_Division_Factor*/
<> 128:9bcdf88f62b0 263 } RCC_PLLInitTypeDef;
<> 128:9bcdf88f62b0 264
<> 128:9bcdf88f62b0 265 /**
<> 128:9bcdf88f62b0 266 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<> 128:9bcdf88f62b0 267 */
<> 128:9bcdf88f62b0 268 typedef struct
<> 128:9bcdf88f62b0 269 {
<> 128:9bcdf88f62b0 270 uint32_t OscillatorType; /*!< The oscillators to be configured.
<> 128:9bcdf88f62b0 271 This parameter can be a value of @ref RCC_Oscillator_Type */
<> 128:9bcdf88f62b0 272
<> 128:9bcdf88f62b0 273 uint32_t HSEState; /*!< The new state of the HSE.
<> 128:9bcdf88f62b0 274 This parameter can be a value of @ref RCC_HSE_Config */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 uint32_t LSEState; /*!< The new state of the LSE.
<> 128:9bcdf88f62b0 277 This parameter can be a value of @ref RCC_LSE_Config */
<> 128:9bcdf88f62b0 278
<> 128:9bcdf88f62b0 279 uint32_t HSIState; /*!< The new state of the HSI.
<> 128:9bcdf88f62b0 280 This parameter can be a value of @ref RCC_HSI_Config */
<> 128:9bcdf88f62b0 281
<> 128:9bcdf88f62b0 282 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 165:d1b4690b3f8b 283 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
<> 128:9bcdf88f62b0 284
<> 128:9bcdf88f62b0 285 uint32_t LSIState; /*!< The new state of the LSI.
<> 128:9bcdf88f62b0 286 This parameter can be a value of @ref RCC_LSI_Config */
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 uint32_t MSIState; /*!< The new state of the MSI.
<> 128:9bcdf88f62b0 289 This parameter can be a value of @ref RCC_MSI_Config */
<> 128:9bcdf88f62b0 290
<> 128:9bcdf88f62b0 291 uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge 165:d1b4690b3f8b 292 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
<> 128:9bcdf88f62b0 293
<> 128:9bcdf88f62b0 294 uint32_t MSIClockRange; /*!< The MSI frequency range.
<> 128:9bcdf88f62b0 295 This parameter can be a value of @ref RCC_MSI_Clock_Range */
<> 128:9bcdf88f62b0 296
<> 128:9bcdf88f62b0 297 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
<> 128:9bcdf88f62b0 298
<> 128:9bcdf88f62b0 299 } RCC_OscInitTypeDef;
<> 128:9bcdf88f62b0 300
<> 128:9bcdf88f62b0 301 /**
<> 128:9bcdf88f62b0 302 * @brief RCC System, AHB and APB busses clock configuration structure definition
<> 128:9bcdf88f62b0 303 */
<> 128:9bcdf88f62b0 304 typedef struct
<> 128:9bcdf88f62b0 305 {
<> 128:9bcdf88f62b0 306 uint32_t ClockType; /*!< The clock to be configured.
<> 128:9bcdf88f62b0 307 This parameter can be a value of @ref RCC_System_Clock_Type */
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<> 128:9bcdf88f62b0 310 This parameter can be a value of @ref RCC_System_Clock_Source */
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<> 128:9bcdf88f62b0 313 This parameter can be a value of @ref RCC_AHB_Clock_Source */
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<> 128:9bcdf88f62b0 316 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<> 128:9bcdf88f62b0 317
<> 128:9bcdf88f62b0 318 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<> 128:9bcdf88f62b0 319 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<> 128:9bcdf88f62b0 320 } RCC_ClkInitTypeDef;
<> 128:9bcdf88f62b0 321
<> 128:9bcdf88f62b0 322 /**
<> 128:9bcdf88f62b0 323 * @}
<> 128:9bcdf88f62b0 324 */
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 327 /** @defgroup RCC_Exported_Constants RCC Exported Constants
<> 128:9bcdf88f62b0 328 * @{
<> 128:9bcdf88f62b0 329 */
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<> 128:9bcdf88f62b0 332 * @{
<> 128:9bcdf88f62b0 333 */
<> 128:9bcdf88f62b0 334
<> 128:9bcdf88f62b0 335 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
<> 128:9bcdf88f62b0 336 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
<> 128:9bcdf88f62b0 337
<> 128:9bcdf88f62b0 338 /**
<> 128:9bcdf88f62b0 339 * @}
<> 128:9bcdf88f62b0 340 */
<> 128:9bcdf88f62b0 341
<> 128:9bcdf88f62b0 342 /** @defgroup RCC_Oscillator_Type Oscillator Type
<> 128:9bcdf88f62b0 343 * @{
<> 128:9bcdf88f62b0 344 */
AnnaBridge 165:d1b4690b3f8b 345 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
AnnaBridge 165:d1b4690b3f8b 346 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
AnnaBridge 165:d1b4690b3f8b 347 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
AnnaBridge 165:d1b4690b3f8b 348 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
AnnaBridge 165:d1b4690b3f8b 349 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
AnnaBridge 165:d1b4690b3f8b 350 #define RCC_OSCILLATORTYPE_MSI (0x00000010U)
<> 128:9bcdf88f62b0 351 /**
<> 128:9bcdf88f62b0 352 * @}
<> 128:9bcdf88f62b0 353 */
<> 128:9bcdf88f62b0 354
<> 128:9bcdf88f62b0 355 /** @defgroup RCC_HSE_Config HSE Config
<> 128:9bcdf88f62b0 356 * @{
<> 128:9bcdf88f62b0 357 */
AnnaBridge 165:d1b4690b3f8b 358 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
AnnaBridge 165:d1b4690b3f8b 359 #define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */
AnnaBridge 165:d1b4690b3f8b 360 #define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */
<> 128:9bcdf88f62b0 361 /**
<> 128:9bcdf88f62b0 362 * @}
<> 128:9bcdf88f62b0 363 */
<> 128:9bcdf88f62b0 364
<> 128:9bcdf88f62b0 365 /** @defgroup RCC_LSE_Config LSE Config
<> 128:9bcdf88f62b0 366 * @{
<> 128:9bcdf88f62b0 367 */
AnnaBridge 165:d1b4690b3f8b 368 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
AnnaBridge 165:d1b4690b3f8b 369 #define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */
AnnaBridge 165:d1b4690b3f8b 370 #define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */
<> 128:9bcdf88f62b0 371
<> 128:9bcdf88f62b0 372 /**
<> 128:9bcdf88f62b0 373 * @}
<> 128:9bcdf88f62b0 374 */
<> 128:9bcdf88f62b0 375
<> 128:9bcdf88f62b0 376 /** @defgroup RCC_HSI_Config HSI Config
<> 128:9bcdf88f62b0 377 * @{
<> 128:9bcdf88f62b0 378 */
AnnaBridge 165:d1b4690b3f8b 379 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
<> 128:9bcdf88f62b0 380 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
<> 128:9bcdf88f62b0 381
AnnaBridge 165:d1b4690b3f8b 382 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
<> 128:9bcdf88f62b0 383
<> 128:9bcdf88f62b0 384 /**
<> 128:9bcdf88f62b0 385 * @}
<> 128:9bcdf88f62b0 386 */
<> 128:9bcdf88f62b0 387
<> 128:9bcdf88f62b0 388 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
<> 128:9bcdf88f62b0 389 * @{
<> 128:9bcdf88f62b0 390 */
<> 128:9bcdf88f62b0 391
<> 128:9bcdf88f62b0 392 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
<> 128:9bcdf88f62b0 393 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
<> 128:9bcdf88f62b0 394 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
<> 128:9bcdf88f62b0 395 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
<> 128:9bcdf88f62b0 396 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
<> 128:9bcdf88f62b0 397 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
<> 128:9bcdf88f62b0 398 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 /**
<> 128:9bcdf88f62b0 401 * @}
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 /** @defgroup RCC_LSI_Config LSI Config
<> 128:9bcdf88f62b0 405 * @{
<> 128:9bcdf88f62b0 406 */
AnnaBridge 165:d1b4690b3f8b 407 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
<> 128:9bcdf88f62b0 408 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
<> 128:9bcdf88f62b0 409
<> 128:9bcdf88f62b0 410 /**
<> 128:9bcdf88f62b0 411 * @}
<> 128:9bcdf88f62b0 412 */
<> 128:9bcdf88f62b0 413
<> 128:9bcdf88f62b0 414 /** @defgroup RCC_MSI_Config MSI Config
<> 128:9bcdf88f62b0 415 * @{
<> 128:9bcdf88f62b0 416 */
AnnaBridge 165:d1b4690b3f8b 417 #define RCC_MSI_OFF (0x00000000U)
AnnaBridge 165:d1b4690b3f8b 418 #define RCC_MSI_ON (0x00000001U)
<> 128:9bcdf88f62b0 419
AnnaBridge 165:d1b4690b3f8b 420 #define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */
<> 128:9bcdf88f62b0 421
<> 128:9bcdf88f62b0 422 /**
<> 128:9bcdf88f62b0 423 * @}
<> 128:9bcdf88f62b0 424 */
<> 128:9bcdf88f62b0 425
<> 128:9bcdf88f62b0 426 /** @defgroup RCC_PLL_Config PLL Config
<> 128:9bcdf88f62b0 427 * @{
<> 128:9bcdf88f62b0 428 */
AnnaBridge 165:d1b4690b3f8b 429 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
AnnaBridge 165:d1b4690b3f8b 430 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
AnnaBridge 165:d1b4690b3f8b 431 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
<> 128:9bcdf88f62b0 432
<> 128:9bcdf88f62b0 433 /**
<> 128:9bcdf88f62b0 434 * @}
<> 128:9bcdf88f62b0 435 */
<> 128:9bcdf88f62b0 436
<> 128:9bcdf88f62b0 437 /** @defgroup RCC_System_Clock_Type System Clock Type
<> 128:9bcdf88f62b0 438 * @{
<> 128:9bcdf88f62b0 439 */
AnnaBridge 165:d1b4690b3f8b 440 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
AnnaBridge 165:d1b4690b3f8b 441 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
AnnaBridge 165:d1b4690b3f8b 442 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
AnnaBridge 165:d1b4690b3f8b 443 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
<> 128:9bcdf88f62b0 444
<> 128:9bcdf88f62b0 445 /**
<> 128:9bcdf88f62b0 446 * @}
<> 128:9bcdf88f62b0 447 */
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 /** @defgroup RCC_System_Clock_Source System Clock Source
<> 128:9bcdf88f62b0 450 * @{
<> 128:9bcdf88f62b0 451 */
<> 128:9bcdf88f62b0 452 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */
<> 128:9bcdf88f62b0 453 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
<> 128:9bcdf88f62b0 454 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
<> 128:9bcdf88f62b0 455 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
<> 128:9bcdf88f62b0 456
<> 128:9bcdf88f62b0 457 /**
<> 128:9bcdf88f62b0 458 * @}
<> 128:9bcdf88f62b0 459 */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<> 128:9bcdf88f62b0 462 * @{
<> 128:9bcdf88f62b0 463 */
<> 128:9bcdf88f62b0 464 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
<> 128:9bcdf88f62b0 465 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
<> 128:9bcdf88f62b0 466 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
<> 128:9bcdf88f62b0 467 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
<> 128:9bcdf88f62b0 468
<> 128:9bcdf88f62b0 469 /**
<> 128:9bcdf88f62b0 470 * @}
<> 128:9bcdf88f62b0 471 */
<> 128:9bcdf88f62b0 472
<> 128:9bcdf88f62b0 473 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<> 128:9bcdf88f62b0 474 * @{
<> 128:9bcdf88f62b0 475 */
<> 128:9bcdf88f62b0 476 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
<> 128:9bcdf88f62b0 477 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
<> 128:9bcdf88f62b0 478 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
<> 128:9bcdf88f62b0 479 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
<> 128:9bcdf88f62b0 480 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
<> 128:9bcdf88f62b0 481 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
<> 128:9bcdf88f62b0 482 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
<> 128:9bcdf88f62b0 483 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
<> 128:9bcdf88f62b0 484 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
<> 128:9bcdf88f62b0 485
<> 128:9bcdf88f62b0 486 /**
<> 128:9bcdf88f62b0 487 * @}
<> 128:9bcdf88f62b0 488 */
<> 128:9bcdf88f62b0 489
<> 128:9bcdf88f62b0 490 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
<> 128:9bcdf88f62b0 491 * @{
<> 128:9bcdf88f62b0 492 */
<> 128:9bcdf88f62b0 493 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
<> 128:9bcdf88f62b0 494 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
<> 128:9bcdf88f62b0 495 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
<> 128:9bcdf88f62b0 496 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
<> 128:9bcdf88f62b0 497 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 498
<> 128:9bcdf88f62b0 499 /**
<> 128:9bcdf88f62b0 500 * @}
<> 128:9bcdf88f62b0 501 */
<> 128:9bcdf88f62b0 502
<> 128:9bcdf88f62b0 503 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
<> 128:9bcdf88f62b0 504 * @{
<> 128:9bcdf88f62b0 505 */
AnnaBridge 165:d1b4690b3f8b 506 #define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */
<> 128:9bcdf88f62b0 507 #define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
<> 128:9bcdf88f62b0 508 #define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
<> 128:9bcdf88f62b0 509 #define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
<> 128:9bcdf88f62b0 510 /**
<> 128:9bcdf88f62b0 511 * @}
<> 128:9bcdf88f62b0 512 */
<> 128:9bcdf88f62b0 513
<> 128:9bcdf88f62b0 514 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
<> 128:9bcdf88f62b0 515 * @{
<> 128:9bcdf88f62b0 516 */
AnnaBridge 165:d1b4690b3f8b 517 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */
<> 128:9bcdf88f62b0 518 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
<> 128:9bcdf88f62b0 519 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
<> 128:9bcdf88f62b0 520 #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */
<> 128:9bcdf88f62b0 521 #define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */
<> 128:9bcdf88f62b0 522 #define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */
<> 128:9bcdf88f62b0 523 #define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */
<> 128:9bcdf88f62b0 524 #define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */
<> 128:9bcdf88f62b0 525 /**
<> 128:9bcdf88f62b0 526 * @}
<> 128:9bcdf88f62b0 527 */
<> 128:9bcdf88f62b0 528
<> 128:9bcdf88f62b0 529 /** @defgroup RCC_PLL_Division_Factor PLL Division Factor
<> 128:9bcdf88f62b0 530 * @{
<> 128:9bcdf88f62b0 531 */
<> 128:9bcdf88f62b0 532
<> 128:9bcdf88f62b0 533 #define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
<> 128:9bcdf88f62b0 534 #define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
<> 128:9bcdf88f62b0 535 #define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
<> 128:9bcdf88f62b0 536
<> 128:9bcdf88f62b0 537 /**
<> 128:9bcdf88f62b0 538 * @}
<> 128:9bcdf88f62b0 539 */
<> 128:9bcdf88f62b0 540
<> 128:9bcdf88f62b0 541 /** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor
<> 128:9bcdf88f62b0 542 * @{
<> 128:9bcdf88f62b0 543 */
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
<> 128:9bcdf88f62b0 546 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
<> 128:9bcdf88f62b0 547 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
<> 128:9bcdf88f62b0 548 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
<> 128:9bcdf88f62b0 549 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
<> 128:9bcdf88f62b0 550 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
<> 128:9bcdf88f62b0 551 #define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
<> 128:9bcdf88f62b0 552 #define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
<> 128:9bcdf88f62b0 553 #define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
<> 128:9bcdf88f62b0 554
<> 128:9bcdf88f62b0 555 /**
<> 128:9bcdf88f62b0 556 * @}
<> 128:9bcdf88f62b0 557 */
<> 128:9bcdf88f62b0 558
<> 128:9bcdf88f62b0 559 /** @defgroup RCC_MCO_Index MCO Index
<> 128:9bcdf88f62b0 560 * @{
<> 128:9bcdf88f62b0 561 */
AnnaBridge 165:d1b4690b3f8b 562 #define RCC_MCO1 (0x00000000U)
<> 128:9bcdf88f62b0 563 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /**
<> 128:9bcdf88f62b0 566 * @}
<> 128:9bcdf88f62b0 567 */
<> 128:9bcdf88f62b0 568
<> 128:9bcdf88f62b0 569 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
<> 128:9bcdf88f62b0 570 * @{
<> 128:9bcdf88f62b0 571 */
<> 128:9bcdf88f62b0 572 #define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
<> 128:9bcdf88f62b0 573 #define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
<> 128:9bcdf88f62b0 574 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
<> 128:9bcdf88f62b0 575 #define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
<> 128:9bcdf88f62b0 576 #define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
<> 128:9bcdf88f62b0 577
<> 128:9bcdf88f62b0 578 /**
<> 128:9bcdf88f62b0 579 * @}
<> 128:9bcdf88f62b0 580 */
<> 128:9bcdf88f62b0 581
<> 128:9bcdf88f62b0 582 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
<> 128:9bcdf88f62b0 583 * @{
<> 128:9bcdf88f62b0 584 */
<> 128:9bcdf88f62b0 585 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<> 128:9bcdf88f62b0 586 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
<> 128:9bcdf88f62b0 587 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
<> 128:9bcdf88f62b0 588 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
<> 128:9bcdf88f62b0 589 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
<> 128:9bcdf88f62b0 590 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
<> 128:9bcdf88f62b0 591 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
<> 128:9bcdf88f62b0 592 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
<> 128:9bcdf88f62b0 593
<> 128:9bcdf88f62b0 594 /**
<> 128:9bcdf88f62b0 595 * @}
<> 128:9bcdf88f62b0 596 */
<> 128:9bcdf88f62b0 597 /** @defgroup RCC_Interrupt Interrupts
<> 128:9bcdf88f62b0 598 * @{
<> 128:9bcdf88f62b0 599 */
<> 128:9bcdf88f62b0 600 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
<> 128:9bcdf88f62b0 601 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
<> 128:9bcdf88f62b0 602 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
<> 128:9bcdf88f62b0 603 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
<> 128:9bcdf88f62b0 604 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
<> 128:9bcdf88f62b0 605 #define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */
<> 128:9bcdf88f62b0 606 #define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */
<> 128:9bcdf88f62b0 607 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
<> 128:9bcdf88f62b0 608 /**
<> 128:9bcdf88f62b0 609 * @}
<> 128:9bcdf88f62b0 610 */
<> 128:9bcdf88f62b0 611
<> 128:9bcdf88f62b0 612 /** @defgroup RCC_Flag Flags
<> 128:9bcdf88f62b0 613 * Elements values convention: XXXYYYYYb
<> 128:9bcdf88f62b0 614 * - YYYYY : Flag position in the register
<> 128:9bcdf88f62b0 615 * - XXX : Register index
<> 128:9bcdf88f62b0 616 * - 001: CR register
<> 128:9bcdf88f62b0 617 * - 010: CSR register
<> 128:9bcdf88f62b0 618 * @{
<> 128:9bcdf88f62b0 619 */
<> 128:9bcdf88f62b0 620 /* Flags in the CR register */
AnnaBridge 165:d1b4690b3f8b 621 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
AnnaBridge 165:d1b4690b3f8b 622 #define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
AnnaBridge 165:d1b4690b3f8b 623 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
AnnaBridge 165:d1b4690b3f8b 624 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
<> 128:9bcdf88f62b0 625
<> 128:9bcdf88f62b0 626 /* Flags in the CSR register */
AnnaBridge 165:d1b4690b3f8b 627 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
AnnaBridge 165:d1b4690b3f8b 628 #define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
AnnaBridge 165:d1b4690b3f8b 629 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
AnnaBridge 165:d1b4690b3f8b 630 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
AnnaBridge 165:d1b4690b3f8b 631 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
AnnaBridge 165:d1b4690b3f8b 632 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
AnnaBridge 165:d1b4690b3f8b 633 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
AnnaBridge 165:d1b4690b3f8b 634 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
AnnaBridge 165:d1b4690b3f8b 635 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
AnnaBridge 165:d1b4690b3f8b 636 #define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
<> 128:9bcdf88f62b0 637
<> 128:9bcdf88f62b0 638 /**
<> 128:9bcdf88f62b0 639 * @}
<> 128:9bcdf88f62b0 640 */
<> 128:9bcdf88f62b0 641
<> 128:9bcdf88f62b0 642 /**
<> 128:9bcdf88f62b0 643 * @}
<> 128:9bcdf88f62b0 644 */
<> 128:9bcdf88f62b0 645
<> 128:9bcdf88f62b0 646 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 647
<> 128:9bcdf88f62b0 648 /** @defgroup RCC_Exported_Macros RCC Exported Macros
<> 128:9bcdf88f62b0 649 * @{
<> 128:9bcdf88f62b0 650 */
<> 128:9bcdf88f62b0 651
<> 128:9bcdf88f62b0 652 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
<> 128:9bcdf88f62b0 653 * @brief Enable or disable the AHB1 peripheral clock.
<> 128:9bcdf88f62b0 654 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 655 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 656 * using it.
<> 128:9bcdf88f62b0 657 * @{
<> 128:9bcdf88f62b0 658 */
<> 128:9bcdf88f62b0 659 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 660 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 661 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
<> 128:9bcdf88f62b0 662 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 663 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
<> 128:9bcdf88f62b0 664 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 665 } while(0U)
<> 128:9bcdf88f62b0 666 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 667 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 668 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
<> 128:9bcdf88f62b0 669 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 670 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
<> 128:9bcdf88f62b0 671 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 672 } while(0U)
<> 128:9bcdf88f62b0 673 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 674 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 675 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
<> 128:9bcdf88f62b0 676 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 677 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
<> 128:9bcdf88f62b0 678 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 679 } while(0U)
<> 128:9bcdf88f62b0 680 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 681 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 128:9bcdf88f62b0 683 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 128:9bcdf88f62b0 685 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 686 } while(0U)
<> 128:9bcdf88f62b0 687 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 688 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
<> 128:9bcdf88f62b0 690 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
<> 128:9bcdf88f62b0 692 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 693 } while(0U)
<> 128:9bcdf88f62b0 694 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 695 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 696 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<> 128:9bcdf88f62b0 697 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<> 128:9bcdf88f62b0 699 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 700 } while(0U)
<> 128:9bcdf88f62b0 701 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 702 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 703 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<> 128:9bcdf88f62b0 704 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 705 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<> 128:9bcdf88f62b0 706 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 707 } while(0U)
<> 128:9bcdf88f62b0 708 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 709 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<> 128:9bcdf88f62b0 711 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<> 128:9bcdf88f62b0 713 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 714 } while(0U)
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
<> 128:9bcdf88f62b0 717 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
<> 128:9bcdf88f62b0 718 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
<> 128:9bcdf88f62b0 719 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
<> 128:9bcdf88f62b0 720 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
<> 128:9bcdf88f62b0 721
<> 128:9bcdf88f62b0 722 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
<> 128:9bcdf88f62b0 723 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
<> 128:9bcdf88f62b0 724 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
<> 128:9bcdf88f62b0 725
<> 128:9bcdf88f62b0 726 /**
<> 128:9bcdf88f62b0 727 * @}
<> 128:9bcdf88f62b0 728 */
<> 128:9bcdf88f62b0 729
<> 128:9bcdf88f62b0 730 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
<> 128:9bcdf88f62b0 731 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 128:9bcdf88f62b0 732 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 733 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 734 * using it.
<> 128:9bcdf88f62b0 735 * @{
<> 128:9bcdf88f62b0 736 */
<> 128:9bcdf88f62b0 737 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 738 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 739 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 128:9bcdf88f62b0 740 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 741 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 128:9bcdf88f62b0 742 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 743 } while(0U)
<> 128:9bcdf88f62b0 744 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 745 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 746 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 128:9bcdf88f62b0 747 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 748 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 128:9bcdf88f62b0 749 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 750 } while(0U)
<> 128:9bcdf88f62b0 751 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 752 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 753 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 128:9bcdf88f62b0 754 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 755 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 128:9bcdf88f62b0 756 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 757 } while(0U)
<> 128:9bcdf88f62b0 758 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 759 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 760 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 128:9bcdf88f62b0 761 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 762 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 128:9bcdf88f62b0 763 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 764 } while(0U)
<> 128:9bcdf88f62b0 765 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 766 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 767 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 128:9bcdf88f62b0 768 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 769 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 128:9bcdf88f62b0 770 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 771 } while(0U)
<> 128:9bcdf88f62b0 772 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 773 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 774 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<> 128:9bcdf88f62b0 775 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 776 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<> 128:9bcdf88f62b0 777 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 778 } while(0U)
<> 128:9bcdf88f62b0 779 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 780 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 128:9bcdf88f62b0 782 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 128:9bcdf88f62b0 784 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 785 } while(0U)
<> 128:9bcdf88f62b0 786 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 787 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 788 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 128:9bcdf88f62b0 789 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 790 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 128:9bcdf88f62b0 791 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 792 } while(0U)
<> 128:9bcdf88f62b0 793 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 794 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 128:9bcdf88f62b0 796 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 128:9bcdf88f62b0 798 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 799 } while(0U)
<> 128:9bcdf88f62b0 800 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 801 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 802 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 128:9bcdf88f62b0 803 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 804 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 128:9bcdf88f62b0 805 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 806 } while(0U)
<> 128:9bcdf88f62b0 807 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 808 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 809 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 128:9bcdf88f62b0 810 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 811 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 128:9bcdf88f62b0 812 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 813 } while(0U)
<> 128:9bcdf88f62b0 814 #define __HAL_RCC_USB_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 815 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 128:9bcdf88f62b0 817 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 128:9bcdf88f62b0 819 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 820 } while(0U)
<> 128:9bcdf88f62b0 821 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 822 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 823 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<> 128:9bcdf88f62b0 824 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 825 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<> 128:9bcdf88f62b0 826 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 827 } while(0U)
<> 128:9bcdf88f62b0 828 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 829 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 830 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 128:9bcdf88f62b0 831 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 832 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 128:9bcdf88f62b0 833 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 834 } while(0U)
<> 128:9bcdf88f62b0 835 #define __HAL_RCC_COMP_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 836 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 837 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
<> 128:9bcdf88f62b0 838 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 839 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
<> 128:9bcdf88f62b0 840 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 841 } while(0U)
<> 128:9bcdf88f62b0 842
<> 128:9bcdf88f62b0 843
<> 128:9bcdf88f62b0 844 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<> 128:9bcdf88f62b0 845 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<> 128:9bcdf88f62b0 846 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<> 128:9bcdf88f62b0 847 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 128:9bcdf88f62b0 848 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 128:9bcdf88f62b0 849 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<> 128:9bcdf88f62b0 850 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<> 128:9bcdf88f62b0 851 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<> 128:9bcdf88f62b0 852 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<> 128:9bcdf88f62b0 853 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<> 128:9bcdf88f62b0 854 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<> 128:9bcdf88f62b0 855 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
<> 128:9bcdf88f62b0 856 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<> 128:9bcdf88f62b0 857 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 128:9bcdf88f62b0 858 #define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
<> 128:9bcdf88f62b0 859
<> 128:9bcdf88f62b0 860 /**
<> 128:9bcdf88f62b0 861 * @}
<> 128:9bcdf88f62b0 862 */
<> 128:9bcdf88f62b0 863
<> 128:9bcdf88f62b0 864 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
<> 128:9bcdf88f62b0 865 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 128:9bcdf88f62b0 866 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 867 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 868 * using it.
<> 128:9bcdf88f62b0 869 * @{
<> 128:9bcdf88f62b0 870 */
<> 128:9bcdf88f62b0 871 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 872 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 873 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<> 128:9bcdf88f62b0 874 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 875 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<> 128:9bcdf88f62b0 876 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 877 } while(0U)
<> 128:9bcdf88f62b0 878 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 879 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 880 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 128:9bcdf88f62b0 881 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 882 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 128:9bcdf88f62b0 883 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 884 } while(0U)
<> 128:9bcdf88f62b0 885 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 886 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 887 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 128:9bcdf88f62b0 888 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 889 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 128:9bcdf88f62b0 890 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 891 } while(0U)
<> 128:9bcdf88f62b0 892 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 893 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 894 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 128:9bcdf88f62b0 895 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 896 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 128:9bcdf88f62b0 897 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 898 } while(0U)
<> 128:9bcdf88f62b0 899 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 900 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 901 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 128:9bcdf88f62b0 902 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 903 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 128:9bcdf88f62b0 904 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 905 } while(0U)
<> 128:9bcdf88f62b0 906 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 907 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 908 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 128:9bcdf88f62b0 909 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 910 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 128:9bcdf88f62b0 911 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 912 } while(0U)
<> 128:9bcdf88f62b0 913 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
<> 128:9bcdf88f62b0 914 __IO uint32_t tmpreg; \
<> 128:9bcdf88f62b0 915 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 128:9bcdf88f62b0 916 /* Delay after an RCC peripheral clock enabling */\
<> 128:9bcdf88f62b0 917 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 128:9bcdf88f62b0 918 UNUSED(tmpreg); \
AnnaBridge 165:d1b4690b3f8b 919 } while(0U)
<> 128:9bcdf88f62b0 920
<> 128:9bcdf88f62b0 921 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
<> 128:9bcdf88f62b0 922 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<> 128:9bcdf88f62b0 923 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
<> 128:9bcdf88f62b0 924 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<> 128:9bcdf88f62b0 925 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<> 128:9bcdf88f62b0 926 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<> 128:9bcdf88f62b0 927 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<> 128:9bcdf88f62b0 928
<> 128:9bcdf88f62b0 929 /**
<> 128:9bcdf88f62b0 930 * @}
<> 128:9bcdf88f62b0 931 */
<> 128:9bcdf88f62b0 932
<> 128:9bcdf88f62b0 933 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
<> 128:9bcdf88f62b0 934 * @brief Force or release AHB peripheral reset.
<> 128:9bcdf88f62b0 935 * @{
<> 128:9bcdf88f62b0 936 */
<> 128:9bcdf88f62b0 937 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
<> 128:9bcdf88f62b0 938 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
<> 128:9bcdf88f62b0 939 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
<> 128:9bcdf88f62b0 940 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
<> 128:9bcdf88f62b0 941 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
<> 128:9bcdf88f62b0 942 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
<> 128:9bcdf88f62b0 943
<> 128:9bcdf88f62b0 944 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
<> 128:9bcdf88f62b0 945 #define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
<> 128:9bcdf88f62b0 946 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
<> 128:9bcdf88f62b0 947
<> 128:9bcdf88f62b0 948 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
<> 128:9bcdf88f62b0 949 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
<> 128:9bcdf88f62b0 950 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
<> 128:9bcdf88f62b0 951 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
<> 128:9bcdf88f62b0 952 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
<> 128:9bcdf88f62b0 953 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
<> 128:9bcdf88f62b0 954
<> 128:9bcdf88f62b0 955 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
<> 128:9bcdf88f62b0 956 #define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
<> 128:9bcdf88f62b0 957 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
<> 128:9bcdf88f62b0 958
<> 128:9bcdf88f62b0 959 /**
<> 128:9bcdf88f62b0 960 * @}
<> 128:9bcdf88f62b0 961 */
<> 128:9bcdf88f62b0 962
<> 128:9bcdf88f62b0 963 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
<> 128:9bcdf88f62b0 964 * @brief Force or release APB1 peripheral reset.
<> 128:9bcdf88f62b0 965 * @{
<> 128:9bcdf88f62b0 966 */
<> 128:9bcdf88f62b0 967 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<> 128:9bcdf88f62b0 968 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
<> 128:9bcdf88f62b0 969 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
<> 128:9bcdf88f62b0 970 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<> 128:9bcdf88f62b0 971 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 128:9bcdf88f62b0 972 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 128:9bcdf88f62b0 973 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
<> 128:9bcdf88f62b0 974 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<> 128:9bcdf88f62b0 975 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
<> 128:9bcdf88f62b0 976 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<> 128:9bcdf88f62b0 977 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
<> 128:9bcdf88f62b0 978 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<> 128:9bcdf88f62b0 979 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<> 128:9bcdf88f62b0 980 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
<> 128:9bcdf88f62b0 981 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 128:9bcdf88f62b0 982 #define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
<> 128:9bcdf88f62b0 983
<> 128:9bcdf88f62b0 984 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
<> 128:9bcdf88f62b0 985 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<> 128:9bcdf88f62b0 986 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<> 128:9bcdf88f62b0 987 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<> 128:9bcdf88f62b0 988 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 128:9bcdf88f62b0 989 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 128:9bcdf88f62b0 990 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<> 128:9bcdf88f62b0 991 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<> 128:9bcdf88f62b0 992 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<> 128:9bcdf88f62b0 993 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<> 128:9bcdf88f62b0 994 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<> 128:9bcdf88f62b0 995 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<> 128:9bcdf88f62b0 996 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<> 128:9bcdf88f62b0 997 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<> 128:9bcdf88f62b0 998 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 128:9bcdf88f62b0 999 #define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
<> 128:9bcdf88f62b0 1000
<> 128:9bcdf88f62b0 1001 /**
<> 128:9bcdf88f62b0 1002 * @}
<> 128:9bcdf88f62b0 1003 */
<> 128:9bcdf88f62b0 1004
<> 128:9bcdf88f62b0 1005 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
<> 128:9bcdf88f62b0 1006 * @brief Force or release APB1 peripheral reset.
<> 128:9bcdf88f62b0 1007 * @{
<> 128:9bcdf88f62b0 1008 */
<> 128:9bcdf88f62b0 1009 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<> 128:9bcdf88f62b0 1010 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
<> 128:9bcdf88f62b0 1011 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
<> 128:9bcdf88f62b0 1012 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
<> 128:9bcdf88f62b0 1013 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
<> 128:9bcdf88f62b0 1014 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
<> 128:9bcdf88f62b0 1015 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
<> 128:9bcdf88f62b0 1016 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
<> 128:9bcdf88f62b0 1017
<> 128:9bcdf88f62b0 1018 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
<> 128:9bcdf88f62b0 1019 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
<> 128:9bcdf88f62b0 1020 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<> 128:9bcdf88f62b0 1021 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
<> 128:9bcdf88f62b0 1022 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<> 128:9bcdf88f62b0 1023 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
<> 128:9bcdf88f62b0 1024 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<> 128:9bcdf88f62b0 1025 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<> 128:9bcdf88f62b0 1026
<> 128:9bcdf88f62b0 1027 /**
<> 128:9bcdf88f62b0 1028 * @}
<> 128:9bcdf88f62b0 1029 */
<> 128:9bcdf88f62b0 1030
<> 128:9bcdf88f62b0 1031 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
<> 128:9bcdf88f62b0 1032 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1033 * power consumption.
<> 128:9bcdf88f62b0 1034 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1035 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1036 * @{
<> 128:9bcdf88f62b0 1037 */
<> 128:9bcdf88f62b0 1038 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
<> 128:9bcdf88f62b0 1039 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
<> 128:9bcdf88f62b0 1040 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
<> 128:9bcdf88f62b0 1041 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
<> 128:9bcdf88f62b0 1042 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
<> 128:9bcdf88f62b0 1043
<> 128:9bcdf88f62b0 1044 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
<> 128:9bcdf88f62b0 1045 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
<> 128:9bcdf88f62b0 1046 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
<> 128:9bcdf88f62b0 1047
<> 128:9bcdf88f62b0 1048 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
<> 128:9bcdf88f62b0 1049 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
<> 128:9bcdf88f62b0 1050 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
<> 128:9bcdf88f62b0 1051 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
<> 128:9bcdf88f62b0 1052 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
<> 128:9bcdf88f62b0 1053
<> 128:9bcdf88f62b0 1054 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
<> 128:9bcdf88f62b0 1055 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
<> 128:9bcdf88f62b0 1056 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
<> 128:9bcdf88f62b0 1057
<> 128:9bcdf88f62b0 1058 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1059 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1060 * power consumption.
<> 128:9bcdf88f62b0 1061 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1062 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1063 */
<> 128:9bcdf88f62b0 1064 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
<> 128:9bcdf88f62b0 1065 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
<> 128:9bcdf88f62b0 1066 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
<> 128:9bcdf88f62b0 1067 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
<> 128:9bcdf88f62b0 1068 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
<> 128:9bcdf88f62b0 1069 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
<> 128:9bcdf88f62b0 1070 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
<> 128:9bcdf88f62b0 1071 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
<> 128:9bcdf88f62b0 1072 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
<> 128:9bcdf88f62b0 1073 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
<> 128:9bcdf88f62b0 1074 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
<> 128:9bcdf88f62b0 1075 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
<> 128:9bcdf88f62b0 1076 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
<> 128:9bcdf88f62b0 1077 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
<> 128:9bcdf88f62b0 1078 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
<> 128:9bcdf88f62b0 1079
<> 128:9bcdf88f62b0 1080 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
<> 128:9bcdf88f62b0 1081 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
<> 128:9bcdf88f62b0 1082 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
<> 128:9bcdf88f62b0 1083 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
<> 128:9bcdf88f62b0 1084 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
<> 128:9bcdf88f62b0 1085 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
<> 128:9bcdf88f62b0 1086 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
<> 128:9bcdf88f62b0 1087 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
<> 128:9bcdf88f62b0 1088 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
<> 128:9bcdf88f62b0 1089 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
<> 128:9bcdf88f62b0 1090 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
<> 128:9bcdf88f62b0 1091 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
<> 128:9bcdf88f62b0 1092 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
<> 128:9bcdf88f62b0 1093 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
<> 128:9bcdf88f62b0 1094 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
<> 128:9bcdf88f62b0 1095
<> 128:9bcdf88f62b0 1096 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1097 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1098 * power consumption.
<> 128:9bcdf88f62b0 1099 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1100 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1101 */
<> 128:9bcdf88f62b0 1102 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
<> 128:9bcdf88f62b0 1103 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
<> 128:9bcdf88f62b0 1104 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
<> 128:9bcdf88f62b0 1105 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
<> 128:9bcdf88f62b0 1106 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
<> 128:9bcdf88f62b0 1107 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
<> 128:9bcdf88f62b0 1108 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
<> 128:9bcdf88f62b0 1109
<> 128:9bcdf88f62b0 1110 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
<> 128:9bcdf88f62b0 1111 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
<> 128:9bcdf88f62b0 1112 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
<> 128:9bcdf88f62b0 1113 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
<> 128:9bcdf88f62b0 1114 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
<> 128:9bcdf88f62b0 1115 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
<> 128:9bcdf88f62b0 1116 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
<> 128:9bcdf88f62b0 1117
<> 128:9bcdf88f62b0 1118 /**
<> 128:9bcdf88f62b0 1119 * @}
<> 128:9bcdf88f62b0 1120 */
<> 128:9bcdf88f62b0 1121
<> 128:9bcdf88f62b0 1122 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
<> 128:9bcdf88f62b0 1123 * @brief Get the enable or disable status of the AHB peripheral clock.
<> 128:9bcdf88f62b0 1124 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 1125 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 1126 * using it.
<> 128:9bcdf88f62b0 1127 * @{
<> 128:9bcdf88f62b0 1128 */
<> 128:9bcdf88f62b0 1129
<> 128:9bcdf88f62b0 1130 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
<> 128:9bcdf88f62b0 1131 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
<> 128:9bcdf88f62b0 1132 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
<> 128:9bcdf88f62b0 1133 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
<> 128:9bcdf88f62b0 1134 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
<> 128:9bcdf88f62b0 1135 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
<> 128:9bcdf88f62b0 1136 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
<> 128:9bcdf88f62b0 1137 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
<> 128:9bcdf88f62b0 1138 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
<> 128:9bcdf88f62b0 1139 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
<> 128:9bcdf88f62b0 1140 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
<> 128:9bcdf88f62b0 1141 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
<> 128:9bcdf88f62b0 1142 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
<> 128:9bcdf88f62b0 1143 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
<> 128:9bcdf88f62b0 1144 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
<> 128:9bcdf88f62b0 1145 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
<> 128:9bcdf88f62b0 1146
<> 128:9bcdf88f62b0 1147 /**
<> 128:9bcdf88f62b0 1148 * @}
<> 128:9bcdf88f62b0 1149 */
<> 128:9bcdf88f62b0 1150
<> 128:9bcdf88f62b0 1151 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<> 128:9bcdf88f62b0 1152 * @brief Get the enable or disable status of the APB1 peripheral clock.
<> 128:9bcdf88f62b0 1153 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 1154 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 1155 * using it.
<> 128:9bcdf88f62b0 1156 * @{
<> 128:9bcdf88f62b0 1157 */
<> 128:9bcdf88f62b0 1158
<> 128:9bcdf88f62b0 1159 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<> 128:9bcdf88f62b0 1160 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<> 128:9bcdf88f62b0 1161 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<> 128:9bcdf88f62b0 1162 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 128:9bcdf88f62b0 1163 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 128:9bcdf88f62b0 1164 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
<> 128:9bcdf88f62b0 1165 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<> 128:9bcdf88f62b0 1166 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<> 128:9bcdf88f62b0 1167 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<> 128:9bcdf88f62b0 1168 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<> 128:9bcdf88f62b0 1169 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<> 128:9bcdf88f62b0 1170 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
<> 128:9bcdf88f62b0 1171 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
<> 128:9bcdf88f62b0 1172 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<> 128:9bcdf88f62b0 1173 #define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != RESET)
<> 128:9bcdf88f62b0 1174 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<> 128:9bcdf88f62b0 1175 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
<> 128:9bcdf88f62b0 1176 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
<> 128:9bcdf88f62b0 1177 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 128:9bcdf88f62b0 1178 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 128:9bcdf88f62b0 1179 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
<> 128:9bcdf88f62b0 1180 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<> 128:9bcdf88f62b0 1181 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<> 128:9bcdf88f62b0 1182 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<> 128:9bcdf88f62b0 1183 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
<> 128:9bcdf88f62b0 1184 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<> 128:9bcdf88f62b0 1185 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
<> 128:9bcdf88f62b0 1186 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
<> 128:9bcdf88f62b0 1187 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
<> 128:9bcdf88f62b0 1188 #define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == RESET)
<> 128:9bcdf88f62b0 1189
<> 128:9bcdf88f62b0 1190 /**
<> 128:9bcdf88f62b0 1191 * @}
<> 128:9bcdf88f62b0 1192 */
<> 128:9bcdf88f62b0 1193
<> 128:9bcdf88f62b0 1194 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<> 128:9bcdf88f62b0 1195 * @brief Get the enable or disable status of the APB2 peripheral clock.
<> 128:9bcdf88f62b0 1196 * @note After reset, the peripheral clock (used for registers read/write access)
<> 128:9bcdf88f62b0 1197 * is disabled and the application software has to enable this clock before
<> 128:9bcdf88f62b0 1198 * using it.
<> 128:9bcdf88f62b0 1199 * @{
<> 128:9bcdf88f62b0 1200 */
<> 128:9bcdf88f62b0 1201
<> 128:9bcdf88f62b0 1202 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
<> 128:9bcdf88f62b0 1203 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
<> 128:9bcdf88f62b0 1204 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
<> 128:9bcdf88f62b0 1205 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
<> 128:9bcdf88f62b0 1206 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<> 128:9bcdf88f62b0 1207 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<> 128:9bcdf88f62b0 1208 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
<> 128:9bcdf88f62b0 1209 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
<> 128:9bcdf88f62b0 1210 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
<> 128:9bcdf88f62b0 1211 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
<> 128:9bcdf88f62b0 1212 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
<> 128:9bcdf88f62b0 1213 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<> 128:9bcdf88f62b0 1214 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
<> 128:9bcdf88f62b0 1215 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<> 128:9bcdf88f62b0 1216
<> 128:9bcdf88f62b0 1217 /**
<> 128:9bcdf88f62b0 1218 * @}
<> 128:9bcdf88f62b0 1219 */
<> 128:9bcdf88f62b0 1220
<> 128:9bcdf88f62b0 1221 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status
<> 128:9bcdf88f62b0 1222 * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1223 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1224 * power consumption.
<> 128:9bcdf88f62b0 1225 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1226 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1227 * @{
<> 128:9bcdf88f62b0 1228 */
<> 128:9bcdf88f62b0 1229
<> 128:9bcdf88f62b0 1230 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != RESET)
<> 128:9bcdf88f62b0 1231 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != RESET)
<> 128:9bcdf88f62b0 1232 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != RESET)
<> 128:9bcdf88f62b0 1233 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != RESET)
<> 128:9bcdf88f62b0 1234 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != RESET)
<> 128:9bcdf88f62b0 1235 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != RESET)
<> 128:9bcdf88f62b0 1236 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != RESET)
<> 128:9bcdf88f62b0 1237 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != RESET)
<> 128:9bcdf88f62b0 1238 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == RESET)
<> 128:9bcdf88f62b0 1239 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == RESET)
<> 128:9bcdf88f62b0 1240 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == RESET)
<> 128:9bcdf88f62b0 1241 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == RESET)
<> 128:9bcdf88f62b0 1242 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == RESET)
<> 128:9bcdf88f62b0 1243 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == RESET)
<> 128:9bcdf88f62b0 1244 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == RESET)
<> 128:9bcdf88f62b0 1245 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == RESET)
<> 128:9bcdf88f62b0 1246
<> 128:9bcdf88f62b0 1247 /**
<> 128:9bcdf88f62b0 1248 * @}
<> 128:9bcdf88f62b0 1249 */
<> 128:9bcdf88f62b0 1250
<> 128:9bcdf88f62b0 1251 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
<> 128:9bcdf88f62b0 1252 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1253 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1254 * power consumption.
<> 128:9bcdf88f62b0 1255 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1256 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1257 * @{
<> 128:9bcdf88f62b0 1258 */
<> 128:9bcdf88f62b0 1259
<> 128:9bcdf88f62b0 1260 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
<> 128:9bcdf88f62b0 1261 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
<> 128:9bcdf88f62b0 1262 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
<> 128:9bcdf88f62b0 1263 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
<> 128:9bcdf88f62b0 1264 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
<> 128:9bcdf88f62b0 1265 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
<> 128:9bcdf88f62b0 1266 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
<> 128:9bcdf88f62b0 1267 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
<> 128:9bcdf88f62b0 1268 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
<> 128:9bcdf88f62b0 1269 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
<> 128:9bcdf88f62b0 1270 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
<> 128:9bcdf88f62b0 1271 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != RESET)
<> 128:9bcdf88f62b0 1272 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
<> 128:9bcdf88f62b0 1273 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
<> 128:9bcdf88f62b0 1274 #define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != RESET)
<> 128:9bcdf88f62b0 1275 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
<> 128:9bcdf88f62b0 1276 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
<> 128:9bcdf88f62b0 1277 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
<> 128:9bcdf88f62b0 1278 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
<> 128:9bcdf88f62b0 1279 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
<> 128:9bcdf88f62b0 1280 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
<> 128:9bcdf88f62b0 1281 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
<> 128:9bcdf88f62b0 1282 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
<> 128:9bcdf88f62b0 1283 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
<> 128:9bcdf88f62b0 1284 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
<> 128:9bcdf88f62b0 1285 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
<> 128:9bcdf88f62b0 1286 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == RESET)
<> 128:9bcdf88f62b0 1287 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
<> 128:9bcdf88f62b0 1288 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
<> 128:9bcdf88f62b0 1289 #define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == RESET)
<> 128:9bcdf88f62b0 1290
<> 128:9bcdf88f62b0 1291 /**
<> 128:9bcdf88f62b0 1292 * @}
<> 128:9bcdf88f62b0 1293 */
<> 128:9bcdf88f62b0 1294
<> 128:9bcdf88f62b0 1295 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
<> 128:9bcdf88f62b0 1296 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
<> 128:9bcdf88f62b0 1297 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 128:9bcdf88f62b0 1298 * power consumption.
<> 128:9bcdf88f62b0 1299 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 128:9bcdf88f62b0 1300 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 128:9bcdf88f62b0 1301 * @{
<> 128:9bcdf88f62b0 1302 */
<> 128:9bcdf88f62b0 1303
<> 128:9bcdf88f62b0 1304 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
<> 128:9bcdf88f62b0 1305 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
<> 128:9bcdf88f62b0 1306 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
<> 128:9bcdf88f62b0 1307 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
<> 128:9bcdf88f62b0 1308 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
<> 128:9bcdf88f62b0 1309 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
<> 128:9bcdf88f62b0 1310 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
<> 128:9bcdf88f62b0 1311 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
<> 128:9bcdf88f62b0 1312 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
<> 128:9bcdf88f62b0 1313 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
<> 128:9bcdf88f62b0 1314 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
<> 128:9bcdf88f62b0 1315 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
<> 128:9bcdf88f62b0 1316 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
<> 128:9bcdf88f62b0 1317 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
<> 128:9bcdf88f62b0 1318
<> 128:9bcdf88f62b0 1319 /**
<> 128:9bcdf88f62b0 1320 * @}
<> 128:9bcdf88f62b0 1321 */
<> 128:9bcdf88f62b0 1322
<> 128:9bcdf88f62b0 1323 /** @defgroup RCC_HSI_Configuration HSI Configuration
<> 128:9bcdf88f62b0 1324 * @{
<> 128:9bcdf88f62b0 1325 */
<> 128:9bcdf88f62b0 1326
<> 128:9bcdf88f62b0 1327 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<> 128:9bcdf88f62b0 1328 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<> 128:9bcdf88f62b0 1329 * @note HSI can not be stopped if it is used as system clock source. In this case,
<> 128:9bcdf88f62b0 1330 * you have to select another source of the system clock then stop the HSI.
<> 128:9bcdf88f62b0 1331 * @note After enabling the HSI, the application software should wait on HSIRDY
<> 128:9bcdf88f62b0 1332 * flag to be set indicating that HSI clock is stable and can be used as
<> 128:9bcdf88f62b0 1333 * system clock source.
<> 128:9bcdf88f62b0 1334 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<> 128:9bcdf88f62b0 1335 * clock cycles.
<> 128:9bcdf88f62b0 1336 */
<> 128:9bcdf88f62b0 1337 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
<> 128:9bcdf88f62b0 1338 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
<> 128:9bcdf88f62b0 1339
<> 128:9bcdf88f62b0 1340 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<> 128:9bcdf88f62b0 1341 * @note The calibration is used to compensate for the variations in voltage
<> 128:9bcdf88f62b0 1342 * and temperature that influence the frequency of the internal HSI RC.
<> 128:9bcdf88f62b0 1343 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
<> 128:9bcdf88f62b0 1344 * (default is RCC_HSICALIBRATION_DEFAULT).
<> 128:9bcdf88f62b0 1345 * This parameter must be a number between 0 and 0x1F.
<> 128:9bcdf88f62b0 1346 */
<> 128:9bcdf88f62b0 1347 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
<> 128:9bcdf88f62b0 1348 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
<> 128:9bcdf88f62b0 1349
<> 128:9bcdf88f62b0 1350 /**
<> 128:9bcdf88f62b0 1351 * @}
<> 128:9bcdf88f62b0 1352 */
<> 128:9bcdf88f62b0 1353
<> 128:9bcdf88f62b0 1354 /** @defgroup RCC_LSI_Configuration LSI Configuration
<> 128:9bcdf88f62b0 1355 * @{
<> 128:9bcdf88f62b0 1356 */
<> 128:9bcdf88f62b0 1357
<> 128:9bcdf88f62b0 1358 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
<> 128:9bcdf88f62b0 1359 * @note After enabling the LSI, the application software should wait on
<> 128:9bcdf88f62b0 1360 * LSIRDY flag to be set indicating that LSI clock is stable and can
<> 128:9bcdf88f62b0 1361 * be used to clock the IWDG and/or the RTC.
<> 128:9bcdf88f62b0 1362 */
<> 128:9bcdf88f62b0 1363 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
<> 128:9bcdf88f62b0 1364
<> 128:9bcdf88f62b0 1365 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
<> 128:9bcdf88f62b0 1366 * @note LSI can not be disabled if the IWDG is running.
<> 128:9bcdf88f62b0 1367 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<> 128:9bcdf88f62b0 1368 * clock cycles.
<> 128:9bcdf88f62b0 1369 */
<> 128:9bcdf88f62b0 1370 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
<> 128:9bcdf88f62b0 1371
<> 128:9bcdf88f62b0 1372 /**
<> 128:9bcdf88f62b0 1373 * @}
<> 128:9bcdf88f62b0 1374 */
<> 128:9bcdf88f62b0 1375
<> 128:9bcdf88f62b0 1376 /** @defgroup RCC_HSE_Configuration HSE Configuration
<> 128:9bcdf88f62b0 1377 * @{
<> 128:9bcdf88f62b0 1378 */
<> 128:9bcdf88f62b0 1379
<> 128:9bcdf88f62b0 1380 /**
<> 128:9bcdf88f62b0 1381 * @brief Macro to configure the External High Speed oscillator (HSE).
<> 128:9bcdf88f62b0 1382 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 128:9bcdf88f62b0 1383 * supported by this macro. User should request a transition to HSE Off
<> 128:9bcdf88f62b0 1384 * first and then HSE On or HSE Bypass.
<> 128:9bcdf88f62b0 1385 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<> 128:9bcdf88f62b0 1386 * software should wait on HSERDY flag to be set indicating that HSE clock
<> 128:9bcdf88f62b0 1387 * is stable and can be used to clock the PLL and/or system clock.
<> 128:9bcdf88f62b0 1388 * @note HSE state can not be changed if it is used directly or through the
<> 128:9bcdf88f62b0 1389 * PLL as system clock. In this case, you have to select another source
<> 128:9bcdf88f62b0 1390 * of the system clock then change the HSE state (ex. disable it).
<> 128:9bcdf88f62b0 1391 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<> 128:9bcdf88f62b0 1392 * @note This function reset the CSSON bit, so if the clock security system(CSS)
<> 128:9bcdf88f62b0 1393 * was previously enabled you have to enable it again after calling this
<> 128:9bcdf88f62b0 1394 * function.
<> 128:9bcdf88f62b0 1395 * @param __STATE__ specifies the new state of the HSE.
<> 128:9bcdf88f62b0 1396 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1397 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
<> 128:9bcdf88f62b0 1398 * 6 HSE oscillator clock cycles.
<> 128:9bcdf88f62b0 1399 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
<> 128:9bcdf88f62b0 1400 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
<> 128:9bcdf88f62b0 1401 */
<> 128:9bcdf88f62b0 1402 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
<> 128:9bcdf88f62b0 1403 do{ \
<> 128:9bcdf88f62b0 1404 if ((__STATE__) == RCC_HSE_ON) \
<> 128:9bcdf88f62b0 1405 { \
<> 128:9bcdf88f62b0 1406 SET_BIT(RCC->CR, RCC_CR_HSEON); \
<> 128:9bcdf88f62b0 1407 } \
<> 128:9bcdf88f62b0 1408 else if ((__STATE__) == RCC_HSE_OFF) \
<> 128:9bcdf88f62b0 1409 { \
<> 128:9bcdf88f62b0 1410 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<> 128:9bcdf88f62b0 1411 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 128:9bcdf88f62b0 1412 } \
<> 128:9bcdf88f62b0 1413 else if ((__STATE__) == RCC_HSE_BYPASS) \
<> 128:9bcdf88f62b0 1414 { \
<> 128:9bcdf88f62b0 1415 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 128:9bcdf88f62b0 1416 SET_BIT(RCC->CR, RCC_CR_HSEON); \
<> 128:9bcdf88f62b0 1417 } \
<> 128:9bcdf88f62b0 1418 else \
<> 128:9bcdf88f62b0 1419 { \
<> 128:9bcdf88f62b0 1420 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<> 128:9bcdf88f62b0 1421 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 128:9bcdf88f62b0 1422 } \
AnnaBridge 165:d1b4690b3f8b 1423 }while(0U)
<> 128:9bcdf88f62b0 1424
<> 128:9bcdf88f62b0 1425 /**
<> 128:9bcdf88f62b0 1426 * @}
<> 128:9bcdf88f62b0 1427 */
<> 128:9bcdf88f62b0 1428
<> 128:9bcdf88f62b0 1429 /** @defgroup RCC_LSE_Configuration LSE Configuration
<> 128:9bcdf88f62b0 1430 * @{
<> 128:9bcdf88f62b0 1431 */
<> 128:9bcdf88f62b0 1432
<> 128:9bcdf88f62b0 1433 /**
<> 128:9bcdf88f62b0 1434 * @brief Macro to configure the External Low Speed oscillator (LSE).
<> 128:9bcdf88f62b0 1435 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<> 128:9bcdf88f62b0 1436 * @note As the LSE is in the Backup domain and write access is denied to
<> 128:9bcdf88f62b0 1437 * this domain after reset, you have to enable write access using
<> 128:9bcdf88f62b0 1438 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<> 128:9bcdf88f62b0 1439 * (to be done once after reset).
<> 128:9bcdf88f62b0 1440 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<> 128:9bcdf88f62b0 1441 * software should wait on LSERDY flag to be set indicating that LSE clock
<> 128:9bcdf88f62b0 1442 * is stable and can be used to clock the RTC.
<> 128:9bcdf88f62b0 1443 * @param __STATE__ specifies the new state of the LSE.
<> 128:9bcdf88f62b0 1444 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1445 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
<> 128:9bcdf88f62b0 1446 * 6 LSE oscillator clock cycles.
<> 128:9bcdf88f62b0 1447 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
<> 128:9bcdf88f62b0 1448 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
<> 128:9bcdf88f62b0 1449 */
<> 128:9bcdf88f62b0 1450 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
<> 128:9bcdf88f62b0 1451 do{ \
<> 128:9bcdf88f62b0 1452 if ((__STATE__) == RCC_LSE_ON) \
<> 128:9bcdf88f62b0 1453 { \
<> 128:9bcdf88f62b0 1454 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
<> 128:9bcdf88f62b0 1455 } \
<> 128:9bcdf88f62b0 1456 else if ((__STATE__) == RCC_LSE_OFF) \
<> 128:9bcdf88f62b0 1457 { \
<> 128:9bcdf88f62b0 1458 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
<> 128:9bcdf88f62b0 1459 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<> 128:9bcdf88f62b0 1460 } \
<> 128:9bcdf88f62b0 1461 else if ((__STATE__) == RCC_LSE_BYPASS) \
<> 128:9bcdf88f62b0 1462 { \
<> 128:9bcdf88f62b0 1463 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<> 128:9bcdf88f62b0 1464 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
<> 128:9bcdf88f62b0 1465 } \
<> 128:9bcdf88f62b0 1466 else \
<> 128:9bcdf88f62b0 1467 { \
<> 128:9bcdf88f62b0 1468 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
<> 128:9bcdf88f62b0 1469 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<> 128:9bcdf88f62b0 1470 } \
AnnaBridge 165:d1b4690b3f8b 1471 }while(0U)
<> 128:9bcdf88f62b0 1472
<> 128:9bcdf88f62b0 1473 /**
<> 128:9bcdf88f62b0 1474 * @}
<> 128:9bcdf88f62b0 1475 */
<> 128:9bcdf88f62b0 1476
<> 128:9bcdf88f62b0 1477 /** @defgroup RCC_MSI_Configuration MSI Configuration
<> 128:9bcdf88f62b0 1478 * @{
<> 128:9bcdf88f62b0 1479 */
<> 128:9bcdf88f62b0 1480
<> 128:9bcdf88f62b0 1481 /** @brief Macro to enable Internal Multi Speed oscillator (MSI).
<> 128:9bcdf88f62b0 1482 * @note After enabling the MSI, the application software should wait on MSIRDY
<> 128:9bcdf88f62b0 1483 * flag to be set indicating that MSI clock is stable and can be used as
<> 128:9bcdf88f62b0 1484 * system clock source.
<> 128:9bcdf88f62b0 1485 */
<> 128:9bcdf88f62b0 1486 #define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE)
<> 128:9bcdf88f62b0 1487
<> 128:9bcdf88f62b0 1488 /** @brief Macro to disable the Internal Multi Speed oscillator (MSI).
<> 128:9bcdf88f62b0 1489 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
<> 128:9bcdf88f62b0 1490 * It is used (enabled by hardware) as system clock source after startup
<> 128:9bcdf88f62b0 1491 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
<> 128:9bcdf88f62b0 1492 * of the HSE used directly or indirectly as system clock (if the Clock
<> 128:9bcdf88f62b0 1493 * Security System CSS is enabled).
<> 128:9bcdf88f62b0 1494 * @note MSI can not be stopped if it is used as system clock source. In this case,
<> 128:9bcdf88f62b0 1495 * you have to select another source of the system clock then stop the MSI.
<> 128:9bcdf88f62b0 1496 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
<> 128:9bcdf88f62b0 1497 * clock cycles.
<> 128:9bcdf88f62b0 1498 */
<> 128:9bcdf88f62b0 1499 #define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE)
<> 128:9bcdf88f62b0 1500
<> 128:9bcdf88f62b0 1501 /** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value.
<> 128:9bcdf88f62b0 1502 * @note The calibration is used to compensate for the variations in voltage
<> 128:9bcdf88f62b0 1503 * and temperature that influence the frequency of the internal MSI RC.
<> 128:9bcdf88f62b0 1504 * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value.
<> 128:9bcdf88f62b0 1505 * (default is RCC_MSICALIBRATION_DEFAULT).
<> 128:9bcdf88f62b0 1506 * This parameter must be a number between 0 and 0xFF.
<> 128:9bcdf88f62b0 1507 */
<> 128:9bcdf88f62b0 1508 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
<> 128:9bcdf88f62b0 1509 (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
<> 128:9bcdf88f62b0 1510
<> 128:9bcdf88f62b0 1511 /* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
<> 128:9bcdf88f62b0 1512 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is
<> 128:9bcdf88f62b0 1513 * around 2.097 MHz. The MSI clock does not change after wake-up from
<> 128:9bcdf88f62b0 1514 * STOP mode.
<> 128:9bcdf88f62b0 1515 * @note The MSI clock range can be modified on the fly.
<> 128:9bcdf88f62b0 1516 * @param _MSIRANGEVALUE_ specifies the MSI Clock range.
<> 128:9bcdf88f62b0 1517 * This parameter must be one of the following values:
<> 128:9bcdf88f62b0 1518 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
<> 128:9bcdf88f62b0 1519 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
<> 128:9bcdf88f62b0 1520 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
<> 128:9bcdf88f62b0 1521 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
<> 128:9bcdf88f62b0 1522 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
<> 128:9bcdf88f62b0 1523 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
<> 128:9bcdf88f62b0 1524 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
<> 128:9bcdf88f62b0 1525 */
<> 128:9bcdf88f62b0 1526 #define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \
<> 128:9bcdf88f62b0 1527 RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
<> 128:9bcdf88f62b0 1528
<> 128:9bcdf88f62b0 1529 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
<> 128:9bcdf88f62b0 1530 * @retval MSI clock range.
<> 128:9bcdf88f62b0 1531 * This parameter must be one of the following values:
<> 128:9bcdf88f62b0 1532 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz
<> 128:9bcdf88f62b0 1533 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz
<> 128:9bcdf88f62b0 1534 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz
<> 128:9bcdf88f62b0 1535 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz
<> 128:9bcdf88f62b0 1536 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz
<> 128:9bcdf88f62b0 1537 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
<> 128:9bcdf88f62b0 1538 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz
<> 128:9bcdf88f62b0 1539 */
<> 128:9bcdf88f62b0 1540 #define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE))
<> 128:9bcdf88f62b0 1541
<> 128:9bcdf88f62b0 1542 /**
<> 128:9bcdf88f62b0 1543 * @}
<> 128:9bcdf88f62b0 1544 */
<> 128:9bcdf88f62b0 1545
<> 128:9bcdf88f62b0 1546 /** @defgroup RCC_PLL_Configuration PLL Configuration
<> 128:9bcdf88f62b0 1547 * @{
<> 128:9bcdf88f62b0 1548 */
<> 128:9bcdf88f62b0 1549
<> 128:9bcdf88f62b0 1550 /** @brief Macro to enable the main PLL.
<> 128:9bcdf88f62b0 1551 * @note After enabling the main PLL, the application software should wait on
<> 128:9bcdf88f62b0 1552 * PLLRDY flag to be set indicating that PLL clock is stable and can
<> 128:9bcdf88f62b0 1553 * be used as system clock source.
<> 128:9bcdf88f62b0 1554 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<> 128:9bcdf88f62b0 1555 */
<> 128:9bcdf88f62b0 1556 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
<> 128:9bcdf88f62b0 1557
<> 128:9bcdf88f62b0 1558 /** @brief Macro to disable the main PLL.
<> 128:9bcdf88f62b0 1559 * @note The main PLL can not be disabled if it is used as system clock source
<> 128:9bcdf88f62b0 1560 */
<> 128:9bcdf88f62b0 1561 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
<> 128:9bcdf88f62b0 1562
<> 128:9bcdf88f62b0 1563 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<> 128:9bcdf88f62b0 1564 * @note This function must be used only when the main PLL is disabled.
<> 128:9bcdf88f62b0 1565 *
<> 128:9bcdf88f62b0 1566 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
<> 128:9bcdf88f62b0 1567 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1568 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
<> 128:9bcdf88f62b0 1569 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
<> 128:9bcdf88f62b0 1570 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
<> 128:9bcdf88f62b0 1571 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1572 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
<> 128:9bcdf88f62b0 1573 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
<> 128:9bcdf88f62b0 1574 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
<> 128:9bcdf88f62b0 1575 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
<> 128:9bcdf88f62b0 1576 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
<> 128:9bcdf88f62b0 1577 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
<> 128:9bcdf88f62b0 1578 * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24
<> 128:9bcdf88f62b0 1579 * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32
<> 128:9bcdf88f62b0 1580 * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48
<> 128:9bcdf88f62b0 1581 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
<> 128:9bcdf88f62b0 1582 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
<> 128:9bcdf88f62b0 1583 * in Range 3.
<> 128:9bcdf88f62b0 1584 *
<> 128:9bcdf88f62b0 1585 * @param __PLLDIV__ specifies the division factor for PLL VCO input clock
<> 128:9bcdf88f62b0 1586 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1587 * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2
<> 128:9bcdf88f62b0 1588 * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3
<> 128:9bcdf88f62b0 1589 * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4
<> 128:9bcdf88f62b0 1590 *
<> 128:9bcdf88f62b0 1591 */
<> 128:9bcdf88f62b0 1592 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
<> 128:9bcdf88f62b0 1593 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
<> 128:9bcdf88f62b0 1594
<> 128:9bcdf88f62b0 1595 /** @brief Get oscillator clock selected as PLL input clock
<> 128:9bcdf88f62b0 1596 * @retval The clock source used for PLL entry. The returned value can be one
<> 128:9bcdf88f62b0 1597 * of the following:
<> 128:9bcdf88f62b0 1598 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
<> 128:9bcdf88f62b0 1599 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
<> 128:9bcdf88f62b0 1600 */
<> 128:9bcdf88f62b0 1601 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
<> 128:9bcdf88f62b0 1602
<> 128:9bcdf88f62b0 1603 /**
<> 128:9bcdf88f62b0 1604 * @}
<> 128:9bcdf88f62b0 1605 */
<> 128:9bcdf88f62b0 1606
<> 128:9bcdf88f62b0 1607 /** @defgroup RCC_Get_Clock_source Get Clock source
<> 128:9bcdf88f62b0 1608 * @{
<> 128:9bcdf88f62b0 1609 */
<> 128:9bcdf88f62b0 1610
<> 128:9bcdf88f62b0 1611 /**
<> 128:9bcdf88f62b0 1612 * @brief Macro to configure the system clock source.
<> 128:9bcdf88f62b0 1613 * @param __SYSCLKSOURCE__ specifies the system clock source.
<> 128:9bcdf88f62b0 1614 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1615 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
<> 128:9bcdf88f62b0 1616 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
<> 128:9bcdf88f62b0 1617 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
<> 128:9bcdf88f62b0 1618 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
<> 128:9bcdf88f62b0 1619 */
<> 128:9bcdf88f62b0 1620 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<> 128:9bcdf88f62b0 1621 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<> 128:9bcdf88f62b0 1622
<> 128:9bcdf88f62b0 1623 /** @brief Macro to get the clock source used as system clock.
<> 128:9bcdf88f62b0 1624 * @retval The clock source used as system clock. The returned value can be one
<> 128:9bcdf88f62b0 1625 * of the following:
<> 128:9bcdf88f62b0 1626 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock
<> 128:9bcdf88f62b0 1627 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
<> 128:9bcdf88f62b0 1628 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
<> 128:9bcdf88f62b0 1629 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
<> 128:9bcdf88f62b0 1630 */
<> 128:9bcdf88f62b0 1631 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
<> 128:9bcdf88f62b0 1632
<> 128:9bcdf88f62b0 1633 /**
<> 128:9bcdf88f62b0 1634 * @}
<> 128:9bcdf88f62b0 1635 */
<> 128:9bcdf88f62b0 1636
<> 128:9bcdf88f62b0 1637 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<> 128:9bcdf88f62b0 1638 * @{
<> 128:9bcdf88f62b0 1639 */
<> 128:9bcdf88f62b0 1640
<> 128:9bcdf88f62b0 1641 /** @brief Macro to configure the MCO clock.
<> 128:9bcdf88f62b0 1642 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
<> 128:9bcdf88f62b0 1643 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1644 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 128:9bcdf88f62b0 1645 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
<> 128:9bcdf88f62b0 1646 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
<> 128:9bcdf88f62b0 1647 * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock
<> 128:9bcdf88f62b0 1648 * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock
<> 128:9bcdf88f62b0 1649 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock
<> 128:9bcdf88f62b0 1650 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock
<> 128:9bcdf88f62b0 1651 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock
<> 128:9bcdf88f62b0 1652 * @param __MCODIV__ specifies the MCO clock prescaler.
<> 128:9bcdf88f62b0 1653 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1654 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
<> 128:9bcdf88f62b0 1655 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
<> 128:9bcdf88f62b0 1656 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
<> 128:9bcdf88f62b0 1657 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
<> 128:9bcdf88f62b0 1658 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
<> 128:9bcdf88f62b0 1659 */
<> 128:9bcdf88f62b0 1660 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<> 128:9bcdf88f62b0 1661 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
<> 128:9bcdf88f62b0 1662
<> 128:9bcdf88f62b0 1663 /**
<> 128:9bcdf88f62b0 1664 * @}
<> 128:9bcdf88f62b0 1665 */
<> 128:9bcdf88f62b0 1666
<> 128:9bcdf88f62b0 1667 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
<> 128:9bcdf88f62b0 1668 * @{
<> 128:9bcdf88f62b0 1669 */
<> 128:9bcdf88f62b0 1670
<> 128:9bcdf88f62b0 1671 /** @brief Macro to configure the RTC clock (RTCCLK).
<> 128:9bcdf88f62b0 1672 * @note As the RTC clock configuration bits are in the Backup domain and write
<> 128:9bcdf88f62b0 1673 * access is denied to this domain after reset, you have to enable write
<> 128:9bcdf88f62b0 1674 * access using the Power Backup Access macro before to configure
<> 128:9bcdf88f62b0 1675 * the RTC clock source (to be done once after reset).
<> 128:9bcdf88f62b0 1676 * @note Once the RTC clock is configured it cannot be changed unless the
<> 128:9bcdf88f62b0 1677 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
<> 128:9bcdf88f62b0 1678 * a Power On Reset (POR).
<> 128:9bcdf88f62b0 1679 * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
<> 128:9bcdf88f62b0 1680 *
<> 128:9bcdf88f62b0 1681 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
<> 128:9bcdf88f62b0 1682 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1683 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<> 128:9bcdf88f62b0 1684 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<> 128:9bcdf88f62b0 1685 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<> 128:9bcdf88f62b0 1686 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
<> 128:9bcdf88f62b0 1687 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
<> 128:9bcdf88f62b0 1688 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
<> 128:9bcdf88f62b0 1689 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
<> 128:9bcdf88f62b0 1690 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<> 128:9bcdf88f62b0 1691 * work in STOP and STANDBY modes, and can be used as wakeup source.
<> 128:9bcdf88f62b0 1692 * However, when the HSE clock is used as RTC clock source, the RTC
<> 128:9bcdf88f62b0 1693 * cannot be used in STOP and STANDBY modes.
<> 128:9bcdf88f62b0 1694 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<> 128:9bcdf88f62b0 1695 * RTC clock source).
<> 128:9bcdf88f62b0 1696 */
<> 128:9bcdf88f62b0 1697 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
<> 128:9bcdf88f62b0 1698 if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
<> 128:9bcdf88f62b0 1699 { \
<> 128:9bcdf88f62b0 1700 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
<> 128:9bcdf88f62b0 1701 } \
AnnaBridge 165:d1b4690b3f8b 1702 } while (0U)
<> 128:9bcdf88f62b0 1703
<> 128:9bcdf88f62b0 1704 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
<> 128:9bcdf88f62b0 1705 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
<> 128:9bcdf88f62b0 1706 RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
AnnaBridge 165:d1b4690b3f8b 1707 } while (0U)
<> 128:9bcdf88f62b0 1708
<> 128:9bcdf88f62b0 1709 /** @brief Macro to get the RTC clock source.
<> 128:9bcdf88f62b0 1710 * @retval The clock source can be one of the following values:
<> 128:9bcdf88f62b0 1711 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<> 128:9bcdf88f62b0 1712 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<> 128:9bcdf88f62b0 1713 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<> 128:9bcdf88f62b0 1714 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
<> 128:9bcdf88f62b0 1715 */
<> 128:9bcdf88f62b0 1716 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
<> 128:9bcdf88f62b0 1717
<> 128:9bcdf88f62b0 1718 /**
<> 128:9bcdf88f62b0 1719 * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
<> 128:9bcdf88f62b0 1720 *
<> 128:9bcdf88f62b0 1721 * @retval Returned value can be one of the following values:
<> 128:9bcdf88f62b0 1722 * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock
<> 128:9bcdf88f62b0 1723 * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock
<> 128:9bcdf88f62b0 1724 * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock
<> 128:9bcdf88f62b0 1725 * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock
<> 128:9bcdf88f62b0 1726 *
<> 128:9bcdf88f62b0 1727 */
<> 128:9bcdf88f62b0 1728 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
<> 128:9bcdf88f62b0 1729
<> 128:9bcdf88f62b0 1730 /** @brief Macro to enable the the RTC clock.
<> 128:9bcdf88f62b0 1731 * @note These macros must be used only after the RTC clock source was selected.
<> 128:9bcdf88f62b0 1732 */
<> 128:9bcdf88f62b0 1733 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE)
<> 128:9bcdf88f62b0 1734
<> 128:9bcdf88f62b0 1735 /** @brief Macro to disable the the RTC clock.
<> 128:9bcdf88f62b0 1736 * @note These macros must be used only after the RTC clock source was selected.
<> 128:9bcdf88f62b0 1737 */
<> 128:9bcdf88f62b0 1738 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE)
<> 128:9bcdf88f62b0 1739
<> 128:9bcdf88f62b0 1740 /** @brief Macro to force the Backup domain reset.
<> 128:9bcdf88f62b0 1741 * @note This function resets the RTC peripheral (including the backup registers)
<> 128:9bcdf88f62b0 1742 * and the RTC clock source selection in RCC_CSR register.
<> 128:9bcdf88f62b0 1743 * @note The BKPSRAM is not affected by this reset.
<> 128:9bcdf88f62b0 1744 */
<> 128:9bcdf88f62b0 1745 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE)
<> 128:9bcdf88f62b0 1746
<> 128:9bcdf88f62b0 1747 /** @brief Macros to release the Backup domain reset.
<> 128:9bcdf88f62b0 1748 */
<> 128:9bcdf88f62b0 1749 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE)
<> 128:9bcdf88f62b0 1750
<> 128:9bcdf88f62b0 1751 /**
<> 128:9bcdf88f62b0 1752 * @}
<> 128:9bcdf88f62b0 1753 */
<> 128:9bcdf88f62b0 1754
<> 128:9bcdf88f62b0 1755 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<> 128:9bcdf88f62b0 1756 * @brief macros to manage the specified RCC Flags and interrupts.
<> 128:9bcdf88f62b0 1757 * @{
<> 128:9bcdf88f62b0 1758 */
<> 128:9bcdf88f62b0 1759
<> 128:9bcdf88f62b0 1760 /** @brief Enable RCC interrupt.
<> 128:9bcdf88f62b0 1761 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
<> 128:9bcdf88f62b0 1762 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 1763 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<> 128:9bcdf88f62b0 1764 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
<> 128:9bcdf88f62b0 1765 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<> 128:9bcdf88f62b0 1766 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
<> 128:9bcdf88f62b0 1767 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<> 128:9bcdf88f62b0 1768 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<> 128:9bcdf88f62b0 1769 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
<> 128:9bcdf88f62b0 1770 */
<> 128:9bcdf88f62b0 1771 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
<> 128:9bcdf88f62b0 1772
<> 128:9bcdf88f62b0 1773 /** @brief Disable RCC interrupt.
<> 128:9bcdf88f62b0 1774 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
<> 128:9bcdf88f62b0 1775 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 1776 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<> 128:9bcdf88f62b0 1777 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
<> 128:9bcdf88f62b0 1778 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<> 128:9bcdf88f62b0 1779 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
<> 128:9bcdf88f62b0 1780 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<> 128:9bcdf88f62b0 1781 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<> 128:9bcdf88f62b0 1782 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
<> 128:9bcdf88f62b0 1783 */
<> 128:9bcdf88f62b0 1784 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<> 128:9bcdf88f62b0 1785
<> 128:9bcdf88f62b0 1786 /** @brief Clear the RCC's interrupt pending bits.
<> 128:9bcdf88f62b0 1787 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<> 128:9bcdf88f62b0 1788 * This parameter can be any combination of the following values:
<> 128:9bcdf88f62b0 1789 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<> 128:9bcdf88f62b0 1790 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<> 128:9bcdf88f62b0 1791 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<> 128:9bcdf88f62b0 1792 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<> 128:9bcdf88f62b0 1793 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<> 128:9bcdf88f62b0 1794 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<> 128:9bcdf88f62b0 1795 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
<> 128:9bcdf88f62b0 1796 * @arg @ref RCC_IT_CSS Clock Security System interrupt
<> 128:9bcdf88f62b0 1797 */
<> 128:9bcdf88f62b0 1798 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<> 128:9bcdf88f62b0 1799
<> 128:9bcdf88f62b0 1800 /** @brief Check the RCC's interrupt has occurred or not.
<> 128:9bcdf88f62b0 1801 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
<> 128:9bcdf88f62b0 1802 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1803 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<> 128:9bcdf88f62b0 1804 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<> 128:9bcdf88f62b0 1805 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<> 128:9bcdf88f62b0 1806 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<> 128:9bcdf88f62b0 1807 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<> 128:9bcdf88f62b0 1808 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
<> 128:9bcdf88f62b0 1809 * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices)
<> 128:9bcdf88f62b0 1810 * @arg @ref RCC_IT_CSS Clock Security System interrupt
<> 128:9bcdf88f62b0 1811 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 1812 */
<> 128:9bcdf88f62b0 1813 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 128:9bcdf88f62b0 1814
<> 128:9bcdf88f62b0 1815 /** @brief Set RMVF bit to clear the reset flags.
<> 128:9bcdf88f62b0 1816 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
<> 128:9bcdf88f62b0 1817 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
<> 128:9bcdf88f62b0 1818 */
<> 128:9bcdf88f62b0 1819 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
<> 128:9bcdf88f62b0 1820
<> 128:9bcdf88f62b0 1821 /** @brief Check RCC flag is set or not.
<> 128:9bcdf88f62b0 1822 * @param __FLAG__ specifies the flag to check.
<> 128:9bcdf88f62b0 1823 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1824 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
<> 128:9bcdf88f62b0 1825 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready.
<> 128:9bcdf88f62b0 1826 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
<> 128:9bcdf88f62b0 1827 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
<> 128:9bcdf88f62b0 1828 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
<> 128:9bcdf88f62b0 1829 * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*)
<> 128:9bcdf88f62b0 1830 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
<> 128:9bcdf88f62b0 1831 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
<> 128:9bcdf88f62b0 1832 * @arg @ref RCC_FLAG_PINRST Pin reset.
<> 128:9bcdf88f62b0 1833 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
<> 128:9bcdf88f62b0 1834 * @arg @ref RCC_FLAG_SFTRST Software reset.
<> 128:9bcdf88f62b0 1835 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
<> 128:9bcdf88f62b0 1836 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
<> 128:9bcdf88f62b0 1837 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
<> 128:9bcdf88f62b0 1838 * @note (*) This bit is available in high and medium+ density devices only.
<> 128:9bcdf88f62b0 1839 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 1840 */
AnnaBridge 165:d1b4690b3f8b 1841 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
<> 128:9bcdf88f62b0 1842
<> 128:9bcdf88f62b0 1843 /**
<> 128:9bcdf88f62b0 1844 * @}
<> 128:9bcdf88f62b0 1845 */
<> 128:9bcdf88f62b0 1846
<> 128:9bcdf88f62b0 1847 /**
<> 128:9bcdf88f62b0 1848 * @}
<> 128:9bcdf88f62b0 1849 */
<> 128:9bcdf88f62b0 1850
<> 128:9bcdf88f62b0 1851 /* Include RCC HAL Extension module */
<> 128:9bcdf88f62b0 1852 #include "stm32l1xx_hal_rcc_ex.h"
<> 128:9bcdf88f62b0 1853
<> 128:9bcdf88f62b0 1854 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1855 /** @addtogroup RCC_Exported_Functions
<> 128:9bcdf88f62b0 1856 * @{
<> 128:9bcdf88f62b0 1857 */
<> 128:9bcdf88f62b0 1858
<> 128:9bcdf88f62b0 1859 /** @addtogroup RCC_Exported_Functions_Group1
<> 128:9bcdf88f62b0 1860 * @{
<> 128:9bcdf88f62b0 1861 */
<> 128:9bcdf88f62b0 1862
<> 128:9bcdf88f62b0 1863 /* Initialization and de-initialization functions ******************************/
<> 128:9bcdf88f62b0 1864 void HAL_RCC_DeInit(void);
<> 128:9bcdf88f62b0 1865 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<> 128:9bcdf88f62b0 1866 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<> 128:9bcdf88f62b0 1867
<> 128:9bcdf88f62b0 1868 /**
<> 128:9bcdf88f62b0 1869 * @}
<> 128:9bcdf88f62b0 1870 */
<> 128:9bcdf88f62b0 1871
<> 128:9bcdf88f62b0 1872 /** @addtogroup RCC_Exported_Functions_Group2
<> 128:9bcdf88f62b0 1873 * @{
<> 128:9bcdf88f62b0 1874 */
<> 128:9bcdf88f62b0 1875
<> 128:9bcdf88f62b0 1876 /* Peripheral Control functions ************************************************/
<> 128:9bcdf88f62b0 1877 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<> 128:9bcdf88f62b0 1878 void HAL_RCC_EnableCSS(void);
AnnaBridge 165:d1b4690b3f8b 1879 /* CSS NMI IRQ handler */
AnnaBridge 165:d1b4690b3f8b 1880 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 165:d1b4690b3f8b 1881 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 165:d1b4690b3f8b 1882 void HAL_RCC_CSSCallback(void);
<> 128:9bcdf88f62b0 1883 void HAL_RCC_DisableCSS(void);
<> 128:9bcdf88f62b0 1884 uint32_t HAL_RCC_GetSysClockFreq(void);
<> 128:9bcdf88f62b0 1885 uint32_t HAL_RCC_GetHCLKFreq(void);
<> 128:9bcdf88f62b0 1886 uint32_t HAL_RCC_GetPCLK1Freq(void);
<> 128:9bcdf88f62b0 1887 uint32_t HAL_RCC_GetPCLK2Freq(void);
<> 128:9bcdf88f62b0 1888 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<> 128:9bcdf88f62b0 1889 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
<> 128:9bcdf88f62b0 1890
<> 128:9bcdf88f62b0 1891 /**
<> 128:9bcdf88f62b0 1892 * @}
<> 128:9bcdf88f62b0 1893 */
<> 128:9bcdf88f62b0 1894
<> 128:9bcdf88f62b0 1895 /**
<> 128:9bcdf88f62b0 1896 * @}
<> 128:9bcdf88f62b0 1897 */
<> 128:9bcdf88f62b0 1898
<> 128:9bcdf88f62b0 1899 /**
<> 128:9bcdf88f62b0 1900 * @}
<> 128:9bcdf88f62b0 1901 */
<> 128:9bcdf88f62b0 1902
<> 128:9bcdf88f62b0 1903 /**
<> 128:9bcdf88f62b0 1904 * @}
<> 128:9bcdf88f62b0 1905 */
<> 128:9bcdf88f62b0 1906
<> 128:9bcdf88f62b0 1907 #ifdef __cplusplus
<> 128:9bcdf88f62b0 1908 }
<> 128:9bcdf88f62b0 1909 #endif
<> 128:9bcdf88f62b0 1910
<> 128:9bcdf88f62b0 1911 #endif /* __STM32L1xx_HAL_RCC_H */
<> 128:9bcdf88f62b0 1912
<> 128:9bcdf88f62b0 1913 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 128:9bcdf88f62b0 1914