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Diff: TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h
- Revision:
- 168:b9e159c1930a
- Parent:
- 163:e59c8e839560
--- a/TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h Fri May 11 16:51:14 2018 +0100 +++ b/TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h Thu May 24 15:35:55 2018 +0100 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f3xx_ll_dma.h * @author MCD Application Team - * @version V1.4.0 - * @date 16-December-2016 * @brief Header file of DMA LL module. ****************************************************************************** * @attention @@ -77,18 +75,6 @@ */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Constants DMA Private Constants - * @{ - */ -/* Define used to get CSELR register offset */ -#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) - -/* Defines used for the bit position in the register and perform offsets */ -#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U)) -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_Private_Macros DMA Private Macros @@ -261,15 +247,15 @@ /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ -#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */ -#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */ -#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */ -#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */ -#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} @@ -278,7 +264,7 @@ /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** @@ -288,7 +274,7 @@ /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ -#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} @@ -298,7 +284,7 @@ * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ @@ -307,7 +293,7 @@ * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ @@ -315,7 +301,7 @@ /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ -#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** @@ -325,7 +311,7 @@ /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ -#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** @@ -335,7 +321,7 @@ /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ -#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ @@ -973,7 +959,8 @@ /** * @brief Configure the Source and Destination addresses. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr) + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance @@ -999,24 +986,21 @@ /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - SrcAddress); - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - DstAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); } } /** * @brief Set the Memory address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetMemoryAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1032,13 +1016,13 @@ */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** * @brief Set the Peripheral address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetPeriphAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1054,8 +1038,7 @@ */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - PeriphAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); } /** @@ -1075,8 +1058,7 @@ */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } /** @@ -1096,13 +1078,13 @@ */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** * @brief Set the Memory to Memory Source address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1118,13 +1100,13 @@ */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); } /** * @brief Set the Memory to Memory Destination address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: @@ -1140,8 +1122,7 @@ */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA, - MemoryAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** @@ -1161,8 +1142,7 @@ */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, - DMA_CPAR_PA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** @@ -1182,8 +1162,7 @@ */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, - DMA_CMAR_MA)); + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } @@ -1511,7 +1490,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } /** @@ -1522,7 +1501,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } /** @@ -1533,7 +1512,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } /** @@ -1544,7 +1523,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } /** @@ -1555,7 +1534,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } /** @@ -1566,7 +1545,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } /** @@ -1577,7 +1556,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } /** @@ -1588,7 +1567,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } /** @@ -1599,7 +1578,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } /** @@ -1610,7 +1589,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } /** @@ -1621,7 +1600,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } /** @@ -1632,7 +1611,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } /** @@ -1643,7 +1622,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } /** @@ -1654,7 +1633,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } /** @@ -1665,7 +1644,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } /** @@ -1676,7 +1655,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } /** @@ -1687,7 +1666,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } /** @@ -1698,7 +1677,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } /** @@ -1709,7 +1688,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } /** @@ -1720,7 +1699,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } /** @@ -1731,7 +1710,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } /** @@ -1742,7 +1721,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } /** @@ -1753,7 +1732,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } /** @@ -1764,7 +1743,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } /** @@ -1775,7 +1754,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } /** @@ -1786,7 +1765,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } /** @@ -1797,7 +1776,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } /** @@ -1808,7 +1787,7 @@ */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } /**