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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
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Diff: TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h
- Revision:
- 159:7130f322cb7e
- Parent:
- 142:4eea097334d6
--- a/TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h Thu Nov 23 11:44:04 2017 +0000
+++ b/TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h Thu Dec 21 18:20:02 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_smu.h
* @brief Security Management Unit (SMU) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -77,7 +77,6 @@
/** SMU peripheral identifiers. */
typedef enum {
-
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
@@ -127,8 +126,12 @@
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
+#if defined(_SMU_PPUPATD0_CSEN_SHIFT)
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+#endif
+#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
@@ -136,7 +139,9 @@
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
@@ -156,6 +161,167 @@
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+#if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+#endif
+#if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+#endif
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+#endif
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+ smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
+ smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+#endif
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+#if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+#endif
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+#if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
+ smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+#endif
+ smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+ smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
+ smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+ smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2 */
+ smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3 */
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1 */
+ smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
+ smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+ smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+#if defined(_SMU_PPUPATD0_ETH_SHIFT)
+ smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH */
+#endif
+ smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+ smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+ smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2 */
+ smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
+#if defined(_SMU_PPUPATD0_LCD_SHIFT)
+ smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
+#endif
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1 */
+ smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+ smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1 */
+ smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+ smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
+ smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
+#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
+ smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0 */
+#endif
+ smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC */
+ smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
+ smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO */
+#endif
+ smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
+ smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
+ smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
+ smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
+ smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
+ smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
+ smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
+ smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1 */
+ smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
+ smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
+ smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4 */
+ smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5 */
+#if defined(_SMU_PPUPATD1_USB_SHIFT)
+ smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB */
+#endif
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+ smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
+ smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2 */
+ smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+ smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+ smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
+#if defined(_SMU_PPUPATD0_LCD_SHIFT)
+ smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
+#endif
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+ smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+ smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+ smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
+ smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
+ smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+ smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
+
#else
#error "No peripherals defined for SMU for this device configuration."
#endif
@@ -164,7 +330,6 @@
/** SMU peripheral privileged access enablers. */
typedef struct {
-
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
@@ -262,6 +427,154 @@
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for */
+ bool privilegedReserved0 : 1;
+ bool privilegedReserved1 : 1;
+ bool privilegedCMU : 1; /**< Privileged access enabler for */
+ bool privilegedReserved2 : 1;
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for */
+ bool privilegedCRYPTO : 1; /**< Privileged access enabler for */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for */
+ bool privilegedPRS : 1; /**< Privileged access enabler for */
+ bool privilegedEMU : 1; /**< Privileged access enabler for */
+ bool privilegedFPUEH : 1; /**< Privileged access enabler for */
+ bool privilegedReserved3 : 1;
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for */
+ bool privilegedIDAC0 : 1; /**< Privileged access enabler for */
+ bool privilegedMSC : 1; /**< Privileged access enabler for */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for */
+ bool privilegedLEUART : 1; /**< Privileged access enabler for */
+ bool privilegedReserved4 : 1;
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for */
+ bool privilegedReserved5 : 1;
+ bool privilegedReserved6 : 1;
+ bool privilegedReserved7 : 1;
+ bool privilegedReserved8 : 1;
+ bool privilegedRMU : 1; /**< Privileged access enabler for */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for */
+ bool privilegedSMU : 1; /**< Privileged access enabler for */
+
+ bool privilegedReserved9 : 1;
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for */
+ bool privilegedWDOG1 : 1; /**< Privileged access enabler for */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
+ bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2 */
+ bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3 */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
+ bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1 */
+ bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
+ bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1 */
+ bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
+ bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
+ bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
+ bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
+ bool privilegedEBI : 1; /**< Privileged access enabler for EBI */
+ bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
+ bool privilegedETH : 1; /**< Privileged access enabler for ETH */
+ bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
+ bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
+ bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
+ bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
+ bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
+ bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
+ bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1 */
+ bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
+ bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1 */
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
+ bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
+ bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
+ bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0 */
+ bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
+ bool privilegedRTC : 1; /**< Privileged access enabler for RTC */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
+ bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO */
+ bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
+ bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
+ bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
+ bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
+ bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
+ bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
+ bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
+ bool privilegedUART1 : 1; /**< Privileged access enabler for UART1 */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
+ bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
+ bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
+ bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4 */
+ bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5 */
+ bool privilegedUSB : 1; /**< Privileged access enabler for USB */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
+ bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+ bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
+ bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2 */
+ bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
+ bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
+ bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
+ bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
+ bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
+ bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
+ bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
+ bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
+ bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
+ bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
+ bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
+ bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
+ bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
+ bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
+ bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
+ bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+ bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
+
#else
#error "No peripherals defined for SMU for this device configuration"
#endif
@@ -280,13 +593,11 @@
bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
} SMU_Init_TypeDef;
-#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
/** Default SMU initialization struct settings. */
-#define SMU_INIT_DEFAULT { \
- {{0}}, /* No peripherals acsess protected. */ \
- true /* Enable SMU.*/ \
+#define SMU_INIT_DEFAULT { \
+ { { 0 } }, /* No peripherals acsess protected. */ \
+ true /* Enable SMU.*/ \
}
-#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
