Diff: TARGET_UNO_91H/TOOLCHAIN_IAR/RDA5981C.icf

Revision:

172:65be27845400

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_UNO_91H/TOOLCHAIN_IAR/RDA5981C.icf	Wed Feb 20 20:53:29 2019 +0000
@@ -0,0 +1,64 @@
+/* Linker file for the IAR Compiler for ARM */
+/* Specials */
+define symbol RDA_ICACHE_DISABLE    = 0;
+define symbol RDA_PARTITION_INDEX   = 0;
+/* Memory Regions */
+define symbol RDA_IRAM_BASE         = 0x00100000;
+define symbol RDA_IRAM_END          = 0x0011FFFF;
+define symbol RDA_DRAM_BASE         = 0x00180000;
+define symbol RDA_DRAM_END          = 0x001A7FFF;
+define symbol RDA_FLASH_BASE        = 0x14000000;
+define symbol RDA_ICACHE_BASE       = 0x18000000;
+if (0 == RDA_PARTITION_INDEX) {
+  define symbol RDA_PADDR_OFST      = 0x00001000;
+} else {
+  define symbol RDA_PADDR_OFST      = 0x001F5000;
+}
+if (1 == RDA_ICACHE_DISABLE) {
+  define symbol RDA_CODE_BASE       = RDA_FLASH_BASE + RDA_PADDR_OFST;
+} else {
+  define symbol RDA_CODE_BASE       = RDA_ICACHE_BASE + RDA_PADDR_OFST;
+}
+define symbol RDA_CODE_END          = RDA_CODE_BASE + 0x1F3FFF;
+define symbol RDA_AHB1_BASE         = 0x40100000;
+define symbol RDA_MEMC_BASE         = RDA_AHB1_BASE + 0x00000;
+define symbol RDA_MEMC_END          = RDA_AHB1_BASE + 0x1FFFF;
+
+define symbol INTVEC_BASE       = RDA_CODE_BASE;
+define symbol INTVEC_RAM_BASE   = RDA_IRAM_BASE;
+define symbol I_DATA_BASE       = RDA_IRAM_BASE + 0x80;
+define symbol I_DATA_END        = RDA_IRAM_END;
+define symbol D_DATA_BASE       = RDA_DRAM_BASE;
+define symbol D_DATA_END        = RDA_DRAM_END;
+define symbol AES_BASE          = RDA_MEMC_BASE + 0x18C00;
+define symbol AES_END           = RDA_MEMC_BASE + 0x197FF;
+define symbol WLAN_BASE         = RDA_MEMC_BASE + 0x19800;
+define symbol WLAN_END          = RDA_MEMC_END;
+
+/* Stack Size & Heap Size*/
+define symbol CSTACK_SIZE   = 0x00400;
+define symbol HEAP_SIZE     = RDA_DRAM_END - RDA_DRAM_BASE + 1;
+
+/*Memory regions*/
+define memory mem with size = 4G;
+define region ROM_REGION    = mem:[from RDA_CODE_BASE to RDA_CODE_END];
+define region IRAM_REGION   = mem:[from I_DATA_BASE to I_DATA_END];
+define region DRAM_REGION   = mem:[from D_DATA_BASE to D_DATA_END];
+define region AES_REGION    = mem:[from AES_BASE to AES_END];
+define region WLAN_REGION   = mem:[from WLAN_BASE to WLAN_END];
+
+define block CSTACK with alignment = 8, size = CSTACK_SIZE { };
+define block HEAP   with alignment = 8, size = HEAP_SIZE   { };
+define block RW     { readwrite };
+define block ZI     { zi };
+
+initialize by copy  { readwrite };
+do not initialize   { section .noinit };
+
+place at address mem:INTVEC_BASE { readonly section .intvec };
+
+place in ROM_REGION     { readonly };
+place in IRAM_REGION    { block RW, block ZI, block CSTACK};
+place in DRAM_REGION    { block HEAP};
+place in AES_REGION     { section AHB1SMEM0 };
+place in WLAN_REGION    { section AHB1SMEM1 };