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Diff: TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h
- Revision:
- 145:64910690c574
- Parent:
- 128:9bcdf88f62b0
--- a/TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h Thu Jun 08 14:53:05 2017 +0100
+++ b/TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h Wed Jun 21 17:31:38 2017 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.5.0
- * @date 06-May-2016
+ * @version V1.7.1
+ * @date 14-April-2017
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,8 @@
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private types -------------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Types FSMC Private Types
* @{
@@ -270,10 +271,10 @@
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
-#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
-#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
-#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
-#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
+#define FSMC_NORSRAM_BANK1 0x00000000U
+#define FSMC_NORSRAM_BANK2 0x00000002U
+#define FSMC_NORSRAM_BANK3 0x00000004U
+#define FSMC_NORSRAM_BANK4 0x00000006U
/**
* @}
*/
@@ -281,8 +282,8 @@
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
-#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
+#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
+#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
/**
* @}
*/
@@ -290,9 +291,9 @@
/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
-#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
-#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
-#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
+#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
+#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
+#define FSMC_MEMORY_TYPE_NOR 0x00000008U
/**
* @}
*/
@@ -300,9 +301,9 @@
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
* @{
*/
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
/**
* @}
*/
@@ -310,8 +311,8 @@
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
/**
* @}
*/
@@ -319,8 +320,8 @@
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
-#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
+#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
+#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
/**
* @}
*/
@@ -328,8 +329,8 @@
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
/**
* @}
*/
@@ -338,8 +339,8 @@
* @note These values are available only for the STM32F405/415/407/417xx devices.
* @{
*/
-#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
+#define FSMC_WRAP_MODE_DISABLE 0x00000000U
+#define FSMC_WRAP_MODE_ENABLE 0x00000400U
/**
* @}
*/
@@ -347,8 +348,8 @@
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
-#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
-#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
+#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
+#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
/**
* @}
*/
@@ -356,8 +357,8 @@
/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
-#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
+#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
+#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
/**
* @}
*/
@@ -365,8 +366,8 @@
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
-#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
+#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
+#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
/**
* @}
*/
@@ -374,8 +375,8 @@
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
-#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
+#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
+#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
/**
* @}
*/
@@ -383,8 +384,8 @@
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
/**
* @}
*/
@@ -392,7 +393,7 @@
/** @defgroup FSMC_Page_Size FSMC Page Size
* @{
*/
-#define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
+#define FSMC_PAGE_SIZE_NONE 0x00000000U
#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
@@ -406,7 +407,7 @@
* @{
*/
#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
-#define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
+#define FSMC_WRITE_FIFO_ENABLE 0x00000000U
/**
* @}
*/
@@ -414,8 +415,8 @@
/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
-#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
+#define FSMC_WRITE_BURST_DISABLE 0x00000000U
+#define FSMC_WRITE_BURST_ENABLE 0x00080000U
/**
* @}
*/
@@ -424,8 +425,8 @@
* @note These values are available only for the STM32F412Vx/Zx/Rx devices.
* @{
*/
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
/**
* @}
*/
@@ -433,10 +434,10 @@
/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
-#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
-#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
-#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
-#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
+#define FSMC_ACCESS_MODE_A 0x00000000U
+#define FSMC_ACCESS_MODE_B 0x10000000U
+#define FSMC_ACCESS_MODE_C 0x20000000U
+#define FSMC_ACCESS_MODE_D 0x30000000U
/**
* @}
*/
@@ -451,8 +452,8 @@
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
*/
-#define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
-#define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
+#define FSMC_NAND_BANK2 0x00000010U
+#define FSMC_NAND_BANK3 0x00000100U
/**
* @}
*/
@@ -460,8 +461,8 @@
/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
/**
* @}
*/
@@ -469,8 +470,8 @@
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
-#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
-#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
+#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
+#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
/**
* @}
*/
@@ -478,8 +479,8 @@
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
/**
* @}
*/
@@ -487,8 +488,8 @@
/** @defgroup FSMC_ECC FSMC ECC
* @{
*/
-#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
-#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
+#define FSMC_NAND_ECC_DISABLE 0x00000000U
+#define FSMC_NAND_ECC_ENABLE 0x00000040U
/**
* @}
*/
@@ -496,12 +497,12 @@
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
/**
* @}
*/
@@ -513,10 +514,10 @@
/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
* @{
*/
-#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
-#define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
-#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
-#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
+#define FSMC_IT_RISING_EDGE 0x00000008U
+#define FSMC_IT_LEVEL 0x00000010U
+#define FSMC_IT_FALLING_EDGE 0x00000020U
+#define FSMC_IT_REFRESH_ERROR 0x00004000U
/**
* @}
*/
@@ -524,10 +525,10 @@
/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
* @{
*/
-#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
-#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
-#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
+#define FSMC_FLAG_RISING_EDGE 0x00000001U
+#define FSMC_FLAG_LEVEL 0x00000002U
+#define FSMC_FLAG_FALLING_EDGE 0x00000004U
+#define FSMC_FLAG_FEMPT 0x00000040U
/**
* @}
*/
@@ -936,6 +937,7 @@
#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
((SIZE) == FSMC_PAGE_SIZE_128) || \
((SIZE) == FSMC_PAGE_SIZE_256) || \
+ ((SIZE) == FSMC_PAGE_SIZE_512) || \
((SIZE) == FSMC_PAGE_SIZE_1024))
#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
@@ -1030,7 +1032,7 @@
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
* @}
