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TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Parent:
128:9bcdf88f62b0 
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_fsmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
bogdanm 89:552587b429a1 7 * @brief Header file of FSMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @addtogroup FSMC_LL
bogdanm 89:552587b429a1 54 * @{
Kojto 99:dbbf35b96557 55 */
bogdanm 89:552587b429a1 56
AnnaBridge 145:64910690c574 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
AnnaBridge 145:64910690c574 58 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
Kojto 99:dbbf35b96557 59 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 60 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
bogdanm 89:552587b429a1 63
bogdanm 89:552587b429a1 64 /**
Kojto 99:dbbf35b96557 65 * @brief FSMC NORSRAM Configuration Structure definition
bogdanm 89:552587b429a1 66 */
bogdanm 89:552587b429a1 67 typedef struct
bogdanm 89:552587b429a1 68 {
bogdanm 89:552587b429a1 69 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 89:552587b429a1 70 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 89:552587b429a1 71
bogdanm 89:552587b429a1 72 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 89:552587b429a1 73 multiplexed on the data bus or not.
bogdanm 89:552587b429a1 74 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 89:552587b429a1 75
bogdanm 89:552587b429a1 76 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 89:552587b429a1 77 the corresponding memory device.
bogdanm 89:552587b429a1 78 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 89:552587b429a1 79
bogdanm 89:552587b429a1 80 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 81 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 89:552587b429a1 82
bogdanm 89:552587b429a1 83 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 89:552587b429a1 84 valid only with synchronous burst Flash memories.
bogdanm 89:552587b429a1 85 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 89:552587b429a1 88 the Flash memory in burst mode.
bogdanm 89:552587b429a1 89 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 89:552587b429a1 90
bogdanm 89:552587b429a1 91 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 89:552587b429a1 92 memory, valid only when accessing Flash memories in burst mode.
Kojto 122:f9eeca106725 93 This parameter can be a value of @ref FSMC_Wrap_Mode
Kojto 122:f9eeca106725 94 This mode is available only for the STM32F405/407/4015/417xx devices */
bogdanm 89:552587b429a1 95
bogdanm 89:552587b429a1 96 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 89:552587b429a1 97 clock cycle before the wait state or during the wait state,
bogdanm 89:552587b429a1 98 valid only when accessing memories in burst mode.
bogdanm 89:552587b429a1 99 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm 89:552587b429a1 102 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 89:552587b429a1 103
bogdanm 89:552587b429a1 104 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 89:552587b429a1 105 signal, valid for Flash memory access in burst mode.
bogdanm 89:552587b429a1 106 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 89:552587b429a1 107
bogdanm 89:552587b429a1 108 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 89:552587b429a1 109 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 89:552587b429a1 110
bogdanm 89:552587b429a1 111 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 89:552587b429a1 112 valid only with asynchronous Flash memories.
bogdanm 89:552587b429a1 113 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 89:552587b429a1 114
bogdanm 89:552587b429a1 115 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 89:552587b429a1 116 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 89:552587b429a1 117
Kojto 122:f9eeca106725 118 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 122:f9eeca106725 119 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 120 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 121 This parameter can be a value of @ref FMC_Continous_Clock
Kojto 122:f9eeca106725 122 This mode is available only for the STM32F412Vx/Zx/Rx devices */
Kojto 122:f9eeca106725 123
Kojto 122:f9eeca106725 124 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 122:f9eeca106725 125 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 126 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 127 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 122:f9eeca106725 128 This mode is available only for the STM32F412Vx/Vx devices */
Kojto 122:f9eeca106725 129
Kojto 122:f9eeca106725 130 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 122:f9eeca106725 131 This parameter can be a value of @ref FMC_Page_Size */
bogdanm 89:552587b429a1 132 }FSMC_NORSRAM_InitTypeDef;
bogdanm 89:552587b429a1 133
bogdanm 89:552587b429a1 134 /**
Kojto 99:dbbf35b96557 135 * @brief FSMC NORSRAM Timing parameters structure definition
bogdanm 89:552587b429a1 136 */
bogdanm 89:552587b429a1 137 typedef struct
bogdanm 89:552587b429a1 138 {
bogdanm 89:552587b429a1 139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 140 the duration of the address setup time.
bogdanm 89:552587b429a1 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 142 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 143
bogdanm 89:552587b429a1 144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 145 the duration of the address hold time.
bogdanm 89:552587b429a1 146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 89:552587b429a1 147 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 150 the duration of the data setup time.
bogdanm 89:552587b429a1 151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 89:552587b429a1 152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 89:552587b429a1 153 NOR Flash memories. */
bogdanm 89:552587b429a1 154
bogdanm 89:552587b429a1 155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 156 the duration of the bus turnaround.
bogdanm 89:552587b429a1 157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 158 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 89:552587b429a1 159
bogdanm 89:552587b429a1 160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 89:552587b429a1 161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 89:552587b429a1 162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 89:552587b429a1 163 accesses. */
bogdanm 89:552587b429a1 164
bogdanm 89:552587b429a1 165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 89:552587b429a1 166 to the memory before getting the first data.
bogdanm 89:552587b429a1 167 The parameter value depends on the memory type as shown below:
bogdanm 89:552587b429a1 168 - It must be set to 0 in case of a CRAM
bogdanm 89:552587b429a1 169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 89:552587b429a1 170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 89:552587b429a1 171 with synchronous burst mode enable */
bogdanm 89:552587b429a1 172
bogdanm 89:552587b429a1 173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 89:552587b429a1 174 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 89:552587b429a1 175
bogdanm 89:552587b429a1 176 }FSMC_NORSRAM_TimingTypeDef;
bogdanm 89:552587b429a1 177
Kojto 110:165afa46840b 178 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 179 /**
Kojto 99:dbbf35b96557 180 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 181 */
bogdanm 89:552587b429a1 182 typedef struct
bogdanm 89:552587b429a1 183 {
bogdanm 89:552587b429a1 184 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 89:552587b429a1 185 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 89:552587b429a1 186
bogdanm 89:552587b429a1 187 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 89:552587b429a1 188 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 189
bogdanm 89:552587b429a1 190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 191 This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm 89:552587b429a1 192
bogdanm 89:552587b429a1 193 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 89:552587b429a1 194 This parameter can be any value of @ref FSMC_ECC */
bogdanm 89:552587b429a1 195
bogdanm 89:552587b429a1 196 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 89:552587b429a1 197 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 89:552587b429a1 198
bogdanm 89:552587b429a1 199 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 200 delay between CLE low and RE low.
bogdanm 89:552587b429a1 201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 202
bogdanm 89:552587b429a1 203 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 204 delay between ALE low and RE low.
bogdanm 89:552587b429a1 205 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 206
Kojto 122:f9eeca106725 207 }FSMC_NAND_InitTypeDef;
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 /**
Kojto 99:dbbf35b96557 210 * @brief FSMC NAND/PCCARD Timing parameters structure definition
bogdanm 89:552587b429a1 211 */
bogdanm 89:552587b429a1 212 typedef struct
bogdanm 89:552587b429a1 213 {
bogdanm 89:552587b429a1 214 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 89:552587b429a1 215 the command assertion for NAND-Flash read or write access
bogdanm 89:552587b429a1 216 to common/Attribute or I/O memory space (depending on
bogdanm 89:552587b429a1 217 the memory space timing to be configured).
bogdanm 89:552587b429a1 218 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 219
bogdanm 89:552587b429a1 220 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 89:552587b429a1 221 command for NAND-Flash read or write access to
bogdanm 89:552587b429a1 222 common/Attribute or I/O memory space (depending on the
bogdanm 89:552587b429a1 223 memory space timing to be configured).
bogdanm 89:552587b429a1 224 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 225
bogdanm 89:552587b429a1 226 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 89:552587b429a1 227 (and data for write access) after the command de-assertion
bogdanm 89:552587b429a1 228 for NAND-Flash read or write access to common/Attribute
bogdanm 89:552587b429a1 229 or I/O memory space (depending on the memory space timing
bogdanm 89:552587b429a1 230 to be configured).
bogdanm 89:552587b429a1 231 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 232
bogdanm 89:552587b429a1 233 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 89:552587b429a1 234 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 89:552587b429a1 235 write access to common/Attribute or I/O memory space (depending
bogdanm 89:552587b429a1 236 on the memory space timing to be configured).
bogdanm 89:552587b429a1 237 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 238
bogdanm 89:552587b429a1 239 }FSMC_NAND_PCC_TimingTypeDef;
bogdanm 89:552587b429a1 240
bogdanm 89:552587b429a1 241 /**
Kojto 99:dbbf35b96557 242 * @brief FSMC NAND Configuration Structure definition
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244 typedef struct
bogdanm 89:552587b429a1 245 {
bogdanm 89:552587b429a1 246 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 89:552587b429a1 247 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 248
bogdanm 89:552587b429a1 249 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 250 delay between CLE low and RE low.
bogdanm 89:552587b429a1 251 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 252
bogdanm 89:552587b429a1 253 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 254 delay between ALE low and RE low.
bogdanm 89:552587b429a1 255 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 256
bogdanm 89:552587b429a1 257 }FSMC_PCCARD_InitTypeDef;
Kojto 99:dbbf35b96557 258 /**
Kojto 99:dbbf35b96557 259 * @}
Kojto 99:dbbf35b96557 260 */
Kojto 110:165afa46840b 261 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 262
Kojto 99:dbbf35b96557 263 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 264 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
Kojto 99:dbbf35b96557 265 * @{
Kojto 99:dbbf35b96557 266 */
bogdanm 89:552587b429a1 267
Kojto 99:dbbf35b96557 268 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
bogdanm 89:552587b429a1 269 * @{
bogdanm 89:552587b429a1 270 */
Kojto 99:dbbf35b96557 271 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
bogdanm 89:552587b429a1 272 * @{
bogdanm 89:552587b429a1 273 */
AnnaBridge 145:64910690c574 274 #define FSMC_NORSRAM_BANK1 0x00000000U
AnnaBridge 145:64910690c574 275 #define FSMC_NORSRAM_BANK2 0x00000002U
AnnaBridge 145:64910690c574 276 #define FSMC_NORSRAM_BANK3 0x00000004U
AnnaBridge 145:64910690c574 277 #define FSMC_NORSRAM_BANK4 0x00000006U
bogdanm 89:552587b429a1 278 /**
bogdanm 89:552587b429a1 279 * @}
bogdanm 89:552587b429a1 280 */
bogdanm 89:552587b429a1 281
Kojto 99:dbbf35b96557 282 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
bogdanm 89:552587b429a1 283 * @{
bogdanm 89:552587b429a1 284 */
AnnaBridge 145:64910690c574 285 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 286 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
bogdanm 89:552587b429a1 287 /**
bogdanm 89:552587b429a1 288 * @}
bogdanm 89:552587b429a1 289 */
bogdanm 89:552587b429a1 290
Kojto 99:dbbf35b96557 291 /** @defgroup FSMC_Memory_Type FSMC Memory Type
bogdanm 89:552587b429a1 292 * @{
bogdanm 89:552587b429a1 293 */
AnnaBridge 145:64910690c574 294 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge 145:64910690c574 295 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge 145:64910690c574 296 #define FSMC_MEMORY_TYPE_NOR 0x00000008U
bogdanm 89:552587b429a1 297 /**
bogdanm 89:552587b429a1 298 * @}
bogdanm 89:552587b429a1 299 */
bogdanm 89:552587b429a1 300
Kojto 99:dbbf35b96557 301 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
bogdanm 89:552587b429a1 302 * @{
bogdanm 89:552587b429a1 303 */
AnnaBridge 145:64910690c574 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge 145:64910690c574 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge 145:64910690c574 306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
bogdanm 89:552587b429a1 307 /**
bogdanm 89:552587b429a1 308 * @}
bogdanm 89:552587b429a1 309 */
bogdanm 89:552587b429a1 310
Kojto 99:dbbf35b96557 311 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
bogdanm 89:552587b429a1 312 * @{
bogdanm 89:552587b429a1 313 */
AnnaBridge 145:64910690c574 314 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge 145:64910690c574 315 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
bogdanm 89:552587b429a1 316 /**
bogdanm 89:552587b429a1 317 * @}
bogdanm 89:552587b429a1 318 */
bogdanm 89:552587b429a1 319
Kojto 99:dbbf35b96557 320 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
bogdanm 89:552587b429a1 321 * @{
bogdanm 89:552587b429a1 322 */
AnnaBridge 145:64910690c574 323 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 324 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
bogdanm 89:552587b429a1 325 /**
bogdanm 89:552587b429a1 326 * @}
bogdanm 89:552587b429a1 327 */
bogdanm 89:552587b429a1 328
Kojto 99:dbbf35b96557 329 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
bogdanm 89:552587b429a1 330 * @{
bogdanm 89:552587b429a1 331 */
AnnaBridge 145:64910690c574 332 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge 145:64910690c574 333 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
bogdanm 89:552587b429a1 334 /**
bogdanm 89:552587b429a1 335 * @}
bogdanm 89:552587b429a1 336 */
bogdanm 89:552587b429a1 337
Kojto 99:dbbf35b96557 338 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
Kojto 122:f9eeca106725 339 * @note These values are available only for the STM32F405/415/407/417xx devices.
Kojto 99:dbbf35b96557 340 * @{
Kojto 99:dbbf35b96557 341 */
AnnaBridge 145:64910690c574 342 #define FSMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 343 #define FSMC_WRAP_MODE_ENABLE 0x00000400U
Kojto 99:dbbf35b96557 344 /**
Kojto 99:dbbf35b96557 345 * @}
Kojto 99:dbbf35b96557 346 */
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
bogdanm 89:552587b429a1 349 * @{
bogdanm 89:552587b429a1 350 */
AnnaBridge 145:64910690c574 351 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge 145:64910690c574 352 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
bogdanm 89:552587b429a1 353 /**
bogdanm 89:552587b429a1 354 * @}
bogdanm 89:552587b429a1 355 */
bogdanm 89:552587b429a1 356
Kojto 99:dbbf35b96557 357 /** @defgroup FSMC_Write_Operation FSMC Write Operation
bogdanm 89:552587b429a1 358 * @{
bogdanm 89:552587b429a1 359 */
AnnaBridge 145:64910690c574 360 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 361 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
bogdanm 89:552587b429a1 362 /**
bogdanm 89:552587b429a1 363 * @}
bogdanm 89:552587b429a1 364 */
bogdanm 89:552587b429a1 365
Kojto 99:dbbf35b96557 366 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
Kojto 99:dbbf35b96557 367 * @{
Kojto 99:dbbf35b96557 368 */
AnnaBridge 145:64910690c574 369 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 370 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
Kojto 99:dbbf35b96557 371 /**
Kojto 99:dbbf35b96557 372 * @}
Kojto 99:dbbf35b96557 373 */
Kojto 99:dbbf35b96557 374
Kojto 99:dbbf35b96557 375 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
Kojto 99:dbbf35b96557 376 * @{
Kojto 99:dbbf35b96557 377 */
AnnaBridge 145:64910690c574 378 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 379 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
Kojto 99:dbbf35b96557 380 /**
Kojto 99:dbbf35b96557 381 * @}
Kojto 99:dbbf35b96557 382 */
Kojto 99:dbbf35b96557 383
Kojto 99:dbbf35b96557 384 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
bogdanm 89:552587b429a1 385 * @{
bogdanm 89:552587b429a1 386 */
AnnaBridge 145:64910690c574 387 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 388 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
bogdanm 89:552587b429a1 389 /**
bogdanm 89:552587b429a1 390 * @}
Kojto 122:f9eeca106725 391 */
Kojto 122:f9eeca106725 392
Kojto 122:f9eeca106725 393 /** @defgroup FSMC_Page_Size FSMC Page Size
Kojto 122:f9eeca106725 394 * @{
Kojto 122:f9eeca106725 395 */
AnnaBridge 145:64910690c574 396 #define FSMC_PAGE_SIZE_NONE 0x00000000U
Kojto 122:f9eeca106725 397 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
Kojto 122:f9eeca106725 398 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
Kojto 122:f9eeca106725 399 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
Kojto 122:f9eeca106725 400 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
Kojto 122:f9eeca106725 401 /**
Kojto 122:f9eeca106725 402 * @}
Kojto 122:f9eeca106725 403 */
Kojto 122:f9eeca106725 404
Kojto 122:f9eeca106725 405 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
Kojto 122:f9eeca106725 406 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
Kojto 122:f9eeca106725 407 * @{
Kojto 122:f9eeca106725 408 */
Kojto 122:f9eeca106725 409 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
AnnaBridge 145:64910690c574 410 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U
Kojto 122:f9eeca106725 411 /**
Kojto 122:f9eeca106725 412 * @}
Kojto 122:f9eeca106725 413 */
bogdanm 89:552587b429a1 414
Kojto 99:dbbf35b96557 415 /** @defgroup FSMC_Write_Burst FSMC Write Burst
bogdanm 89:552587b429a1 416 * @{
bogdanm 89:552587b429a1 417 */
AnnaBridge 145:64910690c574 418 #define FSMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 419 #define FSMC_WRITE_BURST_ENABLE 0x00080000U
bogdanm 89:552587b429a1 420 /**
bogdanm 89:552587b429a1 421 * @}
bogdanm 89:552587b429a1 422 */
bogdanm 89:552587b429a1 423
Kojto 99:dbbf35b96557 424 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
Kojto 122:f9eeca106725 425 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
bogdanm 89:552587b429a1 426 * @{
bogdanm 89:552587b429a1 427 */
AnnaBridge 145:64910690c574 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge 145:64910690c574 429 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
bogdanm 89:552587b429a1 430 /**
bogdanm 89:552587b429a1 431 * @}
bogdanm 89:552587b429a1 432 */
bogdanm 89:552587b429a1 433
Kojto 99:dbbf35b96557 434 /** @defgroup FSMC_Access_Mode FSMC Access Mode
bogdanm 89:552587b429a1 435 * @{
bogdanm 89:552587b429a1 436 */
AnnaBridge 145:64910690c574 437 #define FSMC_ACCESS_MODE_A 0x00000000U
AnnaBridge 145:64910690c574 438 #define FSMC_ACCESS_MODE_B 0x10000000U
AnnaBridge 145:64910690c574 439 #define FSMC_ACCESS_MODE_C 0x20000000U
AnnaBridge 145:64910690c574 440 #define FSMC_ACCESS_MODE_D 0x30000000U
bogdanm 89:552587b429a1 441 /**
bogdanm 89:552587b429a1 442 * @}
bogdanm 89:552587b429a1 443 */
bogdanm 89:552587b429a1 444 /**
bogdanm 89:552587b429a1 445 * @}
bogdanm 89:552587b429a1 446 */
bogdanm 89:552587b429a1 447
Kojto 110:165afa46840b 448 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 449 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
Kojto 99:dbbf35b96557 450 * @{
Kojto 99:dbbf35b96557 451 */
Kojto 99:dbbf35b96557 452 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
Kojto 99:dbbf35b96557 453 * @{
Kojto 99:dbbf35b96557 454 */
AnnaBridge 145:64910690c574 455 #define FSMC_NAND_BANK2 0x00000010U
AnnaBridge 145:64910690c574 456 #define FSMC_NAND_BANK3 0x00000100U
Kojto 99:dbbf35b96557 457 /**
Kojto 99:dbbf35b96557 458 * @}
Kojto 99:dbbf35b96557 459 */
Kojto 99:dbbf35b96557 460
Kojto 99:dbbf35b96557 461 /** @defgroup FSMC_Wait_feature FSMC Wait feature
bogdanm 89:552587b429a1 462 * @{
bogdanm 89:552587b429a1 463 */
AnnaBridge 145:64910690c574 464 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 465 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
bogdanm 89:552587b429a1 466 /**
bogdanm 89:552587b429a1 467 * @}
bogdanm 89:552587b429a1 468 */
bogdanm 89:552587b429a1 469
Kojto 99:dbbf35b96557 470 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
bogdanm 89:552587b429a1 471 * @{
bogdanm 89:552587b429a1 472 */
AnnaBridge 145:64910690c574 473 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge 145:64910690c574 474 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
bogdanm 89:552587b429a1 475 /**
bogdanm 89:552587b429a1 476 * @}
bogdanm 89:552587b429a1 477 */
bogdanm 89:552587b429a1 478
Kojto 99:dbbf35b96557 479 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
bogdanm 89:552587b429a1 480 * @{
bogdanm 89:552587b429a1 481 */
AnnaBridge 145:64910690c574 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge 145:64910690c574 483 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
bogdanm 89:552587b429a1 484 /**
bogdanm 89:552587b429a1 485 * @}
bogdanm 89:552587b429a1 486 */
bogdanm 89:552587b429a1 487
Kojto 99:dbbf35b96557 488 /** @defgroup FSMC_ECC FSMC ECC
bogdanm 89:552587b429a1 489 * @{
bogdanm 89:552587b429a1 490 */
AnnaBridge 145:64910690c574 491 #define FSMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge 145:64910690c574 492 #define FSMC_NAND_ECC_ENABLE 0x00000040U
bogdanm 89:552587b429a1 493 /**
bogdanm 89:552587b429a1 494 * @}
bogdanm 89:552587b429a1 495 */
bogdanm 89:552587b429a1 496
Kojto 99:dbbf35b96557 497 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
bogdanm 89:552587b429a1 498 * @{
bogdanm 89:552587b429a1 499 */
AnnaBridge 145:64910690c574 500 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge 145:64910690c574 501 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge 145:64910690c574 502 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge 145:64910690c574 503 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge 145:64910690c574 504 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge 145:64910690c574 505 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
bogdanm 89:552587b429a1 506 /**
bogdanm 89:552587b429a1 507 * @}
bogdanm 89:552587b429a1 508 */
bogdanm 89:552587b429a1 509 /**
bogdanm 89:552587b429a1 510 * @}
bogdanm 89:552587b429a1 511 */
Kojto 110:165afa46840b 512 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 110:165afa46840b 513
Kojto 99:dbbf35b96557 514 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
bogdanm 89:552587b429a1 515 * @{
bogdanm 89:552587b429a1 516 */
AnnaBridge 145:64910690c574 517 #define FSMC_IT_RISING_EDGE 0x00000008U
AnnaBridge 145:64910690c574 518 #define FSMC_IT_LEVEL 0x00000010U
AnnaBridge 145:64910690c574 519 #define FSMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge 145:64910690c574 520 #define FSMC_IT_REFRESH_ERROR 0x00004000U
bogdanm 89:552587b429a1 521 /**
bogdanm 89:552587b429a1 522 * @}
bogdanm 89:552587b429a1 523 */
bogdanm 89:552587b429a1 524
Kojto 99:dbbf35b96557 525 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
bogdanm 89:552587b429a1 526 * @{
bogdanm 89:552587b429a1 527 */
AnnaBridge 145:64910690c574 528 #define FSMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge 145:64910690c574 529 #define FSMC_FLAG_LEVEL 0x00000002U
AnnaBridge 145:64910690c574 530 #define FSMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge 145:64910690c574 531 #define FSMC_FLAG_FEMPT 0x00000040U
bogdanm 89:552587b429a1 532 /**
bogdanm 89:552587b429a1 533 * @}
bogdanm 89:552587b429a1 534 */
bogdanm 89:552587b429a1 535
Kojto 99:dbbf35b96557 536 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
Kojto 99:dbbf35b96557 537 * @{
bogdanm 89:552587b429a1 538 */
Kojto 99:dbbf35b96557 539 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
Kojto 99:dbbf35b96557 540 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
Kojto 110:165afa46840b 541 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 542 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
Kojto 99:dbbf35b96557 543 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
Kojto 110:165afa46840b 544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 545
Kojto 99:dbbf35b96557 546 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
Kojto 99:dbbf35b96557 547 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
Kojto 110:165afa46840b 548 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 549 #define FSMC_NAND_DEVICE FSMC_Bank2_3
Kojto 99:dbbf35b96557 550 #define FSMC_PCCARD_DEVICE FSMC_Bank4
Kojto 110:165afa46840b 551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 552
Kojto 122:f9eeca106725 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
Kojto 122:f9eeca106725 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
Kojto 122:f9eeca106725 555 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
Kojto 122:f9eeca106725 556
bogdanm 89:552587b429a1 557 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 558 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 559 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
bogdanm 89:552587b429a1 560 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
bogdanm 89:552587b429a1 561
bogdanm 89:552587b429a1 562 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
bogdanm 89:552587b429a1 563 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
bogdanm 89:552587b429a1 564 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
bogdanm 89:552587b429a1 565 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
bogdanm 89:552587b429a1 566 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
bogdanm 89:552587b429a1 567 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
bogdanm 89:552587b429a1 568
bogdanm 89:552587b429a1 569 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
bogdanm 89:552587b429a1 570 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
bogdanm 89:552587b429a1 571
Kojto 110:165afa46840b 572 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 573 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
bogdanm 89:552587b429a1 574 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
bogdanm 89:552587b429a1 575 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
bogdanm 89:552587b429a1 576
bogdanm 89:552587b429a1 577 #define FMC_NAND_Init FSMC_NAND_Init
bogdanm 89:552587b429a1 578 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 579 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 580 #define FMC_NAND_DeInit FSMC_NAND_DeInit
bogdanm 89:552587b429a1 581 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
bogdanm 89:552587b429a1 582 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
bogdanm 89:552587b429a1 583 #define FMC_NAND_GetECC FSMC_NAND_GetECC
bogdanm 89:552587b429a1 584 #define FMC_PCCARD_Init FSMC_PCCARD_Init
bogdanm 89:552587b429a1 585 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 586 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 587 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
bogdanm 89:552587b429a1 588 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
bogdanm 89:552587b429a1 589
bogdanm 89:552587b429a1 590 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
bogdanm 89:552587b429a1 591 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
bogdanm 89:552587b429a1 592 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
bogdanm 89:552587b429a1 593 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
bogdanm 89:552587b429a1 594 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
bogdanm 89:552587b429a1 595 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
bogdanm 89:552587b429a1 596 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
bogdanm 89:552587b429a1 597 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
bogdanm 89:552587b429a1 598 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
bogdanm 89:552587b429a1 599 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
bogdanm 89:552587b429a1 600 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
bogdanm 89:552587b429a1 601 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
Kojto 110:165afa46840b 602 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 603
bogdanm 89:552587b429a1 604 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 605 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 110:165afa46840b 606 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 607 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
bogdanm 89:552587b429a1 608 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
Kojto 110:165afa46840b 609 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 610
Kojto 122:f9eeca106725 611 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
Kojto 110:165afa46840b 612 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
Kojto 110:165afa46840b 613 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 122:f9eeca106725 614 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
bogdanm 89:552587b429a1 615 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
bogdanm 89:552587b429a1 616
bogdanm 89:552587b429a1 617 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
Kojto 110:165afa46840b 618 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 619
bogdanm 92:4fc01daae5a5 620 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
bogdanm 92:4fc01daae5a5 621 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
bogdanm 92:4fc01daae5a5 622 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
bogdanm 92:4fc01daae5a5 623
bogdanm 89:552587b429a1 624 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
bogdanm 89:552587b429a1 625 #define FMC_IT_LEVEL FSMC_IT_LEVEL
bogdanm 89:552587b429a1 626 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
bogdanm 89:552587b429a1 627 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
bogdanm 89:552587b429a1 628
bogdanm 89:552587b429a1 629 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
bogdanm 89:552587b429a1 630 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
bogdanm 89:552587b429a1 631 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
bogdanm 89:552587b429a1 632 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
Kojto 99:dbbf35b96557 633 /**
Kojto 99:dbbf35b96557 634 * @}
Kojto 99:dbbf35b96557 635 */
bogdanm 89:552587b429a1 636
Kojto 99:dbbf35b96557 637 /**
Kojto 99:dbbf35b96557 638 * @}
Kojto 99:dbbf35b96557 639 */
Kojto 99:dbbf35b96557 640
Kojto 99:dbbf35b96557 641 /* Private macro -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 642 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
Kojto 99:dbbf35b96557 643 * @{
Kojto 99:dbbf35b96557 644 */
Kojto 99:dbbf35b96557 645
Kojto 99:dbbf35b96557 646 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
Kojto 99:dbbf35b96557 647 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 99:dbbf35b96557 648 * @{
Kojto 99:dbbf35b96557 649 */
Kojto 99:dbbf35b96557 650 /**
Kojto 99:dbbf35b96557 651 * @brief Enable the NORSRAM device access.
Kojto 99:dbbf35b96557 652 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 653 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 654 * @retval none
Kojto 99:dbbf35b96557 655 */
Kojto 99:dbbf35b96557 656 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 657
Kojto 99:dbbf35b96557 658 /**
Kojto 99:dbbf35b96557 659 * @brief Disable the NORSRAM device access.
Kojto 99:dbbf35b96557 660 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 661 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 662 * @retval none
Kojto 99:dbbf35b96557 663 */
Kojto 99:dbbf35b96557 664 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 665 /**
Kojto 99:dbbf35b96557 666 * @}
Kojto 99:dbbf35b96557 667 */
Kojto 99:dbbf35b96557 668
Kojto 99:dbbf35b96557 669 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
Kojto 99:dbbf35b96557 670 * @brief macros to handle NAND device enable/disable
Kojto 99:dbbf35b96557 671 * @{
Kojto 99:dbbf35b96557 672 */
Kojto 110:165afa46840b 673 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 674 /**
Kojto 99:dbbf35b96557 675 * @brief Enable the NAND device access.
Kojto 99:dbbf35b96557 676 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 677 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 678 * @retval none
Kojto 99:dbbf35b96557 679 */
Kojto 99:dbbf35b96557 680 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 681 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 682
Kojto 99:dbbf35b96557 683 /**
Kojto 99:dbbf35b96557 684 * @brief Disable the NAND device access.
Kojto 99:dbbf35b96557 685 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 686 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 687 * @retval none
Kojto 99:dbbf35b96557 688 */
Kojto 99:dbbf35b96557 689 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 690 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 691 /**
Kojto 99:dbbf35b96557 692 * @}
Kojto 99:dbbf35b96557 693 */
Kojto 99:dbbf35b96557 694
Kojto 99:dbbf35b96557 695 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
Kojto 99:dbbf35b96557 696 * @brief macros to handle SRAM read/write operations
Kojto 99:dbbf35b96557 697 * @{
Kojto 99:dbbf35b96557 698 */
Kojto 99:dbbf35b96557 699 /**
Kojto 99:dbbf35b96557 700 * @brief Enable the PCCARD device access.
Kojto 99:dbbf35b96557 701 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 702 * @retval none
Kojto 99:dbbf35b96557 703 */
Kojto 99:dbbf35b96557 704 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 /**
Kojto 99:dbbf35b96557 707 * @brief Disable the PCCARD device access.
Kojto 99:dbbf35b96557 708 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 709 * @retval none
Kojto 99:dbbf35b96557 710 */
Kojto 99:dbbf35b96557 711 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 712 /**
Kojto 99:dbbf35b96557 713 * @}
Kojto 99:dbbf35b96557 714 */
Kojto 99:dbbf35b96557 715
Kojto 99:dbbf35b96557 716 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
Kojto 99:dbbf35b96557 717 * @brief macros to handle FSMC flags and interrupts
Kojto 99:dbbf35b96557 718 * @{
Kojto 99:dbbf35b96557 719 */
Kojto 99:dbbf35b96557 720 /**
Kojto 99:dbbf35b96557 721 * @brief Enable the NAND device interrupt.
Kojto 99:dbbf35b96557 722 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 723 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 724 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 725 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 726 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 727 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 728 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 729 * @retval None
Kojto 99:dbbf35b96557 730 */
Kojto 99:dbbf35b96557 731 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 122:f9eeca106725 732 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 99:dbbf35b96557 733
Kojto 99:dbbf35b96557 734 /**
Kojto 99:dbbf35b96557 735 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 736 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 737 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 738 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 739 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 740 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 741 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 742 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 743 * @retval None
Kojto 99:dbbf35b96557 744 */
Kojto 99:dbbf35b96557 745 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 122:f9eeca106725 746 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 122:f9eeca106725 747
Kojto 99:dbbf35b96557 748 /**
Kojto 99:dbbf35b96557 749 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 750 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 751 * @param __BANK__ : FSMC_NAND Bank
Kojto 99:dbbf35b96557 752 * @param __FLAG__ : FSMC_NAND flag
Kojto 99:dbbf35b96557 753 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 754 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 755 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 756 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 757 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 758 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 759 */
Kojto 99:dbbf35b96557 760 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 122:f9eeca106725 761 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 122:f9eeca106725 762
Kojto 99:dbbf35b96557 763 /**
Kojto 99:dbbf35b96557 764 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 765 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 766 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 767 * @param __FLAG__: FSMC_NAND flag
Kojto 99:dbbf35b96557 768 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 769 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 770 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 771 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 772 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 773 * @retval None
Kojto 99:dbbf35b96557 774 */
Kojto 99:dbbf35b96557 775 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 122:f9eeca106725 776 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 122:f9eeca106725 777
Kojto 99:dbbf35b96557 778 /**
Kojto 99:dbbf35b96557 779 * @brief Enable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 780 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 781 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 782 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 783 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 784 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 785 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 786 * @retval None
Kojto 99:dbbf35b96557 787 */
Kojto 99:dbbf35b96557 788 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 789
Kojto 99:dbbf35b96557 790 /**
Kojto 99:dbbf35b96557 791 * @brief Disable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 792 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 793 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 794 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 795 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 796 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 797 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 798 * @retval None
Kojto 99:dbbf35b96557 799 */
Kojto 99:dbbf35b96557 800 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 801
Kojto 99:dbbf35b96557 802 /**
Kojto 99:dbbf35b96557 803 * @brief Get flag status of the PCCARD device.
Kojto 99:dbbf35b96557 804 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 805 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 806 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 807 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 808 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 809 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 810 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 811 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 812 */
Kojto 99:dbbf35b96557 813 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 814
Kojto 99:dbbf35b96557 815 /**
Kojto 99:dbbf35b96557 816 * @brief Clear flag status of the PCCARD device.
Kojto 99:dbbf35b96557 817 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 818 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 819 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 820 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 821 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 822 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 823 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 824 * @retval None
Kojto 99:dbbf35b96557 825 */
Kojto 99:dbbf35b96557 826 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 99:dbbf35b96557 827 /**
Kojto 99:dbbf35b96557 828 * @}
Kojto 99:dbbf35b96557 829 */
Kojto 110:165afa46840b 830 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 831
Kojto 99:dbbf35b96557 832 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 99:dbbf35b96557 833 * @{
Kojto 99:dbbf35b96557 834 */
Kojto 99:dbbf35b96557 835 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
Kojto 99:dbbf35b96557 836 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
Kojto 99:dbbf35b96557 837 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
Kojto 99:dbbf35b96557 838 ((__BANK__) == FSMC_NORSRAM_BANK4))
Kojto 99:dbbf35b96557 839
Kojto 99:dbbf35b96557 840 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 99:dbbf35b96557 841 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 99:dbbf35b96557 842
Kojto 99:dbbf35b96557 843 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
Kojto 99:dbbf35b96557 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
Kojto 99:dbbf35b96557 845 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
Kojto 99:dbbf35b96557 846
Kojto 99:dbbf35b96557 847 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 849 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 850
Kojto 99:dbbf35b96557 851 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
Kojto 99:dbbf35b96557 852 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
Kojto 99:dbbf35b96557 853 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
Kojto 99:dbbf35b96557 854 ((__MODE__) == FSMC_ACCESS_MODE_D))
Kojto 99:dbbf35b96557 855
Kojto 99:dbbf35b96557 856 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
Kojto 99:dbbf35b96557 857 ((BANK) == FSMC_NAND_BANK3))
Kojto 99:dbbf35b96557 858
Kojto 99:dbbf35b96557 859 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 99:dbbf35b96557 860 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 99:dbbf35b96557 861
Kojto 99:dbbf35b96557 862 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 863 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 99:dbbf35b96557 864
Kojto 99:dbbf35b96557 865 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
Kojto 99:dbbf35b96557 866 ((STATE) == FSMC_NAND_ECC_ENABLE))
Kojto 99:dbbf35b96557 867
Kojto 99:dbbf35b96557 868 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 99:dbbf35b96557 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 99:dbbf35b96557 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 99:dbbf35b96557 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 99:dbbf35b96557 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 99:dbbf35b96557 873 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 99:dbbf35b96557 874
Kojto 122:f9eeca106725 875 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 876
Kojto 122:f9eeca106725 877 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 878
Kojto 122:f9eeca106725 879 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 880
Kojto 122:f9eeca106725 881 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 882
Kojto 122:f9eeca106725 883 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 884
Kojto 122:f9eeca106725 885 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 886
Kojto 99:dbbf35b96557 887 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
Kojto 99:dbbf35b96557 888
Kojto 99:dbbf35b96557 889 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
Kojto 99:dbbf35b96557 890
Kojto 99:dbbf35b96557 891 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
Kojto 99:dbbf35b96557 892
Kojto 99:dbbf35b96557 893 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
Kojto 99:dbbf35b96557 894
Kojto 99:dbbf35b96557 895 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 896 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
Kojto 99:dbbf35b96557 897
Kojto 99:dbbf35b96557 898 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 99:dbbf35b96557 899 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 99:dbbf35b96557 900
Kojto 99:dbbf35b96557 901 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 902 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
Kojto 99:dbbf35b96557 903
Kojto 99:dbbf35b96557 904 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 99:dbbf35b96557 905 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
Kojto 99:dbbf35b96557 906
Kojto 99:dbbf35b96557 907 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
Kojto 99:dbbf35b96557 908 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
Kojto 99:dbbf35b96557 909
Kojto 99:dbbf35b96557 910 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
Kojto 99:dbbf35b96557 911 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
Kojto 99:dbbf35b96557 912
Kojto 99:dbbf35b96557 913 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 914 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
Kojto 99:dbbf35b96557 915
Kojto 99:dbbf35b96557 916 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 99:dbbf35b96557 917 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 99:dbbf35b96557 918
Kojto 122:f9eeca106725 919 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
Kojto 99:dbbf35b96557 920
Kojto 99:dbbf35b96557 921 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
Kojto 99:dbbf35b96557 922 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
Kojto 99:dbbf35b96557 923
Kojto 122:f9eeca106725 924 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 925
Kojto 122:f9eeca106725 926 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
Kojto 99:dbbf35b96557 927
Kojto 122:f9eeca106725 928 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
Kojto 99:dbbf35b96557 929
Kojto 122:f9eeca106725 930 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 931
Kojto 99:dbbf35b96557 932 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 99:dbbf35b96557 933 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 99:dbbf35b96557 934
Kojto 122:f9eeca106725 935 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
Kojto 122:f9eeca106725 936
Kojto 122:f9eeca106725 937 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
Kojto 122:f9eeca106725 938 ((SIZE) == FSMC_PAGE_SIZE_128) || \
Kojto 122:f9eeca106725 939 ((SIZE) == FSMC_PAGE_SIZE_256) || \
AnnaBridge 145:64910690c574 940 ((SIZE) == FSMC_PAGE_SIZE_512) || \
Kojto 122:f9eeca106725 941 ((SIZE) == FSMC_PAGE_SIZE_1024))
Kojto 122:f9eeca106725 942
Kojto 122:f9eeca106725 943 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
Kojto 122:f9eeca106725 944 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
Kojto 99:dbbf35b96557 945
Kojto 99:dbbf35b96557 946 /**
Kojto 99:dbbf35b96557 947 * @}
Kojto 99:dbbf35b96557 948 */
Kojto 99:dbbf35b96557 949 /**
Kojto 99:dbbf35b96557 950 * @}
Kojto 99:dbbf35b96557 951 */
Kojto 99:dbbf35b96557 952
Kojto 99:dbbf35b96557 953 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 954 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
Kojto 99:dbbf35b96557 955 * @{
Kojto 99:dbbf35b96557 956 */
Kojto 99:dbbf35b96557 957
Kojto 99:dbbf35b96557 958 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
Kojto 99:dbbf35b96557 959 * @{
Kojto 99:dbbf35b96557 960 */
Kojto 99:dbbf35b96557 961
Kojto 99:dbbf35b96557 962 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 963 * @{
Kojto 99:dbbf35b96557 964 */
Kojto 99:dbbf35b96557 965 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
Kojto 99:dbbf35b96557 966 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 967 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 99:dbbf35b96557 968 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 99:dbbf35b96557 969 /**
Kojto 99:dbbf35b96557 970 * @}
Kojto 99:dbbf35b96557 971 */
Kojto 99:dbbf35b96557 972
Kojto 99:dbbf35b96557 973 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 99:dbbf35b96557 974 * @{
Kojto 99:dbbf35b96557 975 */
Kojto 99:dbbf35b96557 976 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 977 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 978 /**
Kojto 99:dbbf35b96557 979 * @}
Kojto 99:dbbf35b96557 980 */
Kojto 99:dbbf35b96557 981 /**
Kojto 99:dbbf35b96557 982 * @}
Kojto 99:dbbf35b96557 983 */
Kojto 99:dbbf35b96557 984
Kojto 110:165afa46840b 985 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 986 /** @defgroup FSMC_LL_NAND NAND
Kojto 99:dbbf35b96557 987 * @{
Kojto 99:dbbf35b96557 988 */
Kojto 99:dbbf35b96557 989 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 99:dbbf35b96557 990 * @{
Kojto 99:dbbf35b96557 991 */
Kojto 99:dbbf35b96557 992 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
Kojto 99:dbbf35b96557 993 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 994 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 995 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 996 /**
Kojto 99:dbbf35b96557 997 * @}
Kojto 99:dbbf35b96557 998 */
Kojto 99:dbbf35b96557 999
Kojto 99:dbbf35b96557 1000 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 99:dbbf35b96557 1001 * @{
Kojto 99:dbbf35b96557 1002 */
Kojto 99:dbbf35b96557 1003 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1004 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1005 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 99:dbbf35b96557 1006 /**
Kojto 99:dbbf35b96557 1007 * @}
Kojto 99:dbbf35b96557 1008 */
Kojto 99:dbbf35b96557 1009 /**
Kojto 99:dbbf35b96557 1010 * @}
Kojto 99:dbbf35b96557 1011 */
Kojto 99:dbbf35b96557 1012
Kojto 99:dbbf35b96557 1013 /** @defgroup FSMC_LL_PCCARD PCCARD
Kojto 99:dbbf35b96557 1014 * @{
Kojto 99:dbbf35b96557 1015 */
Kojto 99:dbbf35b96557 1016 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1017 * @{
Kojto 99:dbbf35b96557 1018 */
Kojto 99:dbbf35b96557 1019 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
Kojto 99:dbbf35b96557 1020 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1021 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1022 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1023 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
Kojto 99:dbbf35b96557 1024 /**
Kojto 99:dbbf35b96557 1025 * @}
Kojto 99:dbbf35b96557 1026 */
Kojto 99:dbbf35b96557 1027 /**
Kojto 99:dbbf35b96557 1028 * @}
Kojto 99:dbbf35b96557 1029 */
Kojto 110:165afa46840b 1030 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 1031
Kojto 99:dbbf35b96557 1032 /**
Kojto 99:dbbf35b96557 1033 * @}
Kojto 99:dbbf35b96557 1034 */
AnnaBridge 145:64910690c574 1035 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
bogdanm 89:552587b429a1 1036
bogdanm 89:552587b429a1 1037 /**
bogdanm 89:552587b429a1 1038 * @}
bogdanm 89:552587b429a1 1039 */
bogdanm 89:552587b429a1 1040
bogdanm 89:552587b429a1 1041 /**
bogdanm 89:552587b429a1 1042 * @}
bogdanm 89:552587b429a1 1043 */
bogdanm 89:552587b429a1 1044
bogdanm 89:552587b429a1 1045 #ifdef __cplusplus
bogdanm 89:552587b429a1 1046 }
bogdanm 89:552587b429a1 1047 #endif
bogdanm 89:552587b429a1 1048
bogdanm 89:552587b429a1 1049 #endif /* __STM32F4xx_LL_FSMC_H */
bogdanm 89:552587b429a1 1050
bogdanm 89:552587b429a1 1051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/