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Diff: TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h
- Revision:
- 160:5571c4ff569f
- Parent:
- 142:4eea097334d6
--- a/TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Thu Nov 23 11:44:04 2017 +0000
+++ b/TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Wed Jan 17 16:13:02 2018 +0000
@@ -2,9 +2,9 @@
* @file em_usart.h
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,6 @@
*
******************************************************************************/
-
#ifndef EM_USART_H
#define EM_USART_H
@@ -102,8 +101,7 @@
******************************************************************************/
/** Databit selection. */
-typedef enum
-{
+typedef enum {
usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
@@ -119,10 +117,8 @@
usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
} USART_Databits_TypeDef;
-
/** Enable selection. */
-typedef enum
-{
+typedef enum {
/** Disable both receiver and transmitter. */
usartDisable = 0x0,
@@ -136,39 +132,40 @@
usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
} USART_Enable_TypeDef;
-
/** Oversampling selection, used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
} USART_OVS_TypeDef;
-
/** Parity selection, mainly used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
} USART_Parity_TypeDef;
-
/** Stopbits selection, used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
} USART_Stopbits_TypeDef;
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
+typedef enum {
+ usartHwFlowControlNone = 0,
+ usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN,
+ usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN,
+ usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN,
+} USART_HwFlowControl_TypeDef;
+#endif
/** Clock polarity/phase mode. */
-typedef enum
-{
+typedef enum {
/** Clock idle low, sample on rising edge. */
usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
@@ -182,10 +179,8 @@
usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
} USART_ClockMode_TypeDef;
-
/** Pulse width selection for IrDA mode. */
-typedef enum
-{
+typedef enum {
/** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
@@ -199,10 +194,8 @@
usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
} USART_IrDAPw_Typedef;
-
/** PRS channel selection for IrDA mode. */
-typedef enum
-{
+typedef enum {
usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
@@ -223,8 +216,7 @@
#if defined(_USART_I2SCTRL_MASK)
/** I2S format selection. */
-typedef enum
-{
+typedef enum {
usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
@@ -236,8 +228,7 @@
} USART_I2sFormat_TypeDef;
/** I2S frame data justify. */
-typedef enum
-{
+typedef enum {
usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
} USART_I2sJustify_TypeDef;
@@ -245,8 +236,7 @@
#if defined(_USART_INPUT_MASK)
/** USART Rx input PRS selection. */
-typedef enum
-{
+typedef enum {
usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
@@ -269,8 +259,7 @@
#endif
/** USART PRS Transmit Trigger Channels */
-typedef enum
-{
+typedef enum {
usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
@@ -289,8 +278,7 @@
******************************************************************************/
/** Asynchronous mode init structure. */
-typedef struct
-{
+typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@@ -334,11 +322,13 @@
/** Auto CS setup time in baud cycles */
uint8_t autoCsSetup;
#endif
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
+ USART_HwFlowControl_TypeDef hwFlowControl;
+#endif
} USART_InitAsync_TypeDef;
/** USART PRS trigger enable */
-typedef struct
-{
+typedef struct {
#if defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable AUTOTX */
bool autoTxTriggerEnable;
@@ -352,71 +342,119 @@
} USART_PrsTriggerInit_TypeDef;
/** Default config for USART async init structure. */
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* Auto CS functionality enable/disable switch */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
-}
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0, /* Auto CS Setup cycles */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0 /* PRS channel 0. */ \
-}
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
+#else
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
+#endif
#else
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
-}
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+ }
+#endif
#endif
/** Default config for USART PRS triggering structure. */
#if defined(USART_TRIGCTRL_AUTOTXTEN)
-#define USART_INITPRSTRIGGER_DEFAULT \
-{ \
- false, /* Do not enable autoTX triggering. */ \
- false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
-}
+#define USART_INITPRSTRIGGER_DEFAULT \
+ { \
+ false, /* Do not enable autoTX triggering. */ \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+ }
#else
-#define USART_INITPRSTRIGGER_DEFAULT \
-{ \
- false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
-}
+#define USART_INITPRSTRIGGER_DEFAULT \
+ { \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+ }
#endif
/** Synchronous mode init structure. */
-typedef struct
-{
+typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@@ -465,52 +503,50 @@
/** Default config for USART sync init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* No AUTOTX mode. */ \
- false, /* No AUTOCS mode */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* No AUTOTX mode. */ \
+ false, /* No AUTOCS mode */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false /* No AUTOTX mode. */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false /* No AUTOTX mode. */ \
+ }
#else
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0 /* Clock idle low, sample on rising edge. */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0 /* Clock idle low, sample on rising edge. */ \
+ }
#endif
-
/** IrDA mode init structure. Inherited from asynchronous mode init structure */
-typedef struct
-{
+typedef struct {
/** General Async initialization structure. */
USART_InitAsync_TypeDef async;
@@ -533,77 +569,145 @@
USART_IrDAPrsSel_Typedef irPrsSel;
} USART_InitIrDA_TypeDef;
-
/** Default config for IrDA mode init structure. */
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* Auto CS functionality enable/disable switch */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0, /* Auto CS Setup cycles */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0 /* PRS channel 0. */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#endif
#else
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0 /* PRS channel 0. */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#endif
#endif
#if defined(_USART_I2SCTRL_MASK)
/** I2S mode init structure. Inherited from synchronous mode init structure */
-typedef struct
-{
+typedef struct {
/** General Sync initialization structure. */
USART_InitSync_TypeDef sync;
@@ -625,53 +729,52 @@
bool mono;
} USART_InitI2s_TypeDef;
-
/** Default config for I2S mode init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITI2S_DEFAULT \
-{ \
{ \
- usartEnableTx, /* Enable TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* Baudrate 1M bits/s. */ \
- usartDatabits16, /* 16 databits. */ \
- true, /* Operate as I2S master. */ \
- true, /* Most significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Don't enable USARTRx via PRS. */ \
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \
- false, /* Disable AUTOTX mode. */ \
- false, /* No AUTOCS mode */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
- }, \
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
- true, /* Delay on I2S data. */ \
- false, /* No DMA split. */ \
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
- false /* Stereo mode. */ \
-}
+ { \
+ usartEnableTx, /* Enable TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* Baudrate 1M bits/s. */ \
+ usartDatabits16, /* 16 databits. */ \
+ true, /* Operate as I2S master. */ \
+ true, /* Most significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Don't enable USARTRx via PRS. */ \
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \
+ false, /* Disable AUTOTX mode. */ \
+ false, /* No AUTOCS mode */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }, \
+ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
+ true, /* Delay on I2S data. */ \
+ false, /* No DMA split. */ \
+ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
+ false /* Stereo mode. */ \
+ }
#else
#define USART_INITI2S_DEFAULT \
-{ \
{ \
- usartEnableTx, /* Enable TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* Baudrate 1M bits/s. */ \
- usartDatabits16, /* 16 databits. */ \
- true, /* Operate as I2S master. */ \
- true, /* Most significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Don't enable USARTRx via PRS. */ \
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \
- false /* Disable AUTOTX mode. */ \
- }, \
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
- true, /* Delay on I2S data. */ \
- false, /* No DMA split. */ \
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
- false /* Stereo mode. */ \
-}
+ { \
+ usartEnableTx, /* Enable TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* Baudrate 1M bits/s. */ \
+ usartDatabits16, /* 16 databits. */ \
+ true, /* Operate as I2S master. */ \
+ true, /* Most significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Don't enable USARTRx via PRS. */ \
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \
+ false /* Disable AUTOTX mode. */ \
+ }, \
+ usartI2sFormatW16D16,/* 16-bit word, 16-bit data */ \
+ true, /* Delay on I2S data. */ \
+ false, /* No DMA split. */ \
+ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
+ false /* Stereo mode. */ \
+ }
#endif
#endif
@@ -759,7 +862,6 @@
usart->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more USART interrupts.
@@ -776,7 +878,6 @@
usart->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more USART interrupts.
@@ -798,7 +899,6 @@
usart->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending USART interrupt flags.
@@ -818,7 +918,6 @@
return usart->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending USART interrupt flags.
@@ -850,7 +949,6 @@
return usart->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending USART interrupts from SW.
@@ -867,7 +965,6 @@
usart->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Get USART STATUS register.
@@ -890,7 +987,6 @@
uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
uint16_t USART_RxExt(USART_TypeDef *usart);
-
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@@ -924,7 +1020,6 @@
return (uint8_t)usart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@@ -962,7 +1057,6 @@
return (uint16_t)usart->RXDOUBLE;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@@ -998,7 +1092,6 @@
return usart->RXDOUBLEX;
}
-
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@@ -1039,7 +1132,6 @@
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
void USART_TxExt(USART_TypeDef *usart, uint16_t data);
-
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */
