Diff: TARGET_NUCLEO_L496ZG/TOOLCHAIN_IAR/stm32l496xx.icf

Revision:

171:3a7713b1edbc

Parent:

157:e7ca05fa8600

Child:

172:65be27845400

--- a/TARGET_NUCLEO_L496ZG/TOOLCHAIN_IAR/stm32l496xx.icf	Thu Sep 06 13:39:34 2018 +0100
+++ b/TARGET_NUCLEO_L496ZG/TOOLCHAIN_IAR/stm32l496xx.icf	Thu Nov 08 11:45:42 2018 +0000
@@ -1,13 +1,16 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+
 /* [ROM = 1024kb = 0x100000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x08000000 + 0x100000 - 1;
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 
 /* [RAM = 0x50000] */
-/* Vector table dynamic copy: Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM */
+/* Vector table dynamic copy: Total: 107 vectors * 4 = 428 bytes (0x1AC) to be reserved in RAM */
 define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200001AC - 1;
-define symbol __region_SRAM1_start__  = 0x200001AC; /* Aligned on 8 bytes (428 = 53 x 8) */
+define symbol __NVIC_end__            = 0x200001AF; /* Add 4 more bytes to be aligned on 8 bytes */
+define symbol __region_SRAM1_start__  = 0x200001B0;
 define symbol __region_SRAM1_end__    = 0x2004FFFF;
 
 /* Memory regions */