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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc.h
- Revision:
- 108:34e6b704fe68
- Parent:
- 93:e188a91d3eaa
- Child:
- 122:f9eeca106725
--- a/TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc.h Wed Sep 16 15:32:31 2015 +0100
+++ b/TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc.h Fri Oct 02 07:35:07 2015 +0200
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_H
@@ -52,53 +52,198 @@
/** @addtogroup RCC
* @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+
+/**
+ * @}
*/
-/* Exported types ------------------------------------------------------------*/
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define CR2_REG_INDEX 2
+#define BDCR_REG_INDEX 3
+#define CSR_REG_INDEX 4
+
+/* Flags in the CFGR register */
+#define RCC_CFGR_PLLMUL_BITNUMBER 18
+#define RCC_CFGR_HPRE_BITNUMBER 4
+#define RCC_CFGR_PPRE_BITNUMBER 8
+/* Flags in the CFGR2 register */
+#define RCC_CFGR2_PREDIV_BITNUMBER 0
+/* Flags in the CR register */
+#define RCC_CR_HSIRDY_BitNumber 1
+#define RCC_CR_HSERDY_BitNumber 17
+#define RCC_CR_PLLRDY_BitNumber 25
+/* Flags in the CR2 register */
+#define RCC_CR2_HSI14RDY_BitNumber 1
+#define RCC_CR2_HSI48RDY_BitNumber 16
+/* Flags in the BDCR register */
+#define RCC_BDCR_LSERDY_BitNumber 1
+/* Flags in the CSR register */
+#define RCC_CSR_LSIRDY_BitNumber 1
+#define RCC_CSR_V18PWRRSTF_BitNumber 23
+#define RCC_CSR_RMVF_BitNumber 24
+#define RCC_CSR_OBLRSTF_BitNumber 25
+#define RCC_CSR_PINRSTF_BitNumber 26
+#define RCC_CSR_PORRSTF_BitNumber 27
+#define RCC_CSR_SFTRSTF_BitNumber 28
+#define RCC_CSR_IWDGRSTF_BitNumber 29
+#define RCC_CSR_WWDGRSTF_BitNumber 30
+#define RCC_CSR_LPWRRSTF_BitNumber 31
+/* Flags in the HSITRIM register */
+#define RCC_CR_HSITRIM_BitNumber 3
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/
-/**
- * @brief RCC PLL configuration structure definition
+/**
+ * @brief RCC PLL configuration structure definition
*/
typedef struct
{
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
- uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
-
-}RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
- uint32_t OscillatorType; /*!< The Oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
uint32_t HSI14State; /*!< The new state of the HSI14.
This parameter can be a value of @ref RCC_HSI14_Config */
@@ -108,94 +253,53 @@
uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
This parameter can be a value of @ref RCCEx_HSI48_Config */
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-}RCC_OscInitTypeDef;
+} RCC_OscInitTypeDef;
+
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_Clock_Source */
-
-}RCC_ClkInitTypeDef;
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_Clock_Source */
+
+} RCC_ClkInitTypeDef;
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
-/* --- CFGR Register ---*/
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
-/* --- CIR Register ---*/
-#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
-/* --- BDCR Register ---*/
-#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
-/* --- CSR Register ---*/
-#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
-/* --- CR2 Register ---*/
-#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
-
-/* CSR register byte 1 (Bits[15:8]) base address */
-#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
-
-/* BDCR register byte 0 (Bits[7:0] base address */
-#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-#define RCC_CFGR_PLLMUL_BITNUMBER 18
-#define RCC_CFGR2_PREDIV_BITNUMBER 0
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
/**
* @}
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-/* LSE state change timeout */
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+ */
-/* Disable Backup domain write protection state change timeout */
-#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
+/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
@@ -204,58 +308,43 @@
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
-#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
-
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
/**
* @}
*/
-/** @defgroup RCC_HSE_Config RCC HSE Config
+/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
+#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
/**
* @}
*/
-/** @defgroup RCC_LSE_Config RCC_LSE_Config
+/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_BYPASS ((uint8_t)0x05)
+#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_HSI_Config RCC HSI Config
+/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
-#define RCC_HSI_OFF ((uint8_t)0x00)
-#define RCC_HSI_ON ((uint8_t)0x01)
+#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
-#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
/**
* @}
*/
-
+
/** @defgroup RCC_HSI14_Config RCC HSI14 Config
* @{
*/
@@ -263,35 +352,106 @@
#define RCC_HSI14_ON RCC_CR2_HSI14ON
#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
-#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
+#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
-#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
+#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
+#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+
/**
* @}
*/
-/** @defgroup RCC_LSI_Config RCC LSI Config
+/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
-#define RCC_LSI_OFF ((uint8_t)0x00)
-#define RCC_LSI_ON ((uint8_t)0x01)
+#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+
/**
* @}
*/
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
+#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
+#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
+#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
+#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
+#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
+#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
+#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
+#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
-/** @defgroup RCC_PLL_Config RCC PLL Config
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
* @{
*/
-#define RCC_PLL_NONE ((uint8_t)0x00)
-#define RCC_PLL_OFF ((uint8_t)0x01)
-#define RCC_PLL_ON ((uint8_t)0x02)
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
/**
* @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
*/
+#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
* @{
@@ -313,18 +473,10 @@
#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
-#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
- ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
- ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
- ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
- ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
- ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
- ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
- ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
/**
* @}
*/
-
+
/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
* @{
*/
@@ -344,110 +496,6 @@
#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
- ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
- ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
- ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
- ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
- ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
- ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
- ((MUL) == RCC_PLL_MUL16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type RCC System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source RCC System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-
-#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
- ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
- ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
- ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
- ((DIV) == RCC_SYSCLK_DIV512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
-
-#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
- ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
- ((DIV) == RCC_HCLK_DIV16))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
/**
* @}
*/
@@ -460,10 +508,6 @@
#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
/**
* @}
*/
@@ -474,18 +518,15 @@
#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
-#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
/**
* @}
*/
-
-/** @defgroup RCC_MCOx_Index RCC MCOx Index
+/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
-#define RCC_MCO ((uint32_t)0x00000000)
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
/**
* @}
*/
@@ -501,70 +542,45 @@
#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
+
/**
* @}
*/
-
-/** @defgroup RCC_Interrupt RCC Interrupt
+
+/** @defgroup RCC_Interrupt Interrupts
* @{
*/
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_HSI14 ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
/**
* @}
*/
-/** @defgroup RCC_Flag RCC Flag
- * Elements values convention: 0XXYYYYYb
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
* - YYYYY : Flag position in the register
- * - XX : Register index
- * - 00: CR register
- * - 01: CR2 register
- * - 10: BDCR register
- * - 11: CSR register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: CR2 register
+ * - 011: BDCR register
+ * - 0100: CSR register
* @{
*/
-#define CR_REG_INDEX 0
-#define CR2_REG_INDEX 1
-#define BDCR_REG_INDEX 2
-#define CSR_REG_INDEX 3
-
/* Flags in the CR register */
-#define RCC_CR_HSIRDY_BitNumber 1
-#define RCC_CR_HSERDY_BitNumber 17
-#define RCC_CR_PLLRDY_BitNumber 25
-
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
/* Flags in the CR2 register */
-#define RCC_CR2_HSI14RDY_BitNumber 1
-
#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
-/* Flags in the BDCR register */
-#define RCC_BDCR_LSERDY_BitNumber 1
-
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
/* Flags in the CSR register */
-#define RCC_CSR_LSIRDY_BitNumber 1
-#define RCC_CSR_V18PWRRSTF_BitNumber 23
-#define RCC_CSR_RMVF_BitNumber 24
-#define RCC_CSR_OBLRSTF_BitNumber 25
-#define RCC_CSR_PINRSTF_BitNumber 26
-#define RCC_CSR_PORRSTF_BitNumber 27
-#define RCC_CSR_SFTRSTF_BitNumber 28
-#define RCC_CSR_IWDGRSTF_BitNumber 29
-#define RCC_CSR_WWDGRSTF_BitNumber 30
-#define RCC_CSR_LPWRRSTF_BitNumber 31
-
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
@@ -575,45 +591,23 @@
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
-/**
- * @}
- */
-/** @defgroup RCC_Calibration_values RCC Calibration values
- * @{
- */
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
/**
* @}
- */
-
-/** @addtogroup RCC_Timeout
- * @{
- */
-
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
-#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+ */
/**
* @}
- */
+ */
-/**
- * @}
- */
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
+ * @{
+ */
/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
* @brief Enable or disable the AHB peripheral clock.
@@ -622,27 +616,102 @@
* using it.
* @{
*/
-#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
-#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
-#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
-#define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
-#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
-#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
-#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
/**
* @}
*/
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
@@ -650,20 +719,72 @@
* using it.
* @{
*/
-#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
/**
* @}
*/
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
@@ -672,42 +793,117 @@
* using it.
* @{
*/
-#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
-#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
-#define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
-#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
/**
* @}
*/
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
* @brief Force or release AHB peripheral reset.
* @{
*/
-#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
-#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
-#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
-#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
-#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
/**
* @}
*/
@@ -716,19 +912,19 @@
* @brief Force or release APB1 peripheral reset.
* @{
*/
-#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
/**
* @}
*/
@@ -737,88 +933,87 @@
* @brief Force or release APB2 peripheral reset.
* @{
*/
-#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
-#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
+/**
+ * @}
+ */
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
+
/**
* @}
*/
-/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
+/** @defgroup RCC_LSI_Configuration LSI Configuration
* @{
*/
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__: specifies the calibration trimming value
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define RCC_CR_HSITRIM_BitNumber 3
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
/**
* @}
*/
-/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
+/** @defgroup RCC_HSE_Configuration HSE Configuration
* @{
*/
-
-/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-/**
- * @}
- */
-/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
- * @{
- */
-
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -836,31 +1031,55 @@
* @arg RCC_HSE_ON: turn ON the HSE oscillator
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
*/
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ }while(0)
/**
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
* @note Predivision factor can not be changed if PLL is used as system clock
* In this case, you have to select another source of the system clock, disable the PLL and
* then change the HSE predivision factor.
- * @param __HSEPredivValue__: specifies the division value applied to HSE.
+ * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
*/
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
+
/**
* @}
*/
-/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
+/** @defgroup RCC_LSE_Configuration LSE Configuration
* @{
- */
+ */
+
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
+ * this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
+ * (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
@@ -868,11 +1087,32 @@
* This parameter can be one of the following values:
* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if ((__STATE__) == RCC_LSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ }while(0)
+
/**
* @}
*/
@@ -963,235 +1203,247 @@
* @}
*/
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macros to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter can be one of the following values:
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
+ } while(0)
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/**
+ * @}
+ */
+
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/
-/** @brief Macros to enable or disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-/** @brief Macro to configure the RTC clock (RTCCLK).
+/** @brief Macro to configures the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR).
- * @param __RTCCLKSource__: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
*
- * @note If the LSE is used as RTC clock source, the RTC continues to
+ * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wakeup source.
* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
* the RTC cannot be used in STOP and STANDBY modes.
* @note The system must always be configured so as to get a PCLK frequency greater than or
* equal to the RTCCLK frequency for a proper operation of the RTC.
*/
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
-
-/** @brief Macro to get the RTC clock source.
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief macros to get the RTC clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
*/
-#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
-/**
- * @}
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macros to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
*/
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
- * @{
- */
-
-/** @brief Macro to force or release the Backup domain reset.
- * @note These macros reset the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
+/** @brief Macros to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
*/
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief Macros to force the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
/**
* @}
*/
-/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
- * @{
- */
-
-/** @brief Macro to enable or disable the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to configure the PLL clock source, multiplication and division factors.
- * @note This macro must be used only when the PLL is disabled.
- *
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
- * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
- * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
- * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
- do { \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
- } while(0)
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source RCC Get Clock source
- * @{
- */
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock.
- * The returned value can be one of the following value:
- * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
- * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
- * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be one
- * of the following:
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
-/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
- * the selected interrupts.).
+/** @brief Enable RCC interrupt.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
- * @arg RCC_IT_LSERDY: LSE ready interrupt enable
- * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
- * @arg RCC_IT_HSERDY: HSE ready interrupt enable
- * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
*/
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
- * the selected interrupts.).
+/** @brief Disable RCC interrupt.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
- * @arg RCC_IT_LSERDY: LSE ready interrupt enable
- * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
- * @arg RCC_IT_HSERDY: HSE ready interrupt enable
- * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
*/
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
- * bits to clear the selected interrupt pending bits.
- * @param __IT__: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
- * @arg RCC_IT_LSERDY: LSE ready interrupt clear
- * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
- * @arg RCC_IT_HSERDY: HSE ready interrupt clear
- * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt clear
- */
-#define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __IT__: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
- * @arg RCC_IT_LSERDY: LSE ready interrupt flag
- * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
- * @arg RCC_IT_HSERDY: HSE ready interrupt flag
- * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt flag
- * @retval The new state of __IT__ (TRUE or FALSE).
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
*/
-#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
/** @brief Check RCC flag is set or not.
* @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
* @arg RCC_FLAG_OBLRST: Option Byte Load reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
-
+/**
+ * @}
+ */
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/* Include RCC HAL Extension module */
#include "stm32f0xx_hal_rcc_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup RCC_Exported_Functions
* @{
*/
@@ -1200,10 +1452,10 @@
* @{
*/
-/* Initialization and de-initialization functions ***************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
* @}
@@ -1212,22 +1464,22 @@
/** @addtogroup RCC_Exported_Functions_Group2
* @{
*/
-
-/* Peripheral Control functions *********************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
+void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CCSCallback(void);
+void HAL_RCC_CSSCallback(void);
/**
* @}
@@ -1235,16 +1487,16 @@
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
-
+
#ifdef __cplusplus
}
#endif
