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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:: AnnaBridge
Date:: Wed Nov 08 17:18:06 2017 +0000
Revision:: 156:ff21514d8981
Child:: 161:aa5281ff4a02

Reverting back to release 154 of the mbed library

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32l4xx_ll_dma.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @version V1.7.1
AnnaBridge	156:ff21514d8981	6	* @date 21-April-2017
AnnaBridge	156:ff21514d8981	7	* @brief Header file of DMA LL module.
AnnaBridge	156:ff21514d8981	8	******************************************************************************
AnnaBridge	156:ff21514d8981	9	* @attention
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	12	*
AnnaBridge	156:ff21514d8981	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	14	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	19	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	21	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	22	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	23	*
AnnaBridge	156:ff21514d8981	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	34	*
AnnaBridge	156:ff21514d8981	35	******************************************************************************
AnnaBridge	156:ff21514d8981	36	*/
AnnaBridge	156:ff21514d8981	37
AnnaBridge	156:ff21514d8981	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	39	#ifndef __STM32L4xx_LL_DMA_H
AnnaBridge	156:ff21514d8981	40	#define __STM32L4xx_LL_DMA_H
AnnaBridge	156:ff21514d8981	41
AnnaBridge	156:ff21514d8981	42	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	43	extern "C" {
AnnaBridge	156:ff21514d8981	44	#endif
AnnaBridge	156:ff21514d8981	45
AnnaBridge	156:ff21514d8981	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	47	#include "stm32l4xx.h"
AnnaBridge	156:ff21514d8981	48
AnnaBridge	156:ff21514d8981	49	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	156:ff21514d8981	50	* @{
AnnaBridge	156:ff21514d8981	51	*/
AnnaBridge	156:ff21514d8981	52
AnnaBridge	156:ff21514d8981	53	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	/** @defgroup DMA_LL DMA
AnnaBridge	156:ff21514d8981	56	* @{
AnnaBridge	156:ff21514d8981	57	*/
AnnaBridge	156:ff21514d8981	58
AnnaBridge	156:ff21514d8981	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	156:ff21514d8981	62	* @{
AnnaBridge	156:ff21514d8981	63	*/
AnnaBridge	156:ff21514d8981	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	156:ff21514d8981	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	156:ff21514d8981	66	{
AnnaBridge	156:ff21514d8981	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	156:ff21514d8981	74	};
AnnaBridge	156:ff21514d8981	75	/**
AnnaBridge	156:ff21514d8981	76	* @}
AnnaBridge	156:ff21514d8981	77	*/
AnnaBridge	156:ff21514d8981	78
AnnaBridge	156:ff21514d8981	79	/* Private constants ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	156:ff21514d8981	81	* @{
AnnaBridge	156:ff21514d8981	82	*/
AnnaBridge	156:ff21514d8981	83	/* Define used to get CSELR register offset */
AnnaBridge	156:ff21514d8981	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	156:ff21514d8981	85
AnnaBridge	156:ff21514d8981	86	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	156:ff21514d8981	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
AnnaBridge	156:ff21514d8981	88	/**
AnnaBridge	156:ff21514d8981	89	* @}
AnnaBridge	156:ff21514d8981	90	*/
AnnaBridge	156:ff21514d8981	91
AnnaBridge	156:ff21514d8981	92	/* Private macros ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	93	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	156:ff21514d8981	95	* @{
AnnaBridge	156:ff21514d8981	96	*/
AnnaBridge	156:ff21514d8981	97	/**
AnnaBridge	156:ff21514d8981	98	* @}
AnnaBridge	156:ff21514d8981	99	*/
AnnaBridge	156:ff21514d8981	100	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	156:ff21514d8981	101
AnnaBridge	156:ff21514d8981	102	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	103	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	156:ff21514d8981	105	* @{
AnnaBridge	156:ff21514d8981	106	*/
AnnaBridge	156:ff21514d8981	107	typedef struct
AnnaBridge	156:ff21514d8981	108	{
AnnaBridge	156:ff21514d8981	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	156:ff21514d8981	110	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	156:ff21514d8981	113
AnnaBridge	156:ff21514d8981	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	156:ff21514d8981	115	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	116
AnnaBridge	156:ff21514d8981	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	156:ff21514d8981	118
AnnaBridge	156:ff21514d8981	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	156:ff21514d8981	120	from memory to memory or from peripheral to memory.
AnnaBridge	156:ff21514d8981	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	156:ff21514d8981	122
AnnaBridge	156:ff21514d8981	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	156:ff21514d8981	124
AnnaBridge	156:ff21514d8981	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	156:ff21514d8981	126	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	156:ff21514d8981	127	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	156:ff21514d8981	128	data transfer direction is configured on the selected Channel
AnnaBridge	156:ff21514d8981	129
AnnaBridge	156:ff21514d8981	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	156:ff21514d8981	131
AnnaBridge	156:ff21514d8981	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	156:ff21514d8981	133	is incremented or not.
AnnaBridge	156:ff21514d8981	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	156:ff21514d8981	135
AnnaBridge	156:ff21514d8981	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	156:ff21514d8981	137
AnnaBridge	156:ff21514d8981	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	156:ff21514d8981	139	is incremented or not.
AnnaBridge	156:ff21514d8981	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	156:ff21514d8981	141
AnnaBridge	156:ff21514d8981	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	156:ff21514d8981	143
AnnaBridge	156:ff21514d8981	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	156:ff21514d8981	145	in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	156:ff21514d8981	149
AnnaBridge	156:ff21514d8981	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	156:ff21514d8981	151	in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	156:ff21514d8981	153
AnnaBridge	156:ff21514d8981	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	156:ff21514d8981	155
AnnaBridge	156:ff21514d8981	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	156:ff21514d8981	157	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	156:ff21514d8981	158	or MemorySize parameters depending in the transfer direction.
AnnaBridge	156:ff21514d8981	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	156:ff21514d8981	160
AnnaBridge	156:ff21514d8981	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	156:ff21514d8981	162
AnnaBridge	156:ff21514d8981	163	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	156:ff21514d8981	164	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	156:ff21514d8981	165
AnnaBridge	156:ff21514d8981	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	156:ff21514d8981	167
AnnaBridge	156:ff21514d8981	168	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	156:ff21514d8981	169	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	} LL_DMA_InitTypeDef;
AnnaBridge	156:ff21514d8981	174	/**
AnnaBridge	156:ff21514d8981	175	* @}
AnnaBridge	156:ff21514d8981	176	*/
AnnaBridge	156:ff21514d8981	177	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	156:ff21514d8981	178
AnnaBridge	156:ff21514d8981	179	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	180	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	156:ff21514d8981	181	* @{
AnnaBridge	156:ff21514d8981	182	*/
AnnaBridge	156:ff21514d8981	183	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	156:ff21514d8981	184	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	156:ff21514d8981	185	* @{
AnnaBridge	156:ff21514d8981	186	*/
AnnaBridge	156:ff21514d8981	187	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	156:ff21514d8981	188	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	156:ff21514d8981	189	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	156:ff21514d8981	190	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	156:ff21514d8981	191	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	156:ff21514d8981	192	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	156:ff21514d8981	193	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	156:ff21514d8981	194	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	156:ff21514d8981	195	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	156:ff21514d8981	196	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	156:ff21514d8981	197	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	156:ff21514d8981	198	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	156:ff21514d8981	199	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	156:ff21514d8981	200	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	156:ff21514d8981	201	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	156:ff21514d8981	202	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	156:ff21514d8981	203	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	156:ff21514d8981	204	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	156:ff21514d8981	205	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	156:ff21514d8981	206	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	156:ff21514d8981	207	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	156:ff21514d8981	208	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	156:ff21514d8981	209	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	156:ff21514d8981	210	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	156:ff21514d8981	211	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	156:ff21514d8981	212	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	156:ff21514d8981	213	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	156:ff21514d8981	214	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	156:ff21514d8981	215	/**
AnnaBridge	156:ff21514d8981	216	* @}
AnnaBridge	156:ff21514d8981	217	*/
AnnaBridge	156:ff21514d8981	218
AnnaBridge	156:ff21514d8981	219	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	156:ff21514d8981	220	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	156:ff21514d8981	221	* @{
AnnaBridge	156:ff21514d8981	222	*/
AnnaBridge	156:ff21514d8981	223	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	156:ff21514d8981	224	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	156:ff21514d8981	225	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	156:ff21514d8981	226	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	156:ff21514d8981	227	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	156:ff21514d8981	228	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	156:ff21514d8981	229	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	156:ff21514d8981	230	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	156:ff21514d8981	231	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	156:ff21514d8981	232	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	156:ff21514d8981	233	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	156:ff21514d8981	234	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	156:ff21514d8981	235	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	156:ff21514d8981	236	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	156:ff21514d8981	237	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	156:ff21514d8981	238	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	156:ff21514d8981	239	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	156:ff21514d8981	240	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	156:ff21514d8981	241	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	156:ff21514d8981	242	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	156:ff21514d8981	243	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	156:ff21514d8981	244	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	156:ff21514d8981	245	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	156:ff21514d8981	246	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	156:ff21514d8981	247	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	156:ff21514d8981	248	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	156:ff21514d8981	249	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	156:ff21514d8981	250	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	156:ff21514d8981	251	/**
AnnaBridge	156:ff21514d8981	252	* @}
AnnaBridge	156:ff21514d8981	253	*/
AnnaBridge	156:ff21514d8981	254
AnnaBridge	156:ff21514d8981	255	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	156:ff21514d8981	256	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	156:ff21514d8981	257	* @{
AnnaBridge	156:ff21514d8981	258	*/
AnnaBridge	156:ff21514d8981	259	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	156:ff21514d8981	260	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	156:ff21514d8981	261	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	156:ff21514d8981	262	/**
AnnaBridge	156:ff21514d8981	263	* @}
AnnaBridge	156:ff21514d8981	264	*/
AnnaBridge	156:ff21514d8981	265
AnnaBridge	156:ff21514d8981	266	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	156:ff21514d8981	267	* @{
AnnaBridge	156:ff21514d8981	268	*/
AnnaBridge	156:ff21514d8981	269	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
AnnaBridge	156:ff21514d8981	270	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
AnnaBridge	156:ff21514d8981	271	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
AnnaBridge	156:ff21514d8981	272	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
AnnaBridge	156:ff21514d8981	273	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
AnnaBridge	156:ff21514d8981	274	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
AnnaBridge	156:ff21514d8981	275	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
AnnaBridge	156:ff21514d8981	276	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	277	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	156:ff21514d8981	278	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	156:ff21514d8981	279	/**
AnnaBridge	156:ff21514d8981	280	* @}
AnnaBridge	156:ff21514d8981	281	*/
AnnaBridge	156:ff21514d8981	282
AnnaBridge	156:ff21514d8981	283	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	156:ff21514d8981	284	* @{
AnnaBridge	156:ff21514d8981	285	*/
AnnaBridge	156:ff21514d8981	286	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
AnnaBridge	156:ff21514d8981	287	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	156:ff21514d8981	288	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	156:ff21514d8981	289	/**
AnnaBridge	156:ff21514d8981	290	* @}
AnnaBridge	156:ff21514d8981	291	*/
AnnaBridge	156:ff21514d8981	292
AnnaBridge	156:ff21514d8981	293	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	156:ff21514d8981	294	* @{
AnnaBridge	156:ff21514d8981	295	*/
AnnaBridge	156:ff21514d8981	296	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
AnnaBridge	156:ff21514d8981	297	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	156:ff21514d8981	298	/**
AnnaBridge	156:ff21514d8981	299	* @}
AnnaBridge	156:ff21514d8981	300	*/
AnnaBridge	156:ff21514d8981	301
AnnaBridge	156:ff21514d8981	302	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	156:ff21514d8981	303	* @{
AnnaBridge	156:ff21514d8981	304	*/
AnnaBridge	156:ff21514d8981	305	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	156:ff21514d8981	306	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
AnnaBridge	156:ff21514d8981	307	/**
AnnaBridge	156:ff21514d8981	308	* @}
AnnaBridge	156:ff21514d8981	309	*/
AnnaBridge	156:ff21514d8981	310
AnnaBridge	156:ff21514d8981	311	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	156:ff21514d8981	312	* @{
AnnaBridge	156:ff21514d8981	313	*/
AnnaBridge	156:ff21514d8981	314	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	156:ff21514d8981	315	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
AnnaBridge	156:ff21514d8981	316	/**
AnnaBridge	156:ff21514d8981	317	* @}
AnnaBridge	156:ff21514d8981	318	*/
AnnaBridge	156:ff21514d8981	319
AnnaBridge	156:ff21514d8981	320	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	156:ff21514d8981	321	* @{
AnnaBridge	156:ff21514d8981	322	*/
AnnaBridge	156:ff21514d8981	323	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
AnnaBridge	156:ff21514d8981	324	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	156:ff21514d8981	325	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	156:ff21514d8981	326	/**
AnnaBridge	156:ff21514d8981	327	* @}
AnnaBridge	156:ff21514d8981	328	*/
AnnaBridge	156:ff21514d8981	329
AnnaBridge	156:ff21514d8981	330	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	156:ff21514d8981	331	* @{
AnnaBridge	156:ff21514d8981	332	*/
AnnaBridge	156:ff21514d8981	333	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
AnnaBridge	156:ff21514d8981	334	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	156:ff21514d8981	335	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	156:ff21514d8981	336	/**
AnnaBridge	156:ff21514d8981	337	* @}
AnnaBridge	156:ff21514d8981	338	*/
AnnaBridge	156:ff21514d8981	339
AnnaBridge	156:ff21514d8981	340	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	156:ff21514d8981	341	* @{
AnnaBridge	156:ff21514d8981	342	*/
AnnaBridge	156:ff21514d8981	343	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
AnnaBridge	156:ff21514d8981	344	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	156:ff21514d8981	345	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	156:ff21514d8981	346	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	156:ff21514d8981	347	/**
AnnaBridge	156:ff21514d8981	348	* @}
AnnaBridge	156:ff21514d8981	349	*/
AnnaBridge	156:ff21514d8981	350
AnnaBridge	156:ff21514d8981	351	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	156:ff21514d8981	352	* @{
AnnaBridge	156:ff21514d8981	353	*/
AnnaBridge	156:ff21514d8981	354	#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /!< DMA peripheral request 0 /
AnnaBridge	156:ff21514d8981	355	#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /!< DMA peripheral request 1 /
AnnaBridge	156:ff21514d8981	356	#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /!< DMA peripheral request 2 /
AnnaBridge	156:ff21514d8981	357	#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /!< DMA peripheral request 3 /
AnnaBridge	156:ff21514d8981	358	#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /!< DMA peripheral request 4 /
AnnaBridge	156:ff21514d8981	359	#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /!< DMA peripheral request 5 /
AnnaBridge	156:ff21514d8981	360	#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /!< DMA peripheral request 6 /
AnnaBridge	156:ff21514d8981	361	#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /!< DMA peripheral request 7 /
AnnaBridge	156:ff21514d8981	362	/**
AnnaBridge	156:ff21514d8981	363	* @}
AnnaBridge	156:ff21514d8981	364	*/
AnnaBridge	156:ff21514d8981	365
AnnaBridge	156:ff21514d8981	366	/**
AnnaBridge	156:ff21514d8981	367	* @}
AnnaBridge	156:ff21514d8981	368	*/
AnnaBridge	156:ff21514d8981	369
AnnaBridge	156:ff21514d8981	370	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	371	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	156:ff21514d8981	372	* @{
AnnaBridge	156:ff21514d8981	373	*/
AnnaBridge	156:ff21514d8981	374
AnnaBridge	156:ff21514d8981	375	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	156:ff21514d8981	376	* @{
AnnaBridge	156:ff21514d8981	377	*/
AnnaBridge	156:ff21514d8981	378	/**
AnnaBridge	156:ff21514d8981	379	* @brief Write a value in DMA register
AnnaBridge	156:ff21514d8981	380	* @param __INSTANCE__ DMA Instance
AnnaBridge	156:ff21514d8981	381	* @param __REG__ Register to be written
AnnaBridge	156:ff21514d8981	382	* @param __VALUE__ Value to be written in the register
AnnaBridge	156:ff21514d8981	383	* @retval None
AnnaBridge	156:ff21514d8981	384	*/
AnnaBridge	156:ff21514d8981	385	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	156:ff21514d8981	386
AnnaBridge	156:ff21514d8981	387	/**
AnnaBridge	156:ff21514d8981	388	* @brief Read a value in DMA register
AnnaBridge	156:ff21514d8981	389	* @param __INSTANCE__ DMA Instance
AnnaBridge	156:ff21514d8981	390	* @param __REG__ Register to be read
AnnaBridge	156:ff21514d8981	391	* @retval Register value
AnnaBridge	156:ff21514d8981	392	*/
AnnaBridge	156:ff21514d8981	393	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	156:ff21514d8981	394	/**
AnnaBridge	156:ff21514d8981	395	* @}
AnnaBridge	156:ff21514d8981	396	*/
AnnaBridge	156:ff21514d8981	397
AnnaBridge	156:ff21514d8981	398	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	156:ff21514d8981	399	* @{
AnnaBridge	156:ff21514d8981	400	*/
AnnaBridge	156:ff21514d8981	401	/**
AnnaBridge	156:ff21514d8981	402	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	156:ff21514d8981	403	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	156:ff21514d8981	404	* @retval DMAx
AnnaBridge	156:ff21514d8981	405	*/
AnnaBridge	156:ff21514d8981	406	#if defined(DMA2)
AnnaBridge	156:ff21514d8981	407	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	408	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	156:ff21514d8981	409	#else
AnnaBridge	156:ff21514d8981	410	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	156:ff21514d8981	411	#endif
AnnaBridge	156:ff21514d8981	412
AnnaBridge	156:ff21514d8981	413	/**
AnnaBridge	156:ff21514d8981	414	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	415	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	156:ff21514d8981	416	* @retval LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	417	*/
AnnaBridge	156:ff21514d8981	418	#if defined (DMA2)
AnnaBridge	156:ff21514d8981	419	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	156:ff21514d8981	420	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	421	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	428	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	429	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	430	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	431	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	432	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	433	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	434	#else
AnnaBridge	156:ff21514d8981	435	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	436	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	438	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	439	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	440	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	441	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	442	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	443	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	444	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	445	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	446	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	447	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	448	#endif
AnnaBridge	156:ff21514d8981	449	#else
AnnaBridge	156:ff21514d8981	450	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	451	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	452	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	453	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	454	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	455	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	456	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	457	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	458	#endif
AnnaBridge	156:ff21514d8981	459
AnnaBridge	156:ff21514d8981	460	/**
AnnaBridge	156:ff21514d8981	461	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	156:ff21514d8981	462	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	156:ff21514d8981	463	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	464	* @retval DMAx_Channely
AnnaBridge	156:ff21514d8981	465	*/
AnnaBridge	156:ff21514d8981	466	#if defined (DMA2)
AnnaBridge	156:ff21514d8981	467	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	156:ff21514d8981	468	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	469	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	156:ff21514d8981	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	156:ff21514d8981	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	156:ff21514d8981	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	156:ff21514d8981	477	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	478	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	156:ff21514d8981	479	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	480	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	156:ff21514d8981	481	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	156:ff21514d8981	482	DMA2_Channel7)
AnnaBridge	156:ff21514d8981	483	#else
AnnaBridge	156:ff21514d8981	484	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	485	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	156:ff21514d8981	487	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	488	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	156:ff21514d8981	489	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	490	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	156:ff21514d8981	491	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	492	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	156:ff21514d8981	493	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	494	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	156:ff21514d8981	495	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	496	DMA1_Channel7)
AnnaBridge	156:ff21514d8981	497	#endif
AnnaBridge	156:ff21514d8981	498	#else
AnnaBridge	156:ff21514d8981	499	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	500	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	501	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	502	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	503	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	504	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	505	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	506	DMA1_Channel7)
AnnaBridge	156:ff21514d8981	507	#endif
AnnaBridge	156:ff21514d8981	508
AnnaBridge	156:ff21514d8981	509	/**
AnnaBridge	156:ff21514d8981	510	* @}
AnnaBridge	156:ff21514d8981	511	*/
AnnaBridge	156:ff21514d8981	512
AnnaBridge	156:ff21514d8981	513	/**
AnnaBridge	156:ff21514d8981	514	* @}
AnnaBridge	156:ff21514d8981	515	*/
AnnaBridge	156:ff21514d8981	516
AnnaBridge	156:ff21514d8981	517	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	518	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	156:ff21514d8981	519	* @{
AnnaBridge	156:ff21514d8981	520	*/
AnnaBridge	156:ff21514d8981	521
AnnaBridge	156:ff21514d8981	522	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	156:ff21514d8981	523	* @{
AnnaBridge	156:ff21514d8981	524	*/
AnnaBridge	156:ff21514d8981	525	/**
AnnaBridge	156:ff21514d8981	526	* @brief Enable DMA channel.
AnnaBridge	156:ff21514d8981	527	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	156:ff21514d8981	528	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	529	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	530	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	531	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	532	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	533	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	534	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	535	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	536	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	537	* @retval None
AnnaBridge	156:ff21514d8981	538	*/
AnnaBridge	156:ff21514d8981	539	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	540	{
AnnaBridge	156:ff21514d8981	541	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	156:ff21514d8981	542	}
AnnaBridge	156:ff21514d8981	543
AnnaBridge	156:ff21514d8981	544	/**
AnnaBridge	156:ff21514d8981	545	* @brief Disable DMA channel.
AnnaBridge	156:ff21514d8981	546	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	156:ff21514d8981	547	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	548	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	549	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	550	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	551	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	552	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	553	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	554	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	555	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	556	* @retval None
AnnaBridge	156:ff21514d8981	557	*/
AnnaBridge	156:ff21514d8981	558	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	559	{
AnnaBridge	156:ff21514d8981	560	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	156:ff21514d8981	561	}
AnnaBridge	156:ff21514d8981	562
AnnaBridge	156:ff21514d8981	563	/**
AnnaBridge	156:ff21514d8981	564	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	156:ff21514d8981	565	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	156:ff21514d8981	566	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	567	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	568	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	569	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	570	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	571	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	572	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	573	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	574	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	575	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	576	*/
AnnaBridge	156:ff21514d8981	577	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	578	{
AnnaBridge	156:ff21514d8981	579	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	580	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	156:ff21514d8981	581	}
AnnaBridge	156:ff21514d8981	582
AnnaBridge	156:ff21514d8981	583	/**
AnnaBridge	156:ff21514d8981	584	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	156:ff21514d8981	585	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	586	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	587	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	588	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	589	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	590	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	591	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	592	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	156:ff21514d8981	593	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	594	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	595	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	596	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	597	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	598	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	599	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	600	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	601	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	602	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	156:ff21514d8981	603	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	604	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	605	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	606	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	607	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	608	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	609	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	610	* @retval None
AnnaBridge	156:ff21514d8981	611	*/
AnnaBridge	156:ff21514d8981	612	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	156:ff21514d8981	613	{
AnnaBridge	156:ff21514d8981	614	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	615	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	156:ff21514d8981	616	Configuration);
AnnaBridge	156:ff21514d8981	617	}
AnnaBridge	156:ff21514d8981	618
AnnaBridge	156:ff21514d8981	619	/**
AnnaBridge	156:ff21514d8981	620	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	156:ff21514d8981	621	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	156:ff21514d8981	622	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	156:ff21514d8981	623	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	624	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	625	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	626	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	627	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	628	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	629	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	630	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	631	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	632	* @param Direction This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	633	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	634	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	635	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	636	* @retval None
AnnaBridge	156:ff21514d8981	637	*/
AnnaBridge	156:ff21514d8981	638	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	156:ff21514d8981	639	{
AnnaBridge	156:ff21514d8981	640	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	641	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	156:ff21514d8981	642	}
AnnaBridge	156:ff21514d8981	643
AnnaBridge	156:ff21514d8981	644	/**
AnnaBridge	156:ff21514d8981	645	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	156:ff21514d8981	646	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	156:ff21514d8981	647	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	156:ff21514d8981	648	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	649	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	650	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	651	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	652	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	653	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	654	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	655	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	656	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	657	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	658	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	659	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	660	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	661	*/
AnnaBridge	156:ff21514d8981	662	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	663	{
AnnaBridge	156:ff21514d8981	664	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	665	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	156:ff21514d8981	666	}
AnnaBridge	156:ff21514d8981	667
AnnaBridge	156:ff21514d8981	668	/**
AnnaBridge	156:ff21514d8981	669	* @brief Set DMA mode circular or normal.
AnnaBridge	156:ff21514d8981	670	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	156:ff21514d8981	671	* data transfer is configured on the selected Channel.
AnnaBridge	156:ff21514d8981	672	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	156:ff21514d8981	673	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	674	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	675	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	676	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	677	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	678	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	679	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	680	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	681	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	682	* @param Mode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	683	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	156:ff21514d8981	684	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	685	* @retval None
AnnaBridge	156:ff21514d8981	686	*/
AnnaBridge	156:ff21514d8981	687	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	156:ff21514d8981	688	{
AnnaBridge	156:ff21514d8981	689	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	156:ff21514d8981	690	Mode);
AnnaBridge	156:ff21514d8981	691	}
AnnaBridge	156:ff21514d8981	692
AnnaBridge	156:ff21514d8981	693	/**
AnnaBridge	156:ff21514d8981	694	* @brief Get DMA mode circular or normal.
AnnaBridge	156:ff21514d8981	695	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	156:ff21514d8981	696	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	697	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	698	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	699	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	700	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	701	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	702	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	703	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	704	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	705	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	706	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	156:ff21514d8981	707	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	708	*/
AnnaBridge	156:ff21514d8981	709	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	710	{
AnnaBridge	156:ff21514d8981	711	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	712	DMA_CCR_CIRC));
AnnaBridge	156:ff21514d8981	713	}
AnnaBridge	156:ff21514d8981	714
AnnaBridge	156:ff21514d8981	715	/**
AnnaBridge	156:ff21514d8981	716	* @brief Set Peripheral increment mode.
AnnaBridge	156:ff21514d8981	717	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	156:ff21514d8981	718	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	719	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	720	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	721	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	722	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	723	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	724	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	725	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	726	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	727	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	728	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	156:ff21514d8981	729	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	730	* @retval None
AnnaBridge	156:ff21514d8981	731	*/
AnnaBridge	156:ff21514d8981	732	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	156:ff21514d8981	733	{
AnnaBridge	156:ff21514d8981	734	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	156:ff21514d8981	735	PeriphOrM2MSrcIncMode);
AnnaBridge	156:ff21514d8981	736	}
AnnaBridge	156:ff21514d8981	737
AnnaBridge	156:ff21514d8981	738	/**
AnnaBridge	156:ff21514d8981	739	* @brief Get Peripheral increment mode.
AnnaBridge	156:ff21514d8981	740	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	156:ff21514d8981	741	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	742	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	743	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	744	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	745	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	746	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	747	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	748	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	749	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	750	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	751	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	156:ff21514d8981	752	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	753	*/
AnnaBridge	156:ff21514d8981	754	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	755	{
AnnaBridge	156:ff21514d8981	756	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	757	DMA_CCR_PINC));
AnnaBridge	156:ff21514d8981	758	}
AnnaBridge	156:ff21514d8981	759
AnnaBridge	156:ff21514d8981	760	/**
AnnaBridge	156:ff21514d8981	761	* @brief Set Memory increment mode.
AnnaBridge	156:ff21514d8981	762	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	156:ff21514d8981	763	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	764	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	765	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	766	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	767	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	768	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	769	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	770	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	771	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	772	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	773	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	156:ff21514d8981	774	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	775	* @retval None
AnnaBridge	156:ff21514d8981	776	*/
AnnaBridge	156:ff21514d8981	777	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	156:ff21514d8981	778	{
AnnaBridge	156:ff21514d8981	779	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	156:ff21514d8981	780	MemoryOrM2MDstIncMode);
AnnaBridge	156:ff21514d8981	781	}
AnnaBridge	156:ff21514d8981	782
AnnaBridge	156:ff21514d8981	783	/**
AnnaBridge	156:ff21514d8981	784	* @brief Get Memory increment mode.
AnnaBridge	156:ff21514d8981	785	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	156:ff21514d8981	786	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	787	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	788	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	789	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	790	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	791	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	792	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	793	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	794	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	795	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	796	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	156:ff21514d8981	797	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	798	*/
AnnaBridge	156:ff21514d8981	799	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	800	{
AnnaBridge	156:ff21514d8981	801	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	802	DMA_CCR_MINC));
AnnaBridge	156:ff21514d8981	803	}
AnnaBridge	156:ff21514d8981	804
AnnaBridge	156:ff21514d8981	805	/**
AnnaBridge	156:ff21514d8981	806	* @brief Set Peripheral size.
AnnaBridge	156:ff21514d8981	807	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	156:ff21514d8981	808	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	809	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	810	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	811	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	812	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	813	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	814	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	815	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	816	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	817	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	818	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	819	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	820	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	821	* @retval None
AnnaBridge	156:ff21514d8981	822	*/
AnnaBridge	156:ff21514d8981	823	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	156:ff21514d8981	824	{
AnnaBridge	156:ff21514d8981	825	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	156:ff21514d8981	826	PeriphOrM2MSrcDataSize);
AnnaBridge	156:ff21514d8981	827	}
AnnaBridge	156:ff21514d8981	828
AnnaBridge	156:ff21514d8981	829	/**
AnnaBridge	156:ff21514d8981	830	* @brief Get Peripheral size.
AnnaBridge	156:ff21514d8981	831	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	156:ff21514d8981	832	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	833	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	834	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	835	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	836	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	837	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	838	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	839	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	840	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	841	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	842	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	843	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	844	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	845	*/
AnnaBridge	156:ff21514d8981	846	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	847	{
AnnaBridge	156:ff21514d8981	848	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	849	DMA_CCR_PSIZE));
AnnaBridge	156:ff21514d8981	850	}
AnnaBridge	156:ff21514d8981	851
AnnaBridge	156:ff21514d8981	852	/**
AnnaBridge	156:ff21514d8981	853	* @brief Set Memory size.
AnnaBridge	156:ff21514d8981	854	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	156:ff21514d8981	855	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	856	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	857	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	858	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	859	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	860	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	861	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	862	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	863	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	864	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	865	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	866	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	867	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	868	* @retval None
AnnaBridge	156:ff21514d8981	869	*/
AnnaBridge	156:ff21514d8981	870	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	156:ff21514d8981	871	{
AnnaBridge	156:ff21514d8981	872	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	156:ff21514d8981	873	MemoryOrM2MDstDataSize);
AnnaBridge	156:ff21514d8981	874	}
AnnaBridge	156:ff21514d8981	875
AnnaBridge	156:ff21514d8981	876	/**
AnnaBridge	156:ff21514d8981	877	* @brief Get Memory size.
AnnaBridge	156:ff21514d8981	878	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	156:ff21514d8981	879	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	880	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	881	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	882	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	883	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	884	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	885	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	886	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	887	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	888	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	889	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	890	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	891	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	892	*/
AnnaBridge	156:ff21514d8981	893	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	894	{
AnnaBridge	156:ff21514d8981	895	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	896	DMA_CCR_MSIZE));
AnnaBridge	156:ff21514d8981	897	}
AnnaBridge	156:ff21514d8981	898
AnnaBridge	156:ff21514d8981	899	/**
AnnaBridge	156:ff21514d8981	900	* @brief Set Channel priority level.
AnnaBridge	156:ff21514d8981	901	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	156:ff21514d8981	902	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	903	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	904	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	905	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	906	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	907	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	908	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	909	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	910	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	911	* @param Priority This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	912	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	156:ff21514d8981	913	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	156:ff21514d8981	914	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	156:ff21514d8981	915	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	916	* @retval None
AnnaBridge	156:ff21514d8981	917	*/
AnnaBridge	156:ff21514d8981	918	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	156:ff21514d8981	919	{
AnnaBridge	156:ff21514d8981	920	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	156:ff21514d8981	921	Priority);
AnnaBridge	156:ff21514d8981	922	}
AnnaBridge	156:ff21514d8981	923
AnnaBridge	156:ff21514d8981	924	/**
AnnaBridge	156:ff21514d8981	925	* @brief Get Channel priority level.
AnnaBridge	156:ff21514d8981	926	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	156:ff21514d8981	927	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	928	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	929	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	930	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	931	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	932	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	933	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	934	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	935	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	936	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	937	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	156:ff21514d8981	938	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	156:ff21514d8981	939	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	156:ff21514d8981	940	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	941	*/
AnnaBridge	156:ff21514d8981	942	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	943	{
AnnaBridge	156:ff21514d8981	944	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	945	DMA_CCR_PL));
AnnaBridge	156:ff21514d8981	946	}
AnnaBridge	156:ff21514d8981	947
AnnaBridge	156:ff21514d8981	948	/**
AnnaBridge	156:ff21514d8981	949	* @brief Set Number of data to transfer.
AnnaBridge	156:ff21514d8981	950	* @note This action has no effect if
AnnaBridge	156:ff21514d8981	951	* channel is enabled.
AnnaBridge	156:ff21514d8981	952	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	156:ff21514d8981	953	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	954	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	955	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	956	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	957	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	958	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	959	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	960	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	961	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	962	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	156:ff21514d8981	963	* @retval None
AnnaBridge	156:ff21514d8981	964	*/
AnnaBridge	156:ff21514d8981	965	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	156:ff21514d8981	966	{
AnnaBridge	156:ff21514d8981	967	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	156:ff21514d8981	968	DMA_CNDTR_NDT, NbData);
AnnaBridge	156:ff21514d8981	969	}
AnnaBridge	156:ff21514d8981	970
AnnaBridge	156:ff21514d8981	971	/**
AnnaBridge	156:ff21514d8981	972	* @brief Get Number of data to transfer.
AnnaBridge	156:ff21514d8981	973	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	156:ff21514d8981	974	* remaining bytes to be transmitted.
AnnaBridge	156:ff21514d8981	975	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	156:ff21514d8981	976	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	977	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	978	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	979	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	980	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	981	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	982	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	983	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	984	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	985	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	986	*/
AnnaBridge	156:ff21514d8981	987	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	988	{
AnnaBridge	156:ff21514d8981	989	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	156:ff21514d8981	990	DMA_CNDTR_NDT));
AnnaBridge	156:ff21514d8981	991	}
AnnaBridge	156:ff21514d8981	992
AnnaBridge	156:ff21514d8981	993	/**
AnnaBridge	156:ff21514d8981	994	* @brief Configure the Source and Destination addresses.
AnnaBridge	156:ff21514d8981	995	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	996	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	156:ff21514d8981	997	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	156:ff21514d8981	998	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	156:ff21514d8981	999	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1000	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1001	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1002	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1003	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1004	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1005	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1006	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1007	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1008	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1009	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1010	* @param Direction This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1011	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	1012	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	1013	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	1014	* @retval None
AnnaBridge	156:ff21514d8981	1015	*/
AnnaBridge	156:ff21514d8981	1016	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	156:ff21514d8981	1017	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	156:ff21514d8981	1018	{
AnnaBridge	156:ff21514d8981	1019	/* Direction Memory to Periph */
AnnaBridge	156:ff21514d8981	1020	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	156:ff21514d8981	1021	{
AnnaBridge	156:ff21514d8981	1022	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	156:ff21514d8981	1023	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	156:ff21514d8981	1024	}
AnnaBridge	156:ff21514d8981	1025	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	156:ff21514d8981	1026	else
AnnaBridge	156:ff21514d8981	1027	{
AnnaBridge	156:ff21514d8981	1028	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	156:ff21514d8981	1029	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	156:ff21514d8981	1030	}
AnnaBridge	156:ff21514d8981	1031	}
AnnaBridge	156:ff21514d8981	1032
AnnaBridge	156:ff21514d8981	1033	/**
AnnaBridge	156:ff21514d8981	1034	* @brief Set the Memory address.
AnnaBridge	156:ff21514d8981	1035	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1036	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1037	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	156:ff21514d8981	1038	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1039	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1040	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1041	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1042	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1043	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1044	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1045	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1046	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1047	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1048	* @retval None
AnnaBridge	156:ff21514d8981	1049	*/
AnnaBridge	156:ff21514d8981	1050	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1051	{
AnnaBridge	156:ff21514d8981	1052	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1053	}
AnnaBridge	156:ff21514d8981	1054
AnnaBridge	156:ff21514d8981	1055	/**
AnnaBridge	156:ff21514d8981	1056	* @brief Set the Peripheral address.
AnnaBridge	156:ff21514d8981	1057	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1058	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1059	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	156:ff21514d8981	1060	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1061	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1062	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1063	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1064	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1065	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1066	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1067	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1068	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1069	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1070	* @retval None
AnnaBridge	156:ff21514d8981	1071	*/
AnnaBridge	156:ff21514d8981	1072	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	156:ff21514d8981	1073	{
AnnaBridge	156:ff21514d8981	1074	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	156:ff21514d8981	1075	}
AnnaBridge	156:ff21514d8981	1076
AnnaBridge	156:ff21514d8981	1077	/**
AnnaBridge	156:ff21514d8981	1078	* @brief Get Memory address.
AnnaBridge	156:ff21514d8981	1079	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1080	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	156:ff21514d8981	1081	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1082	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1083	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1084	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1085	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1086	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1087	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1088	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1089	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1090	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1091	*/
AnnaBridge	156:ff21514d8981	1092	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1093	{
AnnaBridge	156:ff21514d8981	1094	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	156:ff21514d8981	1095	}
AnnaBridge	156:ff21514d8981	1096
AnnaBridge	156:ff21514d8981	1097	/**
AnnaBridge	156:ff21514d8981	1098	* @brief Get Peripheral address.
AnnaBridge	156:ff21514d8981	1099	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1100	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	156:ff21514d8981	1101	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1102	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1103	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1104	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1105	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1106	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1107	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1108	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1109	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1110	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1111	*/
AnnaBridge	156:ff21514d8981	1112	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1113	{
AnnaBridge	156:ff21514d8981	1114	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	156:ff21514d8981	1115	}
AnnaBridge	156:ff21514d8981	1116
AnnaBridge	156:ff21514d8981	1117	/**
AnnaBridge	156:ff21514d8981	1118	* @brief Set the Memory to Memory Source address.
AnnaBridge	156:ff21514d8981	1119	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1120	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1121	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	156:ff21514d8981	1122	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1123	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1124	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1125	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1126	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1127	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1128	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1129	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1130	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1131	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1132	* @retval None
AnnaBridge	156:ff21514d8981	1133	*/
AnnaBridge	156:ff21514d8981	1134	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1135	{
AnnaBridge	156:ff21514d8981	1136	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1137	}
AnnaBridge	156:ff21514d8981	1138
AnnaBridge	156:ff21514d8981	1139	/**
AnnaBridge	156:ff21514d8981	1140	* @brief Set the Memory to Memory Destination address.
AnnaBridge	156:ff21514d8981	1141	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1142	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1143	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	156:ff21514d8981	1144	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1145	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1146	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1147	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1148	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1149	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1150	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1151	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1152	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1153	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1154	* @retval None
AnnaBridge	156:ff21514d8981	1155	*/
AnnaBridge	156:ff21514d8981	1156	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1157	{
AnnaBridge	156:ff21514d8981	1158	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1159	}
AnnaBridge	156:ff21514d8981	1160
AnnaBridge	156:ff21514d8981	1161	/**
AnnaBridge	156:ff21514d8981	1162	* @brief Get the Memory to Memory Source address.
AnnaBridge	156:ff21514d8981	1163	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1164	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	156:ff21514d8981	1165	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1166	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1167	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1168	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1169	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1170	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1171	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1172	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1173	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1174	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1175	*/
AnnaBridge	156:ff21514d8981	1176	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1177	{
AnnaBridge	156:ff21514d8981	1178	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	156:ff21514d8981	1179	}
AnnaBridge	156:ff21514d8981	1180
AnnaBridge	156:ff21514d8981	1181	/**
AnnaBridge	156:ff21514d8981	1182	* @brief Get the Memory to Memory Destination address.
AnnaBridge	156:ff21514d8981	1183	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1184	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	156:ff21514d8981	1185	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1186	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1187	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1188	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1189	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1190	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1191	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1192	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1193	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1194	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1195	*/
AnnaBridge	156:ff21514d8981	1196	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1197	{
AnnaBridge	156:ff21514d8981	1198	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	156:ff21514d8981	1199	}
AnnaBridge	156:ff21514d8981	1200
AnnaBridge	156:ff21514d8981	1201	/**
AnnaBridge	156:ff21514d8981	1202	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	156:ff21514d8981	1203	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	156:ff21514d8981	1204	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1205	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1206	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1207	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1208	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1209	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1210	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	156:ff21514d8981	1211	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1212	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1213	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1214	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1215	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1216	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1217	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1218	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1219	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1220	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1221	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	156:ff21514d8981	1222	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	156:ff21514d8981	1223	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	156:ff21514d8981	1224	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	156:ff21514d8981	1225	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	156:ff21514d8981	1226	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	156:ff21514d8981	1227	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	156:ff21514d8981	1228	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	156:ff21514d8981	1229	* @retval None
AnnaBridge	156:ff21514d8981	1230	*/
AnnaBridge	156:ff21514d8981	1231	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	156:ff21514d8981	1232	{
AnnaBridge	156:ff21514d8981	1233	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	156:ff21514d8981	1234	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	156:ff21514d8981	1235	}
AnnaBridge	156:ff21514d8981	1236
AnnaBridge	156:ff21514d8981	1237	/**
AnnaBridge	156:ff21514d8981	1238	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	156:ff21514d8981	1239	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1240	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1241	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1242	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1243	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1244	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1245	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	156:ff21514d8981	1246	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1247	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1248	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1249	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1250	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1251	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1252	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1253	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1254	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1255	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1256	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	156:ff21514d8981	1257	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	156:ff21514d8981	1258	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	156:ff21514d8981	1259	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	156:ff21514d8981	1260	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	156:ff21514d8981	1261	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	156:ff21514d8981	1262	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	156:ff21514d8981	1263	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	156:ff21514d8981	1264	*/
AnnaBridge	156:ff21514d8981	1265	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1266	{
AnnaBridge	156:ff21514d8981	1267	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	156:ff21514d8981	1268	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	156:ff21514d8981	1269	}
AnnaBridge	156:ff21514d8981	1270
AnnaBridge	156:ff21514d8981	1271	/**
AnnaBridge	156:ff21514d8981	1272	* @}
AnnaBridge	156:ff21514d8981	1273	*/
AnnaBridge	156:ff21514d8981	1274
AnnaBridge	156:ff21514d8981	1275	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	156:ff21514d8981	1276	* @{
AnnaBridge	156:ff21514d8981	1277	*/
AnnaBridge	156:ff21514d8981	1278
AnnaBridge	156:ff21514d8981	1279	/**
AnnaBridge	156:ff21514d8981	1280	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	156:ff21514d8981	1281	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	156:ff21514d8981	1282	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1283	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1284	*/
AnnaBridge	156:ff21514d8981	1285	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1286	{
AnnaBridge	156:ff21514d8981	1287	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	156:ff21514d8981	1288	}
AnnaBridge	156:ff21514d8981	1289
AnnaBridge	156:ff21514d8981	1290	/**
AnnaBridge	156:ff21514d8981	1291	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	156:ff21514d8981	1292	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	156:ff21514d8981	1293	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1294	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1295	*/
AnnaBridge	156:ff21514d8981	1296	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1297	{
AnnaBridge	156:ff21514d8981	1298	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	156:ff21514d8981	1299	}
AnnaBridge	156:ff21514d8981	1300
AnnaBridge	156:ff21514d8981	1301	/**
AnnaBridge	156:ff21514d8981	1302	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	156:ff21514d8981	1303	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	156:ff21514d8981	1304	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1305	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1306	*/
AnnaBridge	156:ff21514d8981	1307	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1308	{
AnnaBridge	156:ff21514d8981	1309	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	156:ff21514d8981	1310	}
AnnaBridge	156:ff21514d8981	1311
AnnaBridge	156:ff21514d8981	1312	/**
AnnaBridge	156:ff21514d8981	1313	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	156:ff21514d8981	1314	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	156:ff21514d8981	1315	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1316	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1317	*/
AnnaBridge	156:ff21514d8981	1318	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1319	{
AnnaBridge	156:ff21514d8981	1320	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	156:ff21514d8981	1321	}
AnnaBridge	156:ff21514d8981	1322
AnnaBridge	156:ff21514d8981	1323	/**
AnnaBridge	156:ff21514d8981	1324	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	156:ff21514d8981	1325	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	156:ff21514d8981	1326	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1327	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1328	*/
AnnaBridge	156:ff21514d8981	1329	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1330	{
AnnaBridge	156:ff21514d8981	1331	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	156:ff21514d8981	1332	}
AnnaBridge	156:ff21514d8981	1333
AnnaBridge	156:ff21514d8981	1334	/**
AnnaBridge	156:ff21514d8981	1335	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	156:ff21514d8981	1336	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	156:ff21514d8981	1337	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1338	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1339	*/
AnnaBridge	156:ff21514d8981	1340	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1341	{
AnnaBridge	156:ff21514d8981	1342	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	156:ff21514d8981	1343	}
AnnaBridge	156:ff21514d8981	1344
AnnaBridge	156:ff21514d8981	1345	/**
AnnaBridge	156:ff21514d8981	1346	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	156:ff21514d8981	1347	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	156:ff21514d8981	1348	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1349	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1350	*/
AnnaBridge	156:ff21514d8981	1351	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1352	{
AnnaBridge	156:ff21514d8981	1353	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	156:ff21514d8981	1354	}
AnnaBridge	156:ff21514d8981	1355
AnnaBridge	156:ff21514d8981	1356	/**
AnnaBridge	156:ff21514d8981	1357	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	156:ff21514d8981	1358	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	156:ff21514d8981	1359	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1360	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1361	*/
AnnaBridge	156:ff21514d8981	1362	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1363	{
AnnaBridge	156:ff21514d8981	1364	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	156:ff21514d8981	1365	}
AnnaBridge	156:ff21514d8981	1366
AnnaBridge	156:ff21514d8981	1367	/**
AnnaBridge	156:ff21514d8981	1368	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	156:ff21514d8981	1369	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	156:ff21514d8981	1370	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1371	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1372	*/
AnnaBridge	156:ff21514d8981	1373	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1374	{
AnnaBridge	156:ff21514d8981	1375	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	156:ff21514d8981	1376	}
AnnaBridge	156:ff21514d8981	1377
AnnaBridge	156:ff21514d8981	1378	/**
AnnaBridge	156:ff21514d8981	1379	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	156:ff21514d8981	1380	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	156:ff21514d8981	1381	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1382	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1383	*/
AnnaBridge	156:ff21514d8981	1384	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1385	{
AnnaBridge	156:ff21514d8981	1386	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	156:ff21514d8981	1387	}
AnnaBridge	156:ff21514d8981	1388
AnnaBridge	156:ff21514d8981	1389	/**
AnnaBridge	156:ff21514d8981	1390	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	156:ff21514d8981	1391	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	156:ff21514d8981	1392	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1393	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1394	*/
AnnaBridge	156:ff21514d8981	1395	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1396	{
AnnaBridge	156:ff21514d8981	1397	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	156:ff21514d8981	1398	}
AnnaBridge	156:ff21514d8981	1399
AnnaBridge	156:ff21514d8981	1400	/**
AnnaBridge	156:ff21514d8981	1401	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	156:ff21514d8981	1402	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	156:ff21514d8981	1403	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1404	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1405	*/
AnnaBridge	156:ff21514d8981	1406	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1407	{
AnnaBridge	156:ff21514d8981	1408	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	156:ff21514d8981	1409	}
AnnaBridge	156:ff21514d8981	1410
AnnaBridge	156:ff21514d8981	1411	/**
AnnaBridge	156:ff21514d8981	1412	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	156:ff21514d8981	1413	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	156:ff21514d8981	1414	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1415	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1416	*/
AnnaBridge	156:ff21514d8981	1417	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1418	{
AnnaBridge	156:ff21514d8981	1419	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	156:ff21514d8981	1420	}
AnnaBridge	156:ff21514d8981	1421
AnnaBridge	156:ff21514d8981	1422	/**
AnnaBridge	156:ff21514d8981	1423	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	156:ff21514d8981	1424	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	156:ff21514d8981	1425	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1426	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1427	*/
AnnaBridge	156:ff21514d8981	1428	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1429	{
AnnaBridge	156:ff21514d8981	1430	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	156:ff21514d8981	1431	}
AnnaBridge	156:ff21514d8981	1432
AnnaBridge	156:ff21514d8981	1433	/**
AnnaBridge	156:ff21514d8981	1434	* @brief Get Channel 1 half transfer flag.
AnnaBridge	156:ff21514d8981	1435	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	156:ff21514d8981	1436	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1437	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1438	*/
AnnaBridge	156:ff21514d8981	1439	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1440	{
AnnaBridge	156:ff21514d8981	1441	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	156:ff21514d8981	1442	}
AnnaBridge	156:ff21514d8981	1443
AnnaBridge	156:ff21514d8981	1444	/**
AnnaBridge	156:ff21514d8981	1445	* @brief Get Channel 2 half transfer flag.
AnnaBridge	156:ff21514d8981	1446	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	156:ff21514d8981	1447	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1448	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1449	*/
AnnaBridge	156:ff21514d8981	1450	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1451	{
AnnaBridge	156:ff21514d8981	1452	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	156:ff21514d8981	1453	}
AnnaBridge	156:ff21514d8981	1454
AnnaBridge	156:ff21514d8981	1455	/**
AnnaBridge	156:ff21514d8981	1456	* @brief Get Channel 3 half transfer flag.
AnnaBridge	156:ff21514d8981	1457	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	156:ff21514d8981	1458	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1459	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1460	*/
AnnaBridge	156:ff21514d8981	1461	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1462	{
AnnaBridge	156:ff21514d8981	1463	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	156:ff21514d8981	1464	}
AnnaBridge	156:ff21514d8981	1465
AnnaBridge	156:ff21514d8981	1466	/**
AnnaBridge	156:ff21514d8981	1467	* @brief Get Channel 4 half transfer flag.
AnnaBridge	156:ff21514d8981	1468	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	156:ff21514d8981	1469	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1470	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1471	*/
AnnaBridge	156:ff21514d8981	1472	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1473	{
AnnaBridge	156:ff21514d8981	1474	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	156:ff21514d8981	1475	}
AnnaBridge	156:ff21514d8981	1476
AnnaBridge	156:ff21514d8981	1477	/**
AnnaBridge	156:ff21514d8981	1478	* @brief Get Channel 5 half transfer flag.
AnnaBridge	156:ff21514d8981	1479	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	156:ff21514d8981	1480	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1481	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1482	*/
AnnaBridge	156:ff21514d8981	1483	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1484	{
AnnaBridge	156:ff21514d8981	1485	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	156:ff21514d8981	1486	}
AnnaBridge	156:ff21514d8981	1487
AnnaBridge	156:ff21514d8981	1488	/**
AnnaBridge	156:ff21514d8981	1489	* @brief Get Channel 6 half transfer flag.
AnnaBridge	156:ff21514d8981	1490	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	156:ff21514d8981	1491	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1492	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1493	*/
AnnaBridge	156:ff21514d8981	1494	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1495	{
AnnaBridge	156:ff21514d8981	1496	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	156:ff21514d8981	1497	}
AnnaBridge	156:ff21514d8981	1498
AnnaBridge	156:ff21514d8981	1499	/**
AnnaBridge	156:ff21514d8981	1500	* @brief Get Channel 7 half transfer flag.
AnnaBridge	156:ff21514d8981	1501	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	156:ff21514d8981	1502	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1503	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1504	*/
AnnaBridge	156:ff21514d8981	1505	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1506	{
AnnaBridge	156:ff21514d8981	1507	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	156:ff21514d8981	1508	}
AnnaBridge	156:ff21514d8981	1509
AnnaBridge	156:ff21514d8981	1510	/**
AnnaBridge	156:ff21514d8981	1511	* @brief Get Channel 1 transfer error flag.
AnnaBridge	156:ff21514d8981	1512	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	156:ff21514d8981	1513	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1514	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1515	*/
AnnaBridge	156:ff21514d8981	1516	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1517	{
AnnaBridge	156:ff21514d8981	1518	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	156:ff21514d8981	1519	}
AnnaBridge	156:ff21514d8981	1520
AnnaBridge	156:ff21514d8981	1521	/**
AnnaBridge	156:ff21514d8981	1522	* @brief Get Channel 2 transfer error flag.
AnnaBridge	156:ff21514d8981	1523	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	156:ff21514d8981	1524	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1525	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1526	*/
AnnaBridge	156:ff21514d8981	1527	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1528	{
AnnaBridge	156:ff21514d8981	1529	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	156:ff21514d8981	1530	}
AnnaBridge	156:ff21514d8981	1531
AnnaBridge	156:ff21514d8981	1532	/**
AnnaBridge	156:ff21514d8981	1533	* @brief Get Channel 3 transfer error flag.
AnnaBridge	156:ff21514d8981	1534	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	156:ff21514d8981	1535	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1536	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1537	*/
AnnaBridge	156:ff21514d8981	1538	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1539	{
AnnaBridge	156:ff21514d8981	1540	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	156:ff21514d8981	1541	}
AnnaBridge	156:ff21514d8981	1542
AnnaBridge	156:ff21514d8981	1543	/**
AnnaBridge	156:ff21514d8981	1544	* @brief Get Channel 4 transfer error flag.
AnnaBridge	156:ff21514d8981	1545	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	156:ff21514d8981	1546	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1547	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1548	*/
AnnaBridge	156:ff21514d8981	1549	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1550	{
AnnaBridge	156:ff21514d8981	1551	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	156:ff21514d8981	1552	}
AnnaBridge	156:ff21514d8981	1553
AnnaBridge	156:ff21514d8981	1554	/**
AnnaBridge	156:ff21514d8981	1555	* @brief Get Channel 5 transfer error flag.
AnnaBridge	156:ff21514d8981	1556	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	156:ff21514d8981	1557	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1558	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1559	*/
AnnaBridge	156:ff21514d8981	1560	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1561	{
AnnaBridge	156:ff21514d8981	1562	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	156:ff21514d8981	1563	}
AnnaBridge	156:ff21514d8981	1564
AnnaBridge	156:ff21514d8981	1565	/**
AnnaBridge	156:ff21514d8981	1566	* @brief Get Channel 6 transfer error flag.
AnnaBridge	156:ff21514d8981	1567	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	156:ff21514d8981	1568	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1569	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1570	*/
AnnaBridge	156:ff21514d8981	1571	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1572	{
AnnaBridge	156:ff21514d8981	1573	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	156:ff21514d8981	1574	}
AnnaBridge	156:ff21514d8981	1575
AnnaBridge	156:ff21514d8981	1576	/**
AnnaBridge	156:ff21514d8981	1577	* @brief Get Channel 7 transfer error flag.
AnnaBridge	156:ff21514d8981	1578	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	156:ff21514d8981	1579	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1580	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1581	*/
AnnaBridge	156:ff21514d8981	1582	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1583	{
AnnaBridge	156:ff21514d8981	1584	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	156:ff21514d8981	1585	}
AnnaBridge	156:ff21514d8981	1586
AnnaBridge	156:ff21514d8981	1587	/**
AnnaBridge	156:ff21514d8981	1588	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	156:ff21514d8981	1589	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	156:ff21514d8981	1590	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1591	* @retval None
AnnaBridge	156:ff21514d8981	1592	*/
AnnaBridge	156:ff21514d8981	1593	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1594	{
AnnaBridge	156:ff21514d8981	1595	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	156:ff21514d8981	1596	}
AnnaBridge	156:ff21514d8981	1597
AnnaBridge	156:ff21514d8981	1598	/**
AnnaBridge	156:ff21514d8981	1599	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	156:ff21514d8981	1600	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	156:ff21514d8981	1601	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1602	* @retval None
AnnaBridge	156:ff21514d8981	1603	*/
AnnaBridge	156:ff21514d8981	1604	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1605	{
AnnaBridge	156:ff21514d8981	1606	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	156:ff21514d8981	1607	}
AnnaBridge	156:ff21514d8981	1608
AnnaBridge	156:ff21514d8981	1609	/**
AnnaBridge	156:ff21514d8981	1610	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	156:ff21514d8981	1611	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	156:ff21514d8981	1612	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1613	* @retval None
AnnaBridge	156:ff21514d8981	1614	*/
AnnaBridge	156:ff21514d8981	1615	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1616	{
AnnaBridge	156:ff21514d8981	1617	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	156:ff21514d8981	1618	}
AnnaBridge	156:ff21514d8981	1619
AnnaBridge	156:ff21514d8981	1620	/**
AnnaBridge	156:ff21514d8981	1621	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	156:ff21514d8981	1622	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	156:ff21514d8981	1623	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1624	* @retval None
AnnaBridge	156:ff21514d8981	1625	*/
AnnaBridge	156:ff21514d8981	1626	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1627	{
AnnaBridge	156:ff21514d8981	1628	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	156:ff21514d8981	1629	}
AnnaBridge	156:ff21514d8981	1630
AnnaBridge	156:ff21514d8981	1631	/**
AnnaBridge	156:ff21514d8981	1632	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	156:ff21514d8981	1633	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	156:ff21514d8981	1634	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1635	* @retval None
AnnaBridge	156:ff21514d8981	1636	*/
AnnaBridge	156:ff21514d8981	1637	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1638	{
AnnaBridge	156:ff21514d8981	1639	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	156:ff21514d8981	1640	}
AnnaBridge	156:ff21514d8981	1641
AnnaBridge	156:ff21514d8981	1642	/**
AnnaBridge	156:ff21514d8981	1643	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	156:ff21514d8981	1644	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	156:ff21514d8981	1645	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1646	* @retval None
AnnaBridge	156:ff21514d8981	1647	*/
AnnaBridge	156:ff21514d8981	1648	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1649	{
AnnaBridge	156:ff21514d8981	1650	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	156:ff21514d8981	1651	}
AnnaBridge	156:ff21514d8981	1652
AnnaBridge	156:ff21514d8981	1653	/**
AnnaBridge	156:ff21514d8981	1654	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	156:ff21514d8981	1655	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	156:ff21514d8981	1656	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1657	* @retval None
AnnaBridge	156:ff21514d8981	1658	*/
AnnaBridge	156:ff21514d8981	1659	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1660	{
AnnaBridge	156:ff21514d8981	1661	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	156:ff21514d8981	1662	}
AnnaBridge	156:ff21514d8981	1663
AnnaBridge	156:ff21514d8981	1664	/**
AnnaBridge	156:ff21514d8981	1665	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	156:ff21514d8981	1666	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	156:ff21514d8981	1667	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1668	* @retval None
AnnaBridge	156:ff21514d8981	1669	*/
AnnaBridge	156:ff21514d8981	1670	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1671	{
AnnaBridge	156:ff21514d8981	1672	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	156:ff21514d8981	1673	}
AnnaBridge	156:ff21514d8981	1674
AnnaBridge	156:ff21514d8981	1675	/**
AnnaBridge	156:ff21514d8981	1676	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	156:ff21514d8981	1677	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	156:ff21514d8981	1678	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1679	* @retval None
AnnaBridge	156:ff21514d8981	1680	*/
AnnaBridge	156:ff21514d8981	1681	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1682	{
AnnaBridge	156:ff21514d8981	1683	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	156:ff21514d8981	1684	}
AnnaBridge	156:ff21514d8981	1685
AnnaBridge	156:ff21514d8981	1686	/**
AnnaBridge	156:ff21514d8981	1687	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	156:ff21514d8981	1688	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	156:ff21514d8981	1689	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1690	* @retval None
AnnaBridge	156:ff21514d8981	1691	*/
AnnaBridge	156:ff21514d8981	1692	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1693	{
AnnaBridge	156:ff21514d8981	1694	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	156:ff21514d8981	1695	}
AnnaBridge	156:ff21514d8981	1696
AnnaBridge	156:ff21514d8981	1697	/**
AnnaBridge	156:ff21514d8981	1698	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	156:ff21514d8981	1699	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	156:ff21514d8981	1700	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1701	* @retval None
AnnaBridge	156:ff21514d8981	1702	*/
AnnaBridge	156:ff21514d8981	1703	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1704	{
AnnaBridge	156:ff21514d8981	1705	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	156:ff21514d8981	1706	}
AnnaBridge	156:ff21514d8981	1707
AnnaBridge	156:ff21514d8981	1708	/**
AnnaBridge	156:ff21514d8981	1709	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	156:ff21514d8981	1710	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	156:ff21514d8981	1711	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1712	* @retval None
AnnaBridge	156:ff21514d8981	1713	*/
AnnaBridge	156:ff21514d8981	1714	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1715	{
AnnaBridge	156:ff21514d8981	1716	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	156:ff21514d8981	1717	}
AnnaBridge	156:ff21514d8981	1718
AnnaBridge	156:ff21514d8981	1719	/**
AnnaBridge	156:ff21514d8981	1720	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	156:ff21514d8981	1721	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	156:ff21514d8981	1722	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1723	* @retval None
AnnaBridge	156:ff21514d8981	1724	*/
AnnaBridge	156:ff21514d8981	1725	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1726	{
AnnaBridge	156:ff21514d8981	1727	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	156:ff21514d8981	1728	}
AnnaBridge	156:ff21514d8981	1729
AnnaBridge	156:ff21514d8981	1730	/**
AnnaBridge	156:ff21514d8981	1731	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	156:ff21514d8981	1732	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	156:ff21514d8981	1733	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1734	* @retval None
AnnaBridge	156:ff21514d8981	1735	*/
AnnaBridge	156:ff21514d8981	1736	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1737	{
AnnaBridge	156:ff21514d8981	1738	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	156:ff21514d8981	1739	}
AnnaBridge	156:ff21514d8981	1740
AnnaBridge	156:ff21514d8981	1741	/**
AnnaBridge	156:ff21514d8981	1742	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	156:ff21514d8981	1743	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	156:ff21514d8981	1744	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1745	* @retval None
AnnaBridge	156:ff21514d8981	1746	*/
AnnaBridge	156:ff21514d8981	1747	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1748	{
AnnaBridge	156:ff21514d8981	1749	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	156:ff21514d8981	1750	}
AnnaBridge	156:ff21514d8981	1751
AnnaBridge	156:ff21514d8981	1752	/**
AnnaBridge	156:ff21514d8981	1753	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	156:ff21514d8981	1754	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	156:ff21514d8981	1755	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1756	* @retval None
AnnaBridge	156:ff21514d8981	1757	*/
AnnaBridge	156:ff21514d8981	1758	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1759	{
AnnaBridge	156:ff21514d8981	1760	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	156:ff21514d8981	1761	}
AnnaBridge	156:ff21514d8981	1762
AnnaBridge	156:ff21514d8981	1763	/**
AnnaBridge	156:ff21514d8981	1764	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	156:ff21514d8981	1765	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	156:ff21514d8981	1766	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1767	* @retval None
AnnaBridge	156:ff21514d8981	1768	*/
AnnaBridge	156:ff21514d8981	1769	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1770	{
AnnaBridge	156:ff21514d8981	1771	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	156:ff21514d8981	1772	}
AnnaBridge	156:ff21514d8981	1773
AnnaBridge	156:ff21514d8981	1774	/**
AnnaBridge	156:ff21514d8981	1775	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	156:ff21514d8981	1776	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	156:ff21514d8981	1777	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1778	* @retval None
AnnaBridge	156:ff21514d8981	1779	*/
AnnaBridge	156:ff21514d8981	1780	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1781	{
AnnaBridge	156:ff21514d8981	1782	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	156:ff21514d8981	1783	}
AnnaBridge	156:ff21514d8981	1784
AnnaBridge	156:ff21514d8981	1785	/**
AnnaBridge	156:ff21514d8981	1786	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	156:ff21514d8981	1787	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	156:ff21514d8981	1788	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1789	* @retval None
AnnaBridge	156:ff21514d8981	1790	*/
AnnaBridge	156:ff21514d8981	1791	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1792	{
AnnaBridge	156:ff21514d8981	1793	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	156:ff21514d8981	1794	}
AnnaBridge	156:ff21514d8981	1795
AnnaBridge	156:ff21514d8981	1796	/**
AnnaBridge	156:ff21514d8981	1797	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	156:ff21514d8981	1798	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	156:ff21514d8981	1799	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1800	* @retval None
AnnaBridge	156:ff21514d8981	1801	*/
AnnaBridge	156:ff21514d8981	1802	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1803	{
AnnaBridge	156:ff21514d8981	1804	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	156:ff21514d8981	1805	}
AnnaBridge	156:ff21514d8981	1806
AnnaBridge	156:ff21514d8981	1807	/**
AnnaBridge	156:ff21514d8981	1808	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	156:ff21514d8981	1809	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	156:ff21514d8981	1810	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1811	* @retval None
AnnaBridge	156:ff21514d8981	1812	*/
AnnaBridge	156:ff21514d8981	1813	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1814	{
AnnaBridge	156:ff21514d8981	1815	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	156:ff21514d8981	1816	}
AnnaBridge	156:ff21514d8981	1817
AnnaBridge	156:ff21514d8981	1818	/**
AnnaBridge	156:ff21514d8981	1819	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	156:ff21514d8981	1820	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	156:ff21514d8981	1821	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1822	* @retval None
AnnaBridge	156:ff21514d8981	1823	*/
AnnaBridge	156:ff21514d8981	1824	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1825	{
AnnaBridge	156:ff21514d8981	1826	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	156:ff21514d8981	1827	}
AnnaBridge	156:ff21514d8981	1828
AnnaBridge	156:ff21514d8981	1829	/**
AnnaBridge	156:ff21514d8981	1830	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	156:ff21514d8981	1831	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	156:ff21514d8981	1832	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1833	* @retval None
AnnaBridge	156:ff21514d8981	1834	*/
AnnaBridge	156:ff21514d8981	1835	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1836	{
AnnaBridge	156:ff21514d8981	1837	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	156:ff21514d8981	1838	}
AnnaBridge	156:ff21514d8981	1839
AnnaBridge	156:ff21514d8981	1840	/**
AnnaBridge	156:ff21514d8981	1841	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	156:ff21514d8981	1842	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	156:ff21514d8981	1843	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1844	* @retval None
AnnaBridge	156:ff21514d8981	1845	*/
AnnaBridge	156:ff21514d8981	1846	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1847	{
AnnaBridge	156:ff21514d8981	1848	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	156:ff21514d8981	1849	}
AnnaBridge	156:ff21514d8981	1850
AnnaBridge	156:ff21514d8981	1851	/**
AnnaBridge	156:ff21514d8981	1852	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	156:ff21514d8981	1853	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	156:ff21514d8981	1854	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1855	* @retval None
AnnaBridge	156:ff21514d8981	1856	*/
AnnaBridge	156:ff21514d8981	1857	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1858	{
AnnaBridge	156:ff21514d8981	1859	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	156:ff21514d8981	1860	}
AnnaBridge	156:ff21514d8981	1861
AnnaBridge	156:ff21514d8981	1862	/**
AnnaBridge	156:ff21514d8981	1863	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	156:ff21514d8981	1864	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	156:ff21514d8981	1865	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1866	* @retval None
AnnaBridge	156:ff21514d8981	1867	*/
AnnaBridge	156:ff21514d8981	1868	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1869	{
AnnaBridge	156:ff21514d8981	1870	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	156:ff21514d8981	1871	}
AnnaBridge	156:ff21514d8981	1872
AnnaBridge	156:ff21514d8981	1873	/**
AnnaBridge	156:ff21514d8981	1874	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	156:ff21514d8981	1875	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	156:ff21514d8981	1876	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1877	* @retval None
AnnaBridge	156:ff21514d8981	1878	*/
AnnaBridge	156:ff21514d8981	1879	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1880	{
AnnaBridge	156:ff21514d8981	1881	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	156:ff21514d8981	1882	}
AnnaBridge	156:ff21514d8981	1883
AnnaBridge	156:ff21514d8981	1884	/**
AnnaBridge	156:ff21514d8981	1885	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	156:ff21514d8981	1886	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	156:ff21514d8981	1887	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1888	* @retval None
AnnaBridge	156:ff21514d8981	1889	*/
AnnaBridge	156:ff21514d8981	1890	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1891	{
AnnaBridge	156:ff21514d8981	1892	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	156:ff21514d8981	1893	}
AnnaBridge	156:ff21514d8981	1894
AnnaBridge	156:ff21514d8981	1895	/**
AnnaBridge	156:ff21514d8981	1896	* @}
AnnaBridge	156:ff21514d8981	1897	*/
AnnaBridge	156:ff21514d8981	1898
AnnaBridge	156:ff21514d8981	1899	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	156:ff21514d8981	1900	* @{
AnnaBridge	156:ff21514d8981	1901	*/
AnnaBridge	156:ff21514d8981	1902	/**
AnnaBridge	156:ff21514d8981	1903	* @brief Enable Transfer complete interrupt.
AnnaBridge	156:ff21514d8981	1904	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	156:ff21514d8981	1905	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1906	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1907	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1908	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1909	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1910	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1911	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1912	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1913	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1914	* @retval None
AnnaBridge	156:ff21514d8981	1915	*/
AnnaBridge	156:ff21514d8981	1916	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1917	{
AnnaBridge	156:ff21514d8981	1918	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	156:ff21514d8981	1919	}
AnnaBridge	156:ff21514d8981	1920
AnnaBridge	156:ff21514d8981	1921	/**
AnnaBridge	156:ff21514d8981	1922	* @brief Enable Half transfer interrupt.
AnnaBridge	156:ff21514d8981	1923	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	156:ff21514d8981	1924	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1925	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1926	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1927	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1928	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1929	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1930	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1931	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1932	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1933	* @retval None
AnnaBridge	156:ff21514d8981	1934	*/
AnnaBridge	156:ff21514d8981	1935	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1936	{
AnnaBridge	156:ff21514d8981	1937	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	156:ff21514d8981	1938	}
AnnaBridge	156:ff21514d8981	1939
AnnaBridge	156:ff21514d8981	1940	/**
AnnaBridge	156:ff21514d8981	1941	* @brief Enable Transfer error interrupt.
AnnaBridge	156:ff21514d8981	1942	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	156:ff21514d8981	1943	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1944	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1945	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1946	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1947	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1948	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1949	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1950	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1951	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1952	* @retval None
AnnaBridge	156:ff21514d8981	1953	*/
AnnaBridge	156:ff21514d8981	1954	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1955	{
AnnaBridge	156:ff21514d8981	1956	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	156:ff21514d8981	1957	}
AnnaBridge	156:ff21514d8981	1958
AnnaBridge	156:ff21514d8981	1959	/**
AnnaBridge	156:ff21514d8981	1960	* @brief Disable Transfer complete interrupt.
AnnaBridge	156:ff21514d8981	1961	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	156:ff21514d8981	1962	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1963	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1964	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1965	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1966	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1967	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1968	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1969	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1970	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1971	* @retval None
AnnaBridge	156:ff21514d8981	1972	*/
AnnaBridge	156:ff21514d8981	1973	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1974	{
AnnaBridge	156:ff21514d8981	1975	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	156:ff21514d8981	1976	}
AnnaBridge	156:ff21514d8981	1977
AnnaBridge	156:ff21514d8981	1978	/**
AnnaBridge	156:ff21514d8981	1979	* @brief Disable Half transfer interrupt.
AnnaBridge	156:ff21514d8981	1980	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	156:ff21514d8981	1981	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1982	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1983	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1984	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1985	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1986	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1987	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1988	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1989	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1990	* @retval None
AnnaBridge	156:ff21514d8981	1991	*/
AnnaBridge	156:ff21514d8981	1992	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1993	{
AnnaBridge	156:ff21514d8981	1994	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	156:ff21514d8981	1995	}
AnnaBridge	156:ff21514d8981	1996
AnnaBridge	156:ff21514d8981	1997	/**
AnnaBridge	156:ff21514d8981	1998	* @brief Disable Transfer error interrupt.
AnnaBridge	156:ff21514d8981	1999	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	156:ff21514d8981	2000	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2001	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2002	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2003	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2004	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2005	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2006	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2007	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2008	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2009	* @retval None
AnnaBridge	156:ff21514d8981	2010	*/
AnnaBridge	156:ff21514d8981	2011	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2012	{
AnnaBridge	156:ff21514d8981	2013	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	156:ff21514d8981	2014	}
AnnaBridge	156:ff21514d8981	2015
AnnaBridge	156:ff21514d8981	2016	/**
AnnaBridge	156:ff21514d8981	2017	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2018	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	156:ff21514d8981	2019	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2020	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2021	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2022	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2023	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2024	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2025	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2026	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2027	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2028	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2029	*/
AnnaBridge	156:ff21514d8981	2030	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2031	{
AnnaBridge	156:ff21514d8981	2032	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2033	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	156:ff21514d8981	2034	}
AnnaBridge	156:ff21514d8981	2035
AnnaBridge	156:ff21514d8981	2036	/**
AnnaBridge	156:ff21514d8981	2037	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2038	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	156:ff21514d8981	2039	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2040	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2041	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2042	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2043	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2044	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2045	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2046	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2047	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2048	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2049	*/
AnnaBridge	156:ff21514d8981	2050	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2051	{
AnnaBridge	156:ff21514d8981	2052	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2053	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	156:ff21514d8981	2054	}
AnnaBridge	156:ff21514d8981	2055
AnnaBridge	156:ff21514d8981	2056	/**
AnnaBridge	156:ff21514d8981	2057	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2058	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	156:ff21514d8981	2059	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2060	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2061	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2062	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2063	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2064	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2065	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2066	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2067	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2068	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2069	*/
AnnaBridge	156:ff21514d8981	2070	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2071	{
AnnaBridge	156:ff21514d8981	2072	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2073	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	156:ff21514d8981	2074	}
AnnaBridge	156:ff21514d8981	2075
AnnaBridge	156:ff21514d8981	2076	/**
AnnaBridge	156:ff21514d8981	2077	* @}
AnnaBridge	156:ff21514d8981	2078	*/
AnnaBridge	156:ff21514d8981	2079
AnnaBridge	156:ff21514d8981	2080	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	2081	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	156:ff21514d8981	2082	* @{
AnnaBridge	156:ff21514d8981	2083	*/
AnnaBridge	156:ff21514d8981	2084
AnnaBridge	156:ff21514d8981	2085	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	156:ff21514d8981	2086	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	156:ff21514d8981	2087	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	156:ff21514d8981	2088
AnnaBridge	156:ff21514d8981	2089	/**
AnnaBridge	156:ff21514d8981	2090	* @}
AnnaBridge	156:ff21514d8981	2091	*/
AnnaBridge	156:ff21514d8981	2092	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	156:ff21514d8981	2093
AnnaBridge	156:ff21514d8981	2094	/**
AnnaBridge	156:ff21514d8981	2095	* @}
AnnaBridge	156:ff21514d8981	2096	*/
AnnaBridge	156:ff21514d8981	2097
AnnaBridge	156:ff21514d8981	2098	/**
AnnaBridge	156:ff21514d8981	2099	* @}
AnnaBridge	156:ff21514d8981	2100	*/
AnnaBridge	156:ff21514d8981	2101
AnnaBridge	156:ff21514d8981	2102	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	156:ff21514d8981	2103
AnnaBridge	156:ff21514d8981	2104	/**
AnnaBridge	156:ff21514d8981	2105	* @}
AnnaBridge	156:ff21514d8981	2106	*/
AnnaBridge	156:ff21514d8981	2107
AnnaBridge	156:ff21514d8981	2108	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	2109	}
AnnaBridge	156:ff21514d8981	2110	#endif
AnnaBridge	156:ff21514d8981	2111
AnnaBridge	156:ff21514d8981	2112	#endif /* __STM32L4xx_LL_DMA_H */
AnnaBridge	156:ff21514d8981	2113
AnnaBridge	156:ff21514d8981	2114	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/