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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h@161:aa5281ff4a02, 2018-02-16 (annotated)

Committer:: AnnaBridge
Date:: Fri Feb 16 16:16:41 2018 +0000
Revision:: 161:aa5281ff4a02
Parent:: 156:ff21514d8981

mbed library. Release version 159.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32l4xx_ll_dma.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @brief Header file of DMA LL module.
AnnaBridge	156:ff21514d8981	6	******************************************************************************
AnnaBridge	156:ff21514d8981	7	* @attention
AnnaBridge	156:ff21514d8981	8	*
AnnaBridge	156:ff21514d8981	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	12	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	14	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	17	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	19	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	20	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	21	*
AnnaBridge	156:ff21514d8981	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	32	*
AnnaBridge	156:ff21514d8981	33	******************************************************************************
AnnaBridge	156:ff21514d8981	34	*/
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	37	#ifndef __STM32L4xx_LL_DMA_H
AnnaBridge	156:ff21514d8981	38	#define __STM32L4xx_LL_DMA_H
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	41	extern "C" {
AnnaBridge	156:ff21514d8981	42	#endif
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	45	#include "stm32l4xx.h"
AnnaBridge	161:aa5281ff4a02	46	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	47	#include "stm32l4xx_ll_dmamux.h"
AnnaBridge	161:aa5281ff4a02	48	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	49
AnnaBridge	156:ff21514d8981	50	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	156:ff21514d8981	51	* @{
AnnaBridge	156:ff21514d8981	52	*/
AnnaBridge	156:ff21514d8981	53
AnnaBridge	156:ff21514d8981	54	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	156:ff21514d8981	55
AnnaBridge	156:ff21514d8981	56	/** @defgroup DMA_LL DMA
AnnaBridge	156:ff21514d8981	57	* @{
AnnaBridge	156:ff21514d8981	58	*/
AnnaBridge	156:ff21514d8981	59
AnnaBridge	156:ff21514d8981	60	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	61	/* Private variables ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	62	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	156:ff21514d8981	63	* @{
AnnaBridge	156:ff21514d8981	64	*/
AnnaBridge	156:ff21514d8981	65	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	156:ff21514d8981	66	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	156:ff21514d8981	67	{
AnnaBridge	156:ff21514d8981	68	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	69	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	70	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	71	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	72	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	73	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	156:ff21514d8981	74	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	156:ff21514d8981	75	};
AnnaBridge	156:ff21514d8981	76	/**
AnnaBridge	156:ff21514d8981	77	* @}
AnnaBridge	156:ff21514d8981	78	*/
AnnaBridge	156:ff21514d8981	79
AnnaBridge	156:ff21514d8981	80	/* Private constants ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	81	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	82	#else
AnnaBridge	156:ff21514d8981	83	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	156:ff21514d8981	84	* @{
AnnaBridge	156:ff21514d8981	85	*/
AnnaBridge	156:ff21514d8981	86	/* Define used to get CSELR register offset */
AnnaBridge	156:ff21514d8981	87	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
AnnaBridge	156:ff21514d8981	88
AnnaBridge	156:ff21514d8981	89	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	156:ff21514d8981	90	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
AnnaBridge	156:ff21514d8981	91	/**
AnnaBridge	156:ff21514d8981	92	* @}
AnnaBridge	156:ff21514d8981	93	*/
AnnaBridge	161:aa5281ff4a02	94	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	95
AnnaBridge	156:ff21514d8981	96	/* Private macros ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	97	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	98	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	161:aa5281ff4a02	99	* @{
AnnaBridge	161:aa5281ff4a02	100	*/
AnnaBridge	161:aa5281ff4a02	101	/**
AnnaBridge	161:aa5281ff4a02	102	* @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
AnnaBridge	161:aa5281ff4a02	103	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	104	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	105	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	161:aa5281ff4a02	106	* @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
AnnaBridge	161:aa5281ff4a02	107	*/
AnnaBridge	161:aa5281ff4a02	108	#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
AnnaBridge	161:aa5281ff4a02	109	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
AnnaBridge	161:aa5281ff4a02	110
AnnaBridge	161:aa5281ff4a02	111	/**
AnnaBridge	161:aa5281ff4a02	112	* @}
AnnaBridge	161:aa5281ff4a02	113	*/
AnnaBridge	161:aa5281ff4a02	114	#else
AnnaBridge	156:ff21514d8981	115	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	116	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	156:ff21514d8981	117	* @{
AnnaBridge	156:ff21514d8981	118	*/
AnnaBridge	156:ff21514d8981	119	/**
AnnaBridge	156:ff21514d8981	120	* @}
AnnaBridge	156:ff21514d8981	121	*/
AnnaBridge	156:ff21514d8981	122	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	161:aa5281ff4a02	123	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	124
AnnaBridge	156:ff21514d8981	125	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	126	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	127	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	156:ff21514d8981	128	* @{
AnnaBridge	156:ff21514d8981	129	*/
AnnaBridge	156:ff21514d8981	130	typedef struct
AnnaBridge	156:ff21514d8981	131	{
AnnaBridge	156:ff21514d8981	132	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	156:ff21514d8981	133	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	134
AnnaBridge	156:ff21514d8981	135	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	156:ff21514d8981	136
AnnaBridge	156:ff21514d8981	137	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	156:ff21514d8981	138	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	139
AnnaBridge	156:ff21514d8981	140	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	156:ff21514d8981	141
AnnaBridge	156:ff21514d8981	142	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	156:ff21514d8981	143	from memory to memory or from peripheral to memory.
AnnaBridge	156:ff21514d8981	144	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	156:ff21514d8981	145
AnnaBridge	156:ff21514d8981	146	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	156:ff21514d8981	149	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	156:ff21514d8981	150	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	156:ff21514d8981	151	data transfer direction is configured on the selected Channel
AnnaBridge	156:ff21514d8981	152
AnnaBridge	156:ff21514d8981	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	156:ff21514d8981	154
AnnaBridge	156:ff21514d8981	155	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	156:ff21514d8981	156	is incremented or not.
AnnaBridge	156:ff21514d8981	157	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	156:ff21514d8981	158
AnnaBridge	156:ff21514d8981	159	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	156:ff21514d8981	160
AnnaBridge	156:ff21514d8981	161	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	156:ff21514d8981	162	is incremented or not.
AnnaBridge	156:ff21514d8981	163	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	156:ff21514d8981	164
AnnaBridge	156:ff21514d8981	165	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	156:ff21514d8981	166
AnnaBridge	156:ff21514d8981	167	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	156:ff21514d8981	168	in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	169	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	156:ff21514d8981	174	in case of memory to memory transfer direction.
AnnaBridge	156:ff21514d8981	175	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	156:ff21514d8981	176
AnnaBridge	156:ff21514d8981	177	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	156:ff21514d8981	178
AnnaBridge	156:ff21514d8981	179	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	156:ff21514d8981	180	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	156:ff21514d8981	181	or MemorySize parameters depending in the transfer direction.
AnnaBridge	156:ff21514d8981	182	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	156:ff21514d8981	183
AnnaBridge	156:ff21514d8981	184	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	161:aa5281ff4a02	185	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	186
AnnaBridge	161:aa5281ff4a02	187	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	161:aa5281ff4a02	188	This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
AnnaBridge	161:aa5281ff4a02	189
AnnaBridge	161:aa5281ff4a02	190	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	161:aa5281ff4a02	191	#else
AnnaBridge	156:ff21514d8981	192
AnnaBridge	156:ff21514d8981	193	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
AnnaBridge	156:ff21514d8981	194	This parameter can be a value of @ref DMA_LL_EC_REQUEST
AnnaBridge	156:ff21514d8981	195
AnnaBridge	156:ff21514d8981	196	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
AnnaBridge	161:aa5281ff4a02	197	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	198
AnnaBridge	156:ff21514d8981	199	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	156:ff21514d8981	200	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	156:ff21514d8981	201
AnnaBridge	156:ff21514d8981	202	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	156:ff21514d8981	203
AnnaBridge	156:ff21514d8981	204	} LL_DMA_InitTypeDef;
AnnaBridge	156:ff21514d8981	205	/**
AnnaBridge	156:ff21514d8981	206	* @}
AnnaBridge	156:ff21514d8981	207	*/
AnnaBridge	156:ff21514d8981	208	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	156:ff21514d8981	209
AnnaBridge	156:ff21514d8981	210	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	211	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	156:ff21514d8981	212	* @{
AnnaBridge	156:ff21514d8981	213	*/
AnnaBridge	156:ff21514d8981	214	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	156:ff21514d8981	215	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	156:ff21514d8981	216	* @{
AnnaBridge	156:ff21514d8981	217	*/
AnnaBridge	156:ff21514d8981	218	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	156:ff21514d8981	219	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	156:ff21514d8981	220	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	156:ff21514d8981	221	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	156:ff21514d8981	222	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	156:ff21514d8981	223	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	156:ff21514d8981	224	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	156:ff21514d8981	225	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	156:ff21514d8981	226	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	156:ff21514d8981	227	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	156:ff21514d8981	228	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	156:ff21514d8981	229	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	156:ff21514d8981	230	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	156:ff21514d8981	231	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	156:ff21514d8981	232	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	156:ff21514d8981	233	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	156:ff21514d8981	234	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	156:ff21514d8981	235	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	156:ff21514d8981	236	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	156:ff21514d8981	237	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	156:ff21514d8981	238	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	156:ff21514d8981	239	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	156:ff21514d8981	240	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	156:ff21514d8981	241	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	156:ff21514d8981	242	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	156:ff21514d8981	243	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	156:ff21514d8981	244	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	156:ff21514d8981	245	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	156:ff21514d8981	246	/**
AnnaBridge	156:ff21514d8981	247	* @}
AnnaBridge	156:ff21514d8981	248	*/
AnnaBridge	156:ff21514d8981	249
AnnaBridge	156:ff21514d8981	250	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	156:ff21514d8981	251	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	156:ff21514d8981	252	* @{
AnnaBridge	156:ff21514d8981	253	*/
AnnaBridge	156:ff21514d8981	254	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	156:ff21514d8981	255	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	156:ff21514d8981	256	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	156:ff21514d8981	257	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	156:ff21514d8981	258	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	156:ff21514d8981	259	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	156:ff21514d8981	260	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	156:ff21514d8981	261	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	156:ff21514d8981	262	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	156:ff21514d8981	263	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	156:ff21514d8981	264	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	156:ff21514d8981	265	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	156:ff21514d8981	266	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	156:ff21514d8981	267	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	156:ff21514d8981	268	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	156:ff21514d8981	269	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	156:ff21514d8981	270	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	156:ff21514d8981	271	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	156:ff21514d8981	272	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	156:ff21514d8981	273	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	156:ff21514d8981	274	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	156:ff21514d8981	275	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	156:ff21514d8981	276	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	156:ff21514d8981	277	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	156:ff21514d8981	278	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	156:ff21514d8981	279	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	156:ff21514d8981	280	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	156:ff21514d8981	281	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	156:ff21514d8981	282	/**
AnnaBridge	156:ff21514d8981	283	* @}
AnnaBridge	156:ff21514d8981	284	*/
AnnaBridge	156:ff21514d8981	285
AnnaBridge	156:ff21514d8981	286	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	156:ff21514d8981	287	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	156:ff21514d8981	288	* @{
AnnaBridge	156:ff21514d8981	289	*/
AnnaBridge	156:ff21514d8981	290	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	156:ff21514d8981	291	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	156:ff21514d8981	292	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	156:ff21514d8981	293	/**
AnnaBridge	156:ff21514d8981	294	* @}
AnnaBridge	156:ff21514d8981	295	*/
AnnaBridge	156:ff21514d8981	296
AnnaBridge	156:ff21514d8981	297	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	156:ff21514d8981	298	* @{
AnnaBridge	156:ff21514d8981	299	*/
AnnaBridge	161:aa5281ff4a02	300	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	161:aa5281ff4a02	301	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	161:aa5281ff4a02	302	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	161:aa5281ff4a02	303	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	161:aa5281ff4a02	304	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	161:aa5281ff4a02	305	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	161:aa5281ff4a02	306	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
AnnaBridge	156:ff21514d8981	307	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	161:aa5281ff4a02	308	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	156:ff21514d8981	309	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	156:ff21514d8981	310	/**
AnnaBridge	156:ff21514d8981	311	* @}
AnnaBridge	156:ff21514d8981	312	*/
AnnaBridge	156:ff21514d8981	313
AnnaBridge	156:ff21514d8981	314	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	156:ff21514d8981	315	* @{
AnnaBridge	156:ff21514d8981	316	*/
AnnaBridge	161:aa5281ff4a02	317	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	156:ff21514d8981	318	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	156:ff21514d8981	319	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	156:ff21514d8981	320	/**
AnnaBridge	156:ff21514d8981	321	* @}
AnnaBridge	156:ff21514d8981	322	*/
AnnaBridge	156:ff21514d8981	323
AnnaBridge	156:ff21514d8981	324	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	156:ff21514d8981	325	* @{
AnnaBridge	156:ff21514d8981	326	*/
AnnaBridge	161:aa5281ff4a02	327	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	156:ff21514d8981	328	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	156:ff21514d8981	329	/**
AnnaBridge	156:ff21514d8981	330	* @}
AnnaBridge	156:ff21514d8981	331	*/
AnnaBridge	156:ff21514d8981	332
AnnaBridge	156:ff21514d8981	333	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	156:ff21514d8981	334	* @{
AnnaBridge	156:ff21514d8981	335	*/
AnnaBridge	156:ff21514d8981	336	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	161:aa5281ff4a02	337	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	156:ff21514d8981	338	/**
AnnaBridge	156:ff21514d8981	339	* @}
AnnaBridge	156:ff21514d8981	340	*/
AnnaBridge	156:ff21514d8981	341
AnnaBridge	156:ff21514d8981	342	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	156:ff21514d8981	343	* @{
AnnaBridge	156:ff21514d8981	344	*/
AnnaBridge	156:ff21514d8981	345	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	161:aa5281ff4a02	346	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	156:ff21514d8981	347	/**
AnnaBridge	156:ff21514d8981	348	* @}
AnnaBridge	156:ff21514d8981	349	*/
AnnaBridge	156:ff21514d8981	350
AnnaBridge	156:ff21514d8981	351	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	156:ff21514d8981	352	* @{
AnnaBridge	156:ff21514d8981	353	*/
AnnaBridge	161:aa5281ff4a02	354	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	156:ff21514d8981	355	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	156:ff21514d8981	356	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	156:ff21514d8981	357	/**
AnnaBridge	156:ff21514d8981	358	* @}
AnnaBridge	156:ff21514d8981	359	*/
AnnaBridge	156:ff21514d8981	360
AnnaBridge	156:ff21514d8981	361	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	156:ff21514d8981	362	* @{
AnnaBridge	156:ff21514d8981	363	*/
AnnaBridge	161:aa5281ff4a02	364	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	156:ff21514d8981	365	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	156:ff21514d8981	366	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	156:ff21514d8981	367	/**
AnnaBridge	156:ff21514d8981	368	* @}
AnnaBridge	156:ff21514d8981	369	*/
AnnaBridge	156:ff21514d8981	370
AnnaBridge	156:ff21514d8981	371	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	156:ff21514d8981	372	* @{
AnnaBridge	156:ff21514d8981	373	*/
AnnaBridge	161:aa5281ff4a02	374	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	156:ff21514d8981	375	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	156:ff21514d8981	376	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	156:ff21514d8981	377	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	156:ff21514d8981	378	/**
AnnaBridge	156:ff21514d8981	379	* @}
AnnaBridge	156:ff21514d8981	380	*/
AnnaBridge	156:ff21514d8981	381
AnnaBridge	161:aa5281ff4a02	382	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	383	/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
AnnaBridge	161:aa5281ff4a02	384	* @{
AnnaBridge	161:aa5281ff4a02	385	*/
AnnaBridge	161:aa5281ff4a02	386	#define LL_DMAMUX_REQUEST_MEM2MEM 0U /!< Memory to memory transfer /
AnnaBridge	161:aa5281ff4a02	387	#define LL_DMAMUX_REQUEST_GENERATOR0 1U /!< DMAMUX request generator 0 /
AnnaBridge	161:aa5281ff4a02	388	#define LL_DMAMUX_REQUEST_GENERATOR1 2U /!< DMAMUX request generator 1 /
AnnaBridge	161:aa5281ff4a02	389	#define LL_DMAMUX_REQUEST_GENERATOR2 3U /!< DMAMUX request generator 2 /
AnnaBridge	161:aa5281ff4a02	390	#define LL_DMAMUX_REQUEST_GENERATOR3 4U /!< DMAMUX request generator 3 /
AnnaBridge	161:aa5281ff4a02	391	#define LL_DMAMUX_REQUEST_ADC1 5U /!< DMAMUX ADC1 request /
AnnaBridge	161:aa5281ff4a02	392	#define LL_DMAMUX_REQUEST_DAC1_CH1 6U /!< DMAMUX DAC1 CH1 request /
AnnaBridge	161:aa5281ff4a02	393	#define LL_DMAMUX_REQUEST_DAC1_CH2 7U /!< DMAMUX DAC1 CH2 request /
AnnaBridge	161:aa5281ff4a02	394	#define LL_DMAMUX_REQUEST_TIM6_UP 8U /!< DMAMUX TIM6 UP request /
AnnaBridge	161:aa5281ff4a02	395	#define LL_DMAMUX_REQUEST_TIM7_UP 9U /!< DMAMUX TIM7 UP request /
AnnaBridge	161:aa5281ff4a02	396	#define LL_DMAMUX_REQUEST_SPI1_RX 10U /!< DMAMUX SPI1 RX request /
AnnaBridge	161:aa5281ff4a02	397	#define LL_DMAMUX_REQUEST_SPI1_TX 11U /!< DMAMUX SPI1 TX request /
AnnaBridge	161:aa5281ff4a02	398	#define LL_DMAMUX_REQUEST_SPI2_RX 12U /!< DMAMUX SPI2 RX request /
AnnaBridge	161:aa5281ff4a02	399	#define LL_DMAMUX_REQUEST_SPI2_TX 13U /!< DMAMUX SPI2 TX request /
AnnaBridge	161:aa5281ff4a02	400	#define LL_DMAMUX_REQUEST_SPI3_RX 14U /!< DMAMUX SPI3 RX request /
AnnaBridge	161:aa5281ff4a02	401	#define LL_DMAMUX_REQUEST_SPI3_TX 15U /!< DMAMUX SPI3 TX request /
AnnaBridge	161:aa5281ff4a02	402	#define LL_DMAMUX_REQUEST_I2C1_RX 16U /!< DMAMUX I2C1 RX request /
AnnaBridge	161:aa5281ff4a02	403	#define LL_DMAMUX_REQUEST_I2C1_TX 17U /!< DMAMUX I2C1 TX request /
AnnaBridge	161:aa5281ff4a02	404	#define LL_DMAMUX_REQUEST_I2C2_RX 18U /!< DMAMUX I2C2 RX request /
AnnaBridge	161:aa5281ff4a02	405	#define LL_DMAMUX_REQUEST_I2C2_TX 19U /!< DMAMUX I2C2 TX request /
AnnaBridge	161:aa5281ff4a02	406	#define LL_DMAMUX_REQUEST_I2C3_RX 20U /!< DMAMUX I2C3 RX request /
AnnaBridge	161:aa5281ff4a02	407	#define LL_DMAMUX_REQUEST_I2C3_TX 21U /!< DMAMUX I2C3 TX request /
AnnaBridge	161:aa5281ff4a02	408	#define LL_DMAMUX_REQUEST_I2C4_RX 22U /!< DMAMUX I2C4 RX request /
AnnaBridge	161:aa5281ff4a02	409	#define LL_DMAMUX_REQUEST_I2C4_TX 23U /!< DMAMUX I2C4 TX request /
AnnaBridge	161:aa5281ff4a02	410	#define LL_DMAMUX_REQUEST_USART1_RX 24U /!< DMAMUX USART1 RX request /
AnnaBridge	161:aa5281ff4a02	411	#define LL_DMAMUX_REQUEST_USART1_TX 25U /!< DMAMUX USART1 TX request /
AnnaBridge	161:aa5281ff4a02	412	#define LL_DMAMUX_REQUEST_USART2_RX 26U /!< DMAMUX USART2 RX request /
AnnaBridge	161:aa5281ff4a02	413	#define LL_DMAMUX_REQUEST_USART2_TX 27U /!< DMAMUX USART2 TX request /
AnnaBridge	161:aa5281ff4a02	414	#define LL_DMAMUX_REQUEST_USART3_RX 28U /!< DMAMUX USART3 RX request /
AnnaBridge	161:aa5281ff4a02	415	#define LL_DMAMUX_REQUEST_USART3_TX 29U /!< DMAMUX USART3 TX request /
AnnaBridge	161:aa5281ff4a02	416	#define LL_DMAMUX_REQUEST_UART4_RX 30U /!< DMAMUX UART4 RX request /
AnnaBridge	161:aa5281ff4a02	417	#define LL_DMAMUX_REQUEST_UART4_TX 31U /!< DMAMUX UART4 TX request /
AnnaBridge	161:aa5281ff4a02	418	#define LL_DMAMUX_REQUEST_UART5_RX 32U /!< DMAMUX UART5 RX request /
AnnaBridge	161:aa5281ff4a02	419	#define LL_DMAMUX_REQUEST_UART5_TX 33U /!< DMAMUX UART5 TX request /
AnnaBridge	161:aa5281ff4a02	420	#define LL_DMAMUX_REQUEST_LPUART1_RX 34U /!< DMAMUX LPUART1 RX request /
AnnaBridge	161:aa5281ff4a02	421	#define LL_DMAMUX_REQUEST_LPUART1_TX 35U /!< DMAMUX LPUART1 TX request /
AnnaBridge	161:aa5281ff4a02	422	#define LL_DMAMUX_REQUEST_SAI1_A 36U /!< DMAMUX SAI1 A request /
AnnaBridge	161:aa5281ff4a02	423	#define LL_DMAMUX_REQUEST_SAI1_B 37U /!< DMAMUX SAI1 B request /
AnnaBridge	161:aa5281ff4a02	424	#define LL_DMAMUX_REQUEST_SAI2_A 38U /!< DMAMUX SAI2 A request /
AnnaBridge	161:aa5281ff4a02	425	#define LL_DMAMUX_REQUEST_SAI2_B 39U /!< DMAMUX SAI2 B request /
AnnaBridge	161:aa5281ff4a02	426	#define LL_DMAMUX_REQUEST_OSPI1 40U /!< DMAMUX OCTOSPI1 request /
AnnaBridge	161:aa5281ff4a02	427	#define LL_DMAMUX_REQUEST_OSPI2 41U /!< DMAMUX OCTOSPI2 request /
AnnaBridge	161:aa5281ff4a02	428	#define LL_DMAMUX_REQUEST_TIM1_CH1 42U /!< DMAMUX TIM1 CH1 request /
AnnaBridge	161:aa5281ff4a02	429	#define LL_DMAMUX_REQUEST_TIM1_CH2 43U /!< DMAMUX TIM1 CH2 request /
AnnaBridge	161:aa5281ff4a02	430	#define LL_DMAMUX_REQUEST_TIM1_CH3 44U /!< DMAMUX TIM1 CH3 request /
AnnaBridge	161:aa5281ff4a02	431	#define LL_DMAMUX_REQUEST_TIM1_CH4 45U /!< DMAMUX TIM1 CH4 request /
AnnaBridge	161:aa5281ff4a02	432	#define LL_DMAMUX_REQUEST_TIM1_UP 46U /!< DMAMUX TIM1 UP request /
AnnaBridge	161:aa5281ff4a02	433	#define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /!< DMAMUX TIM1 TRIG request /
AnnaBridge	161:aa5281ff4a02	434	#define LL_DMAMUX_REQUEST_TIM1_COM 48U /!< DMAMUX TIM1 COM request /
AnnaBridge	161:aa5281ff4a02	435	#define LL_DMAMUX_REQUEST_TIM8_CH1 49U /!< DMAMUX TIM8 CH1 request /
AnnaBridge	161:aa5281ff4a02	436	#define LL_DMAMUX_REQUEST_TIM8_CH2 50U /!< DMAMUX TIM8 CH2 request /
AnnaBridge	161:aa5281ff4a02	437	#define LL_DMAMUX_REQUEST_TIM8_CH3 51U /!< DMAMUX TIM8 CH3 request /
AnnaBridge	161:aa5281ff4a02	438	#define LL_DMAMUX_REQUEST_TIM8_CH4 52U /!< DMAMUX TIM8 CH4 request /
AnnaBridge	161:aa5281ff4a02	439	#define LL_DMAMUX_REQUEST_TIM8_UP 53U /!< DMAMUX TIM8 UP request /
AnnaBridge	161:aa5281ff4a02	440	#define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /!< DMAMUX TIM8 TRIG request /
AnnaBridge	161:aa5281ff4a02	441	#define LL_DMAMUX_REQUEST_TIM8_COM 55U /!< DMAMUX TIM8 COM request /
AnnaBridge	161:aa5281ff4a02	442	#define LL_DMAMUX_REQUEST_TIM2_CH1 56U /!< DMAMUX TIM2 CH1 request /
AnnaBridge	161:aa5281ff4a02	443	#define LL_DMAMUX_REQUEST_TIM2_CH2 57U /!< DMAMUX TIM2 CH2 request /
AnnaBridge	161:aa5281ff4a02	444	#define LL_DMAMUX_REQUEST_TIM2_CH3 58U /!< DMAMUX TIM2 CH3 request /
AnnaBridge	161:aa5281ff4a02	445	#define LL_DMAMUX_REQUEST_TIM2_CH4 59U /!< DMAMUX TIM2 CH4 request /
AnnaBridge	161:aa5281ff4a02	446	#define LL_DMAMUX_REQUEST_TIM2_UP 60U /!< DMAMUX TIM2 UP request /
AnnaBridge	161:aa5281ff4a02	447	#define LL_DMAMUX_REQUEST_TIM3_CH1 61U /!< DMAMUX TIM3 CH1 request /
AnnaBridge	161:aa5281ff4a02	448	#define LL_DMAMUX_REQUEST_TIM3_CH2 62U /!< DMAMUX TIM3 CH2 request /
AnnaBridge	161:aa5281ff4a02	449	#define LL_DMAMUX_REQUEST_TIM3_CH3 63U /!< DMAMUX TIM3 CH3 request /
AnnaBridge	161:aa5281ff4a02	450	#define LL_DMAMUX_REQUEST_TIM3_CH4 64U /!< DMAMUX TIM3 CH4 request /
AnnaBridge	161:aa5281ff4a02	451	#define LL_DMAMUX_REQUEST_TIM3_UP 65U /!< DMAMUX TIM3 UP request /
AnnaBridge	161:aa5281ff4a02	452	#define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /!< DMAMUX TIM3 TRIG request /
AnnaBridge	161:aa5281ff4a02	453	#define LL_DMAMUX_REQUEST_TIM4_CH1 67U /!< DMAMUX TIM4 CH1 request /
AnnaBridge	161:aa5281ff4a02	454	#define LL_DMAMUX_REQUEST_TIM4_CH2 68U /!< DMAMUX TIM4 CH2 request /
AnnaBridge	161:aa5281ff4a02	455	#define LL_DMAMUX_REQUEST_TIM4_CH3 69U /!< DMAMUX TIM4 CH3 request /
AnnaBridge	161:aa5281ff4a02	456	#define LL_DMAMUX_REQUEST_TIM4_CH4 70U /!< DMAMUX TIM4 CH4 request /
AnnaBridge	161:aa5281ff4a02	457	#define LL_DMAMUX_REQUEST_TIM4_UP 71U /!< DMAMUX TIM4 UP request /
AnnaBridge	161:aa5281ff4a02	458	#define LL_DMAMUX_REQUEST_TIM5_CH1 72U /!< DMAMUX TIM5 CH1 request /
AnnaBridge	161:aa5281ff4a02	459	#define LL_DMAMUX_REQUEST_TIM5_CH2 73U /!< DMAMUX TIM5 CH2 request /
AnnaBridge	161:aa5281ff4a02	460	#define LL_DMAMUX_REQUEST_TIM5_CH3 74U /!< DMAMUX TIM5 CH3 request /
AnnaBridge	161:aa5281ff4a02	461	#define LL_DMAMUX_REQUEST_TIM5_CH4 75U /!< DMAMUX TIM5 CH4 request /
AnnaBridge	161:aa5281ff4a02	462	#define LL_DMAMUX_REQUEST_TIM5_UP 76U /!< DMAMUX TIM5 UP request /
AnnaBridge	161:aa5281ff4a02	463	#define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /!< DMAMUX TIM5 TRIG request /
AnnaBridge	161:aa5281ff4a02	464	#define LL_DMAMUX_REQUEST_TIM15_CH1 78U /!< DMAMUX TIM15 CH1 request /
AnnaBridge	161:aa5281ff4a02	465	#define LL_DMAMUX_REQUEST_TIM15_UP 79U /!< DMAMUX TIM15 UP request /
AnnaBridge	161:aa5281ff4a02	466	#define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /!< DMAMUX TIM15 TRIG request /
AnnaBridge	161:aa5281ff4a02	467	#define LL_DMAMUX_REQUEST_TIM15_COM 81U /!< DMAMUX TIM15 COM request /
AnnaBridge	161:aa5281ff4a02	468	#define LL_DMAMUX_REQUEST_TIM16_CH1 82U /!< DMAMUX TIM16 CH1 request /
AnnaBridge	161:aa5281ff4a02	469	#define LL_DMAMUX_REQUEST_TIM16_UP 83U /!< DMAMUX TIM16 UP request /
AnnaBridge	161:aa5281ff4a02	470	#define LL_DMAMUX_REQUEST_TIM17_CH1 84U /!< DMAMUX TIM17 CH1 request /
AnnaBridge	161:aa5281ff4a02	471	#define LL_DMAMUX_REQUEST_TIM17_UP 85U /!< DMAMUX TIM17 UP request /
AnnaBridge	161:aa5281ff4a02	472	#define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /!< DMAMUX DFSDM1_FLT0 request /
AnnaBridge	161:aa5281ff4a02	473	#define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /!< DMAMUX DFSDM1_FLT1 request /
AnnaBridge	161:aa5281ff4a02	474	#define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /!< DMAMUX DFSDM1_FLT2 request /
AnnaBridge	161:aa5281ff4a02	475	#define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /!< DMAMUX DFSDM1_FLT3 request /
AnnaBridge	161:aa5281ff4a02	476	#define LL_DMAMUX_REQUEST_DCMI 90U /!< DMAMUX DCMI request /
AnnaBridge	161:aa5281ff4a02	477	#define LL_DMAMUX_REQUEST_AES_IN 91U /!< DMAMUX AES_IN request /
AnnaBridge	161:aa5281ff4a02	478	#define LL_DMAMUX_REQUEST_AES_OUT 92U /!< DMAMUX AES_OUT request /
AnnaBridge	161:aa5281ff4a02	479	#define LL_DMAMUX_REQUEST_HASH_IN 93U /!< DMAMUX HASH_IN request /
AnnaBridge	161:aa5281ff4a02	480	/**
AnnaBridge	161:aa5281ff4a02	481	* @}
AnnaBridge	161:aa5281ff4a02	482	*/
AnnaBridge	161:aa5281ff4a02	483	#else
AnnaBridge	156:ff21514d8981	484	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
AnnaBridge	156:ff21514d8981	485	* @{
AnnaBridge	156:ff21514d8981	486	*/
AnnaBridge	161:aa5281ff4a02	487	#define LL_DMA_REQUEST_0 0x00000000U /!< DMA peripheral request 0 /
AnnaBridge	161:aa5281ff4a02	488	#define LL_DMA_REQUEST_1 0x00000001U /!< DMA peripheral request 1 /
AnnaBridge	161:aa5281ff4a02	489	#define LL_DMA_REQUEST_2 0x00000002U /!< DMA peripheral request 2 /
AnnaBridge	161:aa5281ff4a02	490	#define LL_DMA_REQUEST_3 0x00000003U /!< DMA peripheral request 3 /
AnnaBridge	161:aa5281ff4a02	491	#define LL_DMA_REQUEST_4 0x00000004U /!< DMA peripheral request 4 /
AnnaBridge	161:aa5281ff4a02	492	#define LL_DMA_REQUEST_5 0x00000005U /!< DMA peripheral request 5 /
AnnaBridge	161:aa5281ff4a02	493	#define LL_DMA_REQUEST_6 0x00000006U /!< DMA peripheral request 6 /
AnnaBridge	161:aa5281ff4a02	494	#define LL_DMA_REQUEST_7 0x00000007U /!< DMA peripheral request 7 /
AnnaBridge	156:ff21514d8981	495	/**
AnnaBridge	156:ff21514d8981	496	* @}
AnnaBridge	156:ff21514d8981	497	*/
AnnaBridge	161:aa5281ff4a02	498	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	499
AnnaBridge	156:ff21514d8981	500	/**
AnnaBridge	156:ff21514d8981	501	* @}
AnnaBridge	156:ff21514d8981	502	*/
AnnaBridge	156:ff21514d8981	503
AnnaBridge	156:ff21514d8981	504	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	505	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	156:ff21514d8981	506	* @{
AnnaBridge	156:ff21514d8981	507	*/
AnnaBridge	156:ff21514d8981	508
AnnaBridge	156:ff21514d8981	509	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	156:ff21514d8981	510	* @{
AnnaBridge	156:ff21514d8981	511	*/
AnnaBridge	156:ff21514d8981	512	/**
AnnaBridge	156:ff21514d8981	513	* @brief Write a value in DMA register
AnnaBridge	156:ff21514d8981	514	* @param __INSTANCE__ DMA Instance
AnnaBridge	156:ff21514d8981	515	* @param __REG__ Register to be written
AnnaBridge	156:ff21514d8981	516	* @param __VALUE__ Value to be written in the register
AnnaBridge	156:ff21514d8981	517	* @retval None
AnnaBridge	156:ff21514d8981	518	*/
AnnaBridge	156:ff21514d8981	519	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	156:ff21514d8981	520
AnnaBridge	156:ff21514d8981	521	/**
AnnaBridge	156:ff21514d8981	522	* @brief Read a value in DMA register
AnnaBridge	156:ff21514d8981	523	* @param __INSTANCE__ DMA Instance
AnnaBridge	156:ff21514d8981	524	* @param __REG__ Register to be read
AnnaBridge	156:ff21514d8981	525	* @retval Register value
AnnaBridge	156:ff21514d8981	526	*/
AnnaBridge	156:ff21514d8981	527	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	156:ff21514d8981	528	/**
AnnaBridge	156:ff21514d8981	529	* @}
AnnaBridge	156:ff21514d8981	530	*/
AnnaBridge	156:ff21514d8981	531
AnnaBridge	156:ff21514d8981	532	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	156:ff21514d8981	533	* @{
AnnaBridge	156:ff21514d8981	534	*/
AnnaBridge	156:ff21514d8981	535	/**
AnnaBridge	156:ff21514d8981	536	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	156:ff21514d8981	537	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	156:ff21514d8981	538	* @retval DMAx
AnnaBridge	156:ff21514d8981	539	*/
AnnaBridge	156:ff21514d8981	540	#if defined(DMA2)
AnnaBridge	156:ff21514d8981	541	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	542	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	156:ff21514d8981	543	#else
AnnaBridge	156:ff21514d8981	544	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	156:ff21514d8981	545	#endif
AnnaBridge	156:ff21514d8981	546
AnnaBridge	156:ff21514d8981	547	/**
AnnaBridge	156:ff21514d8981	548	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	549	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	156:ff21514d8981	550	* @retval LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	551	*/
AnnaBridge	156:ff21514d8981	552	#if defined (DMA2)
AnnaBridge	156:ff21514d8981	553	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	156:ff21514d8981	554	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	555	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	556	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	557	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	558	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	559	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	560	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	561	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	562	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	563	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	564	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	565	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	566	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	567	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	568	#else
AnnaBridge	156:ff21514d8981	569	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	570	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	571	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	572	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	573	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	574	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	575	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	576	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	577	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	578	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	579	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	580	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	581	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	582	#endif
AnnaBridge	156:ff21514d8981	583	#else
AnnaBridge	156:ff21514d8981	584	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	156:ff21514d8981	585	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	156:ff21514d8981	586	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	156:ff21514d8981	587	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	156:ff21514d8981	588	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	156:ff21514d8981	589	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	156:ff21514d8981	590	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	156:ff21514d8981	591	LL_DMA_CHANNEL_7)
AnnaBridge	156:ff21514d8981	592	#endif
AnnaBridge	156:ff21514d8981	593
AnnaBridge	156:ff21514d8981	594	/**
AnnaBridge	156:ff21514d8981	595	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	156:ff21514d8981	596	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	156:ff21514d8981	597	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	156:ff21514d8981	598	* @retval DMAx_Channely
AnnaBridge	156:ff21514d8981	599	*/
AnnaBridge	156:ff21514d8981	600	#if defined (DMA2)
AnnaBridge	156:ff21514d8981	601	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	156:ff21514d8981	602	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	603	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	604	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	156:ff21514d8981	605	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	606	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	156:ff21514d8981	607	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	608	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	156:ff21514d8981	609	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	610	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	156:ff21514d8981	611	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	612	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	156:ff21514d8981	613	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	614	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	156:ff21514d8981	615	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	156:ff21514d8981	616	DMA2_Channel7)
AnnaBridge	156:ff21514d8981	617	#else
AnnaBridge	156:ff21514d8981	618	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	619	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	620	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	156:ff21514d8981	621	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	622	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	156:ff21514d8981	623	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	624	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	156:ff21514d8981	625	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	626	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	156:ff21514d8981	627	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	628	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	156:ff21514d8981	629	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	630	DMA1_Channel7)
AnnaBridge	156:ff21514d8981	631	#endif
AnnaBridge	156:ff21514d8981	632	#else
AnnaBridge	156:ff21514d8981	633	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	156:ff21514d8981	634	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	156:ff21514d8981	635	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	156:ff21514d8981	636	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	156:ff21514d8981	637	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	156:ff21514d8981	638	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	156:ff21514d8981	639	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	156:ff21514d8981	640	DMA1_Channel7)
AnnaBridge	156:ff21514d8981	641	#endif
AnnaBridge	156:ff21514d8981	642
AnnaBridge	156:ff21514d8981	643	/**
AnnaBridge	156:ff21514d8981	644	* @}
AnnaBridge	156:ff21514d8981	645	*/
AnnaBridge	156:ff21514d8981	646
AnnaBridge	156:ff21514d8981	647	/**
AnnaBridge	156:ff21514d8981	648	* @}
AnnaBridge	156:ff21514d8981	649	*/
AnnaBridge	156:ff21514d8981	650
AnnaBridge	156:ff21514d8981	651	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	652	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	156:ff21514d8981	653	* @{
AnnaBridge	156:ff21514d8981	654	*/
AnnaBridge	156:ff21514d8981	655
AnnaBridge	156:ff21514d8981	656	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	156:ff21514d8981	657	* @{
AnnaBridge	156:ff21514d8981	658	*/
AnnaBridge	156:ff21514d8981	659	/**
AnnaBridge	156:ff21514d8981	660	* @brief Enable DMA channel.
AnnaBridge	156:ff21514d8981	661	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	156:ff21514d8981	662	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	663	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	664	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	665	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	666	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	667	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	668	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	669	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	670	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	671	* @retval None
AnnaBridge	156:ff21514d8981	672	*/
AnnaBridge	156:ff21514d8981	673	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	674	{
AnnaBridge	156:ff21514d8981	675	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	156:ff21514d8981	676	}
AnnaBridge	156:ff21514d8981	677
AnnaBridge	156:ff21514d8981	678	/**
AnnaBridge	156:ff21514d8981	679	* @brief Disable DMA channel.
AnnaBridge	156:ff21514d8981	680	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	156:ff21514d8981	681	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	682	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	683	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	684	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	685	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	686	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	687	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	688	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	689	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	690	* @retval None
AnnaBridge	156:ff21514d8981	691	*/
AnnaBridge	156:ff21514d8981	692	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	693	{
AnnaBridge	156:ff21514d8981	694	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	156:ff21514d8981	695	}
AnnaBridge	156:ff21514d8981	696
AnnaBridge	156:ff21514d8981	697	/**
AnnaBridge	156:ff21514d8981	698	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	156:ff21514d8981	699	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	156:ff21514d8981	700	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	701	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	702	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	703	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	704	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	705	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	706	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	707	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	708	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	709	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	710	*/
AnnaBridge	156:ff21514d8981	711	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	712	{
AnnaBridge	156:ff21514d8981	713	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	714	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	156:ff21514d8981	715	}
AnnaBridge	156:ff21514d8981	716
AnnaBridge	156:ff21514d8981	717	/**
AnnaBridge	156:ff21514d8981	718	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	156:ff21514d8981	719	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	720	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	721	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	722	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	723	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	724	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	725	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	156:ff21514d8981	726	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	156:ff21514d8981	727	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	728	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	729	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	730	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	731	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	732	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	733	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	734	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	735	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	736	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	156:ff21514d8981	737	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	738	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	739	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	740	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	741	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	742	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	743	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	744	* @retval None
AnnaBridge	156:ff21514d8981	745	*/
AnnaBridge	156:ff21514d8981	746	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	156:ff21514d8981	747	{
AnnaBridge	156:ff21514d8981	748	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	749	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	156:ff21514d8981	750	Configuration);
AnnaBridge	156:ff21514d8981	751	}
AnnaBridge	156:ff21514d8981	752
AnnaBridge	156:ff21514d8981	753	/**
AnnaBridge	156:ff21514d8981	754	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	156:ff21514d8981	755	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	156:ff21514d8981	756	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	156:ff21514d8981	757	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	758	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	759	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	760	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	761	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	762	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	763	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	764	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	765	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	766	* @param Direction This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	767	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	768	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	769	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	770	* @retval None
AnnaBridge	156:ff21514d8981	771	*/
AnnaBridge	156:ff21514d8981	772	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	156:ff21514d8981	773	{
AnnaBridge	156:ff21514d8981	774	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	775	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	156:ff21514d8981	776	}
AnnaBridge	156:ff21514d8981	777
AnnaBridge	156:ff21514d8981	778	/**
AnnaBridge	156:ff21514d8981	779	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	156:ff21514d8981	780	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	156:ff21514d8981	781	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	156:ff21514d8981	782	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	783	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	784	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	785	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	786	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	787	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	788	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	789	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	790	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	791	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	792	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	793	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	794	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	795	*/
AnnaBridge	156:ff21514d8981	796	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	797	{
AnnaBridge	156:ff21514d8981	798	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	799	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	156:ff21514d8981	800	}
AnnaBridge	156:ff21514d8981	801
AnnaBridge	156:ff21514d8981	802	/**
AnnaBridge	156:ff21514d8981	803	* @brief Set DMA mode circular or normal.
AnnaBridge	156:ff21514d8981	804	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	156:ff21514d8981	805	* data transfer is configured on the selected Channel.
AnnaBridge	156:ff21514d8981	806	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	156:ff21514d8981	807	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	808	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	809	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	810	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	811	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	812	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	813	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	814	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	815	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	816	* @param Mode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	817	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	156:ff21514d8981	818	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	819	* @retval None
AnnaBridge	156:ff21514d8981	820	*/
AnnaBridge	156:ff21514d8981	821	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	156:ff21514d8981	822	{
AnnaBridge	156:ff21514d8981	823	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	156:ff21514d8981	824	Mode);
AnnaBridge	156:ff21514d8981	825	}
AnnaBridge	156:ff21514d8981	826
AnnaBridge	156:ff21514d8981	827	/**
AnnaBridge	156:ff21514d8981	828	* @brief Get DMA mode circular or normal.
AnnaBridge	156:ff21514d8981	829	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	156:ff21514d8981	830	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	831	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	832	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	833	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	834	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	835	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	836	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	837	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	838	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	839	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	840	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	156:ff21514d8981	841	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	156:ff21514d8981	842	*/
AnnaBridge	156:ff21514d8981	843	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	844	{
AnnaBridge	156:ff21514d8981	845	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	846	DMA_CCR_CIRC));
AnnaBridge	156:ff21514d8981	847	}
AnnaBridge	156:ff21514d8981	848
AnnaBridge	156:ff21514d8981	849	/**
AnnaBridge	156:ff21514d8981	850	* @brief Set Peripheral increment mode.
AnnaBridge	156:ff21514d8981	851	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	156:ff21514d8981	852	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	853	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	854	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	855	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	856	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	857	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	858	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	859	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	860	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	861	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	862	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	156:ff21514d8981	863	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	864	* @retval None
AnnaBridge	156:ff21514d8981	865	*/
AnnaBridge	156:ff21514d8981	866	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	156:ff21514d8981	867	{
AnnaBridge	156:ff21514d8981	868	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	156:ff21514d8981	869	PeriphOrM2MSrcIncMode);
AnnaBridge	156:ff21514d8981	870	}
AnnaBridge	156:ff21514d8981	871
AnnaBridge	156:ff21514d8981	872	/**
AnnaBridge	156:ff21514d8981	873	* @brief Get Peripheral increment mode.
AnnaBridge	156:ff21514d8981	874	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	156:ff21514d8981	875	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	876	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	877	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	878	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	879	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	880	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	881	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	882	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	883	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	884	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	885	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	156:ff21514d8981	886	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	156:ff21514d8981	887	*/
AnnaBridge	156:ff21514d8981	888	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	889	{
AnnaBridge	156:ff21514d8981	890	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	891	DMA_CCR_PINC));
AnnaBridge	156:ff21514d8981	892	}
AnnaBridge	156:ff21514d8981	893
AnnaBridge	156:ff21514d8981	894	/**
AnnaBridge	156:ff21514d8981	895	* @brief Set Memory increment mode.
AnnaBridge	156:ff21514d8981	896	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	156:ff21514d8981	897	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	898	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	899	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	900	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	901	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	902	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	903	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	904	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	905	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	906	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	907	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	156:ff21514d8981	908	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	909	* @retval None
AnnaBridge	156:ff21514d8981	910	*/
AnnaBridge	156:ff21514d8981	911	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	156:ff21514d8981	912	{
AnnaBridge	156:ff21514d8981	913	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	156:ff21514d8981	914	MemoryOrM2MDstIncMode);
AnnaBridge	156:ff21514d8981	915	}
AnnaBridge	156:ff21514d8981	916
AnnaBridge	156:ff21514d8981	917	/**
AnnaBridge	156:ff21514d8981	918	* @brief Get Memory increment mode.
AnnaBridge	156:ff21514d8981	919	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	156:ff21514d8981	920	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	921	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	922	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	923	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	924	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	925	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	926	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	927	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	928	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	929	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	930	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	156:ff21514d8981	931	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	156:ff21514d8981	932	*/
AnnaBridge	156:ff21514d8981	933	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	934	{
AnnaBridge	156:ff21514d8981	935	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	936	DMA_CCR_MINC));
AnnaBridge	156:ff21514d8981	937	}
AnnaBridge	156:ff21514d8981	938
AnnaBridge	156:ff21514d8981	939	/**
AnnaBridge	156:ff21514d8981	940	* @brief Set Peripheral size.
AnnaBridge	156:ff21514d8981	941	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	156:ff21514d8981	942	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	943	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	944	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	945	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	946	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	947	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	948	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	949	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	950	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	951	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	952	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	953	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	954	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	955	* @retval None
AnnaBridge	156:ff21514d8981	956	*/
AnnaBridge	156:ff21514d8981	957	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	156:ff21514d8981	958	{
AnnaBridge	156:ff21514d8981	959	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	156:ff21514d8981	960	PeriphOrM2MSrcDataSize);
AnnaBridge	156:ff21514d8981	961	}
AnnaBridge	156:ff21514d8981	962
AnnaBridge	156:ff21514d8981	963	/**
AnnaBridge	156:ff21514d8981	964	* @brief Get Peripheral size.
AnnaBridge	156:ff21514d8981	965	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	156:ff21514d8981	966	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	967	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	968	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	969	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	970	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	971	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	972	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	973	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	974	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	975	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	976	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	977	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	978	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	979	*/
AnnaBridge	156:ff21514d8981	980	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	981	{
AnnaBridge	156:ff21514d8981	982	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	983	DMA_CCR_PSIZE));
AnnaBridge	156:ff21514d8981	984	}
AnnaBridge	156:ff21514d8981	985
AnnaBridge	156:ff21514d8981	986	/**
AnnaBridge	156:ff21514d8981	987	* @brief Set Memory size.
AnnaBridge	156:ff21514d8981	988	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	156:ff21514d8981	989	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	990	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	991	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	992	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	993	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	994	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	995	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	996	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	997	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	998	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	999	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	1000	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	1001	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	1002	* @retval None
AnnaBridge	156:ff21514d8981	1003	*/
AnnaBridge	156:ff21514d8981	1004	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	156:ff21514d8981	1005	{
AnnaBridge	156:ff21514d8981	1006	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	156:ff21514d8981	1007	MemoryOrM2MDstDataSize);
AnnaBridge	156:ff21514d8981	1008	}
AnnaBridge	156:ff21514d8981	1009
AnnaBridge	156:ff21514d8981	1010	/**
AnnaBridge	156:ff21514d8981	1011	* @brief Get Memory size.
AnnaBridge	156:ff21514d8981	1012	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	156:ff21514d8981	1013	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1014	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1015	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1016	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1017	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1018	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1019	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1020	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1021	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1022	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1023	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	156:ff21514d8981	1024	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	156:ff21514d8981	1025	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	156:ff21514d8981	1026	*/
AnnaBridge	156:ff21514d8981	1027	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1028	{
AnnaBridge	156:ff21514d8981	1029	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	1030	DMA_CCR_MSIZE));
AnnaBridge	156:ff21514d8981	1031	}
AnnaBridge	156:ff21514d8981	1032
AnnaBridge	156:ff21514d8981	1033	/**
AnnaBridge	156:ff21514d8981	1034	* @brief Set Channel priority level.
AnnaBridge	156:ff21514d8981	1035	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	156:ff21514d8981	1036	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1037	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1038	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1039	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1040	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1041	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1042	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1043	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1044	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1045	* @param Priority This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1046	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	156:ff21514d8981	1047	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	156:ff21514d8981	1048	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	156:ff21514d8981	1049	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	1050	* @retval None
AnnaBridge	156:ff21514d8981	1051	*/
AnnaBridge	156:ff21514d8981	1052	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	156:ff21514d8981	1053	{
AnnaBridge	156:ff21514d8981	1054	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	156:ff21514d8981	1055	Priority);
AnnaBridge	156:ff21514d8981	1056	}
AnnaBridge	156:ff21514d8981	1057
AnnaBridge	156:ff21514d8981	1058	/**
AnnaBridge	156:ff21514d8981	1059	* @brief Get Channel priority level.
AnnaBridge	156:ff21514d8981	1060	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	156:ff21514d8981	1061	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1062	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1063	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1064	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1065	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1066	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1067	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1068	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1069	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1070	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1071	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	156:ff21514d8981	1072	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	156:ff21514d8981	1073	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	156:ff21514d8981	1074	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	156:ff21514d8981	1075	*/
AnnaBridge	156:ff21514d8981	1076	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1077	{
AnnaBridge	156:ff21514d8981	1078	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	1079	DMA_CCR_PL));
AnnaBridge	156:ff21514d8981	1080	}
AnnaBridge	156:ff21514d8981	1081
AnnaBridge	156:ff21514d8981	1082	/**
AnnaBridge	156:ff21514d8981	1083	* @brief Set Number of data to transfer.
AnnaBridge	156:ff21514d8981	1084	* @note This action has no effect if
AnnaBridge	156:ff21514d8981	1085	* channel is enabled.
AnnaBridge	156:ff21514d8981	1086	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	156:ff21514d8981	1087	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1088	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1089	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1090	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1091	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1092	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1093	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1094	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1095	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1096	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	156:ff21514d8981	1097	* @retval None
AnnaBridge	156:ff21514d8981	1098	*/
AnnaBridge	156:ff21514d8981	1099	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	156:ff21514d8981	1100	{
AnnaBridge	156:ff21514d8981	1101	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	156:ff21514d8981	1102	DMA_CNDTR_NDT, NbData);
AnnaBridge	156:ff21514d8981	1103	}
AnnaBridge	156:ff21514d8981	1104
AnnaBridge	156:ff21514d8981	1105	/**
AnnaBridge	156:ff21514d8981	1106	* @brief Get Number of data to transfer.
AnnaBridge	156:ff21514d8981	1107	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	156:ff21514d8981	1108	* remaining bytes to be transmitted.
AnnaBridge	156:ff21514d8981	1109	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	156:ff21514d8981	1110	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1111	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1112	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1113	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1114	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1115	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1116	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1117	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1118	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1119	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1120	*/
AnnaBridge	156:ff21514d8981	1121	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1122	{
AnnaBridge	156:ff21514d8981	1123	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	156:ff21514d8981	1124	DMA_CNDTR_NDT));
AnnaBridge	156:ff21514d8981	1125	}
AnnaBridge	156:ff21514d8981	1126
AnnaBridge	156:ff21514d8981	1127	/**
AnnaBridge	156:ff21514d8981	1128	* @brief Configure the Source and Destination addresses.
AnnaBridge	156:ff21514d8981	1129	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1130	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	156:ff21514d8981	1131	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	156:ff21514d8981	1132	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	156:ff21514d8981	1133	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1134	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1135	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1136	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1137	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1138	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1139	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1140	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1141	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1142	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1143	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1144	* @param Direction This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1145	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	156:ff21514d8981	1146	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	156:ff21514d8981	1147	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	156:ff21514d8981	1148	* @retval None
AnnaBridge	156:ff21514d8981	1149	*/
AnnaBridge	156:ff21514d8981	1150	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	156:ff21514d8981	1151	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	156:ff21514d8981	1152	{
AnnaBridge	156:ff21514d8981	1153	/* Direction Memory to Periph */
AnnaBridge	156:ff21514d8981	1154	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	156:ff21514d8981	1155	{
AnnaBridge	156:ff21514d8981	1156	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	156:ff21514d8981	1157	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	156:ff21514d8981	1158	}
AnnaBridge	156:ff21514d8981	1159	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	156:ff21514d8981	1160	else
AnnaBridge	156:ff21514d8981	1161	{
AnnaBridge	156:ff21514d8981	1162	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	156:ff21514d8981	1163	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	156:ff21514d8981	1164	}
AnnaBridge	156:ff21514d8981	1165	}
AnnaBridge	156:ff21514d8981	1166
AnnaBridge	156:ff21514d8981	1167	/**
AnnaBridge	156:ff21514d8981	1168	* @brief Set the Memory address.
AnnaBridge	156:ff21514d8981	1169	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1170	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1171	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	156:ff21514d8981	1172	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1173	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1174	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1175	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1176	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1177	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1178	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1179	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1180	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1181	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1182	* @retval None
AnnaBridge	156:ff21514d8981	1183	*/
AnnaBridge	156:ff21514d8981	1184	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1185	{
AnnaBridge	156:ff21514d8981	1186	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1187	}
AnnaBridge	156:ff21514d8981	1188
AnnaBridge	156:ff21514d8981	1189	/**
AnnaBridge	156:ff21514d8981	1190	* @brief Set the Peripheral address.
AnnaBridge	156:ff21514d8981	1191	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1192	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1193	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	156:ff21514d8981	1194	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1195	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1196	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1197	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1198	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1199	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1200	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1201	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1202	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1203	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1204	* @retval None
AnnaBridge	156:ff21514d8981	1205	*/
AnnaBridge	156:ff21514d8981	1206	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	156:ff21514d8981	1207	{
AnnaBridge	156:ff21514d8981	1208	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	156:ff21514d8981	1209	}
AnnaBridge	156:ff21514d8981	1210
AnnaBridge	156:ff21514d8981	1211	/**
AnnaBridge	156:ff21514d8981	1212	* @brief Get Memory address.
AnnaBridge	156:ff21514d8981	1213	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1214	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	156:ff21514d8981	1215	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1216	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1217	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1218	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1219	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1220	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1221	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1222	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1223	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1224	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1225	*/
AnnaBridge	156:ff21514d8981	1226	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1227	{
AnnaBridge	156:ff21514d8981	1228	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	156:ff21514d8981	1229	}
AnnaBridge	156:ff21514d8981	1230
AnnaBridge	156:ff21514d8981	1231	/**
AnnaBridge	156:ff21514d8981	1232	* @brief Get Peripheral address.
AnnaBridge	156:ff21514d8981	1233	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	156:ff21514d8981	1234	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	156:ff21514d8981	1235	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1236	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1237	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1238	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1239	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1240	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1241	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1242	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1243	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1244	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1245	*/
AnnaBridge	156:ff21514d8981	1246	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1247	{
AnnaBridge	156:ff21514d8981	1248	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	156:ff21514d8981	1249	}
AnnaBridge	156:ff21514d8981	1250
AnnaBridge	156:ff21514d8981	1251	/**
AnnaBridge	156:ff21514d8981	1252	* @brief Set the Memory to Memory Source address.
AnnaBridge	156:ff21514d8981	1253	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1254	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1255	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	156:ff21514d8981	1256	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1257	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1258	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1259	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1260	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1261	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1262	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1263	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1264	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1265	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1266	* @retval None
AnnaBridge	156:ff21514d8981	1267	*/
AnnaBridge	156:ff21514d8981	1268	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1269	{
AnnaBridge	156:ff21514d8981	1270	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1271	}
AnnaBridge	156:ff21514d8981	1272
AnnaBridge	156:ff21514d8981	1273	/**
AnnaBridge	156:ff21514d8981	1274	* @brief Set the Memory to Memory Destination address.
AnnaBridge	156:ff21514d8981	1275	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1276	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	156:ff21514d8981	1277	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	156:ff21514d8981	1278	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1279	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1280	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1281	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1282	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1283	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1284	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1285	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1286	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1287	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1288	* @retval None
AnnaBridge	156:ff21514d8981	1289	*/
AnnaBridge	156:ff21514d8981	1290	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	156:ff21514d8981	1291	{
AnnaBridge	156:ff21514d8981	1292	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	156:ff21514d8981	1293	}
AnnaBridge	156:ff21514d8981	1294
AnnaBridge	156:ff21514d8981	1295	/**
AnnaBridge	156:ff21514d8981	1296	* @brief Get the Memory to Memory Source address.
AnnaBridge	156:ff21514d8981	1297	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1298	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	156:ff21514d8981	1299	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1300	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1301	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1302	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1303	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1304	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1305	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1306	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1307	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1308	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1309	*/
AnnaBridge	156:ff21514d8981	1310	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1311	{
AnnaBridge	156:ff21514d8981	1312	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	156:ff21514d8981	1313	}
AnnaBridge	156:ff21514d8981	1314
AnnaBridge	156:ff21514d8981	1315	/**
AnnaBridge	156:ff21514d8981	1316	* @brief Get the Memory to Memory Destination address.
AnnaBridge	156:ff21514d8981	1317	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	156:ff21514d8981	1318	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	156:ff21514d8981	1319	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1320	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1321	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1322	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1323	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1324	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1325	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1326	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1327	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1328	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	156:ff21514d8981	1329	*/
AnnaBridge	156:ff21514d8981	1330	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1331	{
AnnaBridge	156:ff21514d8981	1332	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	156:ff21514d8981	1333	}
AnnaBridge	156:ff21514d8981	1334
AnnaBridge	161:aa5281ff4a02	1335	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	1336	/**
AnnaBridge	161:aa5281ff4a02	1337	* @brief Set DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	161:aa5281ff4a02	1338	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	1339	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	1340	* @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
AnnaBridge	161:aa5281ff4a02	1341	* @param DMAx DMAx Instance
AnnaBridge	161:aa5281ff4a02	1342	* @param Channel This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1343	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	161:aa5281ff4a02	1344	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	161:aa5281ff4a02	1345	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	161:aa5281ff4a02	1346	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	161:aa5281ff4a02	1347	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	161:aa5281ff4a02	1348	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	161:aa5281ff4a02	1349	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	161:aa5281ff4a02	1350	* @param Request This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1351	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	161:aa5281ff4a02	1352	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	161:aa5281ff4a02	1353	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	161:aa5281ff4a02	1354	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	161:aa5281ff4a02	1355	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	161:aa5281ff4a02	1356	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	161:aa5281ff4a02	1357	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	161:aa5281ff4a02	1358	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	161:aa5281ff4a02	1359	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	161:aa5281ff4a02	1360	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	161:aa5281ff4a02	1361	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	161:aa5281ff4a02	1362	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	161:aa5281ff4a02	1363	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	161:aa5281ff4a02	1364	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	161:aa5281ff4a02	1365	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	161:aa5281ff4a02	1366	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	161:aa5281ff4a02	1367	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	161:aa5281ff4a02	1368	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	161:aa5281ff4a02	1369	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	161:aa5281ff4a02	1370	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	161:aa5281ff4a02	1371	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	161:aa5281ff4a02	1372	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	161:aa5281ff4a02	1373	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	161:aa5281ff4a02	1374	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	161:aa5281ff4a02	1375	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	161:aa5281ff4a02	1376	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	161:aa5281ff4a02	1377	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	161:aa5281ff4a02	1378	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	161:aa5281ff4a02	1379	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	161:aa5281ff4a02	1380	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	161:aa5281ff4a02	1381	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	161:aa5281ff4a02	1382	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	161:aa5281ff4a02	1383	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	161:aa5281ff4a02	1384	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	161:aa5281ff4a02	1385	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	161:aa5281ff4a02	1386	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	161:aa5281ff4a02	1387	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	161:aa5281ff4a02	1388	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	161:aa5281ff4a02	1389	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	161:aa5281ff4a02	1390	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	161:aa5281ff4a02	1391	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	161:aa5281ff4a02	1392	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	161:aa5281ff4a02	1393	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	161:aa5281ff4a02	1394	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	161:aa5281ff4a02	1395	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	161:aa5281ff4a02	1396	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	161:aa5281ff4a02	1397	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	161:aa5281ff4a02	1398	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	161:aa5281ff4a02	1399	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	161:aa5281ff4a02	1400	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	161:aa5281ff4a02	1401	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	161:aa5281ff4a02	1402	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	161:aa5281ff4a02	1403	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	161:aa5281ff4a02	1404	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	161:aa5281ff4a02	1405	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	161:aa5281ff4a02	1406	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	161:aa5281ff4a02	1407	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	161:aa5281ff4a02	1408	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	161:aa5281ff4a02	1409	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	161:aa5281ff4a02	1410	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	161:aa5281ff4a02	1411	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	161:aa5281ff4a02	1412	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	161:aa5281ff4a02	1413	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	161:aa5281ff4a02	1414	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	161:aa5281ff4a02	1415	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	161:aa5281ff4a02	1416	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	161:aa5281ff4a02	1417	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	161:aa5281ff4a02	1418	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	161:aa5281ff4a02	1419	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	161:aa5281ff4a02	1420	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	161:aa5281ff4a02	1421	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	161:aa5281ff4a02	1422	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	161:aa5281ff4a02	1423	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	161:aa5281ff4a02	1424	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	161:aa5281ff4a02	1425	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	161:aa5281ff4a02	1426	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	161:aa5281ff4a02	1427	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	161:aa5281ff4a02	1428	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	161:aa5281ff4a02	1429	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	161:aa5281ff4a02	1430	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	161:aa5281ff4a02	1431	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	161:aa5281ff4a02	1432	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	161:aa5281ff4a02	1433	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	161:aa5281ff4a02	1434	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	161:aa5281ff4a02	1435	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	161:aa5281ff4a02	1436	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	161:aa5281ff4a02	1437	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	161:aa5281ff4a02	1438	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	161:aa5281ff4a02	1439	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	161:aa5281ff4a02	1440	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	161:aa5281ff4a02	1441	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	161:aa5281ff4a02	1442	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	161:aa5281ff4a02	1443	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	161:aa5281ff4a02	1444	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	161:aa5281ff4a02	1445	* @retval None
AnnaBridge	161:aa5281ff4a02	1446	*/
AnnaBridge	161:aa5281ff4a02	1447	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
AnnaBridge	161:aa5281ff4a02	1448	{
AnnaBridge	161:aa5281ff4a02	1449	MODIFY_REG(((DMAMUX_Channel_TypeDef)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
AnnaBridge	161:aa5281ff4a02	1450	}
AnnaBridge	161:aa5281ff4a02	1451
AnnaBridge	161:aa5281ff4a02	1452	/**
AnnaBridge	161:aa5281ff4a02	1453	* @brief Get DMA request for DMA Channels on DMAMUX Channel x.
AnnaBridge	161:aa5281ff4a02	1454	* @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	1455	* DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
AnnaBridge	161:aa5281ff4a02	1456	* @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
AnnaBridge	161:aa5281ff4a02	1457	* @param DMAx DMAx Instance
AnnaBridge	161:aa5281ff4a02	1458	* @param Channel This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1459	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	161:aa5281ff4a02	1460	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	161:aa5281ff4a02	1461	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	161:aa5281ff4a02	1462	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	161:aa5281ff4a02	1463	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	161:aa5281ff4a02	1464	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	161:aa5281ff4a02	1465	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	161:aa5281ff4a02	1466	* @retval Returned value can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1467	* @arg @ref LL_DMAMUX_REQUEST_MEM2MEM
AnnaBridge	161:aa5281ff4a02	1468	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR0
AnnaBridge	161:aa5281ff4a02	1469	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR1
AnnaBridge	161:aa5281ff4a02	1470	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR2
AnnaBridge	161:aa5281ff4a02	1471	* @arg @ref LL_DMAMUX_REQUEST_GENERATOR3
AnnaBridge	161:aa5281ff4a02	1472	* @arg @ref LL_DMAMUX_REQUEST_ADC1
AnnaBridge	161:aa5281ff4a02	1473	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1
AnnaBridge	161:aa5281ff4a02	1474	* @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2
AnnaBridge	161:aa5281ff4a02	1475	* @arg @ref LL_DMAMUX_REQUEST_TIM6_UP
AnnaBridge	161:aa5281ff4a02	1476	* @arg @ref LL_DMAMUX_REQUEST_TIM7_UP
AnnaBridge	161:aa5281ff4a02	1477	* @arg @ref LL_DMAMUX_REQUEST_SPI1_RX
AnnaBridge	161:aa5281ff4a02	1478	* @arg @ref LL_DMAMUX_REQUEST_SPI1_TX
AnnaBridge	161:aa5281ff4a02	1479	* @arg @ref LL_DMAMUX_REQUEST_SPI2_RX
AnnaBridge	161:aa5281ff4a02	1480	* @arg @ref LL_DMAMUX_REQUEST_SPI2_TX
AnnaBridge	161:aa5281ff4a02	1481	* @arg @ref LL_DMAMUX_REQUEST_SPI3_RX
AnnaBridge	161:aa5281ff4a02	1482	* @arg @ref LL_DMAMUX_REQUEST_SPI3_TX
AnnaBridge	161:aa5281ff4a02	1483	* @arg @ref LL_DMAMUX_REQUEST_I2C1_RX
AnnaBridge	161:aa5281ff4a02	1484	* @arg @ref LL_DMAMUX_REQUEST_I2C1_TX
AnnaBridge	161:aa5281ff4a02	1485	* @arg @ref LL_DMAMUX_REQUEST_I2C2_RX
AnnaBridge	161:aa5281ff4a02	1486	* @arg @ref LL_DMAMUX_REQUEST_I2C2_TX
AnnaBridge	161:aa5281ff4a02	1487	* @arg @ref LL_DMAMUX_REQUEST_I2C3_RX
AnnaBridge	161:aa5281ff4a02	1488	* @arg @ref LL_DMAMUX_REQUEST_I2C3_TX
AnnaBridge	161:aa5281ff4a02	1489	* @arg @ref LL_DMAMUX_REQUEST_I2C4_RX
AnnaBridge	161:aa5281ff4a02	1490	* @arg @ref LL_DMAMUX_REQUEST_I2C4_TX
AnnaBridge	161:aa5281ff4a02	1491	* @arg @ref LL_DMAMUX_REQUEST_USART1_RX
AnnaBridge	161:aa5281ff4a02	1492	* @arg @ref LL_DMAMUX_REQUEST_USART1_TX
AnnaBridge	161:aa5281ff4a02	1493	* @arg @ref LL_DMAMUX_REQUEST_USART2_RX
AnnaBridge	161:aa5281ff4a02	1494	* @arg @ref LL_DMAMUX_REQUEST_USART2_TX
AnnaBridge	161:aa5281ff4a02	1495	* @arg @ref LL_DMAMUX_REQUEST_USART3_RX
AnnaBridge	161:aa5281ff4a02	1496	* @arg @ref LL_DMAMUX_REQUEST_USART3_TX
AnnaBridge	161:aa5281ff4a02	1497	* @arg @ref LL_DMAMUX_REQUEST_UART4_RX
AnnaBridge	161:aa5281ff4a02	1498	* @arg @ref LL_DMAMUX_REQUEST_UART4_TX
AnnaBridge	161:aa5281ff4a02	1499	* @arg @ref LL_DMAMUX_REQUEST_UART5_RX
AnnaBridge	161:aa5281ff4a02	1500	* @arg @ref LL_DMAMUX_REQUEST_UART5_TX
AnnaBridge	161:aa5281ff4a02	1501	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX
AnnaBridge	161:aa5281ff4a02	1502	* @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX
AnnaBridge	161:aa5281ff4a02	1503	* @arg @ref LL_DMAMUX_REQUEST_SAI1_A
AnnaBridge	161:aa5281ff4a02	1504	* @arg @ref LL_DMAMUX_REQUEST_SAI1_B
AnnaBridge	161:aa5281ff4a02	1505	* @arg @ref LL_DMAMUX_REQUEST_SAI2_A
AnnaBridge	161:aa5281ff4a02	1506	* @arg @ref LL_DMAMUX_REQUEST_SAI2_B
AnnaBridge	161:aa5281ff4a02	1507	* @arg @ref LL_DMAMUX_REQUEST_OSPI1
AnnaBridge	161:aa5281ff4a02	1508	* @arg @ref LL_DMAMUX_REQUEST_OSPI2
AnnaBridge	161:aa5281ff4a02	1509	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1
AnnaBridge	161:aa5281ff4a02	1510	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2
AnnaBridge	161:aa5281ff4a02	1511	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3
AnnaBridge	161:aa5281ff4a02	1512	* @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4
AnnaBridge	161:aa5281ff4a02	1513	* @arg @ref LL_DMAMUX_REQUEST_TIM1_UP
AnnaBridge	161:aa5281ff4a02	1514	* @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG
AnnaBridge	161:aa5281ff4a02	1515	* @arg @ref LL_DMAMUX_REQUEST_TIM1_COM
AnnaBridge	161:aa5281ff4a02	1516	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1
AnnaBridge	161:aa5281ff4a02	1517	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2
AnnaBridge	161:aa5281ff4a02	1518	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3
AnnaBridge	161:aa5281ff4a02	1519	* @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4
AnnaBridge	161:aa5281ff4a02	1520	* @arg @ref LL_DMAMUX_REQUEST_TIM8_UP
AnnaBridge	161:aa5281ff4a02	1521	* @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG
AnnaBridge	161:aa5281ff4a02	1522	* @arg @ref LL_DMAMUX_REQUEST_TIM8_COM
AnnaBridge	161:aa5281ff4a02	1523	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1
AnnaBridge	161:aa5281ff4a02	1524	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2
AnnaBridge	161:aa5281ff4a02	1525	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3
AnnaBridge	161:aa5281ff4a02	1526	* @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4
AnnaBridge	161:aa5281ff4a02	1527	* @arg @ref LL_DMAMUX_REQUEST_TIM2_UP
AnnaBridge	161:aa5281ff4a02	1528	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1
AnnaBridge	161:aa5281ff4a02	1529	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2
AnnaBridge	161:aa5281ff4a02	1530	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3
AnnaBridge	161:aa5281ff4a02	1531	* @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4
AnnaBridge	161:aa5281ff4a02	1532	* @arg @ref LL_DMAMUX_REQUEST_TIM3_UP
AnnaBridge	161:aa5281ff4a02	1533	* @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG
AnnaBridge	161:aa5281ff4a02	1534	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1
AnnaBridge	161:aa5281ff4a02	1535	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2
AnnaBridge	161:aa5281ff4a02	1536	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3
AnnaBridge	161:aa5281ff4a02	1537	* @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4
AnnaBridge	161:aa5281ff4a02	1538	* @arg @ref LL_DMAMUX_REQUEST_TIM4_UP
AnnaBridge	161:aa5281ff4a02	1539	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1
AnnaBridge	161:aa5281ff4a02	1540	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2
AnnaBridge	161:aa5281ff4a02	1541	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3
AnnaBridge	161:aa5281ff4a02	1542	* @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4
AnnaBridge	161:aa5281ff4a02	1543	* @arg @ref LL_DMAMUX_REQUEST_TIM5_UP
AnnaBridge	161:aa5281ff4a02	1544	* @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG
AnnaBridge	161:aa5281ff4a02	1545	* @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1
AnnaBridge	161:aa5281ff4a02	1546	* @arg @ref LL_DMAMUX_REQUEST_TIM15_UP
AnnaBridge	161:aa5281ff4a02	1547	* @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG
AnnaBridge	161:aa5281ff4a02	1548	* @arg @ref LL_DMAMUX_REQUEST_TIM15_COM
AnnaBridge	161:aa5281ff4a02	1549	* @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1
AnnaBridge	161:aa5281ff4a02	1550	* @arg @ref LL_DMAMUX_REQUEST_TIM16_UP
AnnaBridge	161:aa5281ff4a02	1551	* @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1
AnnaBridge	161:aa5281ff4a02	1552	* @arg @ref LL_DMAMUX_REQUEST_TIM17_UP
AnnaBridge	161:aa5281ff4a02	1553	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0
AnnaBridge	161:aa5281ff4a02	1554	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1
AnnaBridge	161:aa5281ff4a02	1555	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2
AnnaBridge	161:aa5281ff4a02	1556	* @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3
AnnaBridge	161:aa5281ff4a02	1557	* @arg @ref LL_DMAMUX_REQUEST_DCMI
AnnaBridge	161:aa5281ff4a02	1558	* @arg @ref LL_DMAMUX_REQUEST_AES_IN
AnnaBridge	161:aa5281ff4a02	1559	* @arg @ref LL_DMAMUX_REQUEST_AES_OUT
AnnaBridge	161:aa5281ff4a02	1560	* @arg @ref LL_DMAMUX_REQUEST_HASH_IN
AnnaBridge	161:aa5281ff4a02	1561	*/
AnnaBridge	161:aa5281ff4a02	1562	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	161:aa5281ff4a02	1563	{
AnnaBridge	161:aa5281ff4a02	1564	return (READ_BIT(((DMAMUX_Channel_TypeDef)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
AnnaBridge	161:aa5281ff4a02	1565	}
AnnaBridge	161:aa5281ff4a02	1566	#else
AnnaBridge	156:ff21514d8981	1567	/**
AnnaBridge	156:ff21514d8981	1568	* @brief Set DMA request for DMA instance on Channel x.
AnnaBridge	156:ff21514d8981	1569	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
AnnaBridge	156:ff21514d8981	1570	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1571	* CSELR C2S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1572	* CSELR C3S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1573	* CSELR C4S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1574	* CSELR C5S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1575	* CSELR C6S LL_DMA_SetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1576	* CSELR C7S LL_DMA_SetPeriphRequest
AnnaBridge	156:ff21514d8981	1577	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1578	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1579	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1580	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1581	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1582	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1583	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1584	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1585	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1586	* @param PeriphRequest This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1587	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	156:ff21514d8981	1588	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	156:ff21514d8981	1589	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	156:ff21514d8981	1590	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	156:ff21514d8981	1591	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	156:ff21514d8981	1592	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	156:ff21514d8981	1593	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	156:ff21514d8981	1594	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	156:ff21514d8981	1595	* @retval None
AnnaBridge	156:ff21514d8981	1596	*/
AnnaBridge	156:ff21514d8981	1597	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
AnnaBridge	156:ff21514d8981	1598	{
AnnaBridge	156:ff21514d8981	1599	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	156:ff21514d8981	1600	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
AnnaBridge	156:ff21514d8981	1601	}
AnnaBridge	156:ff21514d8981	1602
AnnaBridge	156:ff21514d8981	1603	/**
AnnaBridge	156:ff21514d8981	1604	* @brief Get DMA request for DMA instance on Channel x.
AnnaBridge	156:ff21514d8981	1605	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1606	* CSELR C2S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1607	* CSELR C3S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1608	* CSELR C4S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1609	* CSELR C5S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1610	* CSELR C6S LL_DMA_GetPeriphRequest\n
AnnaBridge	156:ff21514d8981	1611	* CSELR C7S LL_DMA_GetPeriphRequest
AnnaBridge	156:ff21514d8981	1612	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1613	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1614	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	1615	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	1616	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	1617	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	1618	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	1619	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	1620	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	1621	* @retval Returned value can be one of the following values:
AnnaBridge	156:ff21514d8981	1622	* @arg @ref LL_DMA_REQUEST_0
AnnaBridge	156:ff21514d8981	1623	* @arg @ref LL_DMA_REQUEST_1
AnnaBridge	156:ff21514d8981	1624	* @arg @ref LL_DMA_REQUEST_2
AnnaBridge	156:ff21514d8981	1625	* @arg @ref LL_DMA_REQUEST_3
AnnaBridge	156:ff21514d8981	1626	* @arg @ref LL_DMA_REQUEST_4
AnnaBridge	156:ff21514d8981	1627	* @arg @ref LL_DMA_REQUEST_5
AnnaBridge	156:ff21514d8981	1628	* @arg @ref LL_DMA_REQUEST_6
AnnaBridge	156:ff21514d8981	1629	* @arg @ref LL_DMA_REQUEST_7
AnnaBridge	156:ff21514d8981	1630	*/
AnnaBridge	156:ff21514d8981	1631	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	1632	{
AnnaBridge	156:ff21514d8981	1633	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
AnnaBridge	156:ff21514d8981	1634	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
AnnaBridge	156:ff21514d8981	1635	}
AnnaBridge	161:aa5281ff4a02	1636	#endif /* DMAMUX1 */
AnnaBridge	156:ff21514d8981	1637
AnnaBridge	156:ff21514d8981	1638	/**
AnnaBridge	156:ff21514d8981	1639	* @}
AnnaBridge	156:ff21514d8981	1640	*/
AnnaBridge	156:ff21514d8981	1641
AnnaBridge	156:ff21514d8981	1642	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	156:ff21514d8981	1643	* @{
AnnaBridge	156:ff21514d8981	1644	*/
AnnaBridge	156:ff21514d8981	1645
AnnaBridge	156:ff21514d8981	1646	/**
AnnaBridge	156:ff21514d8981	1647	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	156:ff21514d8981	1648	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	156:ff21514d8981	1649	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1650	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1651	*/
AnnaBridge	156:ff21514d8981	1652	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1653	{
AnnaBridge	156:ff21514d8981	1654	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	156:ff21514d8981	1655	}
AnnaBridge	156:ff21514d8981	1656
AnnaBridge	156:ff21514d8981	1657	/**
AnnaBridge	156:ff21514d8981	1658	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	156:ff21514d8981	1659	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	156:ff21514d8981	1660	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1661	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1662	*/
AnnaBridge	156:ff21514d8981	1663	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1664	{
AnnaBridge	156:ff21514d8981	1665	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	156:ff21514d8981	1666	}
AnnaBridge	156:ff21514d8981	1667
AnnaBridge	156:ff21514d8981	1668	/**
AnnaBridge	156:ff21514d8981	1669	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	156:ff21514d8981	1670	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	156:ff21514d8981	1671	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1672	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1673	*/
AnnaBridge	156:ff21514d8981	1674	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1675	{
AnnaBridge	156:ff21514d8981	1676	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	156:ff21514d8981	1677	}
AnnaBridge	156:ff21514d8981	1678
AnnaBridge	156:ff21514d8981	1679	/**
AnnaBridge	156:ff21514d8981	1680	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	156:ff21514d8981	1681	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	156:ff21514d8981	1682	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1683	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1684	*/
AnnaBridge	156:ff21514d8981	1685	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1686	{
AnnaBridge	156:ff21514d8981	1687	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	156:ff21514d8981	1688	}
AnnaBridge	156:ff21514d8981	1689
AnnaBridge	156:ff21514d8981	1690	/**
AnnaBridge	156:ff21514d8981	1691	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	156:ff21514d8981	1692	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	156:ff21514d8981	1693	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1694	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1695	*/
AnnaBridge	156:ff21514d8981	1696	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1697	{
AnnaBridge	156:ff21514d8981	1698	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	156:ff21514d8981	1699	}
AnnaBridge	156:ff21514d8981	1700
AnnaBridge	156:ff21514d8981	1701	/**
AnnaBridge	156:ff21514d8981	1702	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	156:ff21514d8981	1703	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	156:ff21514d8981	1704	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1705	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1706	*/
AnnaBridge	156:ff21514d8981	1707	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1708	{
AnnaBridge	156:ff21514d8981	1709	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	156:ff21514d8981	1710	}
AnnaBridge	156:ff21514d8981	1711
AnnaBridge	156:ff21514d8981	1712	/**
AnnaBridge	156:ff21514d8981	1713	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	156:ff21514d8981	1714	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	156:ff21514d8981	1715	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1716	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1717	*/
AnnaBridge	156:ff21514d8981	1718	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1719	{
AnnaBridge	156:ff21514d8981	1720	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	156:ff21514d8981	1721	}
AnnaBridge	156:ff21514d8981	1722
AnnaBridge	156:ff21514d8981	1723	/**
AnnaBridge	156:ff21514d8981	1724	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	156:ff21514d8981	1725	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	156:ff21514d8981	1726	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1727	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1728	*/
AnnaBridge	156:ff21514d8981	1729	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1730	{
AnnaBridge	156:ff21514d8981	1731	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	156:ff21514d8981	1732	}
AnnaBridge	156:ff21514d8981	1733
AnnaBridge	156:ff21514d8981	1734	/**
AnnaBridge	156:ff21514d8981	1735	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	156:ff21514d8981	1736	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	156:ff21514d8981	1737	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1738	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1739	*/
AnnaBridge	156:ff21514d8981	1740	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1741	{
AnnaBridge	156:ff21514d8981	1742	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	156:ff21514d8981	1743	}
AnnaBridge	156:ff21514d8981	1744
AnnaBridge	156:ff21514d8981	1745	/**
AnnaBridge	156:ff21514d8981	1746	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	156:ff21514d8981	1747	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	156:ff21514d8981	1748	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1749	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1750	*/
AnnaBridge	156:ff21514d8981	1751	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1752	{
AnnaBridge	156:ff21514d8981	1753	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	156:ff21514d8981	1754	}
AnnaBridge	156:ff21514d8981	1755
AnnaBridge	156:ff21514d8981	1756	/**
AnnaBridge	156:ff21514d8981	1757	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	156:ff21514d8981	1758	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	156:ff21514d8981	1759	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1760	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1761	*/
AnnaBridge	156:ff21514d8981	1762	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1763	{
AnnaBridge	156:ff21514d8981	1764	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	156:ff21514d8981	1765	}
AnnaBridge	156:ff21514d8981	1766
AnnaBridge	156:ff21514d8981	1767	/**
AnnaBridge	156:ff21514d8981	1768	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	156:ff21514d8981	1769	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	156:ff21514d8981	1770	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1771	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1772	*/
AnnaBridge	156:ff21514d8981	1773	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1774	{
AnnaBridge	156:ff21514d8981	1775	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	156:ff21514d8981	1776	}
AnnaBridge	156:ff21514d8981	1777
AnnaBridge	156:ff21514d8981	1778	/**
AnnaBridge	156:ff21514d8981	1779	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	156:ff21514d8981	1780	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	156:ff21514d8981	1781	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1782	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1783	*/
AnnaBridge	156:ff21514d8981	1784	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1785	{
AnnaBridge	156:ff21514d8981	1786	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	156:ff21514d8981	1787	}
AnnaBridge	156:ff21514d8981	1788
AnnaBridge	156:ff21514d8981	1789	/**
AnnaBridge	156:ff21514d8981	1790	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	156:ff21514d8981	1791	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	156:ff21514d8981	1792	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1793	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1794	*/
AnnaBridge	156:ff21514d8981	1795	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1796	{
AnnaBridge	156:ff21514d8981	1797	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	156:ff21514d8981	1798	}
AnnaBridge	156:ff21514d8981	1799
AnnaBridge	156:ff21514d8981	1800	/**
AnnaBridge	156:ff21514d8981	1801	* @brief Get Channel 1 half transfer flag.
AnnaBridge	156:ff21514d8981	1802	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	156:ff21514d8981	1803	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1804	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1805	*/
AnnaBridge	156:ff21514d8981	1806	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1807	{
AnnaBridge	156:ff21514d8981	1808	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	156:ff21514d8981	1809	}
AnnaBridge	156:ff21514d8981	1810
AnnaBridge	156:ff21514d8981	1811	/**
AnnaBridge	156:ff21514d8981	1812	* @brief Get Channel 2 half transfer flag.
AnnaBridge	156:ff21514d8981	1813	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	156:ff21514d8981	1814	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1815	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1816	*/
AnnaBridge	156:ff21514d8981	1817	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1818	{
AnnaBridge	156:ff21514d8981	1819	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	156:ff21514d8981	1820	}
AnnaBridge	156:ff21514d8981	1821
AnnaBridge	156:ff21514d8981	1822	/**
AnnaBridge	156:ff21514d8981	1823	* @brief Get Channel 3 half transfer flag.
AnnaBridge	156:ff21514d8981	1824	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	156:ff21514d8981	1825	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1826	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1827	*/
AnnaBridge	156:ff21514d8981	1828	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1829	{
AnnaBridge	156:ff21514d8981	1830	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	156:ff21514d8981	1831	}
AnnaBridge	156:ff21514d8981	1832
AnnaBridge	156:ff21514d8981	1833	/**
AnnaBridge	156:ff21514d8981	1834	* @brief Get Channel 4 half transfer flag.
AnnaBridge	156:ff21514d8981	1835	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	156:ff21514d8981	1836	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1837	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1838	*/
AnnaBridge	156:ff21514d8981	1839	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1840	{
AnnaBridge	156:ff21514d8981	1841	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	156:ff21514d8981	1842	}
AnnaBridge	156:ff21514d8981	1843
AnnaBridge	156:ff21514d8981	1844	/**
AnnaBridge	156:ff21514d8981	1845	* @brief Get Channel 5 half transfer flag.
AnnaBridge	156:ff21514d8981	1846	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	156:ff21514d8981	1847	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1848	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1849	*/
AnnaBridge	156:ff21514d8981	1850	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1851	{
AnnaBridge	156:ff21514d8981	1852	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	156:ff21514d8981	1853	}
AnnaBridge	156:ff21514d8981	1854
AnnaBridge	156:ff21514d8981	1855	/**
AnnaBridge	156:ff21514d8981	1856	* @brief Get Channel 6 half transfer flag.
AnnaBridge	156:ff21514d8981	1857	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	156:ff21514d8981	1858	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1859	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1860	*/
AnnaBridge	156:ff21514d8981	1861	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1862	{
AnnaBridge	156:ff21514d8981	1863	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	156:ff21514d8981	1864	}
AnnaBridge	156:ff21514d8981	1865
AnnaBridge	156:ff21514d8981	1866	/**
AnnaBridge	156:ff21514d8981	1867	* @brief Get Channel 7 half transfer flag.
AnnaBridge	156:ff21514d8981	1868	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	156:ff21514d8981	1869	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1870	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1871	*/
AnnaBridge	156:ff21514d8981	1872	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1873	{
AnnaBridge	156:ff21514d8981	1874	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	156:ff21514d8981	1875	}
AnnaBridge	156:ff21514d8981	1876
AnnaBridge	156:ff21514d8981	1877	/**
AnnaBridge	156:ff21514d8981	1878	* @brief Get Channel 1 transfer error flag.
AnnaBridge	156:ff21514d8981	1879	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	156:ff21514d8981	1880	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1881	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1882	*/
AnnaBridge	156:ff21514d8981	1883	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1884	{
AnnaBridge	156:ff21514d8981	1885	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	156:ff21514d8981	1886	}
AnnaBridge	156:ff21514d8981	1887
AnnaBridge	156:ff21514d8981	1888	/**
AnnaBridge	156:ff21514d8981	1889	* @brief Get Channel 2 transfer error flag.
AnnaBridge	156:ff21514d8981	1890	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	156:ff21514d8981	1891	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1892	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1893	*/
AnnaBridge	156:ff21514d8981	1894	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1895	{
AnnaBridge	156:ff21514d8981	1896	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	156:ff21514d8981	1897	}
AnnaBridge	156:ff21514d8981	1898
AnnaBridge	156:ff21514d8981	1899	/**
AnnaBridge	156:ff21514d8981	1900	* @brief Get Channel 3 transfer error flag.
AnnaBridge	156:ff21514d8981	1901	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	156:ff21514d8981	1902	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1903	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1904	*/
AnnaBridge	156:ff21514d8981	1905	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1906	{
AnnaBridge	156:ff21514d8981	1907	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	156:ff21514d8981	1908	}
AnnaBridge	156:ff21514d8981	1909
AnnaBridge	156:ff21514d8981	1910	/**
AnnaBridge	156:ff21514d8981	1911	* @brief Get Channel 4 transfer error flag.
AnnaBridge	156:ff21514d8981	1912	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	156:ff21514d8981	1913	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1914	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1915	*/
AnnaBridge	156:ff21514d8981	1916	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1917	{
AnnaBridge	156:ff21514d8981	1918	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	156:ff21514d8981	1919	}
AnnaBridge	156:ff21514d8981	1920
AnnaBridge	156:ff21514d8981	1921	/**
AnnaBridge	156:ff21514d8981	1922	* @brief Get Channel 5 transfer error flag.
AnnaBridge	156:ff21514d8981	1923	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	156:ff21514d8981	1924	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1925	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1926	*/
AnnaBridge	156:ff21514d8981	1927	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1928	{
AnnaBridge	156:ff21514d8981	1929	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	156:ff21514d8981	1930	}
AnnaBridge	156:ff21514d8981	1931
AnnaBridge	156:ff21514d8981	1932	/**
AnnaBridge	156:ff21514d8981	1933	* @brief Get Channel 6 transfer error flag.
AnnaBridge	156:ff21514d8981	1934	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	156:ff21514d8981	1935	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1936	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1937	*/
AnnaBridge	156:ff21514d8981	1938	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1939	{
AnnaBridge	156:ff21514d8981	1940	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	156:ff21514d8981	1941	}
AnnaBridge	156:ff21514d8981	1942
AnnaBridge	156:ff21514d8981	1943	/**
AnnaBridge	156:ff21514d8981	1944	* @brief Get Channel 7 transfer error flag.
AnnaBridge	156:ff21514d8981	1945	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	156:ff21514d8981	1946	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1947	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	1948	*/
AnnaBridge	156:ff21514d8981	1949	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1950	{
AnnaBridge	156:ff21514d8981	1951	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	156:ff21514d8981	1952	}
AnnaBridge	156:ff21514d8981	1953
AnnaBridge	156:ff21514d8981	1954	/**
AnnaBridge	156:ff21514d8981	1955	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	156:ff21514d8981	1956	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	156:ff21514d8981	1957	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1958	* @retval None
AnnaBridge	156:ff21514d8981	1959	*/
AnnaBridge	156:ff21514d8981	1960	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1961	{
AnnaBridge	156:ff21514d8981	1962	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	156:ff21514d8981	1963	}
AnnaBridge	156:ff21514d8981	1964
AnnaBridge	156:ff21514d8981	1965	/**
AnnaBridge	156:ff21514d8981	1966	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	156:ff21514d8981	1967	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	156:ff21514d8981	1968	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1969	* @retval None
AnnaBridge	156:ff21514d8981	1970	*/
AnnaBridge	156:ff21514d8981	1971	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1972	{
AnnaBridge	156:ff21514d8981	1973	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	156:ff21514d8981	1974	}
AnnaBridge	156:ff21514d8981	1975
AnnaBridge	156:ff21514d8981	1976	/**
AnnaBridge	156:ff21514d8981	1977	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	156:ff21514d8981	1978	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	156:ff21514d8981	1979	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1980	* @retval None
AnnaBridge	156:ff21514d8981	1981	*/
AnnaBridge	156:ff21514d8981	1982	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1983	{
AnnaBridge	156:ff21514d8981	1984	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	156:ff21514d8981	1985	}
AnnaBridge	156:ff21514d8981	1986
AnnaBridge	156:ff21514d8981	1987	/**
AnnaBridge	156:ff21514d8981	1988	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	156:ff21514d8981	1989	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	156:ff21514d8981	1990	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	1991	* @retval None
AnnaBridge	156:ff21514d8981	1992	*/
AnnaBridge	156:ff21514d8981	1993	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	1994	{
AnnaBridge	156:ff21514d8981	1995	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	156:ff21514d8981	1996	}
AnnaBridge	156:ff21514d8981	1997
AnnaBridge	156:ff21514d8981	1998	/**
AnnaBridge	156:ff21514d8981	1999	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	156:ff21514d8981	2000	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	156:ff21514d8981	2001	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2002	* @retval None
AnnaBridge	156:ff21514d8981	2003	*/
AnnaBridge	156:ff21514d8981	2004	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2005	{
AnnaBridge	156:ff21514d8981	2006	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	156:ff21514d8981	2007	}
AnnaBridge	156:ff21514d8981	2008
AnnaBridge	156:ff21514d8981	2009	/**
AnnaBridge	156:ff21514d8981	2010	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	156:ff21514d8981	2011	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	156:ff21514d8981	2012	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2013	* @retval None
AnnaBridge	156:ff21514d8981	2014	*/
AnnaBridge	156:ff21514d8981	2015	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2016	{
AnnaBridge	156:ff21514d8981	2017	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	156:ff21514d8981	2018	}
AnnaBridge	156:ff21514d8981	2019
AnnaBridge	156:ff21514d8981	2020	/**
AnnaBridge	156:ff21514d8981	2021	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	156:ff21514d8981	2022	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	156:ff21514d8981	2023	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2024	* @retval None
AnnaBridge	156:ff21514d8981	2025	*/
AnnaBridge	156:ff21514d8981	2026	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2027	{
AnnaBridge	156:ff21514d8981	2028	WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	156:ff21514d8981	2029	}
AnnaBridge	156:ff21514d8981	2030
AnnaBridge	156:ff21514d8981	2031	/**
AnnaBridge	156:ff21514d8981	2032	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	156:ff21514d8981	2033	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	156:ff21514d8981	2034	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2035	* @retval None
AnnaBridge	156:ff21514d8981	2036	*/
AnnaBridge	156:ff21514d8981	2037	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2038	{
AnnaBridge	156:ff21514d8981	2039	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	156:ff21514d8981	2040	}
AnnaBridge	156:ff21514d8981	2041
AnnaBridge	156:ff21514d8981	2042	/**
AnnaBridge	156:ff21514d8981	2043	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	156:ff21514d8981	2044	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	156:ff21514d8981	2045	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2046	* @retval None
AnnaBridge	156:ff21514d8981	2047	*/
AnnaBridge	156:ff21514d8981	2048	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2049	{
AnnaBridge	156:ff21514d8981	2050	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	156:ff21514d8981	2051	}
AnnaBridge	156:ff21514d8981	2052
AnnaBridge	156:ff21514d8981	2053	/**
AnnaBridge	156:ff21514d8981	2054	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	156:ff21514d8981	2055	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	156:ff21514d8981	2056	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2057	* @retval None
AnnaBridge	156:ff21514d8981	2058	*/
AnnaBridge	156:ff21514d8981	2059	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2060	{
AnnaBridge	156:ff21514d8981	2061	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	156:ff21514d8981	2062	}
AnnaBridge	156:ff21514d8981	2063
AnnaBridge	156:ff21514d8981	2064	/**
AnnaBridge	156:ff21514d8981	2065	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	156:ff21514d8981	2066	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	156:ff21514d8981	2067	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2068	* @retval None
AnnaBridge	156:ff21514d8981	2069	*/
AnnaBridge	156:ff21514d8981	2070	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2071	{
AnnaBridge	156:ff21514d8981	2072	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	156:ff21514d8981	2073	}
AnnaBridge	156:ff21514d8981	2074
AnnaBridge	156:ff21514d8981	2075	/**
AnnaBridge	156:ff21514d8981	2076	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	156:ff21514d8981	2077	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	156:ff21514d8981	2078	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2079	* @retval None
AnnaBridge	156:ff21514d8981	2080	*/
AnnaBridge	156:ff21514d8981	2081	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2082	{
AnnaBridge	156:ff21514d8981	2083	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	156:ff21514d8981	2084	}
AnnaBridge	156:ff21514d8981	2085
AnnaBridge	156:ff21514d8981	2086	/**
AnnaBridge	156:ff21514d8981	2087	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	156:ff21514d8981	2088	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	156:ff21514d8981	2089	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2090	* @retval None
AnnaBridge	156:ff21514d8981	2091	*/
AnnaBridge	156:ff21514d8981	2092	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2093	{
AnnaBridge	156:ff21514d8981	2094	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	156:ff21514d8981	2095	}
AnnaBridge	156:ff21514d8981	2096
AnnaBridge	156:ff21514d8981	2097	/**
AnnaBridge	156:ff21514d8981	2098	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	156:ff21514d8981	2099	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	156:ff21514d8981	2100	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2101	* @retval None
AnnaBridge	156:ff21514d8981	2102	*/
AnnaBridge	156:ff21514d8981	2103	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2104	{
AnnaBridge	156:ff21514d8981	2105	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	156:ff21514d8981	2106	}
AnnaBridge	156:ff21514d8981	2107
AnnaBridge	156:ff21514d8981	2108	/**
AnnaBridge	156:ff21514d8981	2109	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	156:ff21514d8981	2110	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	156:ff21514d8981	2111	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2112	* @retval None
AnnaBridge	156:ff21514d8981	2113	*/
AnnaBridge	156:ff21514d8981	2114	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2115	{
AnnaBridge	156:ff21514d8981	2116	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	156:ff21514d8981	2117	}
AnnaBridge	156:ff21514d8981	2118
AnnaBridge	156:ff21514d8981	2119	/**
AnnaBridge	156:ff21514d8981	2120	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	156:ff21514d8981	2121	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	156:ff21514d8981	2122	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2123	* @retval None
AnnaBridge	156:ff21514d8981	2124	*/
AnnaBridge	156:ff21514d8981	2125	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2126	{
AnnaBridge	156:ff21514d8981	2127	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	156:ff21514d8981	2128	}
AnnaBridge	156:ff21514d8981	2129
AnnaBridge	156:ff21514d8981	2130	/**
AnnaBridge	156:ff21514d8981	2131	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	156:ff21514d8981	2132	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	156:ff21514d8981	2133	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2134	* @retval None
AnnaBridge	156:ff21514d8981	2135	*/
AnnaBridge	156:ff21514d8981	2136	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2137	{
AnnaBridge	156:ff21514d8981	2138	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	156:ff21514d8981	2139	}
AnnaBridge	156:ff21514d8981	2140
AnnaBridge	156:ff21514d8981	2141	/**
AnnaBridge	156:ff21514d8981	2142	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	156:ff21514d8981	2143	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	156:ff21514d8981	2144	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2145	* @retval None
AnnaBridge	156:ff21514d8981	2146	*/
AnnaBridge	156:ff21514d8981	2147	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2148	{
AnnaBridge	156:ff21514d8981	2149	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	156:ff21514d8981	2150	}
AnnaBridge	156:ff21514d8981	2151
AnnaBridge	156:ff21514d8981	2152	/**
AnnaBridge	156:ff21514d8981	2153	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	156:ff21514d8981	2154	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	156:ff21514d8981	2155	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2156	* @retval None
AnnaBridge	156:ff21514d8981	2157	*/
AnnaBridge	156:ff21514d8981	2158	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2159	{
AnnaBridge	156:ff21514d8981	2160	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	156:ff21514d8981	2161	}
AnnaBridge	156:ff21514d8981	2162
AnnaBridge	156:ff21514d8981	2163	/**
AnnaBridge	156:ff21514d8981	2164	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	156:ff21514d8981	2165	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	156:ff21514d8981	2166	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2167	* @retval None
AnnaBridge	156:ff21514d8981	2168	*/
AnnaBridge	156:ff21514d8981	2169	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2170	{
AnnaBridge	156:ff21514d8981	2171	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	156:ff21514d8981	2172	}
AnnaBridge	156:ff21514d8981	2173
AnnaBridge	156:ff21514d8981	2174	/**
AnnaBridge	156:ff21514d8981	2175	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	156:ff21514d8981	2176	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	156:ff21514d8981	2177	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2178	* @retval None
AnnaBridge	156:ff21514d8981	2179	*/
AnnaBridge	156:ff21514d8981	2180	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2181	{
AnnaBridge	156:ff21514d8981	2182	WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	156:ff21514d8981	2183	}
AnnaBridge	156:ff21514d8981	2184
AnnaBridge	156:ff21514d8981	2185	/**
AnnaBridge	156:ff21514d8981	2186	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	156:ff21514d8981	2187	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	156:ff21514d8981	2188	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2189	* @retval None
AnnaBridge	156:ff21514d8981	2190	*/
AnnaBridge	156:ff21514d8981	2191	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2192	{
AnnaBridge	156:ff21514d8981	2193	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	156:ff21514d8981	2194	}
AnnaBridge	156:ff21514d8981	2195
AnnaBridge	156:ff21514d8981	2196	/**
AnnaBridge	156:ff21514d8981	2197	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	156:ff21514d8981	2198	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	156:ff21514d8981	2199	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2200	* @retval None
AnnaBridge	156:ff21514d8981	2201	*/
AnnaBridge	156:ff21514d8981	2202	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2203	{
AnnaBridge	156:ff21514d8981	2204	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	156:ff21514d8981	2205	}
AnnaBridge	156:ff21514d8981	2206
AnnaBridge	156:ff21514d8981	2207	/**
AnnaBridge	156:ff21514d8981	2208	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	156:ff21514d8981	2209	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	156:ff21514d8981	2210	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2211	* @retval None
AnnaBridge	156:ff21514d8981	2212	*/
AnnaBridge	156:ff21514d8981	2213	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2214	{
AnnaBridge	156:ff21514d8981	2215	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	156:ff21514d8981	2216	}
AnnaBridge	156:ff21514d8981	2217
AnnaBridge	156:ff21514d8981	2218	/**
AnnaBridge	156:ff21514d8981	2219	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	156:ff21514d8981	2220	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	156:ff21514d8981	2221	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2222	* @retval None
AnnaBridge	156:ff21514d8981	2223	*/
AnnaBridge	156:ff21514d8981	2224	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2225	{
AnnaBridge	156:ff21514d8981	2226	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	156:ff21514d8981	2227	}
AnnaBridge	156:ff21514d8981	2228
AnnaBridge	156:ff21514d8981	2229	/**
AnnaBridge	156:ff21514d8981	2230	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	156:ff21514d8981	2231	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	156:ff21514d8981	2232	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2233	* @retval None
AnnaBridge	156:ff21514d8981	2234	*/
AnnaBridge	156:ff21514d8981	2235	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2236	{
AnnaBridge	156:ff21514d8981	2237	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	156:ff21514d8981	2238	}
AnnaBridge	156:ff21514d8981	2239
AnnaBridge	156:ff21514d8981	2240	/**
AnnaBridge	156:ff21514d8981	2241	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	156:ff21514d8981	2242	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	156:ff21514d8981	2243	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2244	* @retval None
AnnaBridge	156:ff21514d8981	2245	*/
AnnaBridge	156:ff21514d8981	2246	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2247	{
AnnaBridge	156:ff21514d8981	2248	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	156:ff21514d8981	2249	}
AnnaBridge	156:ff21514d8981	2250
AnnaBridge	156:ff21514d8981	2251	/**
AnnaBridge	156:ff21514d8981	2252	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	156:ff21514d8981	2253	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	156:ff21514d8981	2254	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2255	* @retval None
AnnaBridge	156:ff21514d8981	2256	*/
AnnaBridge	156:ff21514d8981	2257	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	156:ff21514d8981	2258	{
AnnaBridge	156:ff21514d8981	2259	WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	156:ff21514d8981	2260	}
AnnaBridge	156:ff21514d8981	2261
AnnaBridge	156:ff21514d8981	2262	/**
AnnaBridge	156:ff21514d8981	2263	* @}
AnnaBridge	156:ff21514d8981	2264	*/
AnnaBridge	156:ff21514d8981	2265
AnnaBridge	156:ff21514d8981	2266	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	156:ff21514d8981	2267	* @{
AnnaBridge	156:ff21514d8981	2268	*/
AnnaBridge	156:ff21514d8981	2269	/**
AnnaBridge	156:ff21514d8981	2270	* @brief Enable Transfer complete interrupt.
AnnaBridge	156:ff21514d8981	2271	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	156:ff21514d8981	2272	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2273	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2274	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2275	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2276	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2277	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2278	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2279	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2280	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2281	* @retval None
AnnaBridge	156:ff21514d8981	2282	*/
AnnaBridge	156:ff21514d8981	2283	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2284	{
AnnaBridge	156:ff21514d8981	2285	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	156:ff21514d8981	2286	}
AnnaBridge	156:ff21514d8981	2287
AnnaBridge	156:ff21514d8981	2288	/**
AnnaBridge	156:ff21514d8981	2289	* @brief Enable Half transfer interrupt.
AnnaBridge	156:ff21514d8981	2290	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	156:ff21514d8981	2291	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2292	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2293	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2294	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2295	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2296	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2297	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2298	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2299	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2300	* @retval None
AnnaBridge	156:ff21514d8981	2301	*/
AnnaBridge	156:ff21514d8981	2302	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2303	{
AnnaBridge	156:ff21514d8981	2304	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	156:ff21514d8981	2305	}
AnnaBridge	156:ff21514d8981	2306
AnnaBridge	156:ff21514d8981	2307	/**
AnnaBridge	156:ff21514d8981	2308	* @brief Enable Transfer error interrupt.
AnnaBridge	156:ff21514d8981	2309	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	156:ff21514d8981	2310	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2311	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2312	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2313	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2314	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2315	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2316	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2317	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2318	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2319	* @retval None
AnnaBridge	156:ff21514d8981	2320	*/
AnnaBridge	156:ff21514d8981	2321	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2322	{
AnnaBridge	156:ff21514d8981	2323	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	156:ff21514d8981	2324	}
AnnaBridge	156:ff21514d8981	2325
AnnaBridge	156:ff21514d8981	2326	/**
AnnaBridge	156:ff21514d8981	2327	* @brief Disable Transfer complete interrupt.
AnnaBridge	156:ff21514d8981	2328	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	156:ff21514d8981	2329	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2330	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2331	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2332	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2333	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2334	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2335	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2336	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2337	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2338	* @retval None
AnnaBridge	156:ff21514d8981	2339	*/
AnnaBridge	156:ff21514d8981	2340	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2341	{
AnnaBridge	156:ff21514d8981	2342	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	156:ff21514d8981	2343	}
AnnaBridge	156:ff21514d8981	2344
AnnaBridge	156:ff21514d8981	2345	/**
AnnaBridge	156:ff21514d8981	2346	* @brief Disable Half transfer interrupt.
AnnaBridge	156:ff21514d8981	2347	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	156:ff21514d8981	2348	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2349	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2350	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2351	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2352	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2353	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2354	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2355	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2356	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2357	* @retval None
AnnaBridge	156:ff21514d8981	2358	*/
AnnaBridge	156:ff21514d8981	2359	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2360	{
AnnaBridge	156:ff21514d8981	2361	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	156:ff21514d8981	2362	}
AnnaBridge	156:ff21514d8981	2363
AnnaBridge	156:ff21514d8981	2364	/**
AnnaBridge	156:ff21514d8981	2365	* @brief Disable Transfer error interrupt.
AnnaBridge	156:ff21514d8981	2366	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	156:ff21514d8981	2367	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2368	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2369	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2370	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2371	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2372	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2373	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2374	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2375	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2376	* @retval None
AnnaBridge	156:ff21514d8981	2377	*/
AnnaBridge	156:ff21514d8981	2378	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2379	{
AnnaBridge	156:ff21514d8981	2380	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	156:ff21514d8981	2381	}
AnnaBridge	156:ff21514d8981	2382
AnnaBridge	156:ff21514d8981	2383	/**
AnnaBridge	156:ff21514d8981	2384	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2385	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	156:ff21514d8981	2386	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2387	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2388	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2389	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2390	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2391	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2392	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2393	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2394	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2395	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2396	*/
AnnaBridge	156:ff21514d8981	2397	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2398	{
AnnaBridge	156:ff21514d8981	2399	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2400	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	156:ff21514d8981	2401	}
AnnaBridge	156:ff21514d8981	2402
AnnaBridge	156:ff21514d8981	2403	/**
AnnaBridge	156:ff21514d8981	2404	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2405	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	156:ff21514d8981	2406	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2407	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2408	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2409	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2410	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2411	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2412	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2413	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2414	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2415	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2416	*/
AnnaBridge	156:ff21514d8981	2417	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2418	{
AnnaBridge	156:ff21514d8981	2419	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2420	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	156:ff21514d8981	2421	}
AnnaBridge	156:ff21514d8981	2422
AnnaBridge	156:ff21514d8981	2423	/**
AnnaBridge	156:ff21514d8981	2424	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	156:ff21514d8981	2425	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	156:ff21514d8981	2426	* @param DMAx DMAx Instance
AnnaBridge	156:ff21514d8981	2427	* @param Channel This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	2428	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	156:ff21514d8981	2429	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	156:ff21514d8981	2430	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	156:ff21514d8981	2431	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	156:ff21514d8981	2432	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	156:ff21514d8981	2433	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	156:ff21514d8981	2434	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	156:ff21514d8981	2435	* @retval State of bit (1 or 0).
AnnaBridge	156:ff21514d8981	2436	*/
AnnaBridge	156:ff21514d8981	2437	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	156:ff21514d8981	2438	{
AnnaBridge	156:ff21514d8981	2439	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	156:ff21514d8981	2440	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	156:ff21514d8981	2441	}
AnnaBridge	156:ff21514d8981	2442
AnnaBridge	156:ff21514d8981	2443	/**
AnnaBridge	156:ff21514d8981	2444	* @}
AnnaBridge	156:ff21514d8981	2445	*/
AnnaBridge	156:ff21514d8981	2446
AnnaBridge	156:ff21514d8981	2447	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	156:ff21514d8981	2448	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	156:ff21514d8981	2449	* @{
AnnaBridge	156:ff21514d8981	2450	*/
AnnaBridge	156:ff21514d8981	2451
AnnaBridge	156:ff21514d8981	2452	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	156:ff21514d8981	2453	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	156:ff21514d8981	2454	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	156:ff21514d8981	2455
AnnaBridge	156:ff21514d8981	2456	/**
AnnaBridge	156:ff21514d8981	2457	* @}
AnnaBridge	156:ff21514d8981	2458	*/
AnnaBridge	156:ff21514d8981	2459	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	156:ff21514d8981	2460
AnnaBridge	156:ff21514d8981	2461	/**
AnnaBridge	156:ff21514d8981	2462	* @}
AnnaBridge	156:ff21514d8981	2463	*/
AnnaBridge	156:ff21514d8981	2464
AnnaBridge	156:ff21514d8981	2465	/**
AnnaBridge	156:ff21514d8981	2466	* @}
AnnaBridge	156:ff21514d8981	2467	*/
AnnaBridge	156:ff21514d8981	2468
AnnaBridge	156:ff21514d8981	2469	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	156:ff21514d8981	2470
AnnaBridge	156:ff21514d8981	2471	/**
AnnaBridge	156:ff21514d8981	2472	* @}
AnnaBridge	156:ff21514d8981	2473	*/
AnnaBridge	156:ff21514d8981	2474
AnnaBridge	156:ff21514d8981	2475	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	2476	}
AnnaBridge	156:ff21514d8981	2477	#endif
AnnaBridge	156:ff21514d8981	2478
AnnaBridge	156:ff21514d8981	2479	#endif /* __STM32L4xx_LL_DMA_H */
AnnaBridge	156:ff21514d8981	2480
AnnaBridge	156:ff21514d8981	2481	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/