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TARGET_EFM32ZG_STK3200/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Child:
159:7130f322cb7e
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file em_cmu.h
AnnaBridge 156:ff21514d8981 3 * @brief Clock management unit (CMU) API
AnnaBridge 156:ff21514d8981 4 * @version 5.1.2
AnnaBridge 156:ff21514d8981 5 *******************************************************************************
AnnaBridge 156:ff21514d8981 6 * @section License
AnnaBridge 156:ff21514d8981 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 8 *******************************************************************************
AnnaBridge 156:ff21514d8981 9 *
AnnaBridge 156:ff21514d8981 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 12 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 13 *
AnnaBridge 156:ff21514d8981 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 15 * claim that you wrote the original software.
AnnaBridge 156:ff21514d8981 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 17 * misrepresented as being the original software.
AnnaBridge 156:ff21514d8981 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
AnnaBridge 156:ff21514d8981 21 * obligation to support this Software. Silicon Labs is providing the
AnnaBridge 156:ff21514d8981 22 * Software "AS IS", with no express or implied warranties of any kind,
AnnaBridge 156:ff21514d8981 23 * including, but not limited to, any implied warranties of merchantability
AnnaBridge 156:ff21514d8981 24 * or fitness for any particular purpose or warranties against infringement
AnnaBridge 156:ff21514d8981 25 * of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * Silicon Labs will not be liable for any consequential, incidental, or
AnnaBridge 156:ff21514d8981 28 * special damages, or any other relief, or for any claim by any third party,
AnnaBridge 156:ff21514d8981 29 * arising from your use of this Software.
AnnaBridge 156:ff21514d8981 30 *
AnnaBridge 156:ff21514d8981 31 ******************************************************************************/
AnnaBridge 156:ff21514d8981 32 #ifndef EM_CMU_H
AnnaBridge 156:ff21514d8981 33 #define EM_CMU_H
AnnaBridge 156:ff21514d8981 34
AnnaBridge 156:ff21514d8981 35 #include "em_device.h"
AnnaBridge 156:ff21514d8981 36 #if defined( CMU_PRESENT )
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 #include <stdbool.h>
AnnaBridge 156:ff21514d8981 39 #include "em_assert.h"
AnnaBridge 156:ff21514d8981 40 #include "em_bus.h"
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 47 * @addtogroup emlib
AnnaBridge 156:ff21514d8981 48 * @{
AnnaBridge 156:ff21514d8981 49 ******************************************************************************/
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 52 * @addtogroup CMU
AnnaBridge 156:ff21514d8981 53 * @{
AnnaBridge 156:ff21514d8981 54 ******************************************************************************/
AnnaBridge 156:ff21514d8981 55
AnnaBridge 156:ff21514d8981 56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 57
AnnaBridge 156:ff21514d8981 58 /* Select register id's, for internal use. */
AnnaBridge 156:ff21514d8981 59 #define CMU_NOSEL_REG 0
AnnaBridge 156:ff21514d8981 60 #define CMU_HFCLKSEL_REG 1
AnnaBridge 156:ff21514d8981 61 #define CMU_LFACLKSEL_REG 2
AnnaBridge 156:ff21514d8981 62 #define CMU_LFBCLKSEL_REG 3
AnnaBridge 156:ff21514d8981 63 #define CMU_LFCCLKSEL_REG 4
AnnaBridge 156:ff21514d8981 64 #define CMU_LFECLKSEL_REG 5
AnnaBridge 156:ff21514d8981 65 #define CMU_DBGCLKSEL_REG 6
AnnaBridge 156:ff21514d8981 66 #define CMU_USBCCLKSEL_REG 7
AnnaBridge 156:ff21514d8981 67
AnnaBridge 156:ff21514d8981 68 #define CMU_SEL_REG_POS 0
AnnaBridge 156:ff21514d8981 69 #define CMU_SEL_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 70
AnnaBridge 156:ff21514d8981 71 /* Divisor/prescaler register id's, for internal use. */
AnnaBridge 156:ff21514d8981 72 #define CMU_NODIV_REG 0
AnnaBridge 156:ff21514d8981 73 #define CMU_NOPRESC_REG 0
AnnaBridge 156:ff21514d8981 74 #define CMU_HFPRESC_REG 1
AnnaBridge 156:ff21514d8981 75 #define CMU_HFCLKDIV_REG 1
AnnaBridge 156:ff21514d8981 76 #define CMU_HFEXPPRESC_REG 2
AnnaBridge 156:ff21514d8981 77 #define CMU_HFCLKLEPRESC_REG 3
AnnaBridge 156:ff21514d8981 78 #define CMU_HFPERPRESC_REG 4
AnnaBridge 156:ff21514d8981 79 #define CMU_HFPERCLKDIV_REG 4
AnnaBridge 156:ff21514d8981 80 #define CMU_HFCOREPRESC_REG 5
AnnaBridge 156:ff21514d8981 81 #define CMU_HFCORECLKDIV_REG 5
AnnaBridge 156:ff21514d8981 82 #define CMU_LFAPRESC0_REG 6
AnnaBridge 156:ff21514d8981 83 #define CMU_LFBPRESC0_REG 7
AnnaBridge 156:ff21514d8981 84 #define CMU_LFEPRESC0_REG 8
AnnaBridge 156:ff21514d8981 85
AnnaBridge 156:ff21514d8981 86 #define CMU_PRESC_REG_POS 4
AnnaBridge 156:ff21514d8981 87 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
AnnaBridge 156:ff21514d8981 88 #define CMU_PRESC_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 89 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 /* Enable register id's, for internal use. */
AnnaBridge 156:ff21514d8981 92 #define CMU_NO_EN_REG 0
AnnaBridge 156:ff21514d8981 93 #define CMU_CTRL_EN_REG 1
AnnaBridge 156:ff21514d8981 94 #define CMU_HFPERCLKDIV_EN_REG 1
AnnaBridge 156:ff21514d8981 95 #define CMU_HFPERCLKEN0_EN_REG 2
AnnaBridge 156:ff21514d8981 96 #define CMU_HFCORECLKEN0_EN_REG 3
AnnaBridge 156:ff21514d8981 97 #define CMU_HFBUSCLKEN0_EN_REG 5
AnnaBridge 156:ff21514d8981 98 #define CMU_LFACLKEN0_EN_REG 6
AnnaBridge 156:ff21514d8981 99 #define CMU_LFBCLKEN0_EN_REG 7
AnnaBridge 156:ff21514d8981 100 #define CMU_LFCCLKEN0_EN_REG 8
AnnaBridge 156:ff21514d8981 101 #define CMU_LFECLKEN0_EN_REG 9
AnnaBridge 156:ff21514d8981 102 #define CMU_PCNT_EN_REG 10
AnnaBridge 156:ff21514d8981 103
AnnaBridge 156:ff21514d8981 104 #define CMU_EN_REG_POS 8
AnnaBridge 156:ff21514d8981 105 #define CMU_EN_REG_MASK 0xf
AnnaBridge 156:ff21514d8981 106
AnnaBridge 156:ff21514d8981 107 /* Enable register bit positions, for internal use. */
AnnaBridge 156:ff21514d8981 108 #define CMU_EN_BIT_POS 12
AnnaBridge 156:ff21514d8981 109 #define CMU_EN_BIT_MASK 0x1f
AnnaBridge 156:ff21514d8981 110
AnnaBridge 156:ff21514d8981 111 /* Clock branch bitfield positions, for internal use. */
AnnaBridge 156:ff21514d8981 112 #define CMU_HF_CLK_BRANCH 0
AnnaBridge 156:ff21514d8981 113 #define CMU_HFCORE_CLK_BRANCH 1
AnnaBridge 156:ff21514d8981 114 #define CMU_HFPER_CLK_BRANCH 2
AnnaBridge 156:ff21514d8981 115 #define CMU_HFBUS_CLK_BRANCH 4
AnnaBridge 156:ff21514d8981 116 #define CMU_HFEXP_CLK_BRANCH 5
AnnaBridge 156:ff21514d8981 117 #define CMU_DBG_CLK_BRANCH 6
AnnaBridge 156:ff21514d8981 118 #define CMU_AUX_CLK_BRANCH 7
AnnaBridge 156:ff21514d8981 119 #define CMU_RTC_CLK_BRANCH 8
AnnaBridge 156:ff21514d8981 120 #define CMU_RTCC_CLK_BRANCH 9
AnnaBridge 156:ff21514d8981 121 #define CMU_LETIMER0_CLK_BRANCH 10
AnnaBridge 156:ff21514d8981 122 #define CMU_LEUART0_CLK_BRANCH 11
AnnaBridge 156:ff21514d8981 123 #define CMU_LEUART1_CLK_BRANCH 12
AnnaBridge 156:ff21514d8981 124 #define CMU_LFA_CLK_BRANCH 13
AnnaBridge 156:ff21514d8981 125 #define CMU_LFB_CLK_BRANCH 14
AnnaBridge 156:ff21514d8981 126 #define CMU_LFC_CLK_BRANCH 15
AnnaBridge 156:ff21514d8981 127 #define CMU_LFE_CLK_BRANCH 16
AnnaBridge 156:ff21514d8981 128 #define CMU_USBC_CLK_BRANCH 17
AnnaBridge 156:ff21514d8981 129 #define CMU_USBLE_CLK_BRANCH 18
AnnaBridge 156:ff21514d8981 130 #define CMU_LCDPRE_CLK_BRANCH 19
AnnaBridge 156:ff21514d8981 131 #define CMU_LCD_CLK_BRANCH 20
AnnaBridge 156:ff21514d8981 132 #define CMU_LESENSE_CLK_BRANCH 21
AnnaBridge 156:ff21514d8981 133 #define CMU_CSEN_LF_CLK_BRANCH 22
AnnaBridge 156:ff21514d8981 134
AnnaBridge 156:ff21514d8981 135 #define CMU_CLK_BRANCH_POS 17
AnnaBridge 156:ff21514d8981 136 #define CMU_CLK_BRANCH_MASK 0x1f
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 #if defined( _EMU_CMD_EM01VSCALE0_MASK )
AnnaBridge 156:ff21514d8981 139 /* Max clock frequency for VSCALE voltages */
AnnaBridge 156:ff21514d8981 140 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
AnnaBridge 156:ff21514d8981 141 #endif
AnnaBridge 156:ff21514d8981 142 /** @endcond */
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144 /*******************************************************************************
AnnaBridge 156:ff21514d8981 145 ******************************** ENUMS ************************************
AnnaBridge 156:ff21514d8981 146 ******************************************************************************/
AnnaBridge 156:ff21514d8981 147
AnnaBridge 156:ff21514d8981 148 /** Clock divisors. These values are valid for prescalers. */
AnnaBridge 156:ff21514d8981 149 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
AnnaBridge 156:ff21514d8981 150 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
AnnaBridge 156:ff21514d8981 151 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
AnnaBridge 156:ff21514d8981 152 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
AnnaBridge 156:ff21514d8981 153 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
AnnaBridge 156:ff21514d8981 154 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
AnnaBridge 156:ff21514d8981 155 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
AnnaBridge 156:ff21514d8981 156 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
AnnaBridge 156:ff21514d8981 157 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
AnnaBridge 156:ff21514d8981 158 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
AnnaBridge 156:ff21514d8981 159 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
AnnaBridge 156:ff21514d8981 160 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
AnnaBridge 156:ff21514d8981 161 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
AnnaBridge 156:ff21514d8981 162 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
AnnaBridge 156:ff21514d8981 163 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
AnnaBridge 156:ff21514d8981 164 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
AnnaBridge 156:ff21514d8981 165
AnnaBridge 156:ff21514d8981 166 /** Clock divider configuration */
AnnaBridge 156:ff21514d8981 167 typedef uint32_t CMU_ClkDiv_TypeDef;
AnnaBridge 156:ff21514d8981 168
AnnaBridge 156:ff21514d8981 169 #if defined( _SILICON_LABS_32B_SERIES_1 )
AnnaBridge 156:ff21514d8981 170 /** Clockprescaler configuration */
AnnaBridge 156:ff21514d8981 171 typedef uint32_t CMU_ClkPresc_TypeDef;
AnnaBridge 156:ff21514d8981 172 #endif
AnnaBridge 156:ff21514d8981 173
AnnaBridge 156:ff21514d8981 174 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
AnnaBridge 156:ff21514d8981 175 /** High frequency system RCO bands */
AnnaBridge 156:ff21514d8981 176 typedef enum
AnnaBridge 156:ff21514d8981 177 {
AnnaBridge 156:ff21514d8981 178 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1MHz HFRCO band */
AnnaBridge 156:ff21514d8981 179 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7MHz HFRCO band */
AnnaBridge 156:ff21514d8981 180 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11MHz HFRCO band */
AnnaBridge 156:ff21514d8981 181 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14MHz HFRCO band */
AnnaBridge 156:ff21514d8981 182 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21MHz HFRCO band */
AnnaBridge 156:ff21514d8981 183 #if defined( CMU_HFRCOCTRL_BAND_28MHZ )
AnnaBridge 156:ff21514d8981 184 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28MHz HFRCO band */
AnnaBridge 156:ff21514d8981 185 #endif
AnnaBridge 156:ff21514d8981 186 } CMU_HFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 187 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
AnnaBridge 156:ff21514d8981 188
AnnaBridge 156:ff21514d8981 189 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
AnnaBridge 156:ff21514d8981 190 /** AUX High frequency RCO bands */
AnnaBridge 156:ff21514d8981 191 typedef enum
AnnaBridge 156:ff21514d8981 192 {
AnnaBridge 156:ff21514d8981 193 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 194 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 195 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */
AnnaBridge 156:ff21514d8981 196 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14MHz RC band */
AnnaBridge 156:ff21514d8981 197 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21MHz RC band */
AnnaBridge 156:ff21514d8981 198 #if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
AnnaBridge 156:ff21514d8981 199 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28MHz RC band */
AnnaBridge 156:ff21514d8981 200 #endif
AnnaBridge 156:ff21514d8981 201 } CMU_AUXHFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 202 #endif
AnnaBridge 156:ff21514d8981 203
AnnaBridge 156:ff21514d8981 204 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
AnnaBridge 156:ff21514d8981 205 /** USB High frequency RC bands. */
AnnaBridge 156:ff21514d8981 206 typedef enum
AnnaBridge 156:ff21514d8981 207 {
AnnaBridge 156:ff21514d8981 208 /** 24MHz RC band. */
AnnaBridge 156:ff21514d8981 209 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
AnnaBridge 156:ff21514d8981 210 /** 48MHz RC band. */
AnnaBridge 156:ff21514d8981 211 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
AnnaBridge 156:ff21514d8981 212 } CMU_USHFRCOBand_TypeDef;
AnnaBridge 156:ff21514d8981 213 #endif
AnnaBridge 156:ff21514d8981 214
AnnaBridge 156:ff21514d8981 215 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 216 /** High frequency system RCO bands */
AnnaBridge 156:ff21514d8981 217 typedef enum
AnnaBridge 156:ff21514d8981 218 {
AnnaBridge 156:ff21514d8981 219 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 220 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
AnnaBridge 156:ff21514d8981 221 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
AnnaBridge 156:ff21514d8981 222 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 223 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
AnnaBridge 156:ff21514d8981 224 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
AnnaBridge 156:ff21514d8981 225 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
AnnaBridge 156:ff21514d8981 226 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
AnnaBridge 156:ff21514d8981 227 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
AnnaBridge 156:ff21514d8981 228 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
AnnaBridge 156:ff21514d8981 229 cmuHFRCOFreq_UserDefined = 0,
AnnaBridge 156:ff21514d8981 230 } CMU_HFRCOFreq_TypeDef;
AnnaBridge 156:ff21514d8981 231 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
AnnaBridge 156:ff21514d8981 232 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
AnnaBridge 156:ff21514d8981 233 #endif
AnnaBridge 156:ff21514d8981 234
AnnaBridge 156:ff21514d8981 235 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 236 /** AUX High frequency RCO bands */
AnnaBridge 156:ff21514d8981 237 typedef enum
AnnaBridge 156:ff21514d8981 238 {
AnnaBridge 156:ff21514d8981 239 cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
AnnaBridge 156:ff21514d8981 240 cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
AnnaBridge 156:ff21514d8981 241 cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
AnnaBridge 156:ff21514d8981 242 cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
AnnaBridge 156:ff21514d8981 243 cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
AnnaBridge 156:ff21514d8981 244 cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
AnnaBridge 156:ff21514d8981 245 cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
AnnaBridge 156:ff21514d8981 246 cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
AnnaBridge 156:ff21514d8981 247 cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
AnnaBridge 156:ff21514d8981 248 cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
AnnaBridge 156:ff21514d8981 249 cmuAUXHFRCOFreq_UserDefined = 0,
AnnaBridge 156:ff21514d8981 250 } CMU_AUXHFRCOFreq_TypeDef;
AnnaBridge 156:ff21514d8981 251 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
AnnaBridge 156:ff21514d8981 252 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
AnnaBridge 156:ff21514d8981 253 #endif
AnnaBridge 156:ff21514d8981 254
AnnaBridge 156:ff21514d8981 255
AnnaBridge 156:ff21514d8981 256 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
AnnaBridge 156:ff21514d8981 257 typedef enum
AnnaBridge 156:ff21514d8981 258 {
AnnaBridge 156:ff21514d8981 259 /*******************/
AnnaBridge 156:ff21514d8981 260 /* HF clock branch */
AnnaBridge 156:ff21514d8981 261 /*******************/
AnnaBridge 156:ff21514d8981 262
AnnaBridge 156:ff21514d8981 263 /** High frequency clock */
AnnaBridge 156:ff21514d8981 264 #if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
AnnaBridge 156:ff21514d8981 265 || defined( _CMU_HFPRESC_MASK )
AnnaBridge 156:ff21514d8981 266 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 267 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 268 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 269 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 270 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 271 #else
AnnaBridge 156:ff21514d8981 272 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 273 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 274 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 275 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 276 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 277 #endif
AnnaBridge 156:ff21514d8981 278
AnnaBridge 156:ff21514d8981 279 /** Debug clock */
AnnaBridge 156:ff21514d8981 280 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 281 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 282 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 283 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 284 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 285
AnnaBridge 156:ff21514d8981 286 /** AUX clock */
AnnaBridge 156:ff21514d8981 287 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 288 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 289 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 290 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 291 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 292
AnnaBridge 156:ff21514d8981 293 #if defined( _CMU_HFEXPPRESC_MASK )
AnnaBridge 156:ff21514d8981 294 /**********************/
AnnaBridge 156:ff21514d8981 295 /* HF export sub-branch */
AnnaBridge 156:ff21514d8981 296 /**********************/
AnnaBridge 156:ff21514d8981 297
AnnaBridge 156:ff21514d8981 298 /** Export clock */
AnnaBridge 156:ff21514d8981 299 cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 300 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 301 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 302 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 303 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 304 #endif
AnnaBridge 156:ff21514d8981 305
AnnaBridge 156:ff21514d8981 306 #if defined( _CMU_HFBUSCLKEN0_MASK )
AnnaBridge 156:ff21514d8981 307 /**********************************/
AnnaBridge 156:ff21514d8981 308 /* HF bus clock sub-branch */
AnnaBridge 156:ff21514d8981 309 /**********************************/
AnnaBridge 156:ff21514d8981 310
AnnaBridge 156:ff21514d8981 311 /** High frequency bus clock. */
AnnaBridge 156:ff21514d8981 312 cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 313 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 314 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 315 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 316 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 317
AnnaBridge 156:ff21514d8981 318 #if defined( CMU_HFBUSCLKEN0_CRYPTO )
AnnaBridge 156:ff21514d8981 319 /** Cryptography accelerator clock. */
AnnaBridge 156:ff21514d8981 320 cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 321 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 322 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 323 | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 324 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 325 #endif
AnnaBridge 156:ff21514d8981 326
AnnaBridge 156:ff21514d8981 327 #if defined( CMU_HFBUSCLKEN0_CRYPTO0 )
AnnaBridge 156:ff21514d8981 328 /** Cryptography accelerator 0 clock. */
AnnaBridge 156:ff21514d8981 329 cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 330 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 331 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 332 | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 333 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 334 #endif
AnnaBridge 156:ff21514d8981 335
AnnaBridge 156:ff21514d8981 336 #if defined( CMU_HFBUSCLKEN0_CRYPTO1 )
AnnaBridge 156:ff21514d8981 337 /** Cryptography accelerator 1 clock. */
AnnaBridge 156:ff21514d8981 338 cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 339 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 340 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 341 | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 342 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 343 #endif
AnnaBridge 156:ff21514d8981 344
AnnaBridge 156:ff21514d8981 345 #if defined( CMU_HFBUSCLKEN0_LDMA )
AnnaBridge 156:ff21514d8981 346 /** Direct memory access controller clock. */
AnnaBridge 156:ff21514d8981 347 cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 348 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 349 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 350 | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 351 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 352 #endif
AnnaBridge 156:ff21514d8981 353
AnnaBridge 156:ff21514d8981 354 #if defined( CMU_HFBUSCLKEN0_GPCRC )
AnnaBridge 156:ff21514d8981 355 /** General purpose cyclic redundancy checksum clock. */
AnnaBridge 156:ff21514d8981 356 cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 357 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 358 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 359 | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 360 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 361 #endif
AnnaBridge 156:ff21514d8981 362
AnnaBridge 156:ff21514d8981 363 #if defined( CMU_HFBUSCLKEN0_GPIO )
AnnaBridge 156:ff21514d8981 364 /** General purpose input/output clock. */
AnnaBridge 156:ff21514d8981 365 cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 366 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 367 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 368 | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 369 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 370 #endif
AnnaBridge 156:ff21514d8981 371
AnnaBridge 156:ff21514d8981 372 /** Low energy clock divided down from HFBUSCLK. */
AnnaBridge 156:ff21514d8981 373 cmuClock_HFLE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 374 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 375 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 376 | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 377 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 378
AnnaBridge 156:ff21514d8981 379 #if defined( CMU_HFBUSCLKEN0_PRS )
AnnaBridge 156:ff21514d8981 380 /** Peripheral reflex system clock. */
AnnaBridge 156:ff21514d8981 381 cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 382 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 383 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 384 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 385 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 386 #endif
AnnaBridge 156:ff21514d8981 387 #endif
AnnaBridge 156:ff21514d8981 388
AnnaBridge 156:ff21514d8981 389 /**********************************/
AnnaBridge 156:ff21514d8981 390 /* HF peripheral clock sub-branch */
AnnaBridge 156:ff21514d8981 391 /**********************************/
AnnaBridge 156:ff21514d8981 392
AnnaBridge 156:ff21514d8981 393 /** High frequency peripheral clock */
AnnaBridge 156:ff21514d8981 394 #if defined( _CMU_HFPRESC_MASK )
AnnaBridge 156:ff21514d8981 395 cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 396 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 397 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 398 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 399 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 400 #else
AnnaBridge 156:ff21514d8981 401 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 402 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 403 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 404 | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 405 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 406 #endif
AnnaBridge 156:ff21514d8981 407
AnnaBridge 156:ff21514d8981 408 #if defined( CMU_HFPERCLKEN0_USART0 )
AnnaBridge 156:ff21514d8981 409 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 410 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 411 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 412 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 413 | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 414 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 415 #endif
AnnaBridge 156:ff21514d8981 416
AnnaBridge 156:ff21514d8981 417 #if defined( CMU_HFPERCLKEN0_USARTRF0 )
AnnaBridge 156:ff21514d8981 418 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 419 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 420 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 421 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 422 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 423 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 424 #endif
AnnaBridge 156:ff21514d8981 425
AnnaBridge 156:ff21514d8981 426 #if defined( CMU_HFPERCLKEN0_USARTRF1 )
AnnaBridge 156:ff21514d8981 427 /** Universal sync/async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 428 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 429 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 430 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 431 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 432 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 433 #endif
AnnaBridge 156:ff21514d8981 434
AnnaBridge 156:ff21514d8981 435 #if defined( CMU_HFPERCLKEN0_USART1 )
AnnaBridge 156:ff21514d8981 436 /** Universal sync/async receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 437 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 438 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 439 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 440 | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 441 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 442 #endif
AnnaBridge 156:ff21514d8981 443
AnnaBridge 156:ff21514d8981 444 #if defined( CMU_HFPERCLKEN0_USART2 )
AnnaBridge 156:ff21514d8981 445 /** Universal sync/async receiver/transmitter 2 clock. */
AnnaBridge 156:ff21514d8981 446 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 447 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 448 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 449 | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 450 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 451 #endif
AnnaBridge 156:ff21514d8981 452
AnnaBridge 156:ff21514d8981 453 #if defined( CMU_HFPERCLKEN0_USART3 )
AnnaBridge 156:ff21514d8981 454 /** Universal sync/async receiver/transmitter 3 clock. */
AnnaBridge 156:ff21514d8981 455 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 456 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 457 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 458 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 459 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 460 #endif
AnnaBridge 156:ff21514d8981 461
AnnaBridge 156:ff21514d8981 462 #if defined( CMU_HFPERCLKEN0_USART4 )
AnnaBridge 156:ff21514d8981 463 /** Universal sync/async receiver/transmitter 4 clock. */
AnnaBridge 156:ff21514d8981 464 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 465 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 466 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 467 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 468 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 469 #endif
AnnaBridge 156:ff21514d8981 470
AnnaBridge 156:ff21514d8981 471 #if defined( CMU_HFPERCLKEN0_USART5 )
AnnaBridge 156:ff21514d8981 472 /** Universal sync/async receiver/transmitter 5 clock. */
AnnaBridge 156:ff21514d8981 473 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 474 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 475 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 476 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 477 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 478 #endif
AnnaBridge 156:ff21514d8981 479
AnnaBridge 156:ff21514d8981 480
AnnaBridge 156:ff21514d8981 481 #if defined( CMU_HFPERCLKEN0_UART0 )
AnnaBridge 156:ff21514d8981 482 /** Universal async receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 483 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 484 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 485 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 486 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 487 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 488 #endif
AnnaBridge 156:ff21514d8981 489
AnnaBridge 156:ff21514d8981 490 #if defined( CMU_HFPERCLKEN0_UART1 )
AnnaBridge 156:ff21514d8981 491 /** Universal async receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 492 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 493 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 494 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 495 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 496 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 497 #endif
AnnaBridge 156:ff21514d8981 498
AnnaBridge 156:ff21514d8981 499 #if defined( CMU_HFPERCLKEN0_TIMER0 )
AnnaBridge 156:ff21514d8981 500 /** Timer 0 clock. */
AnnaBridge 156:ff21514d8981 501 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 502 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 503 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 504 | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 505 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 506 #endif
AnnaBridge 156:ff21514d8981 507
AnnaBridge 156:ff21514d8981 508 #if defined( CMU_HFPERCLKEN0_TIMER1 )
AnnaBridge 156:ff21514d8981 509 /** Timer 1 clock. */
AnnaBridge 156:ff21514d8981 510 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 511 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 512 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 513 | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 514 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 515 #endif
AnnaBridge 156:ff21514d8981 516
AnnaBridge 156:ff21514d8981 517 #if defined( CMU_HFPERCLKEN0_TIMER2 )
AnnaBridge 156:ff21514d8981 518 /** Timer 2 clock. */
AnnaBridge 156:ff21514d8981 519 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 520 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 521 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 522 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 523 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 524 #endif
AnnaBridge 156:ff21514d8981 525
AnnaBridge 156:ff21514d8981 526 #if defined( CMU_HFPERCLKEN0_TIMER3 )
AnnaBridge 156:ff21514d8981 527 /** Timer 3 clock. */
AnnaBridge 156:ff21514d8981 528 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 529 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 530 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 531 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 532 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 533 #endif
AnnaBridge 156:ff21514d8981 534
AnnaBridge 156:ff21514d8981 535 #if defined( CMU_HFPERCLKEN0_WTIMER0 )
AnnaBridge 156:ff21514d8981 536 /** Wide Timer 0 clock. */
AnnaBridge 156:ff21514d8981 537 cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 538 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 539 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 540 | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 541 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 542 #endif
AnnaBridge 156:ff21514d8981 543
AnnaBridge 156:ff21514d8981 544 #if defined( CMU_HFPERCLKEN0_WTIMER1 )
AnnaBridge 156:ff21514d8981 545 /** Wide Timer 1 clock. */
AnnaBridge 156:ff21514d8981 546 cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 547 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 548 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 549 | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 550 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 551 #endif
AnnaBridge 156:ff21514d8981 552
AnnaBridge 156:ff21514d8981 553 #if defined( CMU_HFPERCLKEN0_CRYOTIMER )
AnnaBridge 156:ff21514d8981 554 /** CRYOtimer clock. */
AnnaBridge 156:ff21514d8981 555 cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 556 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 557 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 558 | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 559 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 560 #endif
AnnaBridge 156:ff21514d8981 561
AnnaBridge 156:ff21514d8981 562 #if defined( CMU_HFPERCLKEN0_ACMP0 )
AnnaBridge 156:ff21514d8981 563 /** Analog comparator 0 clock. */
AnnaBridge 156:ff21514d8981 564 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 565 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 566 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 567 | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 568 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 569 #endif
AnnaBridge 156:ff21514d8981 570
AnnaBridge 156:ff21514d8981 571 #if defined( CMU_HFPERCLKEN0_ACMP1 )
AnnaBridge 156:ff21514d8981 572 /** Analog comparator 1 clock. */
AnnaBridge 156:ff21514d8981 573 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 574 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 575 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 576 | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 577 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 578 #endif
AnnaBridge 156:ff21514d8981 579
AnnaBridge 156:ff21514d8981 580 #if defined( CMU_HFPERCLKEN0_PRS )
AnnaBridge 156:ff21514d8981 581 /** Peripheral reflex system clock. */
AnnaBridge 156:ff21514d8981 582 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 583 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 584 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 585 | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 586 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 587 #endif
AnnaBridge 156:ff21514d8981 588
AnnaBridge 156:ff21514d8981 589 #if defined( CMU_HFPERCLKEN0_DAC0 )
AnnaBridge 156:ff21514d8981 590 /** Digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 591 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 592 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 593 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 594 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 595 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 596 #endif
AnnaBridge 156:ff21514d8981 597
AnnaBridge 156:ff21514d8981 598 #if defined( CMU_HFPERCLKEN0_VDAC0 )
AnnaBridge 156:ff21514d8981 599 /** Voltage digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 600 cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 601 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 602 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 603 | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 604 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 605 #endif
AnnaBridge 156:ff21514d8981 606
AnnaBridge 156:ff21514d8981 607 #if defined( CMU_HFPERCLKEN0_IDAC0 )
AnnaBridge 156:ff21514d8981 608 /** Current digital to analog converter 0 clock. */
AnnaBridge 156:ff21514d8981 609 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 610 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 611 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 612 | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 613 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 614 #endif
AnnaBridge 156:ff21514d8981 615
AnnaBridge 156:ff21514d8981 616 #if defined( CMU_HFPERCLKEN0_GPIO )
AnnaBridge 156:ff21514d8981 617 /** General purpose input/output clock. */
AnnaBridge 156:ff21514d8981 618 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 619 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 620 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 621 | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 622 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 623 #endif
AnnaBridge 156:ff21514d8981 624
AnnaBridge 156:ff21514d8981 625 #if defined( CMU_HFPERCLKEN0_VCMP )
AnnaBridge 156:ff21514d8981 626 /** Voltage comparator clock. */
AnnaBridge 156:ff21514d8981 627 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 628 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 629 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 630 | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 631 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 632 #endif
AnnaBridge 156:ff21514d8981 633
AnnaBridge 156:ff21514d8981 634 #if defined( CMU_HFPERCLKEN0_ADC0 )
AnnaBridge 156:ff21514d8981 635 /** Analog to digital converter 0 clock. */
AnnaBridge 156:ff21514d8981 636 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 637 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 638 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 639 | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 640 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 641 #endif
AnnaBridge 156:ff21514d8981 642
AnnaBridge 156:ff21514d8981 643 #if defined( CMU_HFPERCLKEN0_I2C0 )
AnnaBridge 156:ff21514d8981 644 /** I2C 0 clock. */
AnnaBridge 156:ff21514d8981 645 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 646 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 647 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 648 | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 649 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 650 #endif
AnnaBridge 156:ff21514d8981 651
AnnaBridge 156:ff21514d8981 652 #if defined( CMU_HFPERCLKEN0_I2C1 )
AnnaBridge 156:ff21514d8981 653 /** I2C 1 clock. */
AnnaBridge 156:ff21514d8981 654 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 655 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 656 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 657 | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 658 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 659 #endif
AnnaBridge 156:ff21514d8981 660
AnnaBridge 156:ff21514d8981 661 #if defined( CMU_HFPERCLKEN0_I2C2 )
AnnaBridge 156:ff21514d8981 662 /** I2C 2 clock. */
AnnaBridge 156:ff21514d8981 663 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 664 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 665 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 666 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 667 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 668 #endif
AnnaBridge 156:ff21514d8981 669
AnnaBridge 156:ff21514d8981 670 #if defined( CMU_HFPERCLKEN0_CSEN )
AnnaBridge 156:ff21514d8981 671 /** Capacitive Sense HF clock */
AnnaBridge 156:ff21514d8981 672 cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 673 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 674 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 675 | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 676 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 677 #endif
AnnaBridge 156:ff21514d8981 678
AnnaBridge 156:ff21514d8981 679 #if defined( CMU_HFPERCLKEN0_TRNG0 )
AnnaBridge 156:ff21514d8981 680 /** True random number generator clock */
AnnaBridge 156:ff21514d8981 681 cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 682 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 683 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 684 | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 685 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 686 #endif
AnnaBridge 156:ff21514d8981 687
AnnaBridge 156:ff21514d8981 688 /**********************/
AnnaBridge 156:ff21514d8981 689 /* HF core sub-branch */
AnnaBridge 156:ff21514d8981 690 /**********************/
AnnaBridge 156:ff21514d8981 691
AnnaBridge 156:ff21514d8981 692 /** Core clock */
AnnaBridge 156:ff21514d8981 693 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 694 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 695 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 696 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 697 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 698
AnnaBridge 156:ff21514d8981 699 #if defined( CMU_HFCORECLKEN0_AES )
AnnaBridge 156:ff21514d8981 700 /** Advanced encryption standard accelerator clock. */
AnnaBridge 156:ff21514d8981 701 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 702 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 703 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 704 | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 705 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 706 #endif
AnnaBridge 156:ff21514d8981 707
AnnaBridge 156:ff21514d8981 708 #if defined( CMU_HFCORECLKEN0_DMA )
AnnaBridge 156:ff21514d8981 709 /** Direct memory access controller clock. */
AnnaBridge 156:ff21514d8981 710 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 711 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 712 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 713 | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 714 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 715 #endif
AnnaBridge 156:ff21514d8981 716
AnnaBridge 156:ff21514d8981 717 #if defined( CMU_HFCORECLKEN0_LE )
AnnaBridge 156:ff21514d8981 718 /** Low energy clock divided down from HFCORECLK. */
AnnaBridge 156:ff21514d8981 719 cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 720 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 721 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 722 | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 723 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 724 #endif
AnnaBridge 156:ff21514d8981 725
AnnaBridge 156:ff21514d8981 726 #if defined( CMU_HFCORECLKEN0_EBI )
AnnaBridge 156:ff21514d8981 727 /** External bus interface clock. */
AnnaBridge 156:ff21514d8981 728 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 729 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 730 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 731 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 732 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 733 #endif
AnnaBridge 156:ff21514d8981 734
AnnaBridge 156:ff21514d8981 735 #if defined( CMU_HFCORECLKEN0_USBC )
AnnaBridge 156:ff21514d8981 736 /** USB Core clock. */
AnnaBridge 156:ff21514d8981 737 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 738 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 739 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 740 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 741 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 742
AnnaBridge 156:ff21514d8981 743 #endif
AnnaBridge 156:ff21514d8981 744
AnnaBridge 156:ff21514d8981 745 #if defined( CMU_HFCORECLKEN0_USB )
AnnaBridge 156:ff21514d8981 746 /** USB clock. */
AnnaBridge 156:ff21514d8981 747 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 748 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 749 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 750 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 751 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 752 #endif
AnnaBridge 156:ff21514d8981 753
AnnaBridge 156:ff21514d8981 754 /***************/
AnnaBridge 156:ff21514d8981 755 /* LF A branch */
AnnaBridge 156:ff21514d8981 756 /***************/
AnnaBridge 156:ff21514d8981 757
AnnaBridge 156:ff21514d8981 758 /** Low frequency A clock */
AnnaBridge 156:ff21514d8981 759 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 760 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 761 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 762 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 763 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 764
AnnaBridge 156:ff21514d8981 765 #if defined( CMU_LFACLKEN0_RTC )
AnnaBridge 156:ff21514d8981 766 /** Real time counter clock. */
AnnaBridge 156:ff21514d8981 767 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 768 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 769 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 770 | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 771 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 772 #endif
AnnaBridge 156:ff21514d8981 773
AnnaBridge 156:ff21514d8981 774 #if defined( CMU_LFACLKEN0_LETIMER0 )
AnnaBridge 156:ff21514d8981 775 /** Low energy timer 0 clock. */
AnnaBridge 156:ff21514d8981 776 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 777 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 778 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 779 | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 780 | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 781 #endif
AnnaBridge 156:ff21514d8981 782
AnnaBridge 156:ff21514d8981 783 #if defined( CMU_LFACLKEN0_LCD )
AnnaBridge 156:ff21514d8981 784 /** Liquid crystal display, pre FDIV clock. */
AnnaBridge 156:ff21514d8981 785 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 786 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 787 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 788 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 789 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 790
AnnaBridge 156:ff21514d8981 791 /** Liquid crystal display clock. Please notice that FDIV prescaler
AnnaBridge 156:ff21514d8981 792 * must be set by special API. */
AnnaBridge 156:ff21514d8981 793 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 794 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 795 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 796 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 797 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 798 #endif
AnnaBridge 156:ff21514d8981 799
AnnaBridge 156:ff21514d8981 800 #if defined( CMU_PCNTCTRL_PCNT0CLKEN )
AnnaBridge 156:ff21514d8981 801 /** Pulse counter 0 clock. */
AnnaBridge 156:ff21514d8981 802 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 803 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 804 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 805 | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 806 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 807 #endif
AnnaBridge 156:ff21514d8981 808
AnnaBridge 156:ff21514d8981 809 #if defined( CMU_PCNTCTRL_PCNT1CLKEN )
AnnaBridge 156:ff21514d8981 810 /** Pulse counter 1 clock. */
AnnaBridge 156:ff21514d8981 811 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 812 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 813 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 814 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 815 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 816 #endif
AnnaBridge 156:ff21514d8981 817
AnnaBridge 156:ff21514d8981 818 #if defined( CMU_PCNTCTRL_PCNT2CLKEN )
AnnaBridge 156:ff21514d8981 819 /** Pulse counter 2 clock. */
AnnaBridge 156:ff21514d8981 820 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 821 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 822 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 823 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 824 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 825 #endif
AnnaBridge 156:ff21514d8981 826 #if defined( CMU_LFACLKEN0_LESENSE )
AnnaBridge 156:ff21514d8981 827 /** LESENSE clock. */
AnnaBridge 156:ff21514d8981 828 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 829 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 830 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 831 | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 832 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 833 #endif
AnnaBridge 156:ff21514d8981 834
AnnaBridge 156:ff21514d8981 835 /***************/
AnnaBridge 156:ff21514d8981 836 /* LF B branch */
AnnaBridge 156:ff21514d8981 837 /***************/
AnnaBridge 156:ff21514d8981 838
AnnaBridge 156:ff21514d8981 839 /** Low frequency B clock */
AnnaBridge 156:ff21514d8981 840 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 841 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 842 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 843 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 844 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 845
AnnaBridge 156:ff21514d8981 846 #if defined( CMU_LFBCLKEN0_LEUART0 )
AnnaBridge 156:ff21514d8981 847 /** Low energy universal asynchronous receiver/transmitter 0 clock. */
AnnaBridge 156:ff21514d8981 848 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 849 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 850 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 851 | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 852 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 853 #endif
AnnaBridge 156:ff21514d8981 854
AnnaBridge 156:ff21514d8981 855 #if defined( CMU_LFBCLKEN0_CSEN )
AnnaBridge 156:ff21514d8981 856 /** Capacitive Sense LF clock. */
AnnaBridge 156:ff21514d8981 857 cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 858 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 859 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 860 | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 861 | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 862 #endif
AnnaBridge 156:ff21514d8981 863
AnnaBridge 156:ff21514d8981 864 #if defined( CMU_LFBCLKEN0_LEUART1 )
AnnaBridge 156:ff21514d8981 865 /** Low energy universal asynchronous receiver/transmitter 1 clock. */
AnnaBridge 156:ff21514d8981 866 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 867 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 868 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 869 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 870 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 871 #endif
AnnaBridge 156:ff21514d8981 872
AnnaBridge 156:ff21514d8981 873 #if defined( CMU_LFBCLKEN0_SYSTICK )
AnnaBridge 156:ff21514d8981 874 /** Cortex SYSTICK LF clock. */
AnnaBridge 156:ff21514d8981 875 cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 876 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 877 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 878 | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 879 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 880 #endif
AnnaBridge 156:ff21514d8981 881
AnnaBridge 156:ff21514d8981 882 #if defined( _CMU_LFCCLKEN0_MASK )
AnnaBridge 156:ff21514d8981 883 /***************/
AnnaBridge 156:ff21514d8981 884 /* LF C branch */
AnnaBridge 156:ff21514d8981 885 /***************/
AnnaBridge 156:ff21514d8981 886
AnnaBridge 156:ff21514d8981 887 /** Low frequency C clock */
AnnaBridge 156:ff21514d8981 888 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 889 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 890 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 891 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 892 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 893
AnnaBridge 156:ff21514d8981 894 #if defined( CMU_LFCCLKEN0_USBLE )
AnnaBridge 156:ff21514d8981 895 /** USB LE clock. */
AnnaBridge 156:ff21514d8981 896 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
AnnaBridge 156:ff21514d8981 897 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 898 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 899 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 900 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 901 #endif
AnnaBridge 156:ff21514d8981 902 #endif
AnnaBridge 156:ff21514d8981 903
AnnaBridge 156:ff21514d8981 904 #if defined( _CMU_LFECLKEN0_MASK )
AnnaBridge 156:ff21514d8981 905 /***************/
AnnaBridge 156:ff21514d8981 906 /* LF E branch */
AnnaBridge 156:ff21514d8981 907 /***************/
AnnaBridge 156:ff21514d8981 908
AnnaBridge 156:ff21514d8981 909 /** Low frequency A clock */
AnnaBridge 156:ff21514d8981 910 cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 911 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 912 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 913 | (0 << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 914 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 915
AnnaBridge 156:ff21514d8981 916 /** Real time counter and calendar clock. */
AnnaBridge 156:ff21514d8981 917 #if defined ( CMU_LFECLKEN0_RTCC )
AnnaBridge 156:ff21514d8981 918 cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
AnnaBridge 156:ff21514d8981 919 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
AnnaBridge 156:ff21514d8981 920 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
AnnaBridge 156:ff21514d8981 921 | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
AnnaBridge 156:ff21514d8981 922 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
AnnaBridge 156:ff21514d8981 923 #endif
AnnaBridge 156:ff21514d8981 924 #endif
AnnaBridge 156:ff21514d8981 925
AnnaBridge 156:ff21514d8981 926 } CMU_Clock_TypeDef;
AnnaBridge 156:ff21514d8981 927
AnnaBridge 156:ff21514d8981 928 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 929 /* Deprecated CMU_Clock_TypeDef member */
AnnaBridge 156:ff21514d8981 930 #define cmuClock_CORELE cmuClock_HFLE
AnnaBridge 156:ff21514d8981 931 /** @endcond */
AnnaBridge 156:ff21514d8981 932
AnnaBridge 156:ff21514d8981 933
AnnaBridge 156:ff21514d8981 934 /** Oscillator types. */
AnnaBridge 156:ff21514d8981 935 typedef enum
AnnaBridge 156:ff21514d8981 936 {
AnnaBridge 156:ff21514d8981 937 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 938 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 939 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 940 cmuOsc_HFRCO, /**< High frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 941 cmuOsc_AUXHFRCO, /**< Auxiliary high frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 942 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
AnnaBridge 156:ff21514d8981 943 cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */
AnnaBridge 156:ff21514d8981 944 #endif
AnnaBridge 156:ff21514d8981 945 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
AnnaBridge 156:ff21514d8981 946 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 947 #endif
AnnaBridge 156:ff21514d8981 948 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
AnnaBridge 156:ff21514d8981 949 cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */
AnnaBridge 156:ff21514d8981 950 #endif
AnnaBridge 156:ff21514d8981 951 } CMU_Osc_TypeDef;
AnnaBridge 156:ff21514d8981 952
AnnaBridge 156:ff21514d8981 953 /** Oscillator modes. */
AnnaBridge 156:ff21514d8981 954 typedef enum
AnnaBridge 156:ff21514d8981 955 {
AnnaBridge 156:ff21514d8981 956 cmuOscMode_Crystal, /**< Crystal oscillator. */
AnnaBridge 156:ff21514d8981 957 cmuOscMode_AcCoupled, /**< AC coupled buffer. */
AnnaBridge 156:ff21514d8981 958 cmuOscMode_External, /**< External digital clock. */
AnnaBridge 156:ff21514d8981 959 } CMU_OscMode_TypeDef;
AnnaBridge 156:ff21514d8981 960
AnnaBridge 156:ff21514d8981 961 /** Selectable clock sources. */
AnnaBridge 156:ff21514d8981 962 typedef enum
AnnaBridge 156:ff21514d8981 963 {
AnnaBridge 156:ff21514d8981 964 cmuSelect_Error, /**< Usage error. */
AnnaBridge 156:ff21514d8981 965 cmuSelect_Disabled, /**< Clock selector disabled. */
AnnaBridge 156:ff21514d8981 966 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 967 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 968 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
AnnaBridge 156:ff21514d8981 969 cmuSelect_HFRCO, /**< High frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 970 cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */
AnnaBridge 156:ff21514d8981 971 cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */
AnnaBridge 156:ff21514d8981 972 cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
AnnaBridge 156:ff21514d8981 973 Tiny Gecko and for USBC (not used on Gecko) */
AnnaBridge 156:ff21514d8981 974 #if defined( CMU_STATUS_USHFRCOENS )
AnnaBridge 156:ff21514d8981 975 cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */
AnnaBridge 156:ff21514d8981 976 #endif
AnnaBridge 156:ff21514d8981 977 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
AnnaBridge 156:ff21514d8981 978 cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */
AnnaBridge 156:ff21514d8981 979 #endif
AnnaBridge 156:ff21514d8981 980 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
AnnaBridge 156:ff21514d8981 981 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
AnnaBridge 156:ff21514d8981 982 #endif
AnnaBridge 156:ff21514d8981 983 #if defined( _CMU_STATUS_PLFRCOENS_MASK )
AnnaBridge 156:ff21514d8981 984 cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */
AnnaBridge 156:ff21514d8981 985 #endif
AnnaBridge 156:ff21514d8981 986 } CMU_Select_TypeDef;
AnnaBridge 156:ff21514d8981 987
AnnaBridge 156:ff21514d8981 988 #if defined( CMU_HFCORECLKEN0_LE )
AnnaBridge 156:ff21514d8981 989 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 156:ff21514d8981 990 /* Deprecated CMU_Select_TypeDef member */
AnnaBridge 156:ff21514d8981 991 #define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
AnnaBridge 156:ff21514d8981 992 /** @endcond */
AnnaBridge 156:ff21514d8981 993 #endif
AnnaBridge 156:ff21514d8981 994
AnnaBridge 156:ff21514d8981 995 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
AnnaBridge 156:ff21514d8981 996 /** HFXO tuning modes */
AnnaBridge 156:ff21514d8981 997 typedef enum
AnnaBridge 156:ff21514d8981 998 {
AnnaBridge 156:ff21514d8981 999 cmuHFXOTuningMode_Auto = 0,
AnnaBridge 156:ff21514d8981 1000 cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only */
AnnaBridge 156:ff21514d8981 1001 cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization */
AnnaBridge 156:ff21514d8981 1002 | CMU_CMD_HFXOSHUNTOPTSTART,
AnnaBridge 156:ff21514d8981 1003 } CMU_HFXOTuningMode_TypeDef;
AnnaBridge 156:ff21514d8981 1004 #endif
AnnaBridge 156:ff21514d8981 1005
AnnaBridge 156:ff21514d8981 1006 #if defined( _CMU_CTRL_LFXOBOOST_MASK )
AnnaBridge 156:ff21514d8981 1007 /** LFXO Boost values. */
AnnaBridge 156:ff21514d8981 1008 typedef enum
AnnaBridge 156:ff21514d8981 1009 {
AnnaBridge 156:ff21514d8981 1010 cmuLfxoBoost70 = 0x0,
AnnaBridge 156:ff21514d8981 1011 cmuLfxoBoost100 = 0x2,
AnnaBridge 156:ff21514d8981 1012 #if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
AnnaBridge 156:ff21514d8981 1013 cmuLfxoBoost70Reduced = 0x1,
AnnaBridge 156:ff21514d8981 1014 cmuLfxoBoost100Reduced = 0x3,
AnnaBridge 156:ff21514d8981 1015 #endif
AnnaBridge 156:ff21514d8981 1016 } CMU_LFXOBoost_TypeDef;
AnnaBridge 156:ff21514d8981 1017 #endif
AnnaBridge 156:ff21514d8981 1018
AnnaBridge 156:ff21514d8981 1019 /*******************************************************************************
AnnaBridge 156:ff21514d8981 1020 ******************************* STRUCTS ***********************************
AnnaBridge 156:ff21514d8981 1021 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1022
AnnaBridge 156:ff21514d8981 1023 /** LFXO initialization structure. Init values should be obtained from a configuration tool,
AnnaBridge 156:ff21514d8981 1024 app note or xtal datasheet */
AnnaBridge 156:ff21514d8981 1025 typedef struct
AnnaBridge 156:ff21514d8981 1026 {
AnnaBridge 156:ff21514d8981 1027 #if defined( _CMU_LFXOCTRL_MASK )
AnnaBridge 156:ff21514d8981 1028 uint8_t ctune; /**< CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1029 uint8_t gain; /**< Gain / max startup margin */
AnnaBridge 156:ff21514d8981 1030 #else
AnnaBridge 156:ff21514d8981 1031 CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */
AnnaBridge 156:ff21514d8981 1032 #endif
AnnaBridge 156:ff21514d8981 1033 uint8_t timeout; /**< Startup delay */
AnnaBridge 156:ff21514d8981 1034 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
AnnaBridge 156:ff21514d8981 1035 } CMU_LFXOInit_TypeDef;
AnnaBridge 156:ff21514d8981 1036
AnnaBridge 156:ff21514d8981 1037 #if defined( _CMU_LFXOCTRL_MASK )
AnnaBridge 156:ff21514d8981 1038 /** Default LFXO initialization values for platform 2 devices which contain a
AnnaBridge 156:ff21514d8981 1039 * separate LFXOCTRL register. */
AnnaBridge 156:ff21514d8981 1040 #define CMU_LFXOINIT_DEFAULT \
AnnaBridge 156:ff21514d8981 1041 { \
AnnaBridge 156:ff21514d8981 1042 _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
AnnaBridge 156:ff21514d8981 1043 _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
AnnaBridge 156:ff21514d8981 1044 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
AnnaBridge 156:ff21514d8981 1045 cmuOscMode_Crystal, /* Crystal oscillator */ \
AnnaBridge 156:ff21514d8981 1046 }
AnnaBridge 156:ff21514d8981 1047 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
AnnaBridge 156:ff21514d8981 1048 { \
AnnaBridge 156:ff21514d8981 1049 0, /* No CTUNE value needed */ \
AnnaBridge 156:ff21514d8981 1050 0, /* No LFXO startup gain */ \
AnnaBridge 156:ff21514d8981 1051 _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
AnnaBridge 156:ff21514d8981 1052 cmuOscMode_External, /* External digital clock */ \
AnnaBridge 156:ff21514d8981 1053 }
AnnaBridge 156:ff21514d8981 1054 #else
AnnaBridge 156:ff21514d8981 1055 /** Default LFXO initialization values for platform 1 devices. */
AnnaBridge 156:ff21514d8981 1056 #define CMU_LFXOINIT_DEFAULT \
AnnaBridge 156:ff21514d8981 1057 { \
AnnaBridge 156:ff21514d8981 1058 cmuLfxoBoost70, \
AnnaBridge 156:ff21514d8981 1059 _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1060 cmuOscMode_Crystal, \
AnnaBridge 156:ff21514d8981 1061 }
AnnaBridge 156:ff21514d8981 1062 #define CMU_LFXOINIT_EXTERNAL_CLOCK \
AnnaBridge 156:ff21514d8981 1063 { \
AnnaBridge 156:ff21514d8981 1064 cmuLfxoBoost70, \
AnnaBridge 156:ff21514d8981 1065 _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
AnnaBridge 156:ff21514d8981 1066 cmuOscMode_External, \
AnnaBridge 156:ff21514d8981 1067 }
AnnaBridge 156:ff21514d8981 1068 #endif
AnnaBridge 156:ff21514d8981 1069
AnnaBridge 156:ff21514d8981 1070 /** HFXO initialization structure. Init values should be obtained from a configuration tool,
AnnaBridge 156:ff21514d8981 1071 app note or xtal datasheet */
AnnaBridge 156:ff21514d8981 1072 typedef struct
AnnaBridge 156:ff21514d8981 1073 {
AnnaBridge 156:ff21514d8981 1074 #if defined( _CMU_HFXOCTRL_MASK )
AnnaBridge 156:ff21514d8981 1075 bool lowPowerMode; /**< Enable low-power mode */
AnnaBridge 156:ff21514d8981 1076 bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1077 bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1078 bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
AnnaBridge 156:ff21514d8981 1079 uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1080 uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
AnnaBridge 156:ff21514d8981 1081 uint8_t regIshSteadyState; /**< Shunt steady-state current */
AnnaBridge 156:ff21514d8981 1082 uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
AnnaBridge 156:ff21514d8981 1083 uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
AnnaBridge 156:ff21514d8981 1084 uint8_t thresholdPeakDetect; /**< Peak detection threshold */
AnnaBridge 156:ff21514d8981 1085 uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */
AnnaBridge 156:ff21514d8981 1086 uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
AnnaBridge 156:ff21514d8981 1087 uint8_t timeoutSteady; /**< Timeout - steady-state */
AnnaBridge 156:ff21514d8981 1088 uint8_t timeoutStartup; /**< Timeout - startup */
AnnaBridge 156:ff21514d8981 1089 #else
AnnaBridge 156:ff21514d8981 1090 uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */
AnnaBridge 156:ff21514d8981 1091 uint8_t timeout; /**< Startup delay */
AnnaBridge 156:ff21514d8981 1092 bool glitchDetector; /**< Enable/disable glitch detector */
AnnaBridge 156:ff21514d8981 1093 #endif
AnnaBridge 156:ff21514d8981 1094 CMU_OscMode_TypeDef mode; /**< Oscillator mode */
AnnaBridge 156:ff21514d8981 1095 } CMU_HFXOInit_TypeDef;
AnnaBridge 156:ff21514d8981 1096
AnnaBridge 156:ff21514d8981 1097 #if defined( _CMU_HFXOCTRL_MASK )
AnnaBridge 156:ff21514d8981 1098 /**
AnnaBridge 156:ff21514d8981 1099 * Default HFXO initialization values for Platform 2 devices which contain a
AnnaBridge 156:ff21514d8981 1100 * separate HFXOCTRL register.
AnnaBridge 156:ff21514d8981 1101 */
AnnaBridge 156:ff21514d8981 1102 #if defined( _EFR_DEVICE )
AnnaBridge 156:ff21514d8981 1103 #define CMU_HFXOINIT_DEFAULT \
AnnaBridge 156:ff21514d8981 1104 { \
AnnaBridge 156:ff21514d8981 1105 false, /* Low-noise mode for EFR32 */ \
AnnaBridge 156:ff21514d8981 1106 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1107 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1108 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1109 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
AnnaBridge 156:ff21514d8981 1110 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
AnnaBridge 156:ff21514d8981 1111 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
AnnaBridge 156:ff21514d8981 1112 0x20, /* Matching errata fix in CHIP_Init() */ \
AnnaBridge 156:ff21514d8981 1113 0x7, /* Recommended steady-state XO core bias current */ \
AnnaBridge 156:ff21514d8981 1114 0x6, /* Recommended peak detection threshold */ \
AnnaBridge 156:ff21514d8981 1115 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1116 0xA, /* Recommended peak detection timeout */ \
AnnaBridge 156:ff21514d8981 1117 0x4, /* Recommended steady timeout */ \
AnnaBridge 156:ff21514d8981 1118 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1119 cmuOscMode_Crystal, \
AnnaBridge 156:ff21514d8981 1120 }
AnnaBridge 156:ff21514d8981 1121 #else /* EFM32 device */
AnnaBridge 156:ff21514d8981 1122 #define CMU_HFXOINIT_DEFAULT \
AnnaBridge 156:ff21514d8981 1123 { \
AnnaBridge 156:ff21514d8981 1124 true, /* Low-power mode for EFM32 */ \
AnnaBridge 156:ff21514d8981 1125 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1126 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1127 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1128 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
AnnaBridge 156:ff21514d8981 1129 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
AnnaBridge 156:ff21514d8981 1130 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
AnnaBridge 156:ff21514d8981 1131 0x20, /* Matching errata fix in CHIP_Init() */ \
AnnaBridge 156:ff21514d8981 1132 0x7, /* Recommended steady-state osc core bias current */ \
AnnaBridge 156:ff21514d8981 1133 0x6, /* Recommended peak detection threshold */ \
AnnaBridge 156:ff21514d8981 1134 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1135 0xA, /* Recommended peak detection timeout */ \
AnnaBridge 156:ff21514d8981 1136 0x4, /* Recommended steady timeout */ \
AnnaBridge 156:ff21514d8981 1137 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1138 cmuOscMode_Crystal, \
AnnaBridge 156:ff21514d8981 1139 }
AnnaBridge 156:ff21514d8981 1140 #endif /* _EFR_DEVICE */
AnnaBridge 156:ff21514d8981 1141 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
AnnaBridge 156:ff21514d8981 1142 { \
AnnaBridge 156:ff21514d8981 1143 true, /* Low-power mode */ \
AnnaBridge 156:ff21514d8981 1144 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1145 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1146 false, /* @deprecated no longer in use */ \
AnnaBridge 156:ff21514d8981 1147 0, /* Startup CTUNE=0 recommended for external clock */ \
AnnaBridge 156:ff21514d8981 1148 0, /* Steady CTUNE=0 recommended for external clock */ \
AnnaBridge 156:ff21514d8981 1149 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
AnnaBridge 156:ff21514d8981 1150 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
AnnaBridge 156:ff21514d8981 1151 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
AnnaBridge 156:ff21514d8981 1152 0x6, /* Recommended peak detection threshold */ \
AnnaBridge 156:ff21514d8981 1153 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
AnnaBridge 156:ff21514d8981 1154 0x0, /* Peak-detect not recommended for external clock usage */ \
AnnaBridge 156:ff21514d8981 1155 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
AnnaBridge 156:ff21514d8981 1156 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
AnnaBridge 156:ff21514d8981 1157 cmuOscMode_External, \
AnnaBridge 156:ff21514d8981 1158 }
AnnaBridge 156:ff21514d8981 1159 #else /* _CMU_HFXOCTRL_MASK */
AnnaBridge 156:ff21514d8981 1160 /**
AnnaBridge 156:ff21514d8981 1161 * Default HFXO initialization values for Platform 1 devices.
AnnaBridge 156:ff21514d8981 1162 */
AnnaBridge 156:ff21514d8981 1163 #define CMU_HFXOINIT_DEFAULT \
AnnaBridge 156:ff21514d8981 1164 { \
AnnaBridge 156:ff21514d8981 1165 _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
AnnaBridge 156:ff21514d8981 1166 _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
AnnaBridge 156:ff21514d8981 1167 false, /* Disable glitch detector */ \
AnnaBridge 156:ff21514d8981 1168 cmuOscMode_Crystal, /* Crystal oscillator */ \
AnnaBridge 156:ff21514d8981 1169 }
AnnaBridge 156:ff21514d8981 1170 #define CMU_HFXOINIT_EXTERNAL_CLOCK \
AnnaBridge 156:ff21514d8981 1171 { \
AnnaBridge 156:ff21514d8981 1172 0, /* Minimal HFXO boost, 50% */ \
AnnaBridge 156:ff21514d8981 1173 _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
AnnaBridge 156:ff21514d8981 1174 false, /* Disable glitch detector */ \
AnnaBridge 156:ff21514d8981 1175 cmuOscMode_External, /* External digital clock */ \
AnnaBridge 156:ff21514d8981 1176 }
AnnaBridge 156:ff21514d8981 1177 #endif /* _CMU_HFXOCTRL_MASK */
AnnaBridge 156:ff21514d8981 1178
AnnaBridge 156:ff21514d8981 1179
AnnaBridge 156:ff21514d8981 1180 /*******************************************************************************
AnnaBridge 156:ff21514d8981 1181 ***************************** PROTOTYPES **********************************
AnnaBridge 156:ff21514d8981 1182 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1183
AnnaBridge 156:ff21514d8981 1184 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
AnnaBridge 156:ff21514d8981 1185 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1186 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1187
AnnaBridge 156:ff21514d8981 1188 #elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 1189 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1190 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
AnnaBridge 156:ff21514d8981 1191 #endif
AnnaBridge 156:ff21514d8981 1192
AnnaBridge 156:ff21514d8981 1193 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
AnnaBridge 156:ff21514d8981 1194
AnnaBridge 156:ff21514d8981 1195 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
AnnaBridge 156:ff21514d8981 1196 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
AnnaBridge 156:ff21514d8981 1197 CMU_Osc_TypeDef upSel);
AnnaBridge 156:ff21514d8981 1198 #endif
AnnaBridge 156:ff21514d8981 1199
AnnaBridge 156:ff21514d8981 1200 uint32_t CMU_CalibrateCountGet(void);
AnnaBridge 156:ff21514d8981 1201 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
AnnaBridge 156:ff21514d8981 1202 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1203 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
AnnaBridge 156:ff21514d8981 1204 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1205
AnnaBridge 156:ff21514d8981 1206 #if defined( _SILICON_LABS_32B_SERIES_1 )
AnnaBridge 156:ff21514d8981 1207 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
AnnaBridge 156:ff21514d8981 1208 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1209 #endif
AnnaBridge 156:ff21514d8981 1210
AnnaBridge 156:ff21514d8981 1211 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
AnnaBridge 156:ff21514d8981 1212 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
AnnaBridge 156:ff21514d8981 1213 void CMU_FreezeEnable(bool enable);
AnnaBridge 156:ff21514d8981 1214
AnnaBridge 156:ff21514d8981 1215 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
AnnaBridge 156:ff21514d8981 1216 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1217 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1218
AnnaBridge 156:ff21514d8981 1219 #elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 1220 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1221 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
AnnaBridge 156:ff21514d8981 1222 #endif
AnnaBridge 156:ff21514d8981 1223
AnnaBridge 156:ff21514d8981 1224 uint32_t CMU_HFRCOStartupDelayGet(void);
AnnaBridge 156:ff21514d8981 1225 void CMU_HFRCOStartupDelaySet(uint32_t delay);
AnnaBridge 156:ff21514d8981 1226
AnnaBridge 156:ff21514d8981 1227 #if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
AnnaBridge 156:ff21514d8981 1228 void CMU_HFXOAutostartEnable(uint32_t userSel,
AnnaBridge 156:ff21514d8981 1229 bool enEM0EM1Start,
AnnaBridge 156:ff21514d8981 1230 bool enEM0EM1StartSel);
AnnaBridge 156:ff21514d8981 1231 #endif
AnnaBridge 156:ff21514d8981 1232
AnnaBridge 156:ff21514d8981 1233 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
AnnaBridge 156:ff21514d8981 1234
AnnaBridge 156:ff21514d8981 1235
AnnaBridge 156:ff21514d8981 1236 uint32_t CMU_LCDClkFDIVGet(void);
AnnaBridge 156:ff21514d8981 1237 void CMU_LCDClkFDIVSet(uint32_t div);
AnnaBridge 156:ff21514d8981 1238 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
AnnaBridge 156:ff21514d8981 1239
AnnaBridge 156:ff21514d8981 1240 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
AnnaBridge 156:ff21514d8981 1241 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
AnnaBridge 156:ff21514d8981 1242 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
AnnaBridge 156:ff21514d8981 1243
AnnaBridge 156:ff21514d8981 1244 #if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
AnnaBridge 156:ff21514d8981 1245 bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
AnnaBridge 156:ff21514d8981 1246 bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
AnnaBridge 156:ff21514d8981 1247 CMU_HFXOTuningMode_TypeDef mode,
AnnaBridge 156:ff21514d8981 1248 bool wait);
AnnaBridge 156:ff21514d8981 1249 #endif
AnnaBridge 156:ff21514d8981 1250
AnnaBridge 156:ff21514d8981 1251 bool CMU_PCNTClockExternalGet(unsigned int instance);
AnnaBridge 156:ff21514d8981 1252 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
AnnaBridge 156:ff21514d8981 1253
AnnaBridge 156:ff21514d8981 1254 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
AnnaBridge 156:ff21514d8981 1255 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
AnnaBridge 156:ff21514d8981 1256 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
AnnaBridge 156:ff21514d8981 1257 #endif
AnnaBridge 156:ff21514d8981 1258
AnnaBridge 156:ff21514d8981 1259
AnnaBridge 156:ff21514d8981 1260 #if defined( CMU_CALCTRL_CONT )
AnnaBridge 156:ff21514d8981 1261 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1262 * @brief
AnnaBridge 156:ff21514d8981 1263 * Configures continuous calibration mode
AnnaBridge 156:ff21514d8981 1264 * @param[in] enable
AnnaBridge 156:ff21514d8981 1265 * If true, enables continuous calibration, if false disables continuous
AnnaBridge 156:ff21514d8981 1266 * calibrartion
AnnaBridge 156:ff21514d8981 1267 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1268 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
AnnaBridge 156:ff21514d8981 1269 {
AnnaBridge 156:ff21514d8981 1270 BUS_RegBitWrite(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
AnnaBridge 156:ff21514d8981 1271 }
AnnaBridge 156:ff21514d8981 1272 #endif
AnnaBridge 156:ff21514d8981 1273
AnnaBridge 156:ff21514d8981 1274
AnnaBridge 156:ff21514d8981 1275 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1276 * @brief
AnnaBridge 156:ff21514d8981 1277 * Starts calibration
AnnaBridge 156:ff21514d8981 1278 * @note
AnnaBridge 156:ff21514d8981 1279 * This call is usually invoked after CMU_CalibrateConfig() and possibly
AnnaBridge 156:ff21514d8981 1280 * CMU_CalibrateCont()
AnnaBridge 156:ff21514d8981 1281 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1282 __STATIC_INLINE void CMU_CalibrateStart(void)
AnnaBridge 156:ff21514d8981 1283 {
AnnaBridge 156:ff21514d8981 1284 CMU->CMD = CMU_CMD_CALSTART;
AnnaBridge 156:ff21514d8981 1285 }
AnnaBridge 156:ff21514d8981 1286
AnnaBridge 156:ff21514d8981 1287
AnnaBridge 156:ff21514d8981 1288 #if defined( CMU_CMD_CALSTOP )
AnnaBridge 156:ff21514d8981 1289 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1290 * @brief
AnnaBridge 156:ff21514d8981 1291 * Stop the calibration counters
AnnaBridge 156:ff21514d8981 1292 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1293 __STATIC_INLINE void CMU_CalibrateStop(void)
AnnaBridge 156:ff21514d8981 1294 {
AnnaBridge 156:ff21514d8981 1295 CMU->CMD = CMU_CMD_CALSTOP;
AnnaBridge 156:ff21514d8981 1296 }
AnnaBridge 156:ff21514d8981 1297 #endif
AnnaBridge 156:ff21514d8981 1298
AnnaBridge 156:ff21514d8981 1299
AnnaBridge 156:ff21514d8981 1300 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1301 * @brief
AnnaBridge 156:ff21514d8981 1302 * Convert dividend to logarithmic value. Only works for even
AnnaBridge 156:ff21514d8981 1303 * numbers equal to 2^n.
AnnaBridge 156:ff21514d8981 1304 *
AnnaBridge 156:ff21514d8981 1305 * @param[in] div
AnnaBridge 156:ff21514d8981 1306 * Unscaled dividend.
AnnaBridge 156:ff21514d8981 1307 *
AnnaBridge 156:ff21514d8981 1308 * @return
AnnaBridge 156:ff21514d8981 1309 * Logarithm of 2, as used by fixed prescalers.
AnnaBridge 156:ff21514d8981 1310 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1311 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
AnnaBridge 156:ff21514d8981 1312 {
AnnaBridge 156:ff21514d8981 1313 uint32_t log2;
AnnaBridge 156:ff21514d8981 1314
AnnaBridge 156:ff21514d8981 1315 /* Fixed 2^n prescalers take argument of 32768 or less. */
AnnaBridge 156:ff21514d8981 1316 EFM_ASSERT((div > 0U) && (div <= 32768U));
AnnaBridge 156:ff21514d8981 1317
AnnaBridge 156:ff21514d8981 1318 /* Count leading zeroes and "reverse" result */
AnnaBridge 156:ff21514d8981 1319 log2 = (31U - __CLZ(div));
AnnaBridge 156:ff21514d8981 1320
AnnaBridge 156:ff21514d8981 1321 return log2;
AnnaBridge 156:ff21514d8981 1322 }
AnnaBridge 156:ff21514d8981 1323
AnnaBridge 156:ff21514d8981 1324
AnnaBridge 156:ff21514d8981 1325 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1326 * @brief
AnnaBridge 156:ff21514d8981 1327 * Clear one or more pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1328 *
AnnaBridge 156:ff21514d8981 1329 * @param[in] flags
AnnaBridge 156:ff21514d8981 1330 * CMU interrupt sources to clear.
AnnaBridge 156:ff21514d8981 1331 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1332 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
AnnaBridge 156:ff21514d8981 1333 {
AnnaBridge 156:ff21514d8981 1334 CMU->IFC = flags;
AnnaBridge 156:ff21514d8981 1335 }
AnnaBridge 156:ff21514d8981 1336
AnnaBridge 156:ff21514d8981 1337
AnnaBridge 156:ff21514d8981 1338 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1339 * @brief
AnnaBridge 156:ff21514d8981 1340 * Disable one or more CMU interrupts.
AnnaBridge 156:ff21514d8981 1341 *
AnnaBridge 156:ff21514d8981 1342 * @param[in] flags
AnnaBridge 156:ff21514d8981 1343 * CMU interrupt sources to disable.
AnnaBridge 156:ff21514d8981 1344 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1345 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
AnnaBridge 156:ff21514d8981 1346 {
AnnaBridge 156:ff21514d8981 1347 CMU->IEN &= ~flags;
AnnaBridge 156:ff21514d8981 1348 }
AnnaBridge 156:ff21514d8981 1349
AnnaBridge 156:ff21514d8981 1350
AnnaBridge 156:ff21514d8981 1351 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1352 * @brief
AnnaBridge 156:ff21514d8981 1353 * Enable one or more CMU interrupts.
AnnaBridge 156:ff21514d8981 1354 *
AnnaBridge 156:ff21514d8981 1355 * @note
AnnaBridge 156:ff21514d8981 1356 * Depending on the use, a pending interrupt may already be set prior to
AnnaBridge 156:ff21514d8981 1357 * enabling the interrupt. Consider using CMU_IntClear() prior to enabling
AnnaBridge 156:ff21514d8981 1358 * if such a pending interrupt should be ignored.
AnnaBridge 156:ff21514d8981 1359 *
AnnaBridge 156:ff21514d8981 1360 * @param[in] flags
AnnaBridge 156:ff21514d8981 1361 * CMU interrupt sources to enable.
AnnaBridge 156:ff21514d8981 1362 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1363 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
AnnaBridge 156:ff21514d8981 1364 {
AnnaBridge 156:ff21514d8981 1365 CMU->IEN |= flags;
AnnaBridge 156:ff21514d8981 1366 }
AnnaBridge 156:ff21514d8981 1367
AnnaBridge 156:ff21514d8981 1368
AnnaBridge 156:ff21514d8981 1369 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1370 * @brief
AnnaBridge 156:ff21514d8981 1371 * Get pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1372 *
AnnaBridge 156:ff21514d8981 1373 * @return
AnnaBridge 156:ff21514d8981 1374 * CMU interrupt sources pending.
AnnaBridge 156:ff21514d8981 1375 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1376 __STATIC_INLINE uint32_t CMU_IntGet(void)
AnnaBridge 156:ff21514d8981 1377 {
AnnaBridge 156:ff21514d8981 1378 return CMU->IF;
AnnaBridge 156:ff21514d8981 1379 }
AnnaBridge 156:ff21514d8981 1380
AnnaBridge 156:ff21514d8981 1381
AnnaBridge 156:ff21514d8981 1382 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1383 * @brief
AnnaBridge 156:ff21514d8981 1384 * Get enabled and pending CMU interrupt flags.
AnnaBridge 156:ff21514d8981 1385 *
AnnaBridge 156:ff21514d8981 1386 * @details
AnnaBridge 156:ff21514d8981 1387 * Useful for handling more interrupt sources in the same interrupt handler.
AnnaBridge 156:ff21514d8981 1388 *
AnnaBridge 156:ff21514d8981 1389 * @note
AnnaBridge 156:ff21514d8981 1390 * The event bits are not cleared by the use of this function.
AnnaBridge 156:ff21514d8981 1391 *
AnnaBridge 156:ff21514d8981 1392 * @return
AnnaBridge 156:ff21514d8981 1393 * Pending and enabled CMU interrupt sources
AnnaBridge 156:ff21514d8981 1394 * The return value is the bitwise AND of
AnnaBridge 156:ff21514d8981 1395 * - the enabled interrupt sources in CMU_IEN and
AnnaBridge 156:ff21514d8981 1396 * - the pending interrupt flags CMU_IF
AnnaBridge 156:ff21514d8981 1397 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1398 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
AnnaBridge 156:ff21514d8981 1399 {
AnnaBridge 156:ff21514d8981 1400 uint32_t ien;
AnnaBridge 156:ff21514d8981 1401
AnnaBridge 156:ff21514d8981 1402 ien = CMU->IEN;
AnnaBridge 156:ff21514d8981 1403 return CMU->IF & ien;
AnnaBridge 156:ff21514d8981 1404 }
AnnaBridge 156:ff21514d8981 1405
AnnaBridge 156:ff21514d8981 1406
AnnaBridge 156:ff21514d8981 1407 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 1408 * @brief
AnnaBridge 156:ff21514d8981 1409 * Set one or more pending CMU interrupts.
AnnaBridge 156:ff21514d8981 1410 *
AnnaBridge 156:ff21514d8981 1411 * @param[in] flags
AnnaBridge 156:ff21514d8981 1412 * CMU interrupt sources to set to pending.
AnnaBridge 156:ff21514d8981 1413 *****************************************************************************/
AnnaBridge 156:ff21514d8981 1414 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
AnnaBridge 156:ff21514d8981 1415 {
AnnaBridge 156:ff21514d8981 1416 CMU->IFS = flags;
AnnaBridge 156:ff21514d8981 1417 }
AnnaBridge 156:ff21514d8981 1418
AnnaBridge 156:ff21514d8981 1419
AnnaBridge 156:ff21514d8981 1420 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1421 * @brief
AnnaBridge 156:ff21514d8981 1422 * Lock the CMU in order to protect some of its registers against unintended
AnnaBridge 156:ff21514d8981 1423 * modification.
AnnaBridge 156:ff21514d8981 1424 *
AnnaBridge 156:ff21514d8981 1425 * @details
AnnaBridge 156:ff21514d8981 1426 * Please refer to the reference manual for CMU registers that will be
AnnaBridge 156:ff21514d8981 1427 * locked.
AnnaBridge 156:ff21514d8981 1428 *
AnnaBridge 156:ff21514d8981 1429 * @note
AnnaBridge 156:ff21514d8981 1430 * If locking the CMU registers, they must be unlocked prior to using any
AnnaBridge 156:ff21514d8981 1431 * CMU API functions modifying CMU registers protected by the lock.
AnnaBridge 156:ff21514d8981 1432 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1433 __STATIC_INLINE void CMU_Lock(void)
AnnaBridge 156:ff21514d8981 1434 {
AnnaBridge 156:ff21514d8981 1435 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
AnnaBridge 156:ff21514d8981 1436 }
AnnaBridge 156:ff21514d8981 1437
AnnaBridge 156:ff21514d8981 1438
AnnaBridge 156:ff21514d8981 1439 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1440 * @brief
AnnaBridge 156:ff21514d8981 1441 * Convert logarithm of 2 prescaler to division factor.
AnnaBridge 156:ff21514d8981 1442 *
AnnaBridge 156:ff21514d8981 1443 * @param[in] log2
AnnaBridge 156:ff21514d8981 1444 * Logarithm of 2, as used by fixed prescalers.
AnnaBridge 156:ff21514d8981 1445 *
AnnaBridge 156:ff21514d8981 1446 * @return
AnnaBridge 156:ff21514d8981 1447 * Dividend.
AnnaBridge 156:ff21514d8981 1448 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1449 __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
AnnaBridge 156:ff21514d8981 1450 {
AnnaBridge 156:ff21514d8981 1451 return 1 << log2;
AnnaBridge 156:ff21514d8981 1452 }
AnnaBridge 156:ff21514d8981 1453
AnnaBridge 156:ff21514d8981 1454
AnnaBridge 156:ff21514d8981 1455 #if defined( _SILICON_LABS_32B_SERIES_1 )
AnnaBridge 156:ff21514d8981 1456 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1457 * @brief
AnnaBridge 156:ff21514d8981 1458 * Convert prescaler dividend to logarithmic value. Only works for even
AnnaBridge 156:ff21514d8981 1459 * numbers equal to 2^n.
AnnaBridge 156:ff21514d8981 1460 *
AnnaBridge 156:ff21514d8981 1461 * @param[in] presc
AnnaBridge 156:ff21514d8981 1462 * Unscaled dividend (dividend = presc + 1).
AnnaBridge 156:ff21514d8981 1463 *
AnnaBridge 156:ff21514d8981 1464 * @return
AnnaBridge 156:ff21514d8981 1465 * Logarithm of 2, as used by fixed 2^n prescalers.
AnnaBridge 156:ff21514d8981 1466 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1467 __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
AnnaBridge 156:ff21514d8981 1468 {
AnnaBridge 156:ff21514d8981 1469 uint32_t log2;
AnnaBridge 156:ff21514d8981 1470
AnnaBridge 156:ff21514d8981 1471 /* Integer prescalers take argument less than 32768. */
AnnaBridge 156:ff21514d8981 1472 EFM_ASSERT(presc < 32768U);
AnnaBridge 156:ff21514d8981 1473
AnnaBridge 156:ff21514d8981 1474 /* Count leading zeroes and "reverse" result */
AnnaBridge 156:ff21514d8981 1475 log2 = (31U - __CLZ(presc + 1));
AnnaBridge 156:ff21514d8981 1476
AnnaBridge 156:ff21514d8981 1477 /* Check that presc is a 2^n number */
AnnaBridge 156:ff21514d8981 1478 EFM_ASSERT(presc == (CMU_Log2ToDiv(log2) - 1));
AnnaBridge 156:ff21514d8981 1479
AnnaBridge 156:ff21514d8981 1480 return log2;
AnnaBridge 156:ff21514d8981 1481 }
AnnaBridge 156:ff21514d8981 1482 #endif
AnnaBridge 156:ff21514d8981 1483
AnnaBridge 156:ff21514d8981 1484
AnnaBridge 156:ff21514d8981 1485 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1486 * @brief
AnnaBridge 156:ff21514d8981 1487 * Unlock the CMU so that writing to locked registers again is possible.
AnnaBridge 156:ff21514d8981 1488 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1489 __STATIC_INLINE void CMU_Unlock(void)
AnnaBridge 156:ff21514d8981 1490 {
AnnaBridge 156:ff21514d8981 1491 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
AnnaBridge 156:ff21514d8981 1492 }
AnnaBridge 156:ff21514d8981 1493
AnnaBridge 156:ff21514d8981 1494
AnnaBridge 156:ff21514d8981 1495 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 1496 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1497 * @brief
AnnaBridge 156:ff21514d8981 1498 * Get current HFRCO frequency.
AnnaBridge 156:ff21514d8981 1499 *
AnnaBridge 156:ff21514d8981 1500 * @deprecated
AnnaBridge 156:ff21514d8981 1501 * Deprecated function. New code should use @ref CMU_HFRCOBandGet().
AnnaBridge 156:ff21514d8981 1502 *
AnnaBridge 156:ff21514d8981 1503 * @return
AnnaBridge 156:ff21514d8981 1504 * HFRCO frequency
AnnaBridge 156:ff21514d8981 1505 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1506 __STATIC_INLINE CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
AnnaBridge 156:ff21514d8981 1507 {
AnnaBridge 156:ff21514d8981 1508 return CMU_HFRCOBandGet();
AnnaBridge 156:ff21514d8981 1509 }
AnnaBridge 156:ff21514d8981 1510
AnnaBridge 156:ff21514d8981 1511
AnnaBridge 156:ff21514d8981 1512 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1513 * @brief
AnnaBridge 156:ff21514d8981 1514 * Set HFRCO calibration for the selected target frequency
AnnaBridge 156:ff21514d8981 1515 *
AnnaBridge 156:ff21514d8981 1516 * @deprecated
AnnaBridge 156:ff21514d8981 1517 * Deprecated function. New code should use @ref CMU_HFRCOBandSet().
AnnaBridge 156:ff21514d8981 1518 *
AnnaBridge 156:ff21514d8981 1519 * @param[in] setFreq
AnnaBridge 156:ff21514d8981 1520 * HFRCO frequency to set
AnnaBridge 156:ff21514d8981 1521 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1522 __STATIC_INLINE void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef setFreq)
AnnaBridge 156:ff21514d8981 1523 {
AnnaBridge 156:ff21514d8981 1524 CMU_HFRCOBandSet(setFreq);
AnnaBridge 156:ff21514d8981 1525 }
AnnaBridge 156:ff21514d8981 1526 #endif
AnnaBridge 156:ff21514d8981 1527
AnnaBridge 156:ff21514d8981 1528
AnnaBridge 156:ff21514d8981 1529 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
AnnaBridge 156:ff21514d8981 1530 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1531 * @brief
AnnaBridge 156:ff21514d8981 1532 * Get current AUXHFRCO frequency.
AnnaBridge 156:ff21514d8981 1533 *
AnnaBridge 156:ff21514d8981 1534 * @deprecated
AnnaBridge 156:ff21514d8981 1535 * Deprecated function. New code should use @ref CMU_AUXHFRCOBandGet().
AnnaBridge 156:ff21514d8981 1536 *
AnnaBridge 156:ff21514d8981 1537 * @return
AnnaBridge 156:ff21514d8981 1538 * AUXHFRCO frequency
AnnaBridge 156:ff21514d8981 1539 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1540 __STATIC_INLINE CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
AnnaBridge 156:ff21514d8981 1541 {
AnnaBridge 156:ff21514d8981 1542 return CMU_AUXHFRCOBandGet();
AnnaBridge 156:ff21514d8981 1543 }
AnnaBridge 156:ff21514d8981 1544
AnnaBridge 156:ff21514d8981 1545
AnnaBridge 156:ff21514d8981 1546 /***************************************************************************//**
AnnaBridge 156:ff21514d8981 1547 * @brief
AnnaBridge 156:ff21514d8981 1548 * Set AUXHFRCO calibration for the selected target frequency
AnnaBridge 156:ff21514d8981 1549 *
AnnaBridge 156:ff21514d8981 1550 * @deprecated
AnnaBridge 156:ff21514d8981 1551 * Deprecated function. New code should use @ref CMU_AUXHFRCOBandSet().
AnnaBridge 156:ff21514d8981 1552 *
AnnaBridge 156:ff21514d8981 1553 * @param[in] setFreq
AnnaBridge 156:ff21514d8981 1554 * AUXHFRCO frequency to set
AnnaBridge 156:ff21514d8981 1555 ******************************************************************************/
AnnaBridge 156:ff21514d8981 1556 __STATIC_INLINE void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef setFreq)
AnnaBridge 156:ff21514d8981 1557 {
AnnaBridge 156:ff21514d8981 1558 CMU_AUXHFRCOBandSet(setFreq);
AnnaBridge 156:ff21514d8981 1559 }
AnnaBridge 156:ff21514d8981 1560 #endif
AnnaBridge 156:ff21514d8981 1561
AnnaBridge 156:ff21514d8981 1562 /** @} (end addtogroup CMU) */
AnnaBridge 156:ff21514d8981 1563 /** @} (end addtogroup emlib) */
AnnaBridge 156:ff21514d8981 1564
AnnaBridge 156:ff21514d8981 1565 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 1566 }
AnnaBridge 156:ff21514d8981 1567 #endif
AnnaBridge 156:ff21514d8981 1568
AnnaBridge 156:ff21514d8981 1569 #endif /* defined( CMU_PRESENT ) */
AnnaBridge 156:ff21514d8981 1570 #endif /* EM_CMU_H */