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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_WALLBOT_BLE/nrf51.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
97:433970e64889 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /*
Kojto 122:f9eeca106725 2 * Copyright (c) Nordic Semiconductor ASA
Kojto 122:f9eeca106725 3 * All rights reserved.
Kojto 97:433970e64889 4 *
Kojto 122:f9eeca106725 5 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 6 * are permitted provided that the following conditions are met:
Kojto 97:433970e64889 7 *
Kojto 122:f9eeca106725 8 * 1. Redistributions of source code must retain the above copyright notice, this
Kojto 122:f9eeca106725 9 * list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 10 *
Kojto 122:f9eeca106725 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
Kojto 122:f9eeca106725 12 * list of conditions and the following disclaimer in the documentation and/or
Kojto 122:f9eeca106725 13 * other materials provided with the distribution.
Kojto 122:f9eeca106725 14 *
Kojto 122:f9eeca106725 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Kojto 122:f9eeca106725 16 * contributors to this software may be used to endorse or promote products
Kojto 122:f9eeca106725 17 * derived from this software without specific prior written permission.
Kojto 97:433970e64889 18 *
Kojto 97:433970e64889 19 *
Kojto 122:f9eeca106725 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 122:f9eeca106725 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 122:f9eeca106725 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 122:f9eeca106725 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 122:f9eeca106725 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 122:f9eeca106725 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 122:f9eeca106725 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 122:f9eeca106725 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 122:f9eeca106725 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 30 *
Kojto 122:f9eeca106725 31 */
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 #ifndef NRF51_H
bogdanm 92:4fc01daae5a5 34 #define NRF51_H
bogdanm 92:4fc01daae5a5 35
bogdanm 92:4fc01daae5a5 36 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 37 extern "C" {
bogdanm 92:4fc01daae5a5 38 #endif
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 92:4fc01daae5a5 42
bogdanm 92:4fc01daae5a5 43 typedef enum {
bogdanm 92:4fc01daae5a5 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm 92:4fc01daae5a5 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 92:4fc01daae5a5 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 92:4fc01daae5a5 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 92:4fc01daae5a5 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 92:4fc01daae5a5 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 92:4fc01daae5a5 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 92:4fc01daae5a5 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 122:f9eeca106725 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
bogdanm 92:4fc01daae5a5 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
bogdanm 92:4fc01daae5a5 54 RADIO_IRQn = 1, /*!< 1 RADIO */
bogdanm 92:4fc01daae5a5 55 UART0_IRQn = 2, /*!< 2 UART0 */
bogdanm 92:4fc01daae5a5 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
bogdanm 92:4fc01daae5a5 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
bogdanm 92:4fc01daae5a5 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
bogdanm 92:4fc01daae5a5 59 ADC_IRQn = 7, /*!< 7 ADC */
bogdanm 92:4fc01daae5a5 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
bogdanm 92:4fc01daae5a5 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
bogdanm 92:4fc01daae5a5 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
bogdanm 92:4fc01daae5a5 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
bogdanm 92:4fc01daae5a5 64 TEMP_IRQn = 12, /*!< 12 TEMP */
bogdanm 92:4fc01daae5a5 65 RNG_IRQn = 13, /*!< 13 RNG */
bogdanm 92:4fc01daae5a5 66 ECB_IRQn = 14, /*!< 14 ECB */
bogdanm 92:4fc01daae5a5 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
bogdanm 92:4fc01daae5a5 68 WDT_IRQn = 16, /*!< 16 WDT */
bogdanm 92:4fc01daae5a5 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
bogdanm 92:4fc01daae5a5 70 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 97:433970e64889 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
bogdanm 92:4fc01daae5a5 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
bogdanm 92:4fc01daae5a5 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
bogdanm 92:4fc01daae5a5 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
bogdanm 92:4fc01daae5a5 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
bogdanm 92:4fc01daae5a5 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
bogdanm 92:4fc01daae5a5 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
bogdanm 92:4fc01daae5a5 78 } IRQn_Type;
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80
bogdanm 92:4fc01daae5a5 81 /** @addtogroup Configuration_of_CMSIS
bogdanm 92:4fc01daae5a5 82 * @{
bogdanm 92:4fc01daae5a5 83 */
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 87 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 92:4fc01daae5a5 88 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 89
Kojto 97:433970e64889 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
bogdanm 92:4fc01daae5a5 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
bogdanm 92:4fc01daae5a5 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 92:4fc01daae5a5 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 92:4fc01daae5a5 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 92:4fc01daae5a5 95 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 92:4fc01daae5a5 96
Kojto 97:433970e64889 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Kojto 122:f9eeca106725 98 #include "system_nrf51.h" /*!< nrf51 System */
Kojto 122:f9eeca106725 99
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 102 /* ================ Device Specific Peripheral Section ================ */
bogdanm 92:4fc01daae5a5 103 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 /** @addtogroup Device_Peripheral_Registers
bogdanm 92:4fc01daae5a5 107 * @{
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110
bogdanm 92:4fc01daae5a5 111 /* ------------------- Start of section using anonymous unions ------------------ */
bogdanm 92:4fc01daae5a5 112 #if defined(__CC_ARM)
bogdanm 92:4fc01daae5a5 113 #pragma push
bogdanm 92:4fc01daae5a5 114 #pragma anon_unions
bogdanm 92:4fc01daae5a5 115 #elif defined(__ICCARM__)
bogdanm 92:4fc01daae5a5 116 #pragma language=extended
bogdanm 92:4fc01daae5a5 117 #elif defined(__GNUC__)
bogdanm 92:4fc01daae5a5 118 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 119 #elif defined(__TMS470__)
bogdanm 92:4fc01daae5a5 120 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 121 #elif defined(__TASKING__)
bogdanm 92:4fc01daae5a5 122 #pragma warning 586
bogdanm 92:4fc01daae5a5 123 #else
bogdanm 92:4fc01daae5a5 124 #warning Not supported compiler type
bogdanm 92:4fc01daae5a5 125 #endif
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 typedef struct {
bogdanm 92:4fc01daae5a5 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
bogdanm 92:4fc01daae5a5 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
bogdanm 92:4fc01daae5a5 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
bogdanm 92:4fc01daae5a5 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
bogdanm 92:4fc01daae5a5 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
bogdanm 92:4fc01daae5a5 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
bogdanm 92:4fc01daae5a5 135 } AMLI_RAMPRI_Type;
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 typedef struct {
Kojto 97:433970e64889 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
Kojto 97:433970e64889 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Kojto 97:433970e64889 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
Kojto 97:433970e64889 141 } SPIM_PSEL_Type;
Kojto 97:433970e64889 142
Kojto 97:433970e64889 143 typedef struct {
Kojto 97:433970e64889 144 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Kojto 97:433970e64889 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Kojto 97:433970e64889 147 } SPIM_RXD_Type;
Kojto 97:433970e64889 148
Kojto 97:433970e64889 149 typedef struct {
Kojto 97:433970e64889 150 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Kojto 97:433970e64889 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Kojto 97:433970e64889 153 } SPIM_TXD_Type;
Kojto 97:433970e64889 154
Kojto 97:433970e64889 155 typedef struct {
bogdanm 92:4fc01daae5a5 156 __O uint32_t EN; /*!< Enable channel group. */
bogdanm 92:4fc01daae5a5 157 __O uint32_t DIS; /*!< Disable channel group. */
bogdanm 92:4fc01daae5a5 158 } PPI_TASKS_CHG_Type;
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 typedef struct {
bogdanm 92:4fc01daae5a5 161 __IO uint32_t EEP; /*!< Channel event end-point. */
bogdanm 92:4fc01daae5a5 162 __IO uint32_t TEP; /*!< Channel task end-point. */
bogdanm 92:4fc01daae5a5 163 } PPI_CH_Type;
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165
bogdanm 92:4fc01daae5a5 166 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 167 /* ================ POWER ================ */
bogdanm 92:4fc01daae5a5 168 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 /**
bogdanm 92:4fc01daae5a5 172 * @brief Power Control. (POWER)
bogdanm 92:4fc01daae5a5 173 */
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 typedef struct { /*!< POWER Structure */
bogdanm 92:4fc01daae5a5 176 __I uint32_t RESERVED0[30];
bogdanm 92:4fc01daae5a5 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
bogdanm 92:4fc01daae5a5 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
bogdanm 92:4fc01daae5a5 179 __I uint32_t RESERVED1[34];
bogdanm 92:4fc01daae5a5 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
bogdanm 92:4fc01daae5a5 181 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 184 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 97:433970e64889 186 __I uint32_t RESERVED4[9];
Kojto 97:433970e64889 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Kojto 97:433970e64889 188 __I uint32_t RESERVED5[53];
bogdanm 92:4fc01daae5a5 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 97:433970e64889 190 __I uint32_t RESERVED6[3];
bogdanm 92:4fc01daae5a5 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 97:433970e64889 192 __I uint32_t RESERVED7[2];
bogdanm 92:4fc01daae5a5 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
bogdanm 92:4fc01daae5a5 194 register. */
Kojto 97:433970e64889 195 __I uint32_t RESERVED8;
bogdanm 92:4fc01daae5a5 196 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 97:433970e64889 197 __I uint32_t RESERVED9[7];
bogdanm 92:4fc01daae5a5 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
bogdanm 92:4fc01daae5a5 199 is a retained register. */
Kojto 97:433970e64889 200 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
Kojto 97:433970e64889 202 __I uint32_t RESERVED11[8];
bogdanm 92:4fc01daae5a5 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 97:433970e64889 204 __I uint32_t RESERVED12[291];
Kojto 97:433970e64889 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
bogdanm 92:4fc01daae5a5 206 } NRF_POWER_Type;
bogdanm 92:4fc01daae5a5 207
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 210 /* ================ CLOCK ================ */
bogdanm 92:4fc01daae5a5 211 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 /**
bogdanm 92:4fc01daae5a5 215 * @brief Clock control. (CLOCK)
bogdanm 92:4fc01daae5a5 216 */
bogdanm 92:4fc01daae5a5 217
bogdanm 92:4fc01daae5a5 218 typedef struct { /*!< CLOCK Structure */
bogdanm 92:4fc01daae5a5 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
bogdanm 92:4fc01daae5a5 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
bogdanm 92:4fc01daae5a5 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
bogdanm 92:4fc01daae5a5 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
bogdanm 92:4fc01daae5a5 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
bogdanm 92:4fc01daae5a5 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
bogdanm 92:4fc01daae5a5 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
bogdanm 92:4fc01daae5a5 226 __I uint32_t RESERVED0[57];
bogdanm 92:4fc01daae5a5 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
bogdanm 92:4fc01daae5a5 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
bogdanm 92:4fc01daae5a5 229 __I uint32_t RESERVED1;
Kojto 97:433970e64889 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Kojto 97:433970e64889 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
bogdanm 92:4fc01daae5a5 232 __I uint32_t RESERVED2[124];
bogdanm 92:4fc01daae5a5 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 235 __I uint32_t RESERVED3[63];
Kojto 97:433970e64889 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
bogdanm 92:4fc01daae5a5 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 97:433970e64889 238 __I uint32_t RESERVED4;
Kojto 97:433970e64889 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
bogdanm 92:4fc01daae5a5 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 97:433970e64889 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto 97:433970e64889 242 triggered. */
Kojto 97:433970e64889 243 __I uint32_t RESERVED5[62];
bogdanm 92:4fc01daae5a5 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
bogdanm 92:4fc01daae5a5 245 __I uint32_t RESERVED6[7];
bogdanm 92:4fc01daae5a5 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
bogdanm 92:4fc01daae5a5 247 __I uint32_t RESERVED7[5];
bogdanm 92:4fc01daae5a5 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
bogdanm 92:4fc01daae5a5 249 } NRF_CLOCK_Type;
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 253 /* ================ MPU ================ */
bogdanm 92:4fc01daae5a5 254 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256
bogdanm 92:4fc01daae5a5 257 /**
bogdanm 92:4fc01daae5a5 258 * @brief Memory Protection Unit. (MPU)
bogdanm 92:4fc01daae5a5 259 */
bogdanm 92:4fc01daae5a5 260
bogdanm 92:4fc01daae5a5 261 typedef struct { /*!< MPU Structure */
bogdanm 92:4fc01daae5a5 262 __I uint32_t RESERVED0[330];
bogdanm 92:4fc01daae5a5 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
bogdanm 92:4fc01daae5a5 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
bogdanm 92:4fc01daae5a5 265 __I uint32_t RESERVED1[52];
Kojto 97:433970e64889 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Kojto 97:433970e64889 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
bogdanm 92:4fc01daae5a5 270 } NRF_MPU_Type;
bogdanm 92:4fc01daae5a5 271
bogdanm 92:4fc01daae5a5 272
bogdanm 92:4fc01daae5a5 273 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 274 /* ================ AMLI ================ */
bogdanm 92:4fc01daae5a5 275 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 276
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 /**
bogdanm 92:4fc01daae5a5 279 * @brief AHB Multi-Layer Interface. (AMLI)
bogdanm 92:4fc01daae5a5 280 */
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282 typedef struct { /*!< AMLI Structure */
bogdanm 92:4fc01daae5a5 283 __I uint32_t RESERVED0[896];
bogdanm 92:4fc01daae5a5 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
bogdanm 92:4fc01daae5a5 285 } NRF_AMLI_Type;
bogdanm 92:4fc01daae5a5 286
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 289 /* ================ RADIO ================ */
bogdanm 92:4fc01daae5a5 290 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 291
bogdanm 92:4fc01daae5a5 292
bogdanm 92:4fc01daae5a5 293 /**
bogdanm 92:4fc01daae5a5 294 * @brief The radio. (RADIO)
bogdanm 92:4fc01daae5a5 295 */
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 typedef struct { /*!< RADIO Structure */
bogdanm 92:4fc01daae5a5 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
bogdanm 92:4fc01daae5a5 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
bogdanm 92:4fc01daae5a5 300 __O uint32_t TASKS_START; /*!< Start radio. */
bogdanm 92:4fc01daae5a5 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
bogdanm 92:4fc01daae5a5 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
bogdanm 92:4fc01daae5a5 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
bogdanm 92:4fc01daae5a5 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
bogdanm 92:4fc01daae5a5 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
bogdanm 92:4fc01daae5a5 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
bogdanm 92:4fc01daae5a5 307 __I uint32_t RESERVED0[55];
bogdanm 92:4fc01daae5a5 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
bogdanm 92:4fc01daae5a5 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
bogdanm 92:4fc01daae5a5 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
bogdanm 92:4fc01daae5a5 311 __IO uint32_t EVENTS_END; /*!< End event. */
bogdanm 92:4fc01daae5a5 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
bogdanm 92:4fc01daae5a5 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
bogdanm 92:4fc01daae5a5 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
bogdanm 92:4fc01daae5a5 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
bogdanm 92:4fc01daae5a5 316 sample is ready for readout at the RSSISAMPLE register. */
bogdanm 92:4fc01daae5a5 317 __I uint32_t RESERVED1[2];
Kojto 122:f9eeca106725 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
bogdanm 92:4fc01daae5a5 319 __I uint32_t RESERVED2[53];
Kojto 97:433970e64889 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
bogdanm 92:4fc01daae5a5 321 __I uint32_t RESERVED3[64];
bogdanm 92:4fc01daae5a5 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 324 __I uint32_t RESERVED4[61];
bogdanm 92:4fc01daae5a5 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 122:f9eeca106725 326 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 327 __I uint32_t RXMATCH; /*!< Received address. */
bogdanm 92:4fc01daae5a5 328 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 97:433970e64889 329 __I uint32_t DAI; /*!< Device address match index. */
Kojto 122:f9eeca106725 330 __I uint32_t RESERVED6[60];
bogdanm 92:4fc01daae5a5 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
bogdanm 92:4fc01daae5a5 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
bogdanm 92:4fc01daae5a5 333 __IO uint32_t TXPOWER; /*!< Output power. */
bogdanm 92:4fc01daae5a5 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
bogdanm 92:4fc01daae5a5 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
bogdanm 92:4fc01daae5a5 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
bogdanm 92:4fc01daae5a5 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
bogdanm 92:4fc01daae5a5 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
bogdanm 92:4fc01daae5a5 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
bogdanm 92:4fc01daae5a5 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
bogdanm 92:4fc01daae5a5 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
bogdanm 92:4fc01daae5a5 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
bogdanm 92:4fc01daae5a5 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
bogdanm 92:4fc01daae5a5 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
bogdanm 92:4fc01daae5a5 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
bogdanm 92:4fc01daae5a5 346 __IO uint32_t TEST; /*!< Test features enable register. */
bogdanm 92:4fc01daae5a5 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 97:433970e64889 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 122:f9eeca106725 349 __I uint32_t RESERVED7;
bogdanm 92:4fc01daae5a5 350 __I uint32_t STATE; /*!< Current radio state. */
bogdanm 92:4fc01daae5a5 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 122:f9eeca106725 352 __I uint32_t RESERVED8[2];
bogdanm 92:4fc01daae5a5 353 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 122:f9eeca106725 354 __I uint32_t RESERVED9[39];
bogdanm 92:4fc01daae5a5 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
bogdanm 92:4fc01daae5a5 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
bogdanm 92:4fc01daae5a5 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 122:f9eeca106725 358 __I uint32_t RESERVED10[56];
bogdanm 92:4fc01daae5a5 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
bogdanm 92:4fc01daae5a5 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
bogdanm 92:4fc01daae5a5 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
bogdanm 92:4fc01daae5a5 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
bogdanm 92:4fc01daae5a5 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 122:f9eeca106725 364 __I uint32_t RESERVED11[561];
bogdanm 92:4fc01daae5a5 365 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 366 } NRF_RADIO_Type;
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368
bogdanm 92:4fc01daae5a5 369 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 370 /* ================ UART ================ */
bogdanm 92:4fc01daae5a5 371 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 372
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 /**
bogdanm 92:4fc01daae5a5 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
bogdanm 92:4fc01daae5a5 376 */
bogdanm 92:4fc01daae5a5 377
bogdanm 92:4fc01daae5a5 378 typedef struct { /*!< UART Structure */
bogdanm 92:4fc01daae5a5 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
bogdanm 92:4fc01daae5a5 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
bogdanm 92:4fc01daae5a5 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
bogdanm 92:4fc01daae5a5 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
bogdanm 92:4fc01daae5a5 383 __I uint32_t RESERVED0[3];
bogdanm 92:4fc01daae5a5 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
bogdanm 92:4fc01daae5a5 385 __I uint32_t RESERVED1[56];
bogdanm 92:4fc01daae5a5 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
bogdanm 92:4fc01daae5a5 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
bogdanm 92:4fc01daae5a5 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
bogdanm 92:4fc01daae5a5 389 __I uint32_t RESERVED2[4];
bogdanm 92:4fc01daae5a5 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
bogdanm 92:4fc01daae5a5 391 __I uint32_t RESERVED3;
bogdanm 92:4fc01daae5a5 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
bogdanm 92:4fc01daae5a5 393 __I uint32_t RESERVED4[7];
bogdanm 92:4fc01daae5a5 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
bogdanm 92:4fc01daae5a5 395 __I uint32_t RESERVED5[46];
Kojto 97:433970e64889 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Kojto 97:433970e64889 397 __I uint32_t RESERVED6[64];
bogdanm 92:4fc01daae5a5 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 400 __I uint32_t RESERVED7[93];
bogdanm 92:4fc01daae5a5 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
bogdanm 92:4fc01daae5a5 402 __I uint32_t RESERVED8[31];
bogdanm 92:4fc01daae5a5 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
bogdanm 92:4fc01daae5a5 404 __I uint32_t RESERVED9;
bogdanm 92:4fc01daae5a5 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
bogdanm 92:4fc01daae5a5 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
bogdanm 92:4fc01daae5a5 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
bogdanm 92:4fc01daae5a5 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
bogdanm 92:4fc01daae5a5 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 97:433970e64889 410 Once read the character is consumed. If read when no character
bogdanm 92:4fc01daae5a5 411 available, the UART will stop working. */
bogdanm 92:4fc01daae5a5 412 __O uint32_t TXD; /*!< TXD register. */
bogdanm 92:4fc01daae5a5 413 __I uint32_t RESERVED10;
bogdanm 92:4fc01daae5a5 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
bogdanm 92:4fc01daae5a5 415 __I uint32_t RESERVED11[17];
bogdanm 92:4fc01daae5a5 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
bogdanm 92:4fc01daae5a5 417 __I uint32_t RESERVED12[675];
bogdanm 92:4fc01daae5a5 418 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 419 } NRF_UART_Type;
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421
bogdanm 92:4fc01daae5a5 422 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 423 /* ================ SPI ================ */
bogdanm 92:4fc01daae5a5 424 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 425
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 /**
bogdanm 92:4fc01daae5a5 428 * @brief SPI master 0. (SPI)
bogdanm 92:4fc01daae5a5 429 */
bogdanm 92:4fc01daae5a5 430
bogdanm 92:4fc01daae5a5 431 typedef struct { /*!< SPI Structure */
bogdanm 92:4fc01daae5a5 432 __I uint32_t RESERVED0[66];
bogdanm 92:4fc01daae5a5 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
bogdanm 92:4fc01daae5a5 434 __I uint32_t RESERVED1[126];
bogdanm 92:4fc01daae5a5 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 437 __I uint32_t RESERVED2[125];
bogdanm 92:4fc01daae5a5 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
bogdanm 92:4fc01daae5a5 439 __I uint32_t RESERVED3;
bogdanm 92:4fc01daae5a5 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 92:4fc01daae5a5 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 92:4fc01daae5a5 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 92:4fc01daae5a5 443 __I uint32_t RESERVED4;
Kojto 97:433970e64889 444 __I uint32_t RXD; /*!< RX data. */
bogdanm 92:4fc01daae5a5 445 __IO uint32_t TXD; /*!< TX data. */
bogdanm 92:4fc01daae5a5 446 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
bogdanm 92:4fc01daae5a5 448 __I uint32_t RESERVED6[11];
bogdanm 92:4fc01daae5a5 449 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 450 __I uint32_t RESERVED7[681];
bogdanm 92:4fc01daae5a5 451 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 452 } NRF_SPI_Type;
bogdanm 92:4fc01daae5a5 453
bogdanm 92:4fc01daae5a5 454
bogdanm 92:4fc01daae5a5 455 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 456 /* ================ TWI ================ */
bogdanm 92:4fc01daae5a5 457 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460 /**
bogdanm 92:4fc01daae5a5 461 * @brief Two-wire interface master 0. (TWI)
bogdanm 92:4fc01daae5a5 462 */
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 typedef struct { /*!< TWI Structure */
bogdanm 92:4fc01daae5a5 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
bogdanm 92:4fc01daae5a5 466 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
bogdanm 92:4fc01daae5a5 468 __I uint32_t RESERVED1[2];
bogdanm 92:4fc01daae5a5 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 470 __I uint32_t RESERVED2;
bogdanm 92:4fc01daae5a5 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
bogdanm 92:4fc01daae5a5 473 __I uint32_t RESERVED3[56];
bogdanm 92:4fc01daae5a5 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
bogdanm 92:4fc01daae5a5 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
bogdanm 92:4fc01daae5a5 476 __I uint32_t RESERVED4[4];
bogdanm 92:4fc01daae5a5 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
bogdanm 92:4fc01daae5a5 478 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
bogdanm 92:4fc01daae5a5 480 __I uint32_t RESERVED6[4];
bogdanm 92:4fc01daae5a5 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 97:433970e64889 482 __I uint32_t RESERVED7[3];
Kojto 97:433970e64889 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Kojto 97:433970e64889 484 __I uint32_t RESERVED8[45];
bogdanm 92:4fc01daae5a5 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 97:433970e64889 486 __I uint32_t RESERVED9[64];
bogdanm 92:4fc01daae5a5 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 489 __I uint32_t RESERVED10[110];
bogdanm 92:4fc01daae5a5 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 97:433970e64889 491 __I uint32_t RESERVED11[14];
bogdanm 92:4fc01daae5a5 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 97:433970e64889 493 __I uint32_t RESERVED12;
bogdanm 92:4fc01daae5a5 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
bogdanm 92:4fc01daae5a5 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 97:433970e64889 496 __I uint32_t RESERVED13[2];
Kojto 97:433970e64889 497 __I uint32_t RXD; /*!< RX data register. */
bogdanm 92:4fc01daae5a5 498 __IO uint32_t TXD; /*!< TX data register. */
Kojto 97:433970e64889 499 __I uint32_t RESERVED14;
bogdanm 92:4fc01daae5a5 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 97:433970e64889 501 __I uint32_t RESERVED15[24];
bogdanm 92:4fc01daae5a5 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 97:433970e64889 503 __I uint32_t RESERVED16[668];
bogdanm 92:4fc01daae5a5 504 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 505 } NRF_TWI_Type;
bogdanm 92:4fc01daae5a5 506
bogdanm 92:4fc01daae5a5 507
bogdanm 92:4fc01daae5a5 508 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 509 /* ================ SPIS ================ */
bogdanm 92:4fc01daae5a5 510 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 511
bogdanm 92:4fc01daae5a5 512
bogdanm 92:4fc01daae5a5 513 /**
bogdanm 92:4fc01daae5a5 514 * @brief SPI slave 1. (SPIS)
bogdanm 92:4fc01daae5a5 515 */
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 typedef struct { /*!< SPIS Structure */
bogdanm 92:4fc01daae5a5 518 __I uint32_t RESERVED0[9];
bogdanm 92:4fc01daae5a5 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
bogdanm 92:4fc01daae5a5 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
bogdanm 92:4fc01daae5a5 521 __I uint32_t RESERVED1[54];
bogdanm 92:4fc01daae5a5 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Kojto 122:f9eeca106725 523 __I uint32_t RESERVED2[2];
Kojto 122:f9eeca106725 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 122:f9eeca106725 525 __I uint32_t RESERVED3[5];
bogdanm 92:4fc01daae5a5 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Kojto 122:f9eeca106725 527 __I uint32_t RESERVED4[53];
bogdanm 92:4fc01daae5a5 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Kojto 122:f9eeca106725 529 __I uint32_t RESERVED5[64];
bogdanm 92:4fc01daae5a5 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 532 __I uint32_t RESERVED6[61];
bogdanm 92:4fc01daae5a5 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Kojto 122:f9eeca106725 534 __I uint32_t RESERVED7[15];
bogdanm 92:4fc01daae5a5 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
Kojto 122:f9eeca106725 536 __I uint32_t RESERVED8[47];
bogdanm 92:4fc01daae5a5 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Kojto 122:f9eeca106725 538 __I uint32_t RESERVED9;
bogdanm 92:4fc01daae5a5 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 92:4fc01daae5a5 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 92:4fc01daae5a5 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 92:4fc01daae5a5 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Kojto 122:f9eeca106725 543 __I uint32_t RESERVED10[7];
bogdanm 92:4fc01daae5a5 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
bogdanm 92:4fc01daae5a5 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 97:433970e64889 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Kojto 122:f9eeca106725 547 __I uint32_t RESERVED11;
bogdanm 92:4fc01daae5a5 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
bogdanm 92:4fc01daae5a5 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 97:433970e64889 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Kojto 122:f9eeca106725 551 __I uint32_t RESERVED12;
bogdanm 92:4fc01daae5a5 552 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 553 __I uint32_t RESERVED13;
bogdanm 92:4fc01daae5a5 554 __IO uint32_t DEF; /*!< Default character. */
Kojto 122:f9eeca106725 555 __I uint32_t RESERVED14[24];
bogdanm 92:4fc01daae5a5 556 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 557 __I uint32_t RESERVED15[654];
bogdanm 92:4fc01daae5a5 558 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 559 } NRF_SPIS_Type;
bogdanm 92:4fc01daae5a5 560
bogdanm 92:4fc01daae5a5 561
bogdanm 92:4fc01daae5a5 562 /* ================================================================================ */
Kojto 97:433970e64889 563 /* ================ SPIM ================ */
Kojto 97:433970e64889 564 /* ================================================================================ */
Kojto 97:433970e64889 565
Kojto 97:433970e64889 566
Kojto 97:433970e64889 567 /**
Kojto 97:433970e64889 568 * @brief SPI master with easyDMA 1. (SPIM)
Kojto 97:433970e64889 569 */
Kojto 97:433970e64889 570
Kojto 97:433970e64889 571 typedef struct { /*!< SPIM Structure */
Kojto 97:433970e64889 572 __I uint32_t RESERVED0[4];
Kojto 97:433970e64889 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Kojto 97:433970e64889 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Kojto 97:433970e64889 575 __I uint32_t RESERVED1;
Kojto 97:433970e64889 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Kojto 97:433970e64889 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Kojto 97:433970e64889 578 __I uint32_t RESERVED2[56];
Kojto 97:433970e64889 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Kojto 97:433970e64889 580 __I uint32_t RESERVED3[2];
Kojto 97:433970e64889 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Kojto 122:f9eeca106725 582 __I uint32_t RESERVED4[3];
Kojto 97:433970e64889 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Kojto 122:f9eeca106725 584 __I uint32_t RESERVED5[10];
Kojto 97:433970e64889 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Kojto 122:f9eeca106725 586 __I uint32_t RESERVED6[109];
Kojto 97:433970e64889 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 97:433970e64889 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 589 __I uint32_t RESERVED7[125];
Kojto 97:433970e64889 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Kojto 122:f9eeca106725 591 __I uint32_t RESERVED8;
Kojto 97:433970e64889 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Kojto 122:f9eeca106725 593 __I uint32_t RESERVED9[4];
Kojto 97:433970e64889 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Kojto 122:f9eeca106725 595 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 597 __I uint32_t RESERVED11;
Kojto 97:433970e64889 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 599 __I uint32_t RESERVED12;
Kojto 97:433970e64889 600 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 601 __I uint32_t RESERVED13[26];
Kojto 97:433970e64889 602 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 603 __I uint32_t RESERVED14[654];
Kojto 97:433970e64889 604 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 97:433970e64889 605 } NRF_SPIM_Type;
Kojto 97:433970e64889 606
Kojto 97:433970e64889 607
Kojto 97:433970e64889 608 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 609 /* ================ GPIOTE ================ */
bogdanm 92:4fc01daae5a5 610 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 611
bogdanm 92:4fc01daae5a5 612
bogdanm 92:4fc01daae5a5 613 /**
bogdanm 92:4fc01daae5a5 614 * @brief GPIO tasks and events. (GPIOTE)
bogdanm 92:4fc01daae5a5 615 */
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 typedef struct { /*!< GPIOTE Structure */
bogdanm 92:4fc01daae5a5 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 92:4fc01daae5a5 619 __I uint32_t RESERVED0[60];
bogdanm 92:4fc01daae5a5 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 92:4fc01daae5a5 621 __I uint32_t RESERVED1[27];
bogdanm 92:4fc01daae5a5 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
bogdanm 92:4fc01daae5a5 623 __I uint32_t RESERVED2[97];
bogdanm 92:4fc01daae5a5 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 626 __I uint32_t RESERVED3[129];
bogdanm 92:4fc01daae5a5 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
bogdanm 92:4fc01daae5a5 628 __I uint32_t RESERVED4[695];
bogdanm 92:4fc01daae5a5 629 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 630 } NRF_GPIOTE_Type;
bogdanm 92:4fc01daae5a5 631
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 634 /* ================ ADC ================ */
bogdanm 92:4fc01daae5a5 635 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 636
bogdanm 92:4fc01daae5a5 637
bogdanm 92:4fc01daae5a5 638 /**
bogdanm 92:4fc01daae5a5 639 * @brief Analog to digital converter. (ADC)
bogdanm 92:4fc01daae5a5 640 */
bogdanm 92:4fc01daae5a5 641
bogdanm 92:4fc01daae5a5 642 typedef struct { /*!< ADC Structure */
bogdanm 92:4fc01daae5a5 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
bogdanm 92:4fc01daae5a5 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
bogdanm 92:4fc01daae5a5 645 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
bogdanm 92:4fc01daae5a5 647 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 650 __I uint32_t RESERVED2[61];
bogdanm 92:4fc01daae5a5 651 __I uint32_t BUSY; /*!< ADC busy register. */
bogdanm 92:4fc01daae5a5 652 __I uint32_t RESERVED3[63];
bogdanm 92:4fc01daae5a5 653 __IO uint32_t ENABLE; /*!< ADC enable. */
bogdanm 92:4fc01daae5a5 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
bogdanm 92:4fc01daae5a5 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
bogdanm 92:4fc01daae5a5 656 __I uint32_t RESERVED4[700];
bogdanm 92:4fc01daae5a5 657 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 658 } NRF_ADC_Type;
bogdanm 92:4fc01daae5a5 659
bogdanm 92:4fc01daae5a5 660
bogdanm 92:4fc01daae5a5 661 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 662 /* ================ TIMER ================ */
bogdanm 92:4fc01daae5a5 663 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 664
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666 /**
bogdanm 92:4fc01daae5a5 667 * @brief Timer 0. (TIMER)
bogdanm 92:4fc01daae5a5 668 */
bogdanm 92:4fc01daae5a5 669
bogdanm 92:4fc01daae5a5 670 typedef struct { /*!< TIMER Structure */
bogdanm 92:4fc01daae5a5 671 __O uint32_t TASKS_START; /*!< Start Timer. */
bogdanm 92:4fc01daae5a5 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
bogdanm 92:4fc01daae5a5 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
bogdanm 92:4fc01daae5a5 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 97:433970e64889 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Kojto 97:433970e64889 676 __I uint32_t RESERVED0[11];
bogdanm 92:4fc01daae5a5 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
bogdanm 92:4fc01daae5a5 678 __I uint32_t RESERVED1[60];
bogdanm 92:4fc01daae5a5 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 92:4fc01daae5a5 680 __I uint32_t RESERVED2[44];
bogdanm 92:4fc01daae5a5 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
bogdanm 92:4fc01daae5a5 682 __I uint32_t RESERVED3[64];
bogdanm 92:4fc01daae5a5 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 685 __I uint32_t RESERVED4[126];
bogdanm 92:4fc01daae5a5 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
bogdanm 92:4fc01daae5a5 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
bogdanm 92:4fc01daae5a5 688 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
bogdanm 92:4fc01daae5a5 690 clock frequency is divided by 2^SCALE. */
bogdanm 92:4fc01daae5a5 691 __I uint32_t RESERVED6[11];
bogdanm 92:4fc01daae5a5 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 92:4fc01daae5a5 693 __I uint32_t RESERVED7[683];
bogdanm 92:4fc01daae5a5 694 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 695 } NRF_TIMER_Type;
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697
bogdanm 92:4fc01daae5a5 698 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 699 /* ================ RTC ================ */
bogdanm 92:4fc01daae5a5 700 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 701
bogdanm 92:4fc01daae5a5 702
bogdanm 92:4fc01daae5a5 703 /**
bogdanm 92:4fc01daae5a5 704 * @brief Real time counter 0. (RTC)
bogdanm 92:4fc01daae5a5 705 */
bogdanm 92:4fc01daae5a5 706
bogdanm 92:4fc01daae5a5 707 typedef struct { /*!< RTC Structure */
bogdanm 92:4fc01daae5a5 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
bogdanm 92:4fc01daae5a5 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
bogdanm 92:4fc01daae5a5 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
bogdanm 92:4fc01daae5a5 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
bogdanm 92:4fc01daae5a5 712 __I uint32_t RESERVED0[60];
bogdanm 92:4fc01daae5a5 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
bogdanm 92:4fc01daae5a5 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
bogdanm 92:4fc01daae5a5 715 __I uint32_t RESERVED1[14];
bogdanm 92:4fc01daae5a5 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 92:4fc01daae5a5 717 __I uint32_t RESERVED2[109];
bogdanm 92:4fc01daae5a5 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 720 __I uint32_t RESERVED3[13];
bogdanm 92:4fc01daae5a5 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
bogdanm 92:4fc01daae5a5 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
bogdanm 92:4fc01daae5a5 723 the value of EVTEN. */
bogdanm 92:4fc01daae5a5 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
bogdanm 92:4fc01daae5a5 725 gives the value of EVTEN. */
bogdanm 92:4fc01daae5a5 726 __I uint32_t RESERVED4[110];
Kojto 97:433970e64889 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
bogdanm 92:4fc01daae5a5 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
bogdanm 92:4fc01daae5a5 729 Must be written when RTC is STOPed. */
bogdanm 92:4fc01daae5a5 730 __I uint32_t RESERVED5[13];
bogdanm 92:4fc01daae5a5 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 92:4fc01daae5a5 732 __I uint32_t RESERVED6[683];
bogdanm 92:4fc01daae5a5 733 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 734 } NRF_RTC_Type;
bogdanm 92:4fc01daae5a5 735
bogdanm 92:4fc01daae5a5 736
bogdanm 92:4fc01daae5a5 737 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 738 /* ================ TEMP ================ */
bogdanm 92:4fc01daae5a5 739 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 740
bogdanm 92:4fc01daae5a5 741
bogdanm 92:4fc01daae5a5 742 /**
bogdanm 92:4fc01daae5a5 743 * @brief Temperature Sensor. (TEMP)
bogdanm 92:4fc01daae5a5 744 */
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746 typedef struct { /*!< TEMP Structure */
bogdanm 92:4fc01daae5a5 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
bogdanm 92:4fc01daae5a5 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
bogdanm 92:4fc01daae5a5 749 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
bogdanm 92:4fc01daae5a5 751 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 754 __I uint32_t RESERVED2[127];
bogdanm 92:4fc01daae5a5 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
bogdanm 92:4fc01daae5a5 756 __I uint32_t RESERVED3[700];
bogdanm 92:4fc01daae5a5 757 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 758 } NRF_TEMP_Type;
bogdanm 92:4fc01daae5a5 759
bogdanm 92:4fc01daae5a5 760
bogdanm 92:4fc01daae5a5 761 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 762 /* ================ RNG ================ */
bogdanm 92:4fc01daae5a5 763 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 764
bogdanm 92:4fc01daae5a5 765
bogdanm 92:4fc01daae5a5 766 /**
bogdanm 92:4fc01daae5a5 767 * @brief Random Number Generator. (RNG)
bogdanm 92:4fc01daae5a5 768 */
bogdanm 92:4fc01daae5a5 769
bogdanm 92:4fc01daae5a5 770 typedef struct { /*!< RNG Structure */
bogdanm 92:4fc01daae5a5 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
bogdanm 92:4fc01daae5a5 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
bogdanm 92:4fc01daae5a5 773 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
bogdanm 92:4fc01daae5a5 775 __I uint32_t RESERVED1[63];
Kojto 97:433970e64889 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
bogdanm 92:4fc01daae5a5 777 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
bogdanm 92:4fc01daae5a5 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
bogdanm 92:4fc01daae5a5 780 __I uint32_t RESERVED3[126];
bogdanm 92:4fc01daae5a5 781 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 782 __I uint32_t VALUE; /*!< RNG random number. */
bogdanm 92:4fc01daae5a5 783 __I uint32_t RESERVED4[700];
bogdanm 92:4fc01daae5a5 784 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 785 } NRF_RNG_Type;
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787
bogdanm 92:4fc01daae5a5 788 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 789 /* ================ ECB ================ */
bogdanm 92:4fc01daae5a5 790 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 791
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 /**
bogdanm 92:4fc01daae5a5 794 * @brief AES ECB Mode Encryption. (ECB)
bogdanm 92:4fc01daae5a5 795 */
bogdanm 92:4fc01daae5a5 796
bogdanm 92:4fc01daae5a5 797 typedef struct { /*!< ECB Structure */
bogdanm 92:4fc01daae5a5 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
bogdanm 92:4fc01daae5a5 799 will not initiate a new encryption and the ERRORECB event will
bogdanm 92:4fc01daae5a5 800 be triggered. */
bogdanm 92:4fc01daae5a5 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
bogdanm 92:4fc01daae5a5 802 this will will trigger the ERRORECB event. */
bogdanm 92:4fc01daae5a5 803 __I uint32_t RESERVED0[62];
bogdanm 92:4fc01daae5a5 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
bogdanm 92:4fc01daae5a5 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
bogdanm 92:4fc01daae5a5 806 error. */
bogdanm 92:4fc01daae5a5 807 __I uint32_t RESERVED1[127];
bogdanm 92:4fc01daae5a5 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 810 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
bogdanm 92:4fc01daae5a5 812 __I uint32_t RESERVED3[701];
bogdanm 92:4fc01daae5a5 813 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 814 } NRF_ECB_Type;
bogdanm 92:4fc01daae5a5 815
bogdanm 92:4fc01daae5a5 816
bogdanm 92:4fc01daae5a5 817 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 818 /* ================ AAR ================ */
bogdanm 92:4fc01daae5a5 819 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 820
bogdanm 92:4fc01daae5a5 821
bogdanm 92:4fc01daae5a5 822 /**
bogdanm 92:4fc01daae5a5 823 * @brief Accelerated Address Resolver. (AAR)
bogdanm 92:4fc01daae5a5 824 */
bogdanm 92:4fc01daae5a5 825
bogdanm 92:4fc01daae5a5 826 typedef struct { /*!< AAR Structure */
bogdanm 92:4fc01daae5a5 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
bogdanm 92:4fc01daae5a5 828 data structure. */
bogdanm 92:4fc01daae5a5 829 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
bogdanm 92:4fc01daae5a5 831 __I uint32_t RESERVED1[61];
bogdanm 92:4fc01daae5a5 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
bogdanm 92:4fc01daae5a5 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
bogdanm 92:4fc01daae5a5 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
bogdanm 92:4fc01daae5a5 835 __I uint32_t RESERVED2[126];
bogdanm 92:4fc01daae5a5 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 838 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 839 __I uint32_t STATUS; /*!< Resolution status. */
bogdanm 92:4fc01daae5a5 840 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
bogdanm 92:4fc01daae5a5 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
bogdanm 92:4fc01daae5a5 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
bogdanm 92:4fc01daae5a5 844 __I uint32_t RESERVED5;
bogdanm 92:4fc01daae5a5 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 97:433970e64889 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 847 during resolution. A minimum of 3 bytes must be reserved. */
bogdanm 92:4fc01daae5a5 848 __I uint32_t RESERVED6[697];
bogdanm 92:4fc01daae5a5 849 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 850 } NRF_AAR_Type;
bogdanm 92:4fc01daae5a5 851
bogdanm 92:4fc01daae5a5 852
bogdanm 92:4fc01daae5a5 853 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 854 /* ================ CCM ================ */
bogdanm 92:4fc01daae5a5 855 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 856
bogdanm 92:4fc01daae5a5 857
bogdanm 92:4fc01daae5a5 858 /**
bogdanm 92:4fc01daae5a5 859 * @brief AES CCM Mode Encryption. (CCM)
bogdanm 92:4fc01daae5a5 860 */
bogdanm 92:4fc01daae5a5 861
bogdanm 92:4fc01daae5a5 862 typedef struct { /*!< CCM Structure */
bogdanm 92:4fc01daae5a5 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
bogdanm 92:4fc01daae5a5 864 itself when completed. */
bogdanm 92:4fc01daae5a5 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
bogdanm 92:4fc01daae5a5 866 completed. */
bogdanm 92:4fc01daae5a5 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
bogdanm 92:4fc01daae5a5 868 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
bogdanm 92:4fc01daae5a5 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
bogdanm 92:4fc01daae5a5 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
bogdanm 92:4fc01daae5a5 872 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
bogdanm 92:4fc01daae5a5 874 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 877 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
bogdanm 92:4fc01daae5a5 879 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 880 __IO uint32_t ENABLE; /*!< CCM enable. */
bogdanm 92:4fc01daae5a5 881 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 97:433970e64889 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Kojto 97:433970e64889 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Kojto 97:433970e64889 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Kojto 97:433970e64889 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 886 during resolution. A minimum of 43 bytes must be reserved. */
bogdanm 92:4fc01daae5a5 887 __I uint32_t RESERVED5[697];
bogdanm 92:4fc01daae5a5 888 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 889 } NRF_CCM_Type;
bogdanm 92:4fc01daae5a5 890
bogdanm 92:4fc01daae5a5 891
bogdanm 92:4fc01daae5a5 892 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 893 /* ================ WDT ================ */
bogdanm 92:4fc01daae5a5 894 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 895
bogdanm 92:4fc01daae5a5 896
bogdanm 92:4fc01daae5a5 897 /**
bogdanm 92:4fc01daae5a5 898 * @brief Watchdog Timer. (WDT)
bogdanm 92:4fc01daae5a5 899 */
bogdanm 92:4fc01daae5a5 900
bogdanm 92:4fc01daae5a5 901 typedef struct { /*!< WDT Structure */
bogdanm 92:4fc01daae5a5 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
bogdanm 92:4fc01daae5a5 903 __I uint32_t RESERVED0[63];
bogdanm 92:4fc01daae5a5 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
bogdanm 92:4fc01daae5a5 905 __I uint32_t RESERVED1[128];
bogdanm 92:4fc01daae5a5 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 908 __I uint32_t RESERVED2[61];
bogdanm 92:4fc01daae5a5 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
bogdanm 92:4fc01daae5a5 910 __I uint32_t REQSTATUS; /*!< Request status. */
bogdanm 92:4fc01daae5a5 911 __I uint32_t RESERVED3[63];
bogdanm 92:4fc01daae5a5 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
bogdanm 92:4fc01daae5a5 913 __IO uint32_t RREN; /*!< Reload request enable. */
bogdanm 92:4fc01daae5a5 914 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 92:4fc01daae5a5 915 __I uint32_t RESERVED4[60];
bogdanm 92:4fc01daae5a5 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
bogdanm 92:4fc01daae5a5 917 __I uint32_t RESERVED5[631];
bogdanm 92:4fc01daae5a5 918 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 919 } NRF_WDT_Type;
bogdanm 92:4fc01daae5a5 920
bogdanm 92:4fc01daae5a5 921
bogdanm 92:4fc01daae5a5 922 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 923 /* ================ QDEC ================ */
bogdanm 92:4fc01daae5a5 924 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 925
bogdanm 92:4fc01daae5a5 926
bogdanm 92:4fc01daae5a5 927 /**
bogdanm 92:4fc01daae5a5 928 * @brief Rotary decoder. (QDEC)
bogdanm 92:4fc01daae5a5 929 */
bogdanm 92:4fc01daae5a5 930
bogdanm 92:4fc01daae5a5 931 typedef struct { /*!< QDEC Structure */
bogdanm 92:4fc01daae5a5 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
bogdanm 92:4fc01daae5a5 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
bogdanm 92:4fc01daae5a5 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
bogdanm 92:4fc01daae5a5 935 and clears the ACC registers. */
bogdanm 92:4fc01daae5a5 936 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
bogdanm 92:4fc01daae5a5 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
bogdanm 92:4fc01daae5a5 939 ACC register different than zero. */
bogdanm 92:4fc01daae5a5 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
bogdanm 92:4fc01daae5a5 941 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
bogdanm 92:4fc01daae5a5 943 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 946 __I uint32_t RESERVED3[125];
bogdanm 92:4fc01daae5a5 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
bogdanm 92:4fc01daae5a5 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
bogdanm 92:4fc01daae5a5 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
bogdanm 92:4fc01daae5a5 950 __I int32_t SAMPLE; /*!< Motion sample value. */
bogdanm 92:4fc01daae5a5 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 92:4fc01daae5a5 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
bogdanm 92:4fc01daae5a5 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
bogdanm 92:4fc01daae5a5 954 task. */
bogdanm 92:4fc01daae5a5 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
bogdanm 92:4fc01daae5a5 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
bogdanm 92:4fc01daae5a5 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
bogdanm 92:4fc01daae5a5 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
bogdanm 92:4fc01daae5a5 959 __I uint32_t RESERVED4[5];
bogdanm 92:4fc01daae5a5 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
bogdanm 92:4fc01daae5a5 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
bogdanm 92:4fc01daae5a5 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
bogdanm 92:4fc01daae5a5 963 task. */
bogdanm 92:4fc01daae5a5 964 __I uint32_t RESERVED5[684];
bogdanm 92:4fc01daae5a5 965 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 966 } NRF_QDEC_Type;
bogdanm 92:4fc01daae5a5 967
bogdanm 92:4fc01daae5a5 968
bogdanm 92:4fc01daae5a5 969 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 970 /* ================ LPCOMP ================ */
bogdanm 92:4fc01daae5a5 971 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 972
bogdanm 92:4fc01daae5a5 973
bogdanm 92:4fc01daae5a5 974 /**
Kojto 97:433970e64889 975 * @brief Low power comparator. (LPCOMP)
bogdanm 92:4fc01daae5a5 976 */
bogdanm 92:4fc01daae5a5 977
bogdanm 92:4fc01daae5a5 978 typedef struct { /*!< LPCOMP Structure */
bogdanm 92:4fc01daae5a5 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 92:4fc01daae5a5 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 92:4fc01daae5a5 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 92:4fc01daae5a5 982 __I uint32_t RESERVED0[61];
bogdanm 92:4fc01daae5a5 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
bogdanm 92:4fc01daae5a5 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 92:4fc01daae5a5 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 92:4fc01daae5a5 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 92:4fc01daae5a5 987 __I uint32_t RESERVED1[60];
Kojto 97:433970e64889 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
bogdanm 92:4fc01daae5a5 989 __I uint32_t RESERVED2[64];
bogdanm 92:4fc01daae5a5 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 92:4fc01daae5a5 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 92:4fc01daae5a5 992 __I uint32_t RESERVED3[61];
bogdanm 92:4fc01daae5a5 993 __I uint32_t RESULT; /*!< Result of last compare. */
bogdanm 92:4fc01daae5a5 994 __I uint32_t RESERVED4[63];
bogdanm 92:4fc01daae5a5 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
bogdanm 92:4fc01daae5a5 996 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 92:4fc01daae5a5 997 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 92:4fc01daae5a5 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 92:4fc01daae5a5 999 __I uint32_t RESERVED5[4];
bogdanm 92:4fc01daae5a5 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
bogdanm 92:4fc01daae5a5 1001 __I uint32_t RESERVED6[694];
bogdanm 92:4fc01daae5a5 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 92:4fc01daae5a5 1003 } NRF_LPCOMP_Type;
bogdanm 92:4fc01daae5a5 1004
bogdanm 92:4fc01daae5a5 1005
bogdanm 92:4fc01daae5a5 1006 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1007 /* ================ SWI ================ */
bogdanm 92:4fc01daae5a5 1008 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1009
bogdanm 92:4fc01daae5a5 1010
bogdanm 92:4fc01daae5a5 1011 /**
bogdanm 92:4fc01daae5a5 1012 * @brief SW Interrupts. (SWI)
bogdanm 92:4fc01daae5a5 1013 */
bogdanm 92:4fc01daae5a5 1014
bogdanm 92:4fc01daae5a5 1015 typedef struct { /*!< SWI Structure */
bogdanm 92:4fc01daae5a5 1016 __I uint32_t UNUSED; /*!< Unused. */
bogdanm 92:4fc01daae5a5 1017 } NRF_SWI_Type;
bogdanm 92:4fc01daae5a5 1018
bogdanm 92:4fc01daae5a5 1019
bogdanm 92:4fc01daae5a5 1020 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1021 /* ================ NVMC ================ */
bogdanm 92:4fc01daae5a5 1022 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1023
bogdanm 92:4fc01daae5a5 1024
bogdanm 92:4fc01daae5a5 1025 /**
bogdanm 92:4fc01daae5a5 1026 * @brief Non Volatile Memory Controller. (NVMC)
bogdanm 92:4fc01daae5a5 1027 */
bogdanm 92:4fc01daae5a5 1028
bogdanm 92:4fc01daae5a5 1029 typedef struct { /*!< NVMC Structure */
bogdanm 92:4fc01daae5a5 1030 __I uint32_t RESERVED0[256];
bogdanm 92:4fc01daae5a5 1031 __I uint32_t READY; /*!< Ready flag. */
bogdanm 92:4fc01daae5a5 1032 __I uint32_t RESERVED1[64];
bogdanm 92:4fc01daae5a5 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 1034
Kojto 122:f9eeca106725 1035 union {
Kojto 122:f9eeca106725 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1038 };
bogdanm 92:4fc01daae5a5 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Kojto 122:f9eeca106725 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
bogdanm 92:4fc01daae5a5 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
bogdanm 92:4fc01daae5a5 1042 } NRF_NVMC_Type;
bogdanm 92:4fc01daae5a5 1043
bogdanm 92:4fc01daae5a5 1044
bogdanm 92:4fc01daae5a5 1045 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1046 /* ================ PPI ================ */
bogdanm 92:4fc01daae5a5 1047 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1048
bogdanm 92:4fc01daae5a5 1049
bogdanm 92:4fc01daae5a5 1050 /**
bogdanm 92:4fc01daae5a5 1051 * @brief PPI controller. (PPI)
bogdanm 92:4fc01daae5a5 1052 */
bogdanm 92:4fc01daae5a5 1053
bogdanm 92:4fc01daae5a5 1054 typedef struct { /*!< PPI Structure */
bogdanm 92:4fc01daae5a5 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
bogdanm 92:4fc01daae5a5 1056 __I uint32_t RESERVED0[312];
bogdanm 92:4fc01daae5a5 1057 __IO uint32_t CHEN; /*!< Channel enable. */
bogdanm 92:4fc01daae5a5 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
bogdanm 92:4fc01daae5a5 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
bogdanm 92:4fc01daae5a5 1060 __I uint32_t RESERVED1;
bogdanm 92:4fc01daae5a5 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
bogdanm 92:4fc01daae5a5 1062 __I uint32_t RESERVED2[156];
bogdanm 92:4fc01daae5a5 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
bogdanm 92:4fc01daae5a5 1064 } NRF_PPI_Type;
bogdanm 92:4fc01daae5a5 1065
bogdanm 92:4fc01daae5a5 1066
bogdanm 92:4fc01daae5a5 1067 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1068 /* ================ FICR ================ */
bogdanm 92:4fc01daae5a5 1069 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1070
bogdanm 92:4fc01daae5a5 1071
bogdanm 92:4fc01daae5a5 1072 /**
bogdanm 92:4fc01daae5a5 1073 * @brief Factory Information Configuration. (FICR)
bogdanm 92:4fc01daae5a5 1074 */
bogdanm 92:4fc01daae5a5 1075
bogdanm 92:4fc01daae5a5 1076 typedef struct { /*!< FICR Structure */
bogdanm 92:4fc01daae5a5 1077 __I uint32_t RESERVED0[4];
bogdanm 92:4fc01daae5a5 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
bogdanm 92:4fc01daae5a5 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
bogdanm 92:4fc01daae5a5 1080 __I uint32_t RESERVED1[4];
bogdanm 92:4fc01daae5a5 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
bogdanm 92:4fc01daae5a5 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
bogdanm 92:4fc01daae5a5 1083 __I uint32_t RESERVED2;
bogdanm 92:4fc01daae5a5 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 97:433970e64889 1085
Kojto 97:433970e64889 1086 union {
Kojto 97:433970e64889 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto 97:433970e64889 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto 97:433970e64889 1089 instead. */
Kojto 97:433970e64889 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Kojto 97:433970e64889 1091 };
bogdanm 92:4fc01daae5a5 1092 __I uint32_t RESERVED3[5];
bogdanm 92:4fc01daae5a5 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
bogdanm 92:4fc01daae5a5 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
bogdanm 92:4fc01daae5a5 1095 __I uint32_t RESERVED4[6];
bogdanm 92:4fc01daae5a5 1096 __I uint32_t ER[4]; /*!< Encryption root. */
bogdanm 92:4fc01daae5a5 1097 __I uint32_t IR[4]; /*!< Identity root. */
bogdanm 92:4fc01daae5a5 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
bogdanm 92:4fc01daae5a5 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
bogdanm 92:4fc01daae5a5 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 97:433970e64889 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto 97:433970e64889 1102 mode. */
Kojto 97:433970e64889 1103 __I uint32_t RESERVED5[10];
bogdanm 92:4fc01daae5a5 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
bogdanm 92:4fc01daae5a5 1105 mode. */
bogdanm 92:4fc01daae5a5 1106 } NRF_FICR_Type;
bogdanm 92:4fc01daae5a5 1107
bogdanm 92:4fc01daae5a5 1108
bogdanm 92:4fc01daae5a5 1109 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1110 /* ================ UICR ================ */
bogdanm 92:4fc01daae5a5 1111 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1112
bogdanm 92:4fc01daae5a5 1113
bogdanm 92:4fc01daae5a5 1114 /**
bogdanm 92:4fc01daae5a5 1115 * @brief User Information Configuration. (UICR)
bogdanm 92:4fc01daae5a5 1116 */
bogdanm 92:4fc01daae5a5 1117
bogdanm 92:4fc01daae5a5 1118 typedef struct { /*!< UICR Structure */
bogdanm 92:4fc01daae5a5 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
bogdanm 92:4fc01daae5a5 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
bogdanm 92:4fc01daae5a5 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
bogdanm 92:4fc01daae5a5 1122 __I uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 1123 __I uint32_t FWID; /*!< Firmware ID. */
Kojto 122:f9eeca106725 1124
Kojto 122:f9eeca106725 1125 union {
Kojto 122:f9eeca106725 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
Kojto 122:f9eeca106725 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Kojto 122:f9eeca106725 1128 };
Kojto 122:f9eeca106725 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
Kojto 122:f9eeca106725 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
bogdanm 92:4fc01daae5a5 1131 } NRF_UICR_Type;
bogdanm 92:4fc01daae5a5 1132
bogdanm 92:4fc01daae5a5 1133
bogdanm 92:4fc01daae5a5 1134 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1135 /* ================ GPIO ================ */
bogdanm 92:4fc01daae5a5 1136 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1137
bogdanm 92:4fc01daae5a5 1138
bogdanm 92:4fc01daae5a5 1139 /**
bogdanm 92:4fc01daae5a5 1140 * @brief General purpose input and output. (GPIO)
bogdanm 92:4fc01daae5a5 1141 */
bogdanm 92:4fc01daae5a5 1142
bogdanm 92:4fc01daae5a5 1143 typedef struct { /*!< GPIO Structure */
bogdanm 92:4fc01daae5a5 1144 __I uint32_t RESERVED0[321];
bogdanm 92:4fc01daae5a5 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
bogdanm 92:4fc01daae5a5 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
bogdanm 92:4fc01daae5a5 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
bogdanm 92:4fc01daae5a5 1148 __I uint32_t IN; /*!< Read GPIO port. */
bogdanm 92:4fc01daae5a5 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
bogdanm 92:4fc01daae5a5 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
bogdanm 92:4fc01daae5a5 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
bogdanm 92:4fc01daae5a5 1152 __I uint32_t RESERVED1[120];
bogdanm 92:4fc01daae5a5 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
bogdanm 92:4fc01daae5a5 1154 } NRF_GPIO_Type;
bogdanm 92:4fc01daae5a5 1155
bogdanm 92:4fc01daae5a5 1156
bogdanm 92:4fc01daae5a5 1157 /* -------------------- End of section using anonymous unions ------------------- */
bogdanm 92:4fc01daae5a5 1158 #if defined(__CC_ARM)
bogdanm 92:4fc01daae5a5 1159 #pragma pop
bogdanm 92:4fc01daae5a5 1160 #elif defined(__ICCARM__)
bogdanm 92:4fc01daae5a5 1161 /* leave anonymous unions enabled */
bogdanm 92:4fc01daae5a5 1162 #elif defined(__GNUC__)
bogdanm 92:4fc01daae5a5 1163 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 1164 #elif defined(__TMS470__)
bogdanm 92:4fc01daae5a5 1165 /* anonymous unions are enabled by default */
bogdanm 92:4fc01daae5a5 1166 #elif defined(__TASKING__)
bogdanm 92:4fc01daae5a5 1167 #pragma warning restore
bogdanm 92:4fc01daae5a5 1168 #else
bogdanm 92:4fc01daae5a5 1169 #warning Not supported compiler type
bogdanm 92:4fc01daae5a5 1170 #endif
bogdanm 92:4fc01daae5a5 1171
bogdanm 92:4fc01daae5a5 1172
bogdanm 92:4fc01daae5a5 1173
bogdanm 92:4fc01daae5a5 1174
bogdanm 92:4fc01daae5a5 1175 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1176 /* ================ Peripheral memory map ================ */
bogdanm 92:4fc01daae5a5 1177 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1178
bogdanm 92:4fc01daae5a5 1179 #define NRF_POWER_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1180 #define NRF_CLOCK_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1181 #define NRF_MPU_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1182 #define NRF_AMLI_BASE 0x40000000UL
bogdanm 92:4fc01daae5a5 1183 #define NRF_RADIO_BASE 0x40001000UL
bogdanm 92:4fc01daae5a5 1184 #define NRF_UART0_BASE 0x40002000UL
bogdanm 92:4fc01daae5a5 1185 #define NRF_SPI0_BASE 0x40003000UL
bogdanm 92:4fc01daae5a5 1186 #define NRF_TWI0_BASE 0x40003000UL
bogdanm 92:4fc01daae5a5 1187 #define NRF_SPI1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1188 #define NRF_TWI1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1189 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 97:433970e64889 1190 #define NRF_SPIM1_BASE 0x40004000UL
bogdanm 92:4fc01daae5a5 1191 #define NRF_GPIOTE_BASE 0x40006000UL
bogdanm 92:4fc01daae5a5 1192 #define NRF_ADC_BASE 0x40007000UL
bogdanm 92:4fc01daae5a5 1193 #define NRF_TIMER0_BASE 0x40008000UL
bogdanm 92:4fc01daae5a5 1194 #define NRF_TIMER1_BASE 0x40009000UL
bogdanm 92:4fc01daae5a5 1195 #define NRF_TIMER2_BASE 0x4000A000UL
bogdanm 92:4fc01daae5a5 1196 #define NRF_RTC0_BASE 0x4000B000UL
bogdanm 92:4fc01daae5a5 1197 #define NRF_TEMP_BASE 0x4000C000UL
bogdanm 92:4fc01daae5a5 1198 #define NRF_RNG_BASE 0x4000D000UL
bogdanm 92:4fc01daae5a5 1199 #define NRF_ECB_BASE 0x4000E000UL
bogdanm 92:4fc01daae5a5 1200 #define NRF_AAR_BASE 0x4000F000UL
bogdanm 92:4fc01daae5a5 1201 #define NRF_CCM_BASE 0x4000F000UL
bogdanm 92:4fc01daae5a5 1202 #define NRF_WDT_BASE 0x40010000UL
bogdanm 92:4fc01daae5a5 1203 #define NRF_RTC1_BASE 0x40011000UL
bogdanm 92:4fc01daae5a5 1204 #define NRF_QDEC_BASE 0x40012000UL
bogdanm 92:4fc01daae5a5 1205 #define NRF_LPCOMP_BASE 0x40013000UL
bogdanm 92:4fc01daae5a5 1206 #define NRF_SWI_BASE 0x40014000UL
bogdanm 92:4fc01daae5a5 1207 #define NRF_NVMC_BASE 0x4001E000UL
bogdanm 92:4fc01daae5a5 1208 #define NRF_PPI_BASE 0x4001F000UL
bogdanm 92:4fc01daae5a5 1209 #define NRF_FICR_BASE 0x10000000UL
bogdanm 92:4fc01daae5a5 1210 #define NRF_UICR_BASE 0x10001000UL
bogdanm 92:4fc01daae5a5 1211 #define NRF_GPIO_BASE 0x50000000UL
bogdanm 92:4fc01daae5a5 1212
bogdanm 92:4fc01daae5a5 1213
bogdanm 92:4fc01daae5a5 1214 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1215 /* ================ Peripheral declaration ================ */
bogdanm 92:4fc01daae5a5 1216 /* ================================================================================ */
bogdanm 92:4fc01daae5a5 1217
bogdanm 92:4fc01daae5a5 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
bogdanm 92:4fc01daae5a5 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
bogdanm 92:4fc01daae5a5 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
bogdanm 92:4fc01daae5a5 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
bogdanm 92:4fc01daae5a5 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
bogdanm 92:4fc01daae5a5 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
bogdanm 92:4fc01daae5a5 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
bogdanm 92:4fc01daae5a5 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
bogdanm 92:4fc01daae5a5 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
bogdanm 92:4fc01daae5a5 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
bogdanm 92:4fc01daae5a5 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 97:433970e64889 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
bogdanm 92:4fc01daae5a5 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
bogdanm 92:4fc01daae5a5 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
bogdanm 92:4fc01daae5a5 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
bogdanm 92:4fc01daae5a5 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
bogdanm 92:4fc01daae5a5 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
bogdanm 92:4fc01daae5a5 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
bogdanm 92:4fc01daae5a5 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
bogdanm 92:4fc01daae5a5 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
bogdanm 92:4fc01daae5a5 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
bogdanm 92:4fc01daae5a5 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
bogdanm 92:4fc01daae5a5 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
bogdanm 92:4fc01daae5a5 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
bogdanm 92:4fc01daae5a5 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
bogdanm 92:4fc01daae5a5 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
bogdanm 92:4fc01daae5a5 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
bogdanm 92:4fc01daae5a5 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
bogdanm 92:4fc01daae5a5 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
bogdanm 92:4fc01daae5a5 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
bogdanm 92:4fc01daae5a5 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
bogdanm 92:4fc01daae5a5 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
bogdanm 92:4fc01daae5a5 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
bogdanm 92:4fc01daae5a5 1251
bogdanm 92:4fc01daae5a5 1252
bogdanm 92:4fc01daae5a5 1253 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 122:f9eeca106725 1254 /** @} */ /* End of group nrf51 */
bogdanm 92:4fc01daae5a5 1255 /** @} */ /* End of group Nordic Semiconductor */
bogdanm 92:4fc01daae5a5 1256
bogdanm 92:4fc01daae5a5 1257 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1258 }
bogdanm 92:4fc01daae5a5 1259 #endif
bogdanm 92:4fc01daae5a5 1260
bogdanm 92:4fc01daae5a5 1261
Kojto 122:f9eeca106725 1262 #endif /* nrf51_H */