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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
116:c0f6e94411f5 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f4xx_hal_rcc.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 86:04dd9b1680ae 7 * @brief Header file of RCC HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F4xx_HAL_RCC_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F4xx_HAL_RCC_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f4xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
Kojto 99:dbbf35b96557 49 /* Include RCC HAL Extended module */
Kojto 99:dbbf35b96557 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 99:dbbf35b96557 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 99:dbbf35b96557 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
Kojto 99:dbbf35b96557 57 /** @addtogroup RCC
bogdanm 86:04dd9b1680ae 58 * @{
bogdanm 86:04dd9b1680ae 59 */
bogdanm 86:04dd9b1680ae 60
Kojto 99:dbbf35b96557 61 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 99:dbbf35b96557 63 * @{
bogdanm 86:04dd9b1680ae 64 */
Kojto 99:dbbf35b96557 65
bogdanm 86:04dd9b1680ae 66 /**
bogdanm 86:04dd9b1680ae 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 86:04dd9b1680ae 68 */
bogdanm 86:04dd9b1680ae 69 typedef struct
bogdanm 86:04dd9b1680ae 70 {
bogdanm 86:04dd9b1680ae 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 79
bogdanm 86:04dd9b1680ae 80 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 86:04dd9b1680ae 82
Kojto 122:f9eeca106725 83 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 122:f9eeca106725 85
bogdanm 86:04dd9b1680ae 86 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 86:04dd9b1680ae 87 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 86:04dd9b1680ae 88
Kojto 122:f9eeca106725 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 86:04dd9b1680ae 90 }RCC_OscInitTypeDef;
bogdanm 86:04dd9b1680ae 91
bogdanm 86:04dd9b1680ae 92 /**
bogdanm 86:04dd9b1680ae 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 86:04dd9b1680ae 94 */
bogdanm 86:04dd9b1680ae 95 typedef struct
bogdanm 86:04dd9b1680ae 96 {
bogdanm 86:04dd9b1680ae 97 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 86:04dd9b1680ae 98 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 86:04dd9b1680ae 99
bogdanm 86:04dd9b1680ae 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 86:04dd9b1680ae 101 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 86:04dd9b1680ae 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 86:04dd9b1680ae 105
bogdanm 86:04dd9b1680ae 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 86:04dd9b1680ae 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 86:04dd9b1680ae 108
bogdanm 86:04dd9b1680ae 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 86:04dd9b1680ae 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 86:04dd9b1680ae 111
bogdanm 86:04dd9b1680ae 112 }RCC_ClkInitTypeDef;
bogdanm 86:04dd9b1680ae 113
bogdanm 86:04dd9b1680ae 114 /**
bogdanm 86:04dd9b1680ae 115 * @}
bogdanm 86:04dd9b1680ae 116 */
bogdanm 86:04dd9b1680ae 117
Kojto 99:dbbf35b96557 118 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 99:dbbf35b96557 120 * @{
Kojto 99:dbbf35b96557 121 */
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm 86:04dd9b1680ae 124 * @{
bogdanm 86:04dd9b1680ae 125 */
Kojto 122:f9eeca106725 126 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 127 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 128 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 129 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 130 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
bogdanm 86:04dd9b1680ae 131 /**
bogdanm 86:04dd9b1680ae 132 * @}
bogdanm 86:04dd9b1680ae 133 */
bogdanm 86:04dd9b1680ae 134
Kojto 99:dbbf35b96557 135 /** @defgroup RCC_HSE_Config HSE Config
bogdanm 86:04dd9b1680ae 136 * @{
bogdanm 86:04dd9b1680ae 137 */
Kojto 122:f9eeca106725 138 #define RCC_HSE_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 139 #define RCC_HSE_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 140 #define RCC_HSE_BYPASS ((uint8_t)0x05U)
bogdanm 86:04dd9b1680ae 141 /**
bogdanm 86:04dd9b1680ae 142 * @}
bogdanm 86:04dd9b1680ae 143 */
bogdanm 86:04dd9b1680ae 144
Kojto 99:dbbf35b96557 145 /** @defgroup RCC_LSE_Config LSE Config
bogdanm 86:04dd9b1680ae 146 * @{
bogdanm 86:04dd9b1680ae 147 */
Kojto 122:f9eeca106725 148 #define RCC_LSE_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 149 #define RCC_LSE_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 150 #define RCC_LSE_BYPASS ((uint8_t)0x05U)
bogdanm 86:04dd9b1680ae 151 /**
bogdanm 86:04dd9b1680ae 152 * @}
bogdanm 86:04dd9b1680ae 153 */
bogdanm 86:04dd9b1680ae 154
Kojto 99:dbbf35b96557 155 /** @defgroup RCC_HSI_Config HSI Config
bogdanm 86:04dd9b1680ae 156 * @{
bogdanm 86:04dd9b1680ae 157 */
Kojto 122:f9eeca106725 158 #define RCC_HSI_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 159 #define RCC_HSI_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 160
Kojto 122:f9eeca106725 161 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
bogdanm 86:04dd9b1680ae 162 /**
bogdanm 86:04dd9b1680ae 163 * @}
bogdanm 86:04dd9b1680ae 164 */
bogdanm 86:04dd9b1680ae 165
Kojto 99:dbbf35b96557 166 /** @defgroup RCC_LSI_Config LSI Config
bogdanm 86:04dd9b1680ae 167 * @{
bogdanm 86:04dd9b1680ae 168 */
Kojto 122:f9eeca106725 169 #define RCC_LSI_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 170 #define RCC_LSI_ON ((uint8_t)0x01U)
bogdanm 86:04dd9b1680ae 171 /**
bogdanm 86:04dd9b1680ae 172 * @}
bogdanm 86:04dd9b1680ae 173 */
bogdanm 86:04dd9b1680ae 174
Kojto 99:dbbf35b96557 175 /** @defgroup RCC_PLL_Config PLL Config
bogdanm 86:04dd9b1680ae 176 * @{
bogdanm 86:04dd9b1680ae 177 */
Kojto 122:f9eeca106725 178 #define RCC_PLL_NONE ((uint8_t)0x00U)
Kojto 122:f9eeca106725 179 #define RCC_PLL_OFF ((uint8_t)0x01U)
Kojto 122:f9eeca106725 180 #define RCC_PLL_ON ((uint8_t)0x02U)
bogdanm 86:04dd9b1680ae 181 /**
bogdanm 86:04dd9b1680ae 182 * @}
bogdanm 86:04dd9b1680ae 183 */
bogdanm 86:04dd9b1680ae 184
Kojto 99:dbbf35b96557 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
bogdanm 86:04dd9b1680ae 186 * @{
bogdanm 86:04dd9b1680ae 187 */
Kojto 122:f9eeca106725 188 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 189 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 190 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
Kojto 122:f9eeca106725 191 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
bogdanm 86:04dd9b1680ae 192 /**
bogdanm 86:04dd9b1680ae 193 * @}
bogdanm 86:04dd9b1680ae 194 */
bogdanm 86:04dd9b1680ae 195
Kojto 99:dbbf35b96557 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm 86:04dd9b1680ae 197 * @{
bogdanm 86:04dd9b1680ae 198 */
bogdanm 86:04dd9b1680ae 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm 86:04dd9b1680ae 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm 86:04dd9b1680ae 201 /**
bogdanm 86:04dd9b1680ae 202 * @}
bogdanm 86:04dd9b1680ae 203 */
bogdanm 86:04dd9b1680ae 204
Kojto 99:dbbf35b96557 205 /** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm 86:04dd9b1680ae 206 * @{
bogdanm 86:04dd9b1680ae 207 */
Kojto 122:f9eeca106725 208 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 209 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 210 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 211 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
bogdanm 86:04dd9b1680ae 212 /**
bogdanm 86:04dd9b1680ae 213 * @}
bogdanm 86:04dd9b1680ae 214 */
bogdanm 86:04dd9b1680ae 215
Kojto 99:dbbf35b96557 216 /** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm 86:04dd9b1680ae 217 * @{
bogdanm 86:04dd9b1680ae 218 */
bogdanm 86:04dd9b1680ae 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 86:04dd9b1680ae 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 86:04dd9b1680ae 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 99:dbbf35b96557 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
bogdanm 86:04dd9b1680ae 223 /**
bogdanm 86:04dd9b1680ae 224 * @}
Kojto 99:dbbf35b96557 225 */
bogdanm 86:04dd9b1680ae 226
Kojto 99:dbbf35b96557 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 99:dbbf35b96557 228 * @{
Kojto 99:dbbf35b96557 229 */
Kojto 99:dbbf35b96557 230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 99:dbbf35b96557 231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 99:dbbf35b96557 232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 122:f9eeca106725 233 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
Kojto 99:dbbf35b96557 234 /**
Kojto 99:dbbf35b96557 235 * @}
Kojto 99:dbbf35b96557 236 */
Kojto 99:dbbf35b96557 237
Kojto 99:dbbf35b96557 238 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm 86:04dd9b1680ae 239 * @{
bogdanm 86:04dd9b1680ae 240 */
bogdanm 86:04dd9b1680ae 241 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 86:04dd9b1680ae 242 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 86:04dd9b1680ae 243 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 86:04dd9b1680ae 244 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 86:04dd9b1680ae 245 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 86:04dd9b1680ae 246 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 86:04dd9b1680ae 247 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 86:04dd9b1680ae 248 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 86:04dd9b1680ae 249 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 86:04dd9b1680ae 250 /**
bogdanm 86:04dd9b1680ae 251 * @}
bogdanm 86:04dd9b1680ae 252 */
bogdanm 86:04dd9b1680ae 253
Kojto 99:dbbf35b96557 254 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
bogdanm 86:04dd9b1680ae 255 * @{
bogdanm 86:04dd9b1680ae 256 */
bogdanm 86:04dd9b1680ae 257 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 86:04dd9b1680ae 258 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 86:04dd9b1680ae 259 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 86:04dd9b1680ae 260 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 86:04dd9b1680ae 261 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 86:04dd9b1680ae 262 /**
bogdanm 86:04dd9b1680ae 263 * @}
bogdanm 86:04dd9b1680ae 264 */
bogdanm 86:04dd9b1680ae 265
Kojto 99:dbbf35b96557 266 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm 86:04dd9b1680ae 267 * @{
bogdanm 86:04dd9b1680ae 268 */
Kojto 122:f9eeca106725 269 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 270 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 271 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
Kojto 122:f9eeca106725 272 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
Kojto 122:f9eeca106725 273 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
Kojto 122:f9eeca106725 274 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
Kojto 122:f9eeca106725 275 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
Kojto 122:f9eeca106725 276 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
Kojto 122:f9eeca106725 277 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
Kojto 122:f9eeca106725 278 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
Kojto 122:f9eeca106725 279 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
Kojto 122:f9eeca106725 280 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
Kojto 122:f9eeca106725 281 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
Kojto 122:f9eeca106725 282 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
Kojto 122:f9eeca106725 283 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
Kojto 122:f9eeca106725 284 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
Kojto 122:f9eeca106725 285 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
Kojto 122:f9eeca106725 286 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
Kojto 122:f9eeca106725 287 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
Kojto 122:f9eeca106725 288 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
Kojto 122:f9eeca106725 289 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
Kojto 122:f9eeca106725 290 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
Kojto 122:f9eeca106725 291 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
Kojto 122:f9eeca106725 292 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
Kojto 122:f9eeca106725 293 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
Kojto 122:f9eeca106725 294 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
Kojto 122:f9eeca106725 295 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
Kojto 122:f9eeca106725 296 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
Kojto 122:f9eeca106725 297 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
Kojto 122:f9eeca106725 298 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
Kojto 122:f9eeca106725 299 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
Kojto 122:f9eeca106725 300 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
bogdanm 86:04dd9b1680ae 301 /**
bogdanm 86:04dd9b1680ae 302 * @}
bogdanm 86:04dd9b1680ae 303 */
bogdanm 86:04dd9b1680ae 304
Kojto 99:dbbf35b96557 305 /** @defgroup RCC_MCO_Index MCO Index
bogdanm 86:04dd9b1680ae 306 * @{
bogdanm 86:04dd9b1680ae 307 */
Kojto 122:f9eeca106725 308 #define RCC_MCO1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 309 #define RCC_MCO2 ((uint32_t)0x00000001U)
bogdanm 86:04dd9b1680ae 310 /**
bogdanm 86:04dd9b1680ae 311 * @}
bogdanm 86:04dd9b1680ae 312 */
bogdanm 86:04dd9b1680ae 313
Kojto 99:dbbf35b96557 314 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
bogdanm 86:04dd9b1680ae 315 * @{
bogdanm 86:04dd9b1680ae 316 */
Kojto 122:f9eeca106725 317 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
bogdanm 86:04dd9b1680ae 318 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm 86:04dd9b1680ae 319 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm 86:04dd9b1680ae 320 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm 86:04dd9b1680ae 321 /**
bogdanm 86:04dd9b1680ae 322 * @}
bogdanm 86:04dd9b1680ae 323 */
bogdanm 86:04dd9b1680ae 324
Kojto 99:dbbf35b96557 325 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
bogdanm 86:04dd9b1680ae 326 * @{
bogdanm 86:04dd9b1680ae 327 */
Kojto 122:f9eeca106725 328 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
bogdanm 86:04dd9b1680ae 329 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm 86:04dd9b1680ae 330 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
bogdanm 86:04dd9b1680ae 331 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
bogdanm 86:04dd9b1680ae 332 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm 86:04dd9b1680ae 333 /**
bogdanm 86:04dd9b1680ae 334 * @}
bogdanm 86:04dd9b1680ae 335 */
bogdanm 86:04dd9b1680ae 336
Kojto 99:dbbf35b96557 337 /** @defgroup RCC_Interrupt Interrupts
bogdanm 86:04dd9b1680ae 338 * @{
bogdanm 86:04dd9b1680ae 339 */
Kojto 122:f9eeca106725 340 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
Kojto 122:f9eeca106725 341 #define RCC_IT_LSERDY ((uint8_t)0x02U)
Kojto 122:f9eeca106725 342 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
Kojto 122:f9eeca106725 343 #define RCC_IT_HSERDY ((uint8_t)0x08U)
Kojto 122:f9eeca106725 344 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
Kojto 122:f9eeca106725 345 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
Kojto 122:f9eeca106725 346 #define RCC_IT_CSS ((uint8_t)0x80U)
bogdanm 86:04dd9b1680ae 347 /**
bogdanm 86:04dd9b1680ae 348 * @}
bogdanm 86:04dd9b1680ae 349 */
bogdanm 86:04dd9b1680ae 350
Kojto 99:dbbf35b96557 351 /** @defgroup RCC_Flag Flags
bogdanm 86:04dd9b1680ae 352 * Elements values convention: 0XXYYYYYb
bogdanm 86:04dd9b1680ae 353 * - YYYYY : Flag position in the register
bogdanm 86:04dd9b1680ae 354 * - 0XX : Register index
bogdanm 86:04dd9b1680ae 355 * - 01: CR register
bogdanm 86:04dd9b1680ae 356 * - 10: BDCR register
bogdanm 86:04dd9b1680ae 357 * - 11: CSR register
bogdanm 86:04dd9b1680ae 358 * @{
bogdanm 86:04dd9b1680ae 359 */
bogdanm 86:04dd9b1680ae 360 /* Flags in the CR register */
Kojto 122:f9eeca106725 361 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
Kojto 122:f9eeca106725 362 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
Kojto 122:f9eeca106725 363 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
Kojto 122:f9eeca106725 364 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
bogdanm 86:04dd9b1680ae 365
bogdanm 86:04dd9b1680ae 366 /* Flags in the BDCR register */
Kojto 122:f9eeca106725 367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
bogdanm 86:04dd9b1680ae 368
bogdanm 86:04dd9b1680ae 369 /* Flags in the CSR register */
Kojto 122:f9eeca106725 370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
Kojto 122:f9eeca106725 371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
Kojto 122:f9eeca106725 372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
Kojto 122:f9eeca106725 373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
Kojto 122:f9eeca106725 374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
Kojto 122:f9eeca106725 375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
Kojto 122:f9eeca106725 376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
Kojto 122:f9eeca106725 377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
bogdanm 86:04dd9b1680ae 378 /**
bogdanm 86:04dd9b1680ae 379 * @}
bogdanm 86:04dd9b1680ae 380 */
bogdanm 86:04dd9b1680ae 381
bogdanm 86:04dd9b1680ae 382 /**
bogdanm 86:04dd9b1680ae 383 * @}
Kojto 99:dbbf35b96557 384 */
Kojto 99:dbbf35b96557 385
bogdanm 86:04dd9b1680ae 386 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 387 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 99:dbbf35b96557 388 * @{
Kojto 99:dbbf35b96557 389 */
bogdanm 86:04dd9b1680ae 390
Kojto 99:dbbf35b96557 391 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 392 * @brief Enable or disable the AHB1 peripheral clock.
bogdanm 86:04dd9b1680ae 393 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 394 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 395 * using it.
Kojto 99:dbbf35b96557 396 * @{
bogdanm 86:04dd9b1680ae 397 */
Kojto 122:f9eeca106725 398 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 399 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 401 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 403 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 404 } while(0)
Kojto 122:f9eeca106725 405 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 406 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 408 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 410 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 411 } while(0)
Kojto 122:f9eeca106725 412 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 413 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 415 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 417 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 418 } while(0)
Kojto 122:f9eeca106725 419 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 420 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 422 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 424 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 425 } while(0)
Kojto 122:f9eeca106725 426 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 427 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 428 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 429 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 430 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 431 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 432 } while(0)
Kojto 99:dbbf35b96557 433 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 434 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 436 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 438 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 439 } while(0)
bogdanm 86:04dd9b1680ae 440
Kojto 99:dbbf35b96557 441 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 99:dbbf35b96557 442 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 99:dbbf35b96557 443 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 99:dbbf35b96557 444 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 99:dbbf35b96557 445 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 99:dbbf35b96557 446 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 99:dbbf35b96557 447 /**
Kojto 99:dbbf35b96557 448 * @}
Kojto 99:dbbf35b96557 449 */
Kojto 99:dbbf35b96557 450
Kojto 122:f9eeca106725 451 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 452 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 122:f9eeca106725 453 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 454 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 455 * using it.
Kojto 122:f9eeca106725 456 * @{
Kojto 122:f9eeca106725 457 */
Kojto 122:f9eeca106725 458 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto 122:f9eeca106725 459 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto 122:f9eeca106725 460 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto 122:f9eeca106725 461 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto 122:f9eeca106725 462 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
Kojto 122:f9eeca106725 463 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 464
Kojto 122:f9eeca106725 465 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto 122:f9eeca106725 466 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto 122:f9eeca106725 467 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto 122:f9eeca106725 468 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto 122:f9eeca106725 469 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
Kojto 122:f9eeca106725 470 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 471 /**
Kojto 122:f9eeca106725 472 * @}
Kojto 122:f9eeca106725 473 */
Kojto 122:f9eeca106725 474
Kojto 99:dbbf35b96557 475 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 476 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 477 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 478 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 479 * using it.
Kojto 99:dbbf35b96557 480 * @{
bogdanm 86:04dd9b1680ae 481 */
Kojto 99:dbbf35b96557 482 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 483 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 485 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 487 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 488 } while(0)
Kojto 99:dbbf35b96557 489 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 490 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 492 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 494 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 495 } while(0)
Kojto 99:dbbf35b96557 496 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 497 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 499 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 501 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 502 } while(0)
Kojto 99:dbbf35b96557 503 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 504 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 506 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 508 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 509 } while(0)
Kojto 99:dbbf35b96557 510 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 511 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 513 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 515 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 516 } while(0)
Kojto 99:dbbf35b96557 517 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 518 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 519 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 520 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 521 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 522 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 523 } while(0)
Kojto 99:dbbf35b96557 524 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 525 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 526 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 527 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 528 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 529 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 530 } while(0)
Kojto 110:165afa46840b 531
Kojto 99:dbbf35b96557 532 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 99:dbbf35b96557 533 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 99:dbbf35b96557 534 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 99:dbbf35b96557 535 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 99:dbbf35b96557 536 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 99:dbbf35b96557 537 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 99:dbbf35b96557 538 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 99:dbbf35b96557 539 /**
Kojto 99:dbbf35b96557 540 * @}
Kojto 99:dbbf35b96557 541 */
bogdanm 86:04dd9b1680ae 542
Kojto 122:f9eeca106725 543 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 544 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 122:f9eeca106725 545 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 546 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 547 * using it.
Kojto 122:f9eeca106725 548 * @{
Kojto 122:f9eeca106725 549 */
Kojto 122:f9eeca106725 550 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 122:f9eeca106725 551 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 122:f9eeca106725 552 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 553 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto 122:f9eeca106725 554 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 122:f9eeca106725 555 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 556 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 122:f9eeca106725 557
Kojto 122:f9eeca106725 558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 122:f9eeca106725 559 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 122:f9eeca106725 560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 561 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto 122:f9eeca106725 562 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 122:f9eeca106725 563 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 564 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 122:f9eeca106725 565 /**
Kojto 122:f9eeca106725 566 * @}
Kojto 122:f9eeca106725 567 */
Kojto 122:f9eeca106725 568
Kojto 122:f9eeca106725 569 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 570 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 571 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 572 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 573 * using it.
Kojto 99:dbbf35b96557 574 * @{
bogdanm 86:04dd9b1680ae 575 */
Kojto 99:dbbf35b96557 576 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 577 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 579 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 581 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 582 } while(0)
Kojto 99:dbbf35b96557 583 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 584 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 586 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 588 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 589 } while(0)
Kojto 99:dbbf35b96557 590 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 591 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 592 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 593 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 594 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 595 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 596 } while(0)
Kojto 99:dbbf35b96557 597 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 598 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 599 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 600 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 601 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 602 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 603 } while(0)
Kojto 99:dbbf35b96557 604 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 605 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 606 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 607 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 608 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 609 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 610 } while(0)
Kojto 99:dbbf35b96557 611 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 612 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 613 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 614 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 615 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 616 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 617 } while(0)
Kojto 99:dbbf35b96557 618 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 619 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 620 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 621 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 622 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 623 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 624 } while(0)
Kojto 99:dbbf35b96557 625 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 626 __IO uint32_t tmpreg = 0x00U; \
Kojto 99:dbbf35b96557 627 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 628 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 629 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 630 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 631 } while(0)
bogdanm 86:04dd9b1680ae 632
Kojto 99:dbbf35b96557 633 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 99:dbbf35b96557 634 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 99:dbbf35b96557 635 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 99:dbbf35b96557 636 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 99:dbbf35b96557 637 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 99:dbbf35b96557 638 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 99:dbbf35b96557 639 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 99:dbbf35b96557 640 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 99:dbbf35b96557 641 /**
Kojto 99:dbbf35b96557 642 * @}
Kojto 99:dbbf35b96557 643 */
bogdanm 86:04dd9b1680ae 644
Kojto 122:f9eeca106725 645 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 646 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 122:f9eeca106725 647 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 648 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 649 * using it.
Kojto 122:f9eeca106725 650 * @{
Kojto 122:f9eeca106725 651 */
Kojto 122:f9eeca106725 652 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 122:f9eeca106725 653 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 122:f9eeca106725 654 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto 122:f9eeca106725 655 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 122:f9eeca106725 656 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 657 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 122:f9eeca106725 658 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 122:f9eeca106725 659 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 122:f9eeca106725 660
Kojto 122:f9eeca106725 661 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 122:f9eeca106725 662 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 122:f9eeca106725 663 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto 122:f9eeca106725 664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 122:f9eeca106725 665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 666 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 122:f9eeca106725 667 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 122:f9eeca106725 668 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 122:f9eeca106725 669 /**
Kojto 122:f9eeca106725 670 * @}
Kojto 122:f9eeca106725 671 */
Kojto 122:f9eeca106725 672
Kojto 99:dbbf35b96557 673 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 99:dbbf35b96557 674 * @brief Force or release AHB1 peripheral reset.
Kojto 99:dbbf35b96557 675 * @{
bogdanm 86:04dd9b1680ae 676 */
Kojto 122:f9eeca106725 677 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 678 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 679 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 680 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 681 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 682 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 683 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
bogdanm 86:04dd9b1680ae 684
Kojto 122:f9eeca106725 685 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Kojto 99:dbbf35b96557 686 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 687 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 688 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 689 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 690 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 691 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 99:dbbf35b96557 692 /**
Kojto 99:dbbf35b96557 693 * @}
Kojto 99:dbbf35b96557 694 */
bogdanm 86:04dd9b1680ae 695
Kojto 99:dbbf35b96557 696 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 99:dbbf35b96557 697 * @brief Force or release APB1 peripheral reset.
Kojto 99:dbbf35b96557 698 * @{
Kojto 99:dbbf35b96557 699 */
Kojto 122:f9eeca106725 700 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 701 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 702 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 703 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 704 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 705 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 706 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 707 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 86:04dd9b1680ae 708
Kojto 122:f9eeca106725 709 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Kojto 99:dbbf35b96557 710 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 711 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 712 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 713 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 714 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 715 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 716 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 99:dbbf35b96557 717 /**
Kojto 99:dbbf35b96557 718 * @}
Kojto 99:dbbf35b96557 719 */
bogdanm 86:04dd9b1680ae 720
Kojto 99:dbbf35b96557 721 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 99:dbbf35b96557 722 * @brief Force or release APB2 peripheral reset.
Kojto 99:dbbf35b96557 723 * @{
bogdanm 86:04dd9b1680ae 724 */
Kojto 122:f9eeca106725 725 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto 99:dbbf35b96557 726 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 727 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 728 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 729 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 730 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 731 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 732 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 733 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
bogdanm 86:04dd9b1680ae 734
Kojto 122:f9eeca106725 735 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Kojto 99:dbbf35b96557 736 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 737 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 738 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 739 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 740 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 741 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 742 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 743 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 99:dbbf35b96557 744 /**
Kojto 99:dbbf35b96557 745 * @}
Kojto 99:dbbf35b96557 746 */
bogdanm 86:04dd9b1680ae 747
Kojto 99:dbbf35b96557 748 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 749 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 750 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 751 * power consumption.
Kojto 99:dbbf35b96557 752 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 753 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 754 * @{
bogdanm 86:04dd9b1680ae 755 */
Kojto 99:dbbf35b96557 756 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 757 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 758 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 759 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 760 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 761 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm 86:04dd9b1680ae 762
Kojto 99:dbbf35b96557 763 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 764 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 765 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 766 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 767 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 768 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 99:dbbf35b96557 769 /**
Kojto 99:dbbf35b96557 770 * @}
Kojto 99:dbbf35b96557 771 */
bogdanm 86:04dd9b1680ae 772
Kojto 99:dbbf35b96557 773 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 774 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 775 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 776 * power consumption.
Kojto 99:dbbf35b96557 777 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 778 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 779 * @{
bogdanm 86:04dd9b1680ae 780 */
Kojto 99:dbbf35b96557 781 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 783 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 784 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 785 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 786 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 787 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
bogdanm 86:04dd9b1680ae 788
Kojto 99:dbbf35b96557 789 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 790 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 791 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 792 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 793 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 794 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 795 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 99:dbbf35b96557 796 /**
Kojto 99:dbbf35b96557 797 * @}
Kojto 99:dbbf35b96557 798 */
bogdanm 86:04dd9b1680ae 799
Kojto 99:dbbf35b96557 800 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 801 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 86:04dd9b1680ae 802 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 86:04dd9b1680ae 803 * power consumption.
Kojto 99:dbbf35b96557 804 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 86:04dd9b1680ae 805 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 806 * @{
bogdanm 86:04dd9b1680ae 807 */
Kojto 99:dbbf35b96557 808 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 809 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 810 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 811 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 812 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 813 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 814 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 815 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
bogdanm 86:04dd9b1680ae 816
Kojto 99:dbbf35b96557 817 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 818 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 819 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 820 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 821 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 822 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 823 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 824 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 99:dbbf35b96557 825 /**
Kojto 99:dbbf35b96557 826 * @}
Kojto 99:dbbf35b96557 827 */
bogdanm 86:04dd9b1680ae 828
Kojto 99:dbbf35b96557 829 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 99:dbbf35b96557 830 * @{
Kojto 99:dbbf35b96557 831 */
Kojto 99:dbbf35b96557 832
bogdanm 86:04dd9b1680ae 833 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 86:04dd9b1680ae 834 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 835 * It is used (enabled by hardware) as system clock source after startup
Kojto 99:dbbf35b96557 836 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
bogdanm 86:04dd9b1680ae 837 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 86:04dd9b1680ae 838 * Security System CSS is enabled).
bogdanm 86:04dd9b1680ae 839 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 86:04dd9b1680ae 840 * you have to select another source of the system clock then stop the HSI.
bogdanm 86:04dd9b1680ae 841 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 86:04dd9b1680ae 842 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 86:04dd9b1680ae 843 * system clock source.
bogdanm 86:04dd9b1680ae 844 * This parameter can be: ENABLE or DISABLE.
bogdanm 86:04dd9b1680ae 845 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 86:04dd9b1680ae 846 * clock cycles.
bogdanm 86:04dd9b1680ae 847 */
Kojto 99:dbbf35b96557 848 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 99:dbbf35b96557 849 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
bogdanm 86:04dd9b1680ae 850
bogdanm 86:04dd9b1680ae 851 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 86:04dd9b1680ae 852 * @note The calibration is used to compensate for the variations in voltage
bogdanm 86:04dd9b1680ae 853 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 86:04dd9b1680ae 854 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 122:f9eeca106725 855 * (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm 86:04dd9b1680ae 856 * This parameter must be a number between 0 and 0x1F.
bogdanm 86:04dd9b1680ae 857 */
bogdanm 86:04dd9b1680ae 858 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm 86:04dd9b1680ae 859 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 99:dbbf35b96557 860 /**
Kojto 99:dbbf35b96557 861 * @}
Kojto 99:dbbf35b96557 862 */
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 99:dbbf35b96557 865 * @{
Kojto 99:dbbf35b96557 866 */
bogdanm 86:04dd9b1680ae 867
bogdanm 86:04dd9b1680ae 868 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 86:04dd9b1680ae 869 * @note After enabling the LSI, the application software should wait on
bogdanm 86:04dd9b1680ae 870 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 86:04dd9b1680ae 871 * be used to clock the IWDG and/or the RTC.
bogdanm 86:04dd9b1680ae 872 * @note LSI can not be disabled if the IWDG is running.
bogdanm 86:04dd9b1680ae 873 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 86:04dd9b1680ae 874 * clock cycles.
bogdanm 86:04dd9b1680ae 875 */
Kojto 99:dbbf35b96557 876 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 99:dbbf35b96557 877 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 99:dbbf35b96557 878 /**
Kojto 99:dbbf35b96557 879 * @}
Kojto 99:dbbf35b96557 880 */
Kojto 99:dbbf35b96557 881
Kojto 99:dbbf35b96557 882 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 99:dbbf35b96557 883 * @{
Kojto 99:dbbf35b96557 884 */
bogdanm 86:04dd9b1680ae 885
bogdanm 86:04dd9b1680ae 886 /**
bogdanm 86:04dd9b1680ae 887 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 99:dbbf35b96557 888 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 889 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
bogdanm 86:04dd9b1680ae 890 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 86:04dd9b1680ae 891 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 86:04dd9b1680ae 892 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 86:04dd9b1680ae 893 * @note HSE state can not be changed if it is used directly or through the
bogdanm 86:04dd9b1680ae 894 * PLL as system clock. In this case, you have to select another source
bogdanm 86:04dd9b1680ae 895 * of the system clock then change the HSE state (ex. disable it).
bogdanm 86:04dd9b1680ae 896 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 897 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 86:04dd9b1680ae 898 * was previously enabled you have to enable it again after calling this
bogdanm 86:04dd9b1680ae 899 * function.
bogdanm 86:04dd9b1680ae 900 * @param __STATE__: specifies the new state of the HSE.
bogdanm 86:04dd9b1680ae 901 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 902 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 86:04dd9b1680ae 903 * 6 HSE oscillator clock cycles.
bogdanm 86:04dd9b1680ae 904 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 86:04dd9b1680ae 905 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 86:04dd9b1680ae 906 */
Kojto 99:dbbf35b96557 907 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 908 /**
Kojto 99:dbbf35b96557 909 * @}
Kojto 99:dbbf35b96557 910 */
Kojto 99:dbbf35b96557 911
Kojto 99:dbbf35b96557 912 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 99:dbbf35b96557 913 * @{
Kojto 99:dbbf35b96557 914 */
bogdanm 86:04dd9b1680ae 915
bogdanm 86:04dd9b1680ae 916 /**
bogdanm 86:04dd9b1680ae 917 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 99:dbbf35b96557 918 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 919 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
bogdanm 86:04dd9b1680ae 920 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 86:04dd9b1680ae 921 * this domain after reset, you have to enable write access using
bogdanm 86:04dd9b1680ae 922 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 86:04dd9b1680ae 923 * (to be done once after reset).
bogdanm 86:04dd9b1680ae 924 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 86:04dd9b1680ae 925 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 86:04dd9b1680ae 926 * is stable and can be used to clock the RTC.
bogdanm 86:04dd9b1680ae 927 * @param __STATE__: specifies the new state of the LSE.
bogdanm 86:04dd9b1680ae 928 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 929 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 86:04dd9b1680ae 930 * 6 LSE oscillator clock cycles.
bogdanm 86:04dd9b1680ae 931 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 86:04dd9b1680ae 932 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 86:04dd9b1680ae 933 */
Kojto 99:dbbf35b96557 934 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 935
Kojto 99:dbbf35b96557 936 /**
Kojto 99:dbbf35b96557 937 * @}
Kojto 99:dbbf35b96557 938 */
bogdanm 86:04dd9b1680ae 939
Kojto 99:dbbf35b96557 940 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 99:dbbf35b96557 941 * @{
Kojto 99:dbbf35b96557 942 */
Kojto 99:dbbf35b96557 943
Kojto 99:dbbf35b96557 944 /** @brief Macros to enable or disable the RTC clock.
bogdanm 86:04dd9b1680ae 945 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 86:04dd9b1680ae 946 */
Kojto 99:dbbf35b96557 947 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 99:dbbf35b96557 948 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm 86:04dd9b1680ae 949
bogdanm 86:04dd9b1680ae 950 /** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm 86:04dd9b1680ae 951 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 86:04dd9b1680ae 952 * access is denied to this domain after reset, you have to enable write
bogdanm 86:04dd9b1680ae 953 * access using the Power Backup Access macro before to configure
bogdanm 86:04dd9b1680ae 954 * the RTC clock source (to be done once after reset).
bogdanm 86:04dd9b1680ae 955 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 86:04dd9b1680ae 956 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 86:04dd9b1680ae 957 * a Power On Reset (POR).
bogdanm 86:04dd9b1680ae 958 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 86:04dd9b1680ae 959 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 960 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm 86:04dd9b1680ae 961 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm 86:04dd9b1680ae 962 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm 86:04dd9b1680ae 963 * as RTC clock, where x:[2,31]
bogdanm 86:04dd9b1680ae 964 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 99:dbbf35b96557 965 * work in STOP and STANDBY modes, and can be used as wake-up source.
bogdanm 86:04dd9b1680ae 966 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 86:04dd9b1680ae 967 * cannot be used in STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 968 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 86:04dd9b1680ae 969 * RTC clock source).
bogdanm 86:04dd9b1680ae 970 */
bogdanm 86:04dd9b1680ae 971 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 122:f9eeca106725 972 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 86:04dd9b1680ae 973
bogdanm 86:04dd9b1680ae 974 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 122:f9eeca106725 975 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
bogdanm 86:04dd9b1680ae 976 } while (0)
bogdanm 86:04dd9b1680ae 977
bogdanm 86:04dd9b1680ae 978 /** @brief Macros to force or release the Backup domain reset.
bogdanm 86:04dd9b1680ae 979 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 86:04dd9b1680ae 980 * and the RTC clock source selection in RCC_CSR register.
bogdanm 86:04dd9b1680ae 981 * @note The BKPSRAM is not affected by this reset.
bogdanm 86:04dd9b1680ae 982 */
Kojto 99:dbbf35b96557 983 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 99:dbbf35b96557 984 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 99:dbbf35b96557 985 /**
Kojto 99:dbbf35b96557 986 * @}
Kojto 99:dbbf35b96557 987 */
Kojto 99:dbbf35b96557 988
Kojto 99:dbbf35b96557 989 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 99:dbbf35b96557 990 * @{
Kojto 99:dbbf35b96557 991 */
bogdanm 86:04dd9b1680ae 992
bogdanm 86:04dd9b1680ae 993 /** @brief Macros to enable or disable the main PLL.
bogdanm 86:04dd9b1680ae 994 * @note After enabling the main PLL, the application software should wait on
bogdanm 86:04dd9b1680ae 995 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 86:04dd9b1680ae 996 * be used as system clock source.
bogdanm 86:04dd9b1680ae 997 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 86:04dd9b1680ae 998 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 86:04dd9b1680ae 999 */
Kojto 99:dbbf35b96557 1000 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 99:dbbf35b96557 1001 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
bogdanm 86:04dd9b1680ae 1002
Kojto 99:dbbf35b96557 1003 /** @brief Macro to configure the PLL clock source.
bogdanm 86:04dd9b1680ae 1004 * @note This function must be used only when the main PLL is disabled.
Kojto 99:dbbf35b96557 1005 * @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm 86:04dd9b1680ae 1006 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1007 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 86:04dd9b1680ae 1008 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 99:dbbf35b96557 1009 *
Kojto 99:dbbf35b96557 1010 */
Kojto 99:dbbf35b96557 1011 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 99:dbbf35b96557 1012
Kojto 99:dbbf35b96557 1013 /** @brief Macro to configure the PLL multiplication factor.
Kojto 99:dbbf35b96557 1014 * @note This function must be used only when the main PLL is disabled.
bogdanm 86:04dd9b1680ae 1015 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 86:04dd9b1680ae 1016 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 86:04dd9b1680ae 1017 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 86:04dd9b1680ae 1018 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 86:04dd9b1680ae 1019 * of 2 MHz to limit PLL jitter.
Kojto 99:dbbf35b96557 1020 *
bogdanm 86:04dd9b1680ae 1021 */
Kojto 99:dbbf35b96557 1022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 99:dbbf35b96557 1023 /**
Kojto 99:dbbf35b96557 1024 * @}
Kojto 122:f9eeca106725 1025 */
Kojto 122:f9eeca106725 1026
Kojto 99:dbbf35b96557 1027 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 99:dbbf35b96557 1028 * @{
bogdanm 86:04dd9b1680ae 1029 */
Kojto 99:dbbf35b96557 1030 /**
Kojto 99:dbbf35b96557 1031 * @brief Macro to configure the system clock source.
Kojto 99:dbbf35b96557 1032 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 99:dbbf35b96557 1033 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 1034 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1035 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1036 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 99:dbbf35b96557 1037 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 99:dbbf35b96557 1038 */
Kojto 99:dbbf35b96557 1039 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
bogdanm 86:04dd9b1680ae 1040
bogdanm 86:04dd9b1680ae 1041 /** @brief Macro to get the clock source used as system clock.
bogdanm 86:04dd9b1680ae 1042 * @retval The clock source used as system clock. The returned value can be one
bogdanm 86:04dd9b1680ae 1043 * of the following:
Kojto 99:dbbf35b96557 1044 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 99:dbbf35b96557 1045 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 99:dbbf35b96557 1046 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 99:dbbf35b96557 1047 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
bogdanm 86:04dd9b1680ae 1048 */
bogdanm 86:04dd9b1680ae 1049 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 86:04dd9b1680ae 1050
bogdanm 86:04dd9b1680ae 1051 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 86:04dd9b1680ae 1052 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 86:04dd9b1680ae 1053 * of the following:
bogdanm 86:04dd9b1680ae 1054 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 86:04dd9b1680ae 1055 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 86:04dd9b1680ae 1056 */
bogdanm 86:04dd9b1680ae 1057 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 99:dbbf35b96557 1058 /**
Kojto 99:dbbf35b96557 1059 * @}
Kojto 99:dbbf35b96557 1060 */
Kojto 99:dbbf35b96557 1061
Kojto 110:165afa46840b 1062 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 110:165afa46840b 1063 * @{
Kojto 110:165afa46840b 1064 */
Kojto 110:165afa46840b 1065
Kojto 110:165afa46840b 1066 /** @brief Macro to configure the MCO1 clock.
Kojto 110:165afa46840b 1067 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1068 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1069 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 110:165afa46840b 1070 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 110:165afa46840b 1071 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 110:165afa46840b 1072 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 110:165afa46840b 1073 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1074 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1075 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1076 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1077 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1078 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1079 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1080 */
Kojto 110:165afa46840b 1081 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1082 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 1083
Kojto 110:165afa46840b 1084 /** @brief Macro to configure the MCO2 clock.
Kojto 110:165afa46840b 1085 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1086 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1087 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 110:165afa46840b 1088 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto 110:165afa46840b 1089 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto 110:165afa46840b 1090 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 110:165afa46840b 1091 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 110:165afa46840b 1092 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1093 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1094 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1095 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1096 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1097 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1098 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 122:f9eeca106725 1099 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
Kojto 122:f9eeca106725 1100 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto 110:165afa46840b 1101 */
Kojto 110:165afa46840b 1102 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 1103 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Kojto 110:165afa46840b 1104 /**
Kojto 110:165afa46840b 1105 * @}
Kojto 110:165afa46840b 1106 */
Kojto 110:165afa46840b 1107
Kojto 99:dbbf35b96557 1108 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 99:dbbf35b96557 1109 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 99:dbbf35b96557 1110 * @{
Kojto 99:dbbf35b96557 1111 */
bogdanm 86:04dd9b1680ae 1112
bogdanm 86:04dd9b1680ae 1113 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm 86:04dd9b1680ae 1114 * the selected interrupts).
bogdanm 86:04dd9b1680ae 1115 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 86:04dd9b1680ae 1116 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1117 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 86:04dd9b1680ae 1118 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 86:04dd9b1680ae 1119 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 86:04dd9b1680ae 1120 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 86:04dd9b1680ae 1121 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 86:04dd9b1680ae 1122 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 86:04dd9b1680ae 1123 */
Kojto 99:dbbf35b96557 1124 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1125
bogdanm 86:04dd9b1680ae 1126 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm 86:04dd9b1680ae 1127 * the selected interrupts).
bogdanm 86:04dd9b1680ae 1128 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 86:04dd9b1680ae 1129 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1130 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 86:04dd9b1680ae 1131 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 86:04dd9b1680ae 1132 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 86:04dd9b1680ae 1133 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 86:04dd9b1680ae 1134 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 86:04dd9b1680ae 1135 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 86:04dd9b1680ae 1136 */
Kojto 122:f9eeca106725 1137 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 1138
bogdanm 86:04dd9b1680ae 1139 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 86:04dd9b1680ae 1140 * bits to clear the selected interrupt pending bits.
bogdanm 86:04dd9b1680ae 1141 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 86:04dd9b1680ae 1142 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 1143 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 86:04dd9b1680ae 1144 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 86:04dd9b1680ae 1145 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 86:04dd9b1680ae 1146 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 86:04dd9b1680ae 1147 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 86:04dd9b1680ae 1148 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 86:04dd9b1680ae 1149 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 86:04dd9b1680ae 1150 */
Kojto 99:dbbf35b96557 1151 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1152
bogdanm 86:04dd9b1680ae 1153 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 1154 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 86:04dd9b1680ae 1155 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1156 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 86:04dd9b1680ae 1157 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 86:04dd9b1680ae 1158 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 86:04dd9b1680ae 1159 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 86:04dd9b1680ae 1160 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 86:04dd9b1680ae 1161 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 86:04dd9b1680ae 1162 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 86:04dd9b1680ae 1163 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1164 */
bogdanm 86:04dd9b1680ae 1165 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1166
bogdanm 86:04dd9b1680ae 1167 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 86:04dd9b1680ae 1168 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm 86:04dd9b1680ae 1169 */
bogdanm 86:04dd9b1680ae 1170 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 86:04dd9b1680ae 1171
bogdanm 86:04dd9b1680ae 1172 /** @brief Check RCC flag is set or not.
bogdanm 86:04dd9b1680ae 1173 * @param __FLAG__: specifies the flag to check.
bogdanm 86:04dd9b1680ae 1174 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1175 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm 86:04dd9b1680ae 1176 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm 86:04dd9b1680ae 1177 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm 86:04dd9b1680ae 1178 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm 86:04dd9b1680ae 1179 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm 86:04dd9b1680ae 1180 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm 86:04dd9b1680ae 1181 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm 86:04dd9b1680ae 1182 * @arg RCC_FLAG_PINRST: Pin reset.
bogdanm 86:04dd9b1680ae 1183 * @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm 86:04dd9b1680ae 1184 * @arg RCC_FLAG_SFTRST: Software reset.
bogdanm 86:04dd9b1680ae 1185 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm 86:04dd9b1680ae 1186 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm 86:04dd9b1680ae 1187 * @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm 86:04dd9b1680ae 1188 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 1189 */
Kojto 122:f9eeca106725 1190 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
Kojto 122:f9eeca106725 1191 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
bogdanm 86:04dd9b1680ae 1192
Kojto 99:dbbf35b96557 1193 /**
Kojto 99:dbbf35b96557 1194 * @}
Kojto 99:dbbf35b96557 1195 */
Kojto 99:dbbf35b96557 1196
Kojto 99:dbbf35b96557 1197 /**
Kojto 99:dbbf35b96557 1198 * @}
Kojto 99:dbbf35b96557 1199 */
bogdanm 86:04dd9b1680ae 1200
bogdanm 86:04dd9b1680ae 1201 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 1202 /** @addtogroup RCC_Exported_Functions
Kojto 99:dbbf35b96557 1203 * @{
Kojto 99:dbbf35b96557 1204 */
Kojto 99:dbbf35b96557 1205
Kojto 99:dbbf35b96557 1206 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 99:dbbf35b96557 1207 * @{
Kojto 99:dbbf35b96557 1208 */
bogdanm 86:04dd9b1680ae 1209 /* Initialization and de-initialization functions ******************************/
bogdanm 86:04dd9b1680ae 1210 void HAL_RCC_DeInit(void);
bogdanm 86:04dd9b1680ae 1211 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 86:04dd9b1680ae 1212 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 99:dbbf35b96557 1213 /**
Kojto 99:dbbf35b96557 1214 * @}
Kojto 99:dbbf35b96557 1215 */
bogdanm 86:04dd9b1680ae 1216
Kojto 99:dbbf35b96557 1217 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 99:dbbf35b96557 1218 * @{
Kojto 99:dbbf35b96557 1219 */
bogdanm 86:04dd9b1680ae 1220 /* Peripheral Control functions ************************************************/
bogdanm 86:04dd9b1680ae 1221 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 86:04dd9b1680ae 1222 void HAL_RCC_EnableCSS(void);
bogdanm 86:04dd9b1680ae 1223 void HAL_RCC_DisableCSS(void);
bogdanm 86:04dd9b1680ae 1224 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 86:04dd9b1680ae 1225 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 86:04dd9b1680ae 1226 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 86:04dd9b1680ae 1227 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 86:04dd9b1680ae 1228 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 86:04dd9b1680ae 1229 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 86:04dd9b1680ae 1230
bogdanm 86:04dd9b1680ae 1231 /* CSS NMI IRQ handler */
bogdanm 86:04dd9b1680ae 1232 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 86:04dd9b1680ae 1233
bogdanm 86:04dd9b1680ae 1234 /* User Callbacks in non blocking mode (IT mode) */
Kojto 99:dbbf35b96557 1235 void HAL_RCC_CSSCallback(void);
Kojto 99:dbbf35b96557 1236
Kojto 99:dbbf35b96557 1237 /**
Kojto 99:dbbf35b96557 1238 * @}
Kojto 99:dbbf35b96557 1239 */
Kojto 99:dbbf35b96557 1240
Kojto 99:dbbf35b96557 1241 /**
Kojto 99:dbbf35b96557 1242 * @}
Kojto 99:dbbf35b96557 1243 */
Kojto 99:dbbf35b96557 1244
Kojto 99:dbbf35b96557 1245 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1246 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1247 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1248 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 99:dbbf35b96557 1249 * @{
Kojto 99:dbbf35b96557 1250 */
Kojto 99:dbbf35b96557 1251
Kojto 99:dbbf35b96557 1252 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 99:dbbf35b96557 1253 * @brief RCC registers bit address in the alias region
Kojto 99:dbbf35b96557 1254 * @{
Kojto 99:dbbf35b96557 1255 */
Kojto 99:dbbf35b96557 1256 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 1257 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 1258 /* Alias word address of HSION bit */
Kojto 122:f9eeca106725 1259 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
Kojto 122:f9eeca106725 1260 #define RCC_HSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1261 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1262 /* Alias word address of CSSON bit */
Kojto 122:f9eeca106725 1263 #define RCC_CSSON_BIT_NUMBER 0x13U
Kojto 122:f9eeca106725 1264 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1265 /* Alias word address of PLLON bit */
Kojto 122:f9eeca106725 1266 #define RCC_PLLON_BIT_NUMBER 0x18U
Kojto 122:f9eeca106725 1267 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1268
Kojto 99:dbbf35b96557 1269 /* --- BDCR Register ---*/
Kojto 99:dbbf35b96557 1270 /* Alias word address of RTCEN bit */
Kojto 122:f9eeca106725 1271 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
Kojto 122:f9eeca106725 1272 #define RCC_RTCEN_BIT_NUMBER 0x0FU
Kojto 122:f9eeca106725 1273 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1274 /* Alias word address of BDRST bit */
Kojto 122:f9eeca106725 1275 #define RCC_BDRST_BIT_NUMBER 0x10U
Kojto 122:f9eeca106725 1276 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1277
Kojto 99:dbbf35b96557 1278 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 1279 /* Alias word address of LSION bit */
Kojto 122:f9eeca106725 1280 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
Kojto 122:f9eeca106725 1281 #define RCC_LSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1282 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
Kojto 99:dbbf35b96557 1283
Kojto 99:dbbf35b96557 1284 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 122:f9eeca106725 1285 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
Kojto 99:dbbf35b96557 1286
Kojto 99:dbbf35b96557 1287 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 122:f9eeca106725 1288 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
Kojto 99:dbbf35b96557 1289
Kojto 99:dbbf35b96557 1290 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 122:f9eeca106725 1291 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
Kojto 99:dbbf35b96557 1292
Kojto 99:dbbf35b96557 1293 /* BDCR register base address */
Kojto 99:dbbf35b96557 1294 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 99:dbbf35b96557 1295
Kojto 122:f9eeca106725 1296 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
Kojto 122:f9eeca106725 1297 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 99:dbbf35b96557 1298
Kojto 99:dbbf35b96557 1299 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 122:f9eeca106725 1300 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
Kojto 122:f9eeca106725 1301 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
Kojto 99:dbbf35b96557 1302
Kojto 99:dbbf35b96557 1303 /**
Kojto 99:dbbf35b96557 1304 * @}
Kojto 99:dbbf35b96557 1305 */
Kojto 99:dbbf35b96557 1306
Kojto 99:dbbf35b96557 1307 /**
Kojto 99:dbbf35b96557 1308 * @}
Kojto 99:dbbf35b96557 1309 */
Kojto 99:dbbf35b96557 1310
Kojto 99:dbbf35b96557 1311 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 1312 /** @defgroup RCC_Private_Macros RCC Private Macros
Kojto 99:dbbf35b96557 1313 * @{
Kojto 99:dbbf35b96557 1314 */
Kojto 99:dbbf35b96557 1315
Kojto 99:dbbf35b96557 1316 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 99:dbbf35b96557 1317 * @{
Kojto 99:dbbf35b96557 1318 */
Kojto 122:f9eeca106725 1319 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
Kojto 99:dbbf35b96557 1320
Kojto 99:dbbf35b96557 1321 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 99:dbbf35b96557 1322 ((HSE) == RCC_HSE_BYPASS))
Kojto 99:dbbf35b96557 1323
Kojto 99:dbbf35b96557 1324 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 99:dbbf35b96557 1325 ((LSE) == RCC_LSE_BYPASS))
Kojto 99:dbbf35b96557 1326
Kojto 99:dbbf35b96557 1327 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 99:dbbf35b96557 1328
Kojto 99:dbbf35b96557 1329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 99:dbbf35b96557 1330
Kojto 99:dbbf35b96557 1331 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 99:dbbf35b96557 1332
Kojto 99:dbbf35b96557 1333 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1334 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 99:dbbf35b96557 1335
Kojto 99:dbbf35b96557 1336 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1337 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 99:dbbf35b96557 1338 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 99:dbbf35b96557 1339 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 99:dbbf35b96557 1340
Kojto 122:f9eeca106725 1341 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 1342 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 1343 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
Kojto 122:f9eeca106725 1344 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
Kojto 122:f9eeca106725 1345 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
Kojto 122:f9eeca106725 1346 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
Kojto 122:f9eeca106725 1347 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
Kojto 122:f9eeca106725 1348 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
Kojto 122:f9eeca106725 1349 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
Kojto 122:f9eeca106725 1350 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
Kojto 122:f9eeca106725 1351 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
Kojto 122:f9eeca106725 1352 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
Kojto 122:f9eeca106725 1353 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
Kojto 122:f9eeca106725 1354 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
Kojto 122:f9eeca106725 1355 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
Kojto 122:f9eeca106725 1356 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
Kojto 122:f9eeca106725 1357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
Kojto 122:f9eeca106725 1358 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
Kojto 122:f9eeca106725 1359 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
Kojto 122:f9eeca106725 1360 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
Kojto 122:f9eeca106725 1361 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
Kojto 122:f9eeca106725 1362 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
Kojto 122:f9eeca106725 1363 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
Kojto 122:f9eeca106725 1364 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
Kojto 122:f9eeca106725 1365 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
Kojto 122:f9eeca106725 1366 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
Kojto 122:f9eeca106725 1367 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
Kojto 122:f9eeca106725 1368 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
Kojto 122:f9eeca106725 1369 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
Kojto 122:f9eeca106725 1370 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
Kojto 122:f9eeca106725 1371 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
Kojto 122:f9eeca106725 1372 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
Kojto 122:f9eeca106725 1373
Kojto 122:f9eeca106725 1374 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto 99:dbbf35b96557 1375
Kojto 122:f9eeca106725 1376 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
Kojto 99:dbbf35b96557 1377
Kojto 122:f9eeca106725 1378 #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
Kojto 99:dbbf35b96557 1379
Kojto 99:dbbf35b96557 1380 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 99:dbbf35b96557 1381 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 99:dbbf35b96557 1382 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 99:dbbf35b96557 1383 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 99:dbbf35b96557 1384 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 99:dbbf35b96557 1385
Kojto 122:f9eeca106725 1386 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
Kojto 99:dbbf35b96557 1387
Kojto 99:dbbf35b96557 1388 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 99:dbbf35b96557 1389 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 99:dbbf35b96557 1390 ((PCLK) == RCC_HCLK_DIV16))
Kojto 99:dbbf35b96557 1391
Kojto 99:dbbf35b96557 1392 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 99:dbbf35b96557 1393
Kojto 99:dbbf35b96557 1394 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 99:dbbf35b96557 1395 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 99:dbbf35b96557 1396
Kojto 99:dbbf35b96557 1397 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 99:dbbf35b96557 1398 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 99:dbbf35b96557 1399 ((DIV) == RCC_MCODIV_5))
Kojto 122:f9eeca106725 1400 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
Kojto 99:dbbf35b96557 1401
Kojto 99:dbbf35b96557 1402 /**
Kojto 99:dbbf35b96557 1403 * @}
Kojto 99:dbbf35b96557 1404 */
Kojto 99:dbbf35b96557 1405
Kojto 99:dbbf35b96557 1406 /**
Kojto 99:dbbf35b96557 1407 * @}
Kojto 99:dbbf35b96557 1408 */
bogdanm 86:04dd9b1680ae 1409
bogdanm 86:04dd9b1680ae 1410 /**
bogdanm 86:04dd9b1680ae 1411 * @}
bogdanm 86:04dd9b1680ae 1412 */
bogdanm 86:04dd9b1680ae 1413
bogdanm 86:04dd9b1680ae 1414 /**
bogdanm 86:04dd9b1680ae 1415 * @}
bogdanm 86:04dd9b1680ae 1416 */
bogdanm 86:04dd9b1680ae 1417
bogdanm 86:04dd9b1680ae 1418 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1419 }
bogdanm 86:04dd9b1680ae 1420 #endif
bogdanm 86:04dd9b1680ae 1421
bogdanm 86:04dd9b1680ae 1422 #endif /* __STM32F4xx_HAL_RCC_H */
bogdanm 86:04dd9b1680ae 1423
bogdanm 86:04dd9b1680ae 1424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/